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| MCIMX27rm rev. 0.2 9/2007 MCIMX27 multimedia applications processor reference manual
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor iii contents audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix suggested reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx definitions, acronyms, and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx chapter 1 introduction to the i.mx27 multimedia applications processor 1.1 i.mx27 applications processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 summary of core and modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1 arm9 ? platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.3 standard system resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.4 power management and backup modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.5 system security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.6 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.7 wireline connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.2.8 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.9 memory expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.2.10 video codec and enhanced multimedia accelerator lite (emma_lt) . . . . . . . . . . . . . . . 1-17 1.2.11 multimedia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.2.12 human interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.2.13 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 chapter 2 system memory and register map 2.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.1 detailed memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 chapter 3 clocks, power management, and reset control 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 clock controller architecture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2.1 high frequency clock source and distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.2 output frequency calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 pll operation at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.2 pll operation at wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 MCIMX27 multimedia applications processor reference manual, rev. 0.2 iv freescale semiconductor 3.3.3 i.mx27 processor low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.4 sdram power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.5 power management in the pll clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.6 power management using frequency control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -9 3.4.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2 clock source control register (cscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3 mpll control register 0 (mpctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.4 mcu and system pll control register 1 (mpctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.5 programming the serial peripheral pll (spll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.6 spll control register 0 (spctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.7 spll control register 1 (spctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.8 oscillator 26m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.4.9 peripheral clock divider register 0 (pcdr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.10 peripheral clock divider register 1 (pcdr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.11 peripheral clock control register 0 (pccr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.4.12 peripheral clock control register 1 (pccr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.4.13 clock control status register (ccsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.4.14 wakeup guard mode control register (wkgdctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.5 functional description of the reset module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.5.1 global reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.5.2 arm9 platform reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 chapter 4 system control 4.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 4.2.1 chip id register (cid). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 function multiplexing control register (fmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.3 global peripheral control register (gpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.4 well bias system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.5 well bias control register (wbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.6 drive strength control register 1 (dscr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.7 drive strength control register 2 (dscr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.8 drive strength control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 14 4.2.9 drive strength control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 17 4.2.10 drive strength control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -18 4.2.11 drive strength control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -21 4.2.12 drive strength control register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -23 4.2.13 drive strength control register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -25 4.2.14 drive strength control register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -28 4.2.15 drive strength control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 30 4.2.16 drive strength control register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 32 4.2.17 drive strength control register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 34 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor v 4.2.18 drive strength control register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 36 4.2.19 pull strength control register (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.2.20 priority control and select register (pcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4.2.21 power management control register (pmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4.2.22 dptc comparator value register 0 (dcvr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 4.2.23 dptc comparator value register 1 (dcvr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 4.2.24 dptc comparator value register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 4.2.25 dptc comparator value register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.2.26 pmic pad control register (ppcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.3 system boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 chapter 5 signal descriptions and pin assignments 5.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 i/o power supply and signal multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.1 pull/pull strength/open drain descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.2 gpio default and pull-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.3 i/o mode and supply level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 package pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 chapter 6 general-purpose i/o (gpio) 6.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 gpio features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.4 external signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.6 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 4 6.6.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.6.2 data direction register (ptn_ddir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.6.3 output configuration register 1 (ocr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.6.4 output configuration register 2 (ocr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.6.5 input configuration register a1 (iconfa1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6.6 input configuration register a2 (iconfa2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.6.7 input configuration register b1 (iconfb1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.6.8 input configuration register b2 (iconfb2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.6.9 data register (dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.6.10 gpio in use registers (gius) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.6.11 gpio in use register reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.6.12 sample status register (ssr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.6.13 interrupt configuration register 1 (icr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.6.14 interrupt configuration register 2 (icr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.6.15 interrupt mask register (imr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 MCIMX27 multimedia applications processor reference manual, rev. 0.2 vi freescale semiconductor 6.6.16 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.6.17 general purpose register (gpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 27 6.6.18 software reset register (swr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 28 6.6.19 pull-up enable register (puen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 9 6.6.20 port interrupt mask register (pmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 chapter 7 jtag controller (jtagc) 7.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.4 jtag controller pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.5 jtag overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.6 jtag modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.6.1 arm926 platform mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.6.2 i.mx27 jtag controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 3 7.7 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.8 instruction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.8.1 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.8.2 sample/preload instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.8.3 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.8.4 enable_extradebug instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.8.5 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.8.6 clamp instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.8.7 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.9 tms sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.9.1 tms sequence to check id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.9.2 tms sequence to write to extradebug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.9.3 tms sequence to read extradebug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.10 i.mx27 jtag restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 chapter 8 bootstrap mode operation 8.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 uart/usb configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3 enter bootstrap mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.4 bootstrap flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4.1 bootstrap protocol and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 chapter 9 arm9 platform 9.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.1.1 design methodology summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor vii 9.1.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2 arm9 platform sub-modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.1 arm926ej-s processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.2 arm9 embedded trace macrocell and embedded trace bu ffer . . . . . . . . . . . . . . . . . . . . 9-6 9.2.3 the 6 x 3 multi-layer ahb crossbar switch (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.4 arm interrupt controller (aitc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9- 7 9.2.5 memory controller and bist engine (mctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.2.6 ahb ip bus interface (aipi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.2.7 pahbmux?primary ahb mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.2.8 rompatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.2.9 clock control module (clkctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.2.10 jam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.2.11 test wrapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3 arm9 platform hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4 jtag id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5 system memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5.1 arm9 platform memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5.2 external peripheral space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5.3 external boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5.4 memory map considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 4 9.6 platform clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.6.1 arm926ej-s clock considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.6.2 arm926ej-s jtag port clocking considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.6.3 external alternate bus master interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.6.4 external secondary ahb ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 6 9.7 platform resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.7.1 hreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.7.2 por and jtag_trst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -17 9.8 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.8.1 register level clock gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.8.2 block level clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.8.3 external clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.8.4 well biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9.9 platform ahb interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9.9.1 definition of ahb-lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.9.2 alternate bus master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.9.3 single master seamless connection to abm port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.9.4 multiple external masters connection to abm port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.9.5 alternate bus master design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 9.9.6 max ahb slave ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 9.9.7 endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.10 preliminary size estimate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.11 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 9.12 arm9 platform i/o signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 9.13 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 MCIMX27 multimedia applications processor reference manual, rev. 0.2 viii freescale semiconductor 9.13.1 conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.13.2 well bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.13.3 clk and jtag_tck relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41 9.13.4 clocks and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41 9.13.5 alternate bus master (abm) interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42 9.13.6 secondary ahb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.13.7 ram and rom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 chapter 10 arm926ej-s interrupt controller (aitc) 10.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 -3 10.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.3 interrupt control register (intcntl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.2.4 normal interrupt mask register (nimask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.2.5 interrupt enable number register (intennum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.2.6 interrupt disable number register (intdisnum). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.2.7 interrupt enable register high (intenableh ) and low (intenablel) . . . . . . . . 10-12 10.2.8 interrupt type register high (inttypeh) and lo w (inttypel). . . . . . . . . . . . . . . . 10-13 10.2.9 normal interrupt priority level registers (nipriority n ) . . . . . . . . . . . . . . . . . . . . . . 10-14 10.2.10 normal interrupt vector and status register (nivec sr). . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.2.11 fast interrupt vector and status register (fivecsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.2.12 interrupt source register high (intsrch) and low (intsrcl). . . . . . . . . . . . . . . . . 10-24 10.2.13 interrupt force register high (intfrch) and low (intfrcl). . . . . . . . . . . . . . . . . . 10-27 10.2.14 normal interrupt pending register high (nip ndh) and low (nipndl) . . . . . . . . . . . 10-28 10.2.15 fast interrupt pending register high (fipndh) and low (fipndl) . . . . . . . . . . . . . . 10-29 10.3 arm926ej-s interrupt controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.1 arm926ej-s prioritization of exception sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.2 aitc prioritization of interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.3 assigning and enabling interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.4 enabling interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.5 typical interrupt entry sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 1 10.3.6 writing reentrant normal interrupt routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.3.7 ahb interface of aitc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 chapter 11 security controller (scc) 11.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor ix chapter 12 symmetric/asymmetric hashing and random accelerator (sahara2) 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 chapter 13 run-time integrity checker (rtic) 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2.1 system application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 chapter 14 ic identification (iim) 14.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 chapter 15 external memory interface (emi) 15.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3 pcmcia host adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3.1 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3.2 card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3.3 trueide support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.4 nand flash controller (nfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.4.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5 enhanced sdram controller (esdramc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.6 m3if ahb mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.6.1 overview of emi ahb mux operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.7 m3if i/o mux. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.7.1 overview of emi i/o mux operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.7.2 emi input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.8 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 chapter 16 multi-master memory interface (m3if) 16.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 m3if interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -6 MCIMX27 multimedia applications processor reference manual, rev. 0.2 x freescale semiconductor 16.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.4.1 master port gasket (mpg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6-17 16.4.2 master port gasket 64 (mpg64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.3 m3if arbitration (m3a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.4.4 master arbitration and buffering (mab) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36 16.4.5 snooping logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 16.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40 16.5.1 m3if in a system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40 chapter 17 wireless external interface module (weim) 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.4 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.5 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -7 17.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.5.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.6.1 configurable bus sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.6.2 weim operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -25 17.6.3 burst mode memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.6.4 burst clock divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.5 burst clock start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.6 page mode emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.7 psram mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -27 17.6.8 multiplexed address/data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.9 mixed ahb/memory burst modes support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.10 ahb bus cycles support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.11 dtack mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.6.12 internal input data capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.6.13 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.8 external bus timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.8.1 asynchronous memory accesses timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.8.2 page mode timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 0 17.8.3 dtack mode memory accesses timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-51 17.8.4 burst memory accesses timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-54 17.8.5 synchronous accesses timing diagrams with psram . . . . . . . . . . . . . . . . . . . . . . . . . 17-65 17.8.6 multiplexed a/d mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xi chapter 18 enhanced sdram controller (esdramc) 18.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 sdram command controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.2 bank model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.3 decoder and address mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8-1 18.1.4 esdramc control and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.5 refresh sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.6 command sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.7 size logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.8 mobile/low power ddr (lpddr) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.9 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.1.10 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 -9 18.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36 18.4.1 enhanced sdram controller optimization strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 18.4.2 address multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 18.4.3 multiplexed address bus?during ?special? mode (smode 1 or 3) . . . . . . . . . . . . . . 18-47 18.4.4 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 18.4.5 low power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 9 18.4.6 sdram (sdr and lpddr) command encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60 18.4.7 normal read/write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 18.4.8 precharge command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 1 18.4.9 auto-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-93 18.4.10 manual self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-94 18.4.11 set mode register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-94 18.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.1 memory device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8-96 18.5.2 configuring controller for sdram memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.3 cas latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.4 sdram/lpddr initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-97 chapter 19 nand flash controller (nfc) 19.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xii freescale semiconductor 19.4.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.5 nfc buffer memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.5.1 main and spare area buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 -7 19.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.6.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.7 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.7.1 internal sram size (nfc_bufsize). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.7.2 buffer number for page data transfer (ram _buffer_address) . . . . . . . . . . . . . 19-10 19.7.3 nand flash address (nand_flash_add). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.7.4 nand flash command (nand_flash_cmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.7.5 nfc internal buffer lock cont rol (nfc_configuration) . . . . . . . . . . . . . . . . . . . 19-11 19.7.6 controller status and result of flash operat ion (ecc_status_result). . . . . . . . . 19-12 19.7.7 ecc error position of main area data er ror x8 (ecc_rslt_main_area). . . . . . . 19-12 19.7.8 ecc error position of main area data er ror x16 (ecc_rslt_main_area). . . . . . 19-13 19.7.9 ecc error position of spare area data error x8 (ecc_rslt_spare_area) . . . . . 19-14 19.7.10 ecc error position of spare area data error x16 (ecc_rslt_spare_area) . . . . 19-14 19.7.11 nand flash write protection (nf_wr_prot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.7.12 address to unlock in write protection mode?start (unlock_start_blk_add) 19-15 19.7.13 address to unlock in write protection mode?end (unlock_end_blk_add). . . 19-16 19.7.14 nand flash write protection status (nand_flash_wr_pr_st) . . . . . . . . . . . . . . 19-16 19.7.15 nand flash operation configuration (nand_flash_config1) . . . . . . . . . . . . . . 19-17 19.7.16 nand flash operation configuration 2 (nand_flash_config2) . . . . . . . . . . . . . 19-18 19.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.8.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.8.2 booting from a nand flash device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 19.8.3 nand flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 19.8.4 error code correction (ecc) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.8.5 address control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.8.6 ram buffer (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.7 registers (command, address, status, and others.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.8 read and write control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.9 data output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.10 host control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.11 ahb bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 4 19.8.12 i/o pins sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.9 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.9.1 normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.9.2 ecc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34 19.9.3 write protection operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35 19.9.4 memory configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xiii chapter 20 personal computer memory card international association (pcmcia) controller 20.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 -6 20.4.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.2 windowing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.3 wait signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.6 reset and three-score control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 -24 20.5.7 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.8 16-bit/8-bit support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 20.5.9 data and control signals relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 5 20.5.10 true ide mode access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.11 card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.12 trueide support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.5.13 endianness support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 chapter 21 1-wire interface (1-wire) 21.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.2 port definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.4 clock enable and aipi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1-3 21.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5.2 reset sequence with reset pulse presence pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5.3 write 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.5.4 write 1 and read data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.5.5 program pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 -5 21.6.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.6.2 time divider register (time_divider). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.6.3 reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xiv freescale semiconductor chapter 22 advanced technology attachment (ata) 22.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.4 pio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.4.1 dma mode (multi-word dma and ultra dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.5.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 -6 22.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.6.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.6.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 22.8 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 22.8.1 resetting ata bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.8.2 access to ata bus in pio mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.8.3 using dma mode to receive data from ata bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.8.4 using dma mode to transmit data to ata bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 chapter 23 configurable serial peripheral interface (cspi) 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 external signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 module input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3.1 phase and polarity configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3-5 23.3.2 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3.3 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.4 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.3.5 dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.4 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.4.1 software restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23.5 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 3 23.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 23.5.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 23.5.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 23.6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 chapter 24 inter-integrated circuit (i 2 c) 24.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xv 24.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.1 detailed external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24- 3 24.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 -4 24.3.1 i 2 c memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 -4 24.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.4.1 i 2 c system configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.4.2 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.4.3 arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.4 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.5 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.6 clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.7 ip bus accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.8 generation of transfer error on ip bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.5.1 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.5.2 generation of start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.5.3 post-transfer software response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 5 24.5.4 generation of stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 24.5.5 generation of repeated start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 24.5.6 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 24.5.7 arbitration lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.5.8 timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 chapter 25 keypad port (kpp) 25.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 -3 25.3.1 kpp memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.1 keypad matrix construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.2 keypad port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.3 keypad matrix scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.4 keypad standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.5 glitch suppression on keypad inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.6 multiple key closures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.4.7 3-point contact keys support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 -14 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xvi freescale semiconductor 25.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.5.1 typical keypad configuration and s canning sequence . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.5.2 key press interrupt scanning sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.5.3 additional comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 chapter 26 memory stick host controller (mshc) 26.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 -3 26.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.4.1 sony memory stick controller (smsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.4.2 mshc gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 chapter 27 secured digital host controller (sdhc) 27.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -3 27.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 27.4.1 data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 27.4.2 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-34 27.4.3 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-35 27.4.4 sdio card interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-36 27.4.5 card insertion and removal detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-38 27.4.6 power management and wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-39 27.4.7 command/data interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7-40 27.4.8 system clock controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-42 27.4.9 dat/cmd transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7-43 27.5 initialization/application of sdhc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-43 27.5.1 command submit?response receive basic operation . . . . . . . . . . . . . . . . . . . . . . . . . 27-44 27.5.2 card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-45 27.5.3 card access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50 27.6 commands for mmc/sd/sdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xvii chapter 28 universal asynchronous receiver/transmitters (uart) 28.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -3 28.3.1 memory map and register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.3.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.3.3 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.4.1 interrupts and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28- 27 28.4.2 clocking considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28 28.4.3 general uart definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8-31 28.4.4 sub-block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.4.5 binary rate multiplier (brm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28- 40 28.4.6 baud rate automatic detection logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42 28.4.7 escape sequence detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8-44 28.4.8 uart operation in low-power system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-48 28.4.9 uart operation in system debug state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-49 chapter 29 fast ethernet controller (fec) 29.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.1 full and half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9-2 29.3.2 interface options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.3 address recognition options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.4 internal loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.4 fec top-level functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 -3 29.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.5.1 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.5.2 user initialization (prior to asse rting ecr[ether_en]) . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.5.3 microcontroller initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.4 user initialization (after asserting ecr[ether_en]) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.5 network interface options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.6 fec frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.5.7 fec frame reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 29.5.8 ethernet address recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.9 hash algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xviii freescale semiconductor 29.5.10 full duplex flow control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29.5.11 inter-packet gap (ipg) time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15 29.5.12 collision handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15 29.5.13 internal and external loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9-15 29.5.14 ethernet error-handling procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 6 29.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 7 29.6.1 high-level module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29.6.2 detailed memory map (control/status registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18 29.6.3 mib block counters memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 29.6.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-21 29.6.5 buffer descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37 chapter 30 high-speed usb on-the-go (hs usb-otg) 30.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3.1 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.5 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30- 4 30.5.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.6.1 usb host controller 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.6.2 usb host controller 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12 30.6.3 usb otg controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 30.6.4 usb power control module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30- 15 30.6.5 tll mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.6.6 usb bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.6.7 ulpi/serial mux. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.6.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.7.1 software model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.7.2 register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 30.8 summary of register layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-27 30.8.1 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30 30.8.2 host data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-76 30.8.3 host operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-101 30.8.4 ehci deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-182 30.8.5 device data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-188 30.8.6 device operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 -194 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xix chapter 31 general purpose timer (gpt) 31.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2.1 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.2 operation during low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.3 capture event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.4 compare event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.1 gpt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.3.2 gpt prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.3.3 gpt compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.3.4 gpt capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.3.5 gpt counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.3.6 gpt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 chapter 32 pulse-width modulator (pwm) 32.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.2 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.2.1 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 -4 32.3.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.4.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.5 pwm clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14 32.5.1 pwm clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15 32.5.2 ipg_enable_clk generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 chapter 33 real time clock (rtc) 33.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 -3 33.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.4.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.4.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xx freescale semiconductor 33.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-17 33.5.1 prescaler and counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-17 33.5.2 alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-18 33.5.3 sampling timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-18 33.5.4 minute stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-19 33.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-19 33.6.1 flowchart of rtc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 -19 33.6.2 code example of arm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-20 chapter 34 watchdog timer (wdog) 34.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.2.1 detailed external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34- 2 34.2.2 internal port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.3 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34- 4 34.3.1 watchdog timer memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.4.1 watchdog control register (wcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.4.2 watchdog service register (wsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.5.1 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.5.2 watchdog during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.5.3 watchdog after reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.5.4 generation of transfer error on the ip bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 34.5.5 low-power and debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 34.5.6 watchdog reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.5.7 wdog operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 34.6.1 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 chapter 35 ahb-lite ip interface (aipi) module 35.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35.1.1 peripheral size registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.2 peripheral access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2 aipi1 and aipi2 peripheral widths and psr setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.3 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6 35.3.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6 35.3.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6 35.3.3 aborted cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxi chapter 36 multi-layer ahb crossbar switch (max) 36.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.3 general operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2 36.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 -3 36.4.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.4.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.4.3 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.4.4 max register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 36.4.5 master priority registers (mpr0?mpr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 36.4.6 alternate master priority register for slave port 0?2 (ampr0?2). . . . . . . . . . . . . . . . . . 36-7 36.4.7 general purpose control register for slave port 0?2 (sgpcr0?2) . . . . . . . . . . . . . . . . . 36-9 36.4.8 alternate sgpcr for slave port 0?2 (asgpcr0?2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11 36.5 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14 36.5.1 arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14 36.5.2 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15 36.5.3 master port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-16 36.5.4 slave port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19 36.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-25 36.7 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 36.7.1 master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 36.7.2 slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 chapter 37 direct memory access controller (dmac) 37.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.2 dma request and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 -2 37.2.1 dma request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 37.2.2 external dma request and grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 37.3 dma request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 37.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 -5 37.4.1 dmac memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5 37.4.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6 37.4.3 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-10 37.4.4 2d memory registers (a and b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-16 37.4.5 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-19 37.5 dma chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 37.6 special cases of burst length and access size settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 37.6.1 memory increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 37.6.2 memory decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.7 special cases when ccnr and cntr values differ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.7.1 cntr not a multiple of destination access size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.7.2 bl is not a multiple of destination access size, cntr is. . . . . . . . . . . . . . . . . . . . . . . 37-32 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxii freescale semiconductor 37.8 application note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-32 37.9 dma burst termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-32 37.10 glossary of terms used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-33 chapter 38 digital audio mux (audmux) 38.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.3 internal network mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.4 tx/rx switch and external network mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.5 frame sync and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5 38.6 synchronous mode (4-wire interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 -6 38.7 asynchronous mode (6-wire interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38- 7 38.8 ssi to peripheral connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7 38.9 ssi to sap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.10 peripheral port to peripheral port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.11 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38- 14 38.11.1 audmux memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.11.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.11.3 host port configuration register (hpcr1?2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16 38.11.4 peripheral port configuration registers (ppcr1?2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-18 38.12 peripheral connectivity through audmux configuration . . . . . . . . . . . . . . . . . . . . . . . . . 38-20 38.12.1 generic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-20 38.12.2 audmux configuration with ssi1 and sap as master. . . . . . . . . . . . . . . . . . . . . . . . . 38-22 38.12.3 tx-rx switch enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-23 38.12.4 internal/external network mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38- 24 chapter 39 cmos sensor interface (csi) 39.1 csi architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.2 csi interface signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2 39.2.1 signals from csi to emma pre-processor block (prp). . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.3 principles of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.3.1 gated clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.3.2 non-gated clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.3.3 ccir656 interlace mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.3.4 ccir656 progressive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9-6 39.3.5 error correction for ccir656 coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7 39.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7 39.4.1 start of frame interrupt (sof_int) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7 39.4.2 end of frame interrupt (eof_int). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8 39.4.3 change of field interrupt (cof_int). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8 39.4.4 ccir error interrupt (ecc_int). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39- 8 39.4.5 data packing style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxiii 39.4.6 rx fifo path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9 39.4.7 stat fifo path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-10 39.5 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 1 39.5.1 csi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.5.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.5.3 csi control register 1 (csicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-14 39.5.4 csi control register 2 (csicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-17 39.5.5 csi control register 3 (csicr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-19 39.5.6 csi status register (csisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9-20 39.5.7 csi statfifo register (csistatfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.5.8 csi rxfifo register (csirfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.5.9 csi rx count register (csirxcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-23 chapter 40 video codec (video_codec) 40.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.3 clock domain and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.3.1 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 -4 40.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 40.4.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7 40.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-12 40.5.1 video codec architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-12 40.5.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-14 40.6 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-15 40.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-15 40.7.1 video codec processing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 5 40.7.2 application using cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-24 chapter 41 enhanced multimedia accelerator light (emma_lt) 41.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.2 emma_lt architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.2.1 pre-processor (prp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2.2 post-processor (pp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2.3 64-bit gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.3 post-processor (pp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.3.1 color space conversion (csc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 -7 41.3.2 input interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.3.3 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxiv freescale semiconductor 41.3.4 data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11 41.3.5 relationship of register fields re lated to the input frame . . . . . . . . . . . . . . . . . . . . . . . 41-11 41.3.6 relationship of register fields re lated to output frame . . . . . . . . . . . . . . . . . . . . . . . . 41-12 41.4 post processor (pp) programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-13 41.4.1 pp control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-14 41.4.2 pp interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15 41.4.3 pp interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16 41.4.4 pp source y address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 -17 41.4.5 pp source cb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41- 18 41.4.6 pp source cr address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41- 19 41.4.7 pp destination rgb frame start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-19 41.4.8 pp quantizer start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-20 41.4.9 pp process frame parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21 41.4.10 pp source frame width register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 1 41.4.11 pp destination display width register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22 41.4.12 pp destination image size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 3 41.4.13 pp destination frame format control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-24 41.4.14 pp resize table index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1-25 41.4.15 pp csc coef 123 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 -26 41.4.16 pp csc coef_4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1-27 41.4.17 pp resize coefficient table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-28 41.5 pre-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-30 41.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31 41.5.2 input data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31 41.5.3 resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-32 41.5.4 color space conversion (csc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 5 41.5.5 rgb to yuv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-35 41.5.6 frame skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-36 41.5.7 loop mode (len) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-37 41.5.8 channel-1 and channel-2 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-37 41.5.9 channel-2 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-38 41.5.10 line buffer overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-38 41.5.11 relationship of register fields re lated to the input frame . . . . . . . . . . . . . . . . . . . . . . . 41-38 41.5.12 relationship of register fields related to channel-1 ou tput frame . . . . . . . . . . . . . . . 41-39 41.5.13 csi frame cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-40 41.5.14 csi-prp link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-41 41.6 pre-processor (prp) programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-43 41.6.1 prp control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-44 41.6.2 prp interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-47 41.6.3 prp interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-49 41.6.4 prp source y address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41- 50 41.6.5 prp source cb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 1 41.6.6 prp source cr address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41- 51 41.6.7 prp destination rgb1 frame start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-52 41.6.8 prp destination rgb2 frame start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-53 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxv 41.6.9 prp destination y address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-53 41.6.10 prp destination cb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-54 41.6.11 prp destination cr address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 5 41.6.12 prp source frame size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 -55 41.6.13 prp destination channel-1 line stride register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-56 41.6.14 prp source pixel format control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-57 41.6.15 prp channel-1 pixel format control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-59 41.6.16 prp destination channel-1 output image size register . . . . . . . . . . . . . . . . . . . . . . . . . 41-61 41.6.17 prp destination channel-2 output image size register . . . . . . . . . . . . . . . . . . . . . . . . . 41-61 41.6.18 prp source line stride register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1-62 41.6.19 prp csc coefficient 012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-63 41.6.20 prp csc coefficient 345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-64 41.6.21 prp csc coefficient 678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-65 41.6.22 prp channel 1 horizontal resize coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-67 41.6.23 prp channel1 horizontal resize coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-68 41.6.24 prp channel 1 horizontal resize valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-69 41.6.25 prp channel1 vertical resize coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-70 41.6.26 prp channel 1 vertical resize coefficient 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-71 41.6.27 prp channel 1 vertical resize valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 2 41.6.28 prp channel-2 horizontal resize coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-73 41.6.29 prp channel-2 horizontal resize coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-74 41.6.30 prp channel-2 horizontal resize valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-75 41.6.31 prp channel2 vertical resize coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-76 41.6.32 prp channel 2 vertical resize coefficient 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-78 41.6.33 prp channel 2 vertical resize valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 9 chapter 42 synchronous serial interface (ssi) 42.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2 42.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 42.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 42.2.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 42.2.3 internal i/o signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-25 42.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2 7 42.3.1 r/wssi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2-27 42.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-28 42.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-32 42.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 42.4.1 ssi architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 42.4.2 ssi clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 42.4.3 receive interrupt enable bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-69 42.4.4 transmit interrupt enable bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-69 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxvi freescale semiconductor 42.4.5 ip bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-70 42.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-70 chapter 43 liquid crystal display controller (lcdc) 43.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.2.1 lcd screen format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.2.2 graphic window on screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4 43.2.3 panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.2.4 display data mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.2.5 black-and-white operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7 43.2.6 gray-scale operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7 43.2.7 color generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8 43.2.8 frame rate modulation control (frc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-10 43.2.9 panel interface signals and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 1 43.2.10 8 bpp mode color stn panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 -14 43.3 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-19 43.3.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-20 43.3.2 lcdc screen start address register (lssar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-24 43.3.3 lcdc size register (lsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3-24 43.3.4 lcdc virtual page width register (lvpwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-25 43.3.5 lcdc cursor position register (lcpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.3.6 lcdc cursor width height and blink register (lcwhb) . . . . . . . . . . . . . . . . . . . . . . 43-27 43.3.7 lcdc color cursor mapping register (lccmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-28 43.3.8 lcdc panel configuration register (lpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-29 43.3.9 lcdc horizontal configuration register (lhcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-31 43.3.10 lcdc vertical configuration register (lvcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-32 43.3.11 lcdc panning offset register (lpor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-33 43.3.12 lcdc sharp configuration register (lscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-34 43.3.13 lcdc pwm contrast control register (lpccr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-36 43.3.14 lcdc dma control register (ldcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-37 43.3.15 lcdc refresh mode control register (lrmcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-38 43.3.16 lcdc interrupt configuration register (licr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-39 43.3.17 lcdc interrupt enable register (lier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-40 43.3.18 lcdc interrupt status register (lisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-41 43.3.19 lcdc graphic window start address register (lgwsar) . . . . . . . . . . . . . . . . . . . . . 43-43 43.3.20 lcdc graphic window size register (lgwsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-43 43.3.21 lcdc graphic window virtual page width register (lgwvpwr) . . . . . . . . . . . . . . 43-44 43.3.22 lcdc graphic window panning offset register (lgwpor) . . . . . . . . . . . . . . . . . . . . 43-44 43.3.23 lcdc graphic window position register (lgwpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-45 43.3.24 lcdc graphic window control register (lgwcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-46 43.3.25 lcdc graphic window dma control register (lgw dcr) . . . . . . . . . . . . . . . . . . . . 43-47 43.3.26 lcdc aus mode control register (lauscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-48 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxvii 43.3.27 lcdc aus mode cursor control register (lausccr) . . . . . . . . . . . . . . . . . . . . . . . . 43-49 43.3.28 bglut and gwlut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3-50 chapter 44 smart liquid crystal display controller (slcdc) 44.1 slcdc module pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.1 word size definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.2 image endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.3 accessing the lcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.4 aborting slcdc transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 -14 44.2.5 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 4 44.2.6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-14 44.2.7 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-15 44.2.8 sldc register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4-16 44.2.9 data buffer base addre ss register (databaseadr). . . . . . . . . . . . . . . . . . . . . . . . . 44-18 44.2.10 data buffer size register (databufsize) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-18 44.2.11 command buffer base address regist er (combaseadr) . . . . . . . . . . . . . . . . . . . . . 44-19 44.2.12 command buffer size register (combufsiz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-19 44.2.13 command string size register (comstringsiz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-20 44.2.14 fifo configuration register (fifoc onfig). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-21 44.2.15 lcd controller configuration register (lcdconfig). . . . . . . . . . . . . . . . . . . . . . . . . 44-21 44.2.16 lcd transfer configuration regi ster (lcdtransconfig) . . . . . . . . . . . . . . . . . . . 44-22 44.2.17 slcdc control/status register (slcdccontrol/status) . . . . . . . . . . . . . . . . . . 44-23 44.2.18 lcd clock configuration register (lcdclockconfig) . . . . . . . . . . . . . . . . . . . . . 44-26 44.2.19 lcd write data register (lcdwritedata) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-26 44.3 lcd controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-27 44.3.1 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-27 44.3.2 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-29 44.4 lcd clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-30 44.5 r-ahb interface and slcdc fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-31 MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxviii freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxix about this book the MCIMX27 multimedia applications processor reference manual describes the features and operation of the i.mx27 microprocessor, the seventh generation of the dragonball family of products. it provides the details of how to initialize, configure, and program the i.mx27 device. the manual presumes basic knowledge of arm926ej-s? architecture. audience the MCIMX27 multimedia applicati ons processor reference manual is intended to provide a design engineer with the necessary data to successfully in tegrate the i.mx27 processor into a wide variety of applications. it is assumed that the reader has a good working knowledge of th e arm926ej-s processor. for programming information about the arm926ej-s processor, see the documents listed in the suggested reading section of this preface. organization this reference manual is organized into two books: 1. book i contains chapters that detail integrati on information, including the signals, clocks, power management, muxing tables, and jtag/boot operation of the ic. 2. book ii is divided into parts that consist of ch apters that cover the operation and programming of the i.mx27 device. document revision history since the last revision, rev. 0.1, base addresses a nd memory addresses for some modules were updated for easier reader access. suggested reading the following documents are recommended for a complete description of the i.mx27 multimedia applications processor, and enable proper design with the i.mx27 device. especially for those not familiar with the arm926ej-s processor or previous dra gonball products, the following documents will be helpful when used in conjunction with this manual. ? amba ahb specifications , (arm ltd.) ? arm926ej-s platform specifications (also named arm926 platform ) ? hip7a kilobit single port hp sram compiler , memctc (may 8, 2002) ? hip7a sami rom compiler , memctc (november 16, 2001) ? hip7a kilobit hd via rom compiler , memctc (june 28, 2002) ? arm926ej-s platform test guide (arm ltd.) MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxx freescale semiconductor ? arm architecture reference manual (arm ltd., order number arm ddi 0100) ? arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) ? arm technical reference manual (arm ltd., order number arm ddi 0151c) ? mc9328mx1 i.mx integrated portable system processor reference manual (order number mc9328mx1rm) ? MCIMX27 multimedia application processor data sheet? (order number MCIMX27)) these manuals can be found at the arm ltd. world wi de web site at http://w ww.arm.com and freescale semiconductors world wide web site at http:/ /www.freescale.com/imx. these documents can be downloaded directly from the world wide web site, or printed versions may be ordered. the world wide web site may also have useful application notes. conventions this reference uses the following conventions: ? overbar is used to indicate a signal that is active when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conve ys or changes in state convey information. ?a pin is an external physical connection. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic level zero to logic level one. ? negated means that an asserted discre te signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic level one to logic level zero. ? lsb means least significant bit or bits, and msb me ans most significant bit or bits. references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are binary. numbers preceded by a 0x are hexadecimal. definitions, acronyms, and abbreviations the following list defines acronyms and abbreviations used in this document. adc analog-to-digital converter afe analog front end api application programming interface bcd binary coded decimal ber bit error ratio cgm clock generation module MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor xxxi cmos complimentary metal-oxide semiconductor crc cyclic redundancy check csic complex instruction set computer dac digital-to-analog converter ddr ram double data rate ram dma direct memory access dram dynamic random access memory dsp digital signal processor fec forward error correction fifo first in first out firi fast ir interface gpio general purpose input/output i/o input/output ice in-circuit emulation irda infrared data association jtag joint test action group map mold array process mapbga mold array process ball grid array mips million instructions per second mmc multimedia card pll phase locked loop pwm pulse-width modulator rtc real-time clock sd secure digital sdram synchronous dynamic random access memory spi serial peripheral interface sram static random access memory tqfp thin quad flat pack uart universal asynchronous receiver/transmitter usb universal serial bus usb otg usb on-the-go xtal crystal be/le big endian/little endian ccm clock control module, also called ?clkctl? module lv low voltage MCIMX27 multimedia applications processor reference manual, rev. 0.2 xxxii freescale semiconductor lwb late-write buffer mctl memory controller ram random access memory rom read only memory r-ahb bus reduced advanced high-performance bus (ahb), related to arm bus architecture sram static ram arm advanced risc machines processor architecture api application programming interface fabrication path path within rom boot strap for fabrication test execution flash path path within rom bootstrap lead ing towards executing a flash application. gpcr global peripheral control registry of the i.mx27. hw hardware iram processor-internal ram irom processor-internal rom nfc nand flash controller nand flash a flash rom technology rom bootstrap internal boot code encompassing main boot flow as well as exception vectors, usb/uart bootloader blocks. ram path path within rom bootstrap lead ing towards downloading and executing a ram application sidr silicon id register of the i.mx27 sync flash a flash rom technology tbd to be determined uart universal asynchronous receiver/transmitter usb universal serial bus v-sync flash a flash rom technology word 32 bits type identifier that distinguishes a production or engineering device. uid unique id; a field in the processor a nd csf identifying a device or group of devices wtls wireless transport layer security, a pa rt of the wireless application protocol MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book i: i.mx27 applications processor integration and description introduction book i comprises detailed descriptions and inform ation on the integration of the i.mx27 multimedia applications processor. book i includes the following chapters. device introduction and memory map chapter 1, ?introduction to the i.mx27 multimedia applications processor ,? on page 1-1 chapter 2, ?system memory and register map ,? on page 2-1 clocks, power management and reset chapter 3, ?clocks, power management, and reset control ,? on page 3-1 pins chapter 4, ?system control ,? on page 4-1 chapter 5, ?signal descriptions and pin assignments ,? on page 5-1 chapter 6, ?general-purpose i/o (gpio) ,? on page 6-1 debug chapter 7, ?jtag controller (jtagc) ,? on page 7-1 boot chapter 8, ?bootstrap mode operation ,? on page 8-1 MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-1 chapter 1 introduction to the i.mx27 multimedia applications processor as part of the i.mx growing family of multimedia- focused products, the i.mx27 multimedia applications processor takes the mobile multimedia experience to another level. whether you are designing mobile entertainment, a smartphone, wireless pda, or any ot her portable device, the i.mx27 processor offers a high degree of integration to significantly reduce your design time while providing low-power consumption with performance to spare, and the flex ibility necessary for today?s competitive marketplace. the i.mx27 processor is packaged in a 404-pin mapbga. differentiating features of the i.mx27 device include: ? advanced and power-efficient implementation of the arm926ej-s? core, operating at speeds up to 400 mhz ? enhanced multimedia accelerator lite (emma_lt) ?mpeg-4 and h.264 hardware encode or decode up to d1 resolution at 30 fps or enc ode and decode up to vga resolution at 24 fps. ? high-speed usb on-the-go controller, host or client ? smart speed crossbar switch?multi-layer amba-c ompliant bus allows any one of the six bus masters to talk to any of the three slaves w ithout interfering with the other bus master/slave transactions to provide system level parallelism. ? pcmcia/compact flash interface?supports hot-insertion, card insert, and removal detection ? security?software and hardware combined securi ty solution allows secure e-commerce, digital rights management (drm), information encrypti on, secure boot, and secure software downloads. ? smart power management?include s run, doze, and sleep modes, frequency scaling, active well biasing and clock gating ? lcd panels?supports both smart and standard lcd panels ? fast ethernet?supports 10/100 baset ethernet mac 1.1 i.mx27 applications processor block diagram figure 1-1 is a simplified functional block diagram of the i.mx27 processor. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-2 freescale semiconductor figure 1-1. i.mx27 processor functional block diagram 1.2 summary of core and modules this section describes the arm926e j-s as it applies to the i.mx27 pr ocessor and the function of the modules within the i.mx27 device. 1.2.1 arm9? platform the arm9? platform consists of the arm926ej-s core, operating at speeds up to 400 mhz at 1.6 v, and 266 mhz at 1.2 v. the arm926ej-s core includes a 16-kbyte level 1 (l1) cache system, a 6 3 multi-layer ahb crossbar switch, and a 16 channel dma. the arm926ej-s is a member of the arm9 family of general-purpose microprocessors targeted at multi-tasking applications. the arm9 pl atform provides the following features: ? arm926ej-s microprocessor core ? 16k instruction cache and 16k data cache ? high-performance arm ? 32-bit risc engine ? thumb ? 16-bit compressed instruction set fo r a leading level of code density connectivity cspi (3) ssi (2) i 2 c (2) wireline uart (6) usb 2.0 1-wire expansion sdhc (3) mshc i.mx27 cpu complex arm926ej-s i-cache d-cache mmu internal control bus control memory control external sdramc eim nfc m3if emma lite video codec system control jtag/etm9 bootstrap crm std system resource gpt (6) pwm wdog srtc gpio sdma human interface lcdc and slcdc fec keypad control multimedia interface csi multimedia accelerator ata pcmcia/cf system security scc sahara2 rtic iim memory interface (smart speed switch) max introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-3 ? efficient execution of java byte codes ? embeddedice? jtag software debug ? 100 % user code binary compatibility with arm7tdmi? ? advanced microcontroller bus architecture (amba?) system-on-chip multi-master bus interface ? support for mixed loads of real-time and user applications via cache locking facilities ? virtual memory management unit (vmmu) ? support for little endian only ? cpu and system speed ? arm926ej-s core: up to 400 mhz ? system clock: up to 133 mhz ? external memory interface: same clock source as system, up to 133 mhz at 1.8 v supply ? system clock is derived from the cpu clock through an integer divider ? arm interrupt controller (aitc) ? the aitc is connected to the primary ahb as a slave device and provides support for up to 64 interrupt sources. it genera tes normal and fast interrupts to the processor core. the aitc supports a hardware-assisted vectoring mode for automatic vectoring to reduce interrupt latency. ? clock control module (clkctl)?the cl kctl performs block level clock gating, arm926ej-s jtag synchronization requirements, as well as other miscellaneous clock control for the platform. ? ahb to ip bus interfaces (aipis)?provide a communication interface between the high-speed ahb to a lower-speed ip bus for slave peripherals ? the multi-layer 6 3 ahb crossbar switch (max)?the crossbar switch allows for concurrent transactions to proceed from any input port (bus ma ster) to any output port (bus slave): that is, it is possible for all three output ports to be active at the same time as a result of three independent input or output requests. ? well bias charge pump (wbcp)?with the exception of the memories, the entire arm9 platform supports two active well biasing to reduce leakage current to minimum levels. the well bias enable inputs (wt_en and wt_en_dnw) are driven by the external well bias charge pump (wbcp) to the arm9 platform. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-4 freescale semiconductor 1.2.2 system control to ensure optimum power use and clock signal stability, the i.mx27 processor uses the following modules to generate, control, and distribute clock and c ontrol signals throughout the i.mx27 processor and to external devices. 1.2.2.1 clock controller module (ccm) the ccm generates clock and reset signals used throughout the i.mx27 device and for external peripherals. it also enables system software to cont rol, customize, or read the status of the following functions: ? chip id ? multiplexing of i/o signals ? i/o driving strength ? i/o pull enable control ? well bias control ? system boot mode selection ? dptc control 1.2.2.2 jtag controller (jtagc) the jtagc provides debug access to the arm926ej-s co re and boundary scan test control. the i.mx27 processor offers designers and programers with full-debug capabilit ies through industry-standard jtag interface and the ability to bootload using either a serial or usb interface. ? uart bootstrap mode function: ? allows system initialization and program or data download to system memory via usb or uart1 ? accepts execution command to run program stored in system memory ? supports memory/register read/write operation of selectable data size of byte, half-word, or word ? provides a 16-byte instruction buffer for arm instruction storage and execution ? usb bootstrap mode function ? supports bootstrapping through usb otg port ? jtag port to support generic arm debug tools 1.2.3 standard system resources the i.mx27 processor contains various timers and resource features to optimize the control and security of both the internal modules and external devices. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-5 1.2.3.1 general purpose timer (gpt) the six general-purpose timer (gpt) modules cont ain identical general-pur pose 32-bit timers with programmable prescalers and compare and capture registers with the following features: ? automatic interrupt generation ? programmable timer input/output pins ? input capture channels capability with programmable trigger edge for each gpt ? output compare channels with programmable mode for each gpt 1.2.3.2 pulse-width modulator (pwm) the pulse-width modulator (pwm) has a 16-bit counter and is optimiz ed to generate sound from stored sample audio images. it also generate tones. the following features characterize the pwm module: ?4 16 fifo to minimize interrupt overhead ? 16-bit resolution ? sound and melody generation 1.2.3.3 real time clock (rtc) the real-time clock (rtc) module maintains the syst em clock, provides stopwatch, alarm, and interrupt functions, and supports the following features: ? 32.768 khz and 32 khz input operation ? full clock features: seconds, minutes, hours, days ? capable of counting up to 512 days ? minute countdown timer with interrupt ? programmable daily alarm with interrupt ? sampling timer with interrupt ? once-per-second, once-per-minute, once- per-hour, and once-per-day interrupts ? interrupt generation for digitiz er sampling or keyboard debouncing ? independent power supply 1.2.3.4 watchdog timer module (wdog) the watchdog timer module (wdog timer) module pr otects against system failures by providing a method for the system to recover from unexpected events or programming errors. the wdog timer module also generates a system reset using a softwa re write to the watchdog control register (wcr), a detection of a clock monitor event, an external reset, an external jtag reset signal, or an occurrence of a power-on reset. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-6 freescale semiconductor the wdog timer provides the following: ? programmable time out of 0.5 s to 64 s ? resolution of 0.5 s 1.2.3.5 general-purpose i/o ports (gpio) the gpio module provides six genera l purpose i/o ports. each single gpio port is a 32-bit port that may be multiplexed with one or more dedi cated functions. the gpio features are: ? supports level or edge trigger interr upt and is system wake-up capable ? most i/o signals are multiplexed with dedicated functions for pin efficiency. 1.2.3.6 direct memory access controller (dmac) the direct memory access controller (dmac) provides 16 channels to support linear memory, 2d memory, fifo, and end-of-burst en able fifo transfers to support a wide variety of dma operations. features include the following: ? supports 16 channels linear memory, 2d memory , and fifo for both source and destination ? supports 8-bit, 16-bit, or 32-bit fifo port size and memory port size data transfer ? dma burst length is configurable up to maximum of 16 words, 32 half-words, or 64 bytes for each channel ? bus utilization control for a channel that is not triggered by dma request ? interrupts that are provided to interrupt handler on bulk data transfer comp lete or transfer error ? dma burst time-out error to terminate dma cycle when the burst cannot be completed in a programmed timing period ? dedicated external dma request and grant signal ? supports increment, decrement, and no increment for source and destination addressing ? supports dma chaining 1.2.4 power management and backup modes the i.mx27 processor?s power management features are as follows: ? supports 3 power modes of operation: run, doze, and stop ? aggressive clock gating within modules to minimize cmos switching power ? active well biasing technique to reduce standby mode current consumption ? voltage/frequency scalable capability ? dynamic process temp erature compensation 1.2.4.1 scc, rtc, and oscillator power supply the i.mx27 processor has a separate power domain from the main power domain for the scc, rtc, and the 32 khz oscillator (osc32k) power supply, so that when the main power domain shuts down, the scc introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-7 internal memory data and status is maintained. also, the rtc and osc32k works as normal using the backup power supply that is provided by power management. 1.2.4.2 enter/exit mode power management provides the power_cut to indicat e the main power cut: 1?main power_cut; 0?main power_on. ? mode enter?when power_cut is set to 1 by the power management chip, then the main power can shut down. ? mode exit?power_cut must be set to 1 when th e main power is not on; after main power_on is restored (after the main power reset ends), power_cut should be set to 0. ? power on initial?in the initial process, power_cut must be set to 0, and por must give a valid 0 slot for the scc, rtc power_on reset. 1.2.4.3 reset strategy the por is active to the rtc and scc. when power_cut is set to 1 (in the backed power mode), then the reset from the chip system will be gated, preventin g any chip reset sources from resetting scc and rtc. when power_cut is set to 0 (not in the backed power mode), then the reset from the chip system will be active to scc and rtc, which means all ch ip reset sources can reset the scc and rtc. 1.2.5 system security to address the need for secure wireless communi cation, the i.mx27 processor provides confidentiality, authentication, integrity, and legitimacy within its arch itecture. this section describes the modules that provide these types of security?the security controller, sahara2, run-time integrity checker, and the ic identification module?whose built-in features s upport a broad range of se curity-enabled products. 1.2.5.1 security controller module (scc) the scc is a hardware component composed of tw o blocks?the secure ram module and the security monitor. the secure ram securely stores sensitive information. the security monitor implements the security policy, checking algorithm sequencing, and c ontrolling the secure state. there is also a unique encryption key accessible only to secure ram. 1.2.5.2 symmetric/asymmetric hashing and random accelerator (sahara2) sahara2 is a security co-processor within the i.mx27 processor used to implement block encryption algorithms, hashing algorithms, stream cipher al gorithms, and hardware random number generation. sahara2 accelerates the following secu rity protocols and their features: ? aes encryption/decryption ? ecb, cbc, ctr, and ccm modes ? 128 bit key ?des/3des introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-8 freescale semiconductor ? ebc, cbc, and ctr modes ? 56 key with parity (des) ? 112 bit or 168 bit key parity (3des) ? ar4 (rc4 compatible cipher) ? 5?16 byte key ? host accessible s-box ? md5, sha-1, sha-224 and sha-256 hashing algorithms ? message lengths are multiples of bytes ? auto padding supported ? hmac (support for ipad and opad via descriptors) ? up to 4-gbyte message length ? random number generator (nist approved prng ? fips 186-2) ? entropy is generated via an inde pendent free running ring oscillator 1.2.5.3 run-time integrity checkers (rtic) the rtic ensures the integrity of the contents of the peripheral memory and assists with boot authentication. the rtic offers the following features: ? sha-1 message authentication ? input dma (amba-ahb lite 1 bus master) interface ? segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) ? works with high assurance boot (hab) process ? secure-scan dft security ? support for up to four independent memory blocks ? programmable dma bus duty cycle timer and watchdog timer ? power-saving clock gating logic ? hardware configurable big/little-endian data format ? full word memory reads (word-aligned addresses, multiple of 32-bit lengths) 1.2.5.4 ic identification module (iim) the ic identification module (iim) provides an interf ace for reading, and in some cases, programming, and for overriding identification and control in formation stored in on-chip fuse elements. 1. ahb-lite interface provides support for request/grant bus arbitration introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-9 1.2.6 connectivity this section describes how the modules within th e i.mx27 processor interface with each other, and provides a high-level overview on how the architectu re of the buses are configured and multiplexed. figure 1-2. i.mx27 connectivity example 1.2.6.1 configurable serial peripheral interfaces (cspi) the i.mx27 processor has three configurable serial pe ripheral interface (cspi) modules that allow rapid data communication with fewer software interrupts th an conventional serial co mmunications. each cspi is equipped with data fifo and is a master/slave configurable serial peripheral interface module, enabling the i.mx27 processor to interface with external spi master or slave devices. ? master/slave configurable ? two chip-selects each for master mode operation external memory interface (emi) esdram nfc m3if pcmcia/cf eim emma_lt video codec h.264 csi ccir656 camera slcdc smart lcdc dumb displays display keypad ata fec ethernet audmux bluetooth audio ssi voice ssi bluetooth secure sd mshc memory stick pro 1-wire serial usb host 1 usb host 2 uart4 uart5 uart6 uart3 uart2 uart1 i 2 c cpu etb ssi1 ssi2 sahara2 scc digital i.mx27 dmac linear fifo 2d crm eeprom hard drive ide ata p i memory human interface security multimedia external connectivity internal connectivity cspi1 cspi2 usb otg ro m pat c h etm jtagc max iim rtic mpeg-4 rs-232 irda gps irda irda memory expansion kpp irda i 2 c introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-10 freescale semiconductor ? up to 16-bit programmable data transfer ?8 16 fifo for both transmit and receive data 1.2.6.2 inter-ic connectivity (i 2 c) bus module the two i 2 c modules are two-wire, bidirectional serial bus es that provide a simple, efficient method of data exchange, minimizing the interconnection between de vices. these buses are suitable for applications requiring occasional communications over a short dist ance between several devices. the flexible i 2 c allows additional devices to be connected to the bus for expansion and system development. the i 2 c features include: ? multiple-master operation ? software-programmable for 1 of 64 different serial clock frequencies ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? start and stop signal generation and detection ? repeated start signal generation ? acknowledge bit generation and detection ? bus-busy detection 1.2.6.3 synchronous serial interface (ssi) the two synchronous serial interfaces are full-duplex , serial ports that enable the i.mx27 device to communicate with a variety of serial devices, such as standard codecs, digital signal processors (dsps), microprocessors, peripherals, and popular industry audi o codecs that implement the inter-ic sound bus standard (i 2 s) and intel ac97 standard. features include the following: ? supports generic ssi interface for timeslot based communication with synchronous voice codecs ? timeslot mode supports up to four channels for communication among devices, bluetooth? voice port, voice codecs, and baseband audio ports. ? supports philips standard inter-ic sound (i 2 s) bus for external digital audio chip interface at 44.1 khz and 48 khz ? ac97 host controller mode with support for two audio channels supporting fi xed and variable rate transfers ? used together with the digital audio mux (audmux) module to provide flexible audio and voice routing options 1.2.6.4 bus control the six modules that control the bus in the mx27 are li sted here. this section pr ovides a brief description for each. ? ahb-lite ip interface module (aipi) introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-11 ? arm926ej-s interrupt controller (aitc) ? intellectual property bus multiplexer (ipmux) ? multi-layer ahb crossbar switch (max) 1.2.6.4.1 ahb-lite ip interface module (aipi) the aipi acts as an interface between the arm advanced high-performance bus lite. (ahb-lite) and lower bandwidth peripherals that conform to the ip bus specification, rev 2.0 . 1.2.6.4.2 arm926ej-s interrupt controller (aitc) aitc is connected to the primary ahb as a slave devi ce. it generates the normal and fast interrupts to the arm926ej-s processor. 1.2.6.4.3 intellectual property bus multiplexer (ipmux) the intellectual property bus multiplexer (ipmux) is used to select the read data, transfer wait, and transfer error signals from the various modules a nd pass it to the aipi in the arm9 platform. 1.2.6.4.4 multi-layer ahb crossbar switch (max) the arm926ej-s core?s instruction and data buses and all alternate bus master interfaces arbitrate for resources via a 6 3 multi-layer ahb crossbar switch (m ax)?also known as a smart speed switch. there are six fully functional master ports (m0?m5) and three fully functional slave ports (s0?s2). the max is uni-directional. all master and slave ports are ahb-lite compliant. 1.2.7 wireline connectivity the i.mx27 device provides a variety of external wire line connectivity. this section describes the modules for this support. 1.2.7.1 universal asynchronous receiver/transmitter (uart) the i.mx27 processor includes six universal asynchr onous receiver/transmitter (uart) modules that provide serial communication with external devi ces through either an rs-232 cable or by using irda-compatible infrared. each of the six uarts features the following: ? supports serial data transmit/recei ve operation: 7 or 8 data bits , 1 or 2 stop bits, programmable parity (even, odd, or none) ? programmable baud rates up to 1.875 mhz ? automatic baud rate detection ? 32-bytes fifo for transmit and 32 half-words fifo for receive data ? irda serial infra-red (sir) mode support introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-12 freescale semiconductor 1.2.7.2 high speed usb 2.0 interface (usb) the i.mx27 processor supports three independent us b 2.0 ports, two of which support high speed (hs) operation: ? otg?high speed (480 mbps) ? host 1?high speed (480 mbps) ? host 2?full speed (12 mbps) the usb connectivity of the i.mx27 processor provide s extremely fast synchronization with a pc or between two devices. any of the usb ports may be us ed for transceiver-free connection or for external transceiver-based connection. the usb otg port can connect to a pc as either a de vice or as a host to any of the following peripherals: keyboard, printer, mouse, speakers, storage device, digital camera, and so on. it supports 16 endpoints for each host and device. usb host 1 is typically connected to dedicated ic s that support wlan, bluetooth? wireless technology, and gps. host 1 supports 16 endpoints. usb host 2 is typically used to connect to ics for baseband or wlan, bluetooth wireless technology, or gps. host 2 supports four endpoints. 1.2.7.3 1-wire interface (1-wire) the 1-wire ? module provides bi-directional communication between the arm926ej-s and the add-only-memory eprom (ds2502). the 1-kbit eprom is used to hold information about the battery and to communicate with the arm9 platform using the ip interface. 1.2.7.4 advanced technology attachment (ata) the advanced technology attachment (ata) block of the i.mx27 processor is an at attachment host interface and is used to interface with ide hard disk drives and atapi optical disk drives. this feature allows designers to attach storage devices at low costs per unit, which is a critical selling point in the portable digital player market. the ata controller inte rfaces with ata devices using the industry-standard ata-6 specification. the ata interface is compliant to the ata-6 standard, and supports following protocols: ? pio mode 0, 1, 2, 3, and 4 ? multiword dma mode 0, 1, and 2 ? ultra dma modes 0, 1, 2, 3, and 4 with bus clock of 50 mhz or higher ? ultra dma modes 5 with bus clock of 80 mhz or higher 1.2.7.5 fast ethernet controller (fec) the fast ethernet controller (fec) performs the full set of ieee 802.3/ethernet csma/cd media access control and channel interface f unctions. the fec supports connecti on and functionality for the 10/100 introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-13 mbps 802.3 media independent interface (mii). it require s an external transceiver (phy) to complete the interface to the media. the fec provides the following features: ? supports three different ethernet physical interfaces: ? 100 mbps ieee 802.3 mii ? 10 mbps ieee 802.3 mii ? 10 mbps 7-wire interface (industry standard) ? ieee 802.3 full-duplex flow control ? programmable maximum frame length supports ieee 802.1 vlan tags and priority ? supports full-duplex operation (200 mbps throughput) with a minimum system clock rate of 50 mhz ? supports half-duplex operation (100 mbps throughput ) with a minimum system clock rate of 25 mhz ? retransmission from transmit fifo following a collision (no processor bus utilization) ? automatic internal flushing of the receive fifo for runts (collision fragments) and address recognition rejects (no processor bus utilization) ? address recognition ? frames with broadcast a ddress may be always accepted or always rejected ? exact match for single 48-bit individual (unicast) address ? hash (64-bit hash) check of individual (unicast) addresses ? hash (64-bit hash) check of group (multicast) addresses ? promiscuous mode 1.2.8 external memory interface the external memory interface (emi) of the i.mx 27 processor consists of the sdram controller (sdramc), the pcmcia controller, the nand flas h controller (nfc), and the external interface module (eim), using the multi-master memory interface (m3if) as the controller through the external memory ports. the individual features of thes e controllers are provided in this section. to allow the maximum number of potential designs, the emi supports the following memory types: ? sdram?133 mhz, 32/16-bit ? ddr?266 mhz, 32/16-bit ? nand flash?dedicated 8-bit, shared 16-bit ?psram 1.2.8.1 multi-master memory interface (m3if) the multi-master memory interface (m3if) controls memory accesses from one or more masters through different port interfaces to the external memory controllers sdram, pcmcia, nand flash, and eim. the m3if includes these distinctive features: ? supports multiple requests from masters through input port interfaces introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-14 freescale semiconductor ? arbitrates requests to the different memory controllers ? multiple requests capabilities to sdramc through a dedicated arbitration mechanism ? flexible round robin access arbitration, with a pr ogrammable priority scheme to selective masters ? programmable master that controls (locks) ac cesses to sdram/ddr, a nd a programmable master that controls (locks) accesses to other memories (nfc, eim) ? multi-endianness support for all memory controllers ? supports memory ?snooping??that is, monitors a region in external memory for write accesses 1.2.8.2 sdram controller (sdramc) the sdram controller (sdramc) pr ovides an interface and control for synchronous dram memories for the system. the sdramc supports the following: ? optimization of consecutive memory accesse s using memory command anticipation (latency hiding) ? hiding latency (or ?command anticipation?) by optimizing the commands to both connected chip-selects ? monitoring open memory pages ? bank-wise memory address mapping ? sdram burst length configuration of 4 1 or 8 bursts or full-page mode ? mddr burst length configuration of 8 bursts ? support of different internal burst length (1/4/8 words) by using burst truncate commands ? arm/amba/ahb-lite compliant ? shared address and command bus to sdram/mddr ? supports 64, 128, 256, 512 mbit, 1 gbit, and 2 gbit, 4 bank, single data rate, synchronous sdram, and mddr ? two independent chip-selects ? up to 128 mbytes per chip-select ? up to four banks active simultaneously per chip-select ? jedec standard pinout/operation ? supports mobile ddr266 devices (both 16-bit and 32-bit) ? pc133 compliant interface ? 133-mhz system clock achievable with ??7? option pc133 compliant memories ? single fixed-length (4/8-word) burst or full page access ? access time of 9-1-1-1-1-1-1-1 at 133 mhz (for re ad access when the memory bus is available, the row is open and cas latency configured to three cycles). the access time includes the m3if delay (assuming there is no arbitration penalty). ? software configurable for different system and memory devices requirements ? 16-bit or 32-bit memory data bus width 1. for 16-bit memory burst length 4 is not supported. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-15 ? many row and column addresses ? row cycle delay (trc) ? row precharge delay (trp) ? row-to-column delay (trcd) ? column-to-data delay (cas latency) ? load mode register to active command (tmrd) ? write to precharge (twr) ? write to read (twtr) for mddr memories only ? mddr exit power down to next valid command delay (txs) ? active to precharge (tras) ? active to active (trrd) ? built-in auto-refresh timer and state machine ? hardware and software supported self-refresh entry and exit ? keeps data valid during system reset and low-power modes ? auto power down timer (one per chip-select) ? auto precharge timer (one per bank in each chip-select) 1.2.8.3 nand flash controller (nfc) the nand flash controller (nfc) interfaces standard nand flash memory devices to the i.mx27 processor and hides the complexities of a ccessing nand flash. the nfc features include: ? contains hardware boot loader for automatic boot up from nand flash devices ? supports all 8-bit/16-bit nand flash device s regardless of density and organization ? supports 512-byte and 2-kbyte page sizes ? internal 2 kbytes of buffer ram used as boot ra m during cold startup and as read/write page buffers to relieve cpu intervention ? automatic ecc detection and selectable correction ? data protection for ram buffer and nand flash pages 1.2.8.4 personal computer memory card international association (pcmcia) the pcmcia host adapter module provides the control logic for pcmcia socket interfaces, and requires some additional external analog power switching logic and buffering. the pcmcia controller provides the following features: ? a host adapter interface fully compliant with the pcmcia standard release 2.1 (pc card -16) ? supports one pcmcia socket ? supports hot-insertion ? supports card detection introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-16 freescale semiconductor ? mappings to common memory space, attribute memo ry space, and i/o space. each space is up to 64 mbytes in size. ? supports five memory windows ? generates a single interrupt to the cpu ? pc card access timing is fully programmable ? handles interrupts from the card ? the pcmcia_if signal is part of the emi complex and shares pins with the eim, sdramc, and nfc controller. ? supports ata disk emulation 1.2.8.5 external interface module (eim) the external interface module (eim) interfaces to de vices external to the chip, including generation of chip-selects, clock and control for external peri pherals, and memory. the ei m provides asynchronous and synchronous access to devices with an sram-like interface. the eim includes the following features: ? six chip-selects for external devices, with cs [0] and cs [1] each covering a range of 128 mbytes, and cs [2] ? cs [5], each covering a range of 32 mbytes ?cs [0] range can be increased to 256 mbytes when collapsed with cs [1] ? selectable protection for each chip-select ? programmable data port size for each chip-select ? asynchronous accesses with programmable setup and hold times for control signals ? synchronous memory burst read mode support fo r amd, intel, and micron burst flash memory ? synchronous memory burst write m ode support for psram (cellularram tm from micron, infineon, and cypress) ? support for multiplexed a ddress/data bus operation ? external cycle termination/postpone with dtack signal ? programmable wait-state generator for each chip-select ? support for big endian and little endian modes of operation per access ? arm ahb slave interface 1.2.9 memory expansion the i.mx27 processor offers memory expa nsion options for sd, memory stick pro ? , and ata-6. each expansion port reflects the latest version of the respective specification for that interface. brief descriptions of each expansion port follow. 1.2.9.1 memory stick host controller (mshc) the i.mx27 processor?s memory stick host controll er supports one memory stick pro slot. the mshc conforms to memory stick standard format specifications, ver.1.4-00 and memory stick standard introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-17 memory stick pro format specification, ver.1.00-01. the mshc communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. in addition to multimedia cards, the module can be used to communicate to high-bit rate communication devices, such as wlan 802.11 a/b, and bluetooth wireless technology, among others. the mshc is placed between the aipi and the customer memory stick to support data transfer from th e i.mx27 device to the customer memory stick. 1.2.9.2 secured digital host controller (sdhc) the three secured digital host controllers (sdhc) in the i.mx27 device control the secure digital memory cards and i/o functions by sending commands to the cards and performing data accesses to and from the cards. sdhc features include: ? fully compatible with the sd memory card specification 1.0 and sd i/o specification 1.0 with 1 and 4 channel(s) ? supports hot swappable operation ? data rates from 25 mbps to 100 mbps ? dedicated power pin 1.2.10 video codec and enhanced multimedia accelerator lite (emma_lt) the i.mx27 processor uses a video codec and an enhanced multimedia accelerator lite (emma_lt) to provide h.264, mpeg-4 and h.263 hardware a cceleration with pre- and post-processing. 1.2.10.1 video codec the video codec module supports full-duplex video codec with mpeg-4 and h.264 hardware encode or decode up to d1 resolution at 30 fps or encode and decode up to vga resolution at 24 fps, and integrates multiple video processing standards, such as h.264 bp, mpeg-4 sp, and h.263 p3. the video codec architecture is shown in the figure 1-3 . introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-18 freescale semiconductor figure 1-3. video codec architecture diagram the video codec provides the following capabilities: ? multi-standard video codec ? mpeg-4 part-ii simple prof ile (sp) encoding/decoding ? h.264/avc baseline profile (bp) encoding/decoding ? h.263 p3 encoding/decoding ? multi-party call: one stream encoding and two streams decoding simultaneously ? multi-format: encodes mpeg-4 bitstream, and decodes h.264 bitstream simultaneously ? coding tools ? high-performance motion estimation (single reference frame for both mpeg-4 and h.264 encoding) ? quarter-pel and half-pel accuracy motion estimation ?[ 16, 16] search range ? all variable block sizes are supported. (in case of encoding, 8 4, 4 8, and 4 4 block sizes are not supported.) ? unrestricted motion vector ? mpeg-4 ac/dc prediction and intra-prediction (h.264) ? h.264/avc intra-prediction axi to ahb bus video processing ip memory bist engine memories block apb to ip bus read channel 1 and 2 logic write channel logic 32to64 gasket emi internal sram aipi crm te s t interrupt signal signal ahb64_sel clock and reset 64bit 64bit 64bit 32 bit axi 32bit introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-19 ? h.263 annex i, j, k, and t are supported ? error resilience tools ? mpeg-4 resync. marker and data-partitioning with rvlc (fixed number of bits/macroblocks between macroblocks) ? h.264/avc fmo and aso ? h.263 slice structured mode ? bit-rate control (cbr and vbr) ? pre/post rotation/mirroring ? 8 rotation/mirroring modes for image to be encoded ? 8 rotation/mirroring modes fo r image to be displayed ? programmability ? embeds c and m proprietary 16-bi t dsp processor that is dedi cated to processing bitstream and driving the codec hardware ? general purpose registers and interrupt for co mmunication between internal host processor and video codec ip ? performance ? up to full-duplex vga 24 fps encoding/decoding ? up to half-duplex sd 30 fps encoding/decoding 1.2.10.2 enhanced multimedia accelerator lite (emma_lt) the i.mx27 processor comes with an enhanced multimedia accelerator lite (emma_lt), which comprises independent pre-proce ssing and post-processing stages th at provide exceptional image and video quality. the emma_lt represents a major breakt hrough to solve the problem of high mips required for video encode and decode operati ons in mobile and wireless applica tions. tight integration and memory pipelining coupled with ahb master mode operation ensure minimal system loading. to further offload the cpu, live video stream data enters the emma_lt module directly through an internal private data interface. the i.mx27 processor?s emma_lt features the following: ? enables simultaneous mpeg-4 simple profile (sp) video encoding and decoding ? supports real-time video decode in a ny of the following advanced formats: ? mpeg-4 simple profile (sp) ? h.264 ? provides video and image data pre/post-processing (resizing, color conversion, filtering) that is fully hardware accelerated the emma_lt architecture is shown in figure 1-4 . introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-20 freescale semiconductor figure 1-4. emma_lt architecture 1.2.10.2.1 image pre-processor (prp) the image pre-processor block performs color space conversion and image resizing for the viewfinder display, and data formatting for the video encoder. it also performs color space conversions of the still image for input to either a hardware- or softwa re-based video encoder or image compressor. the pre-processor has two media input and output paths a nd can accept input from system memory or from a private data bus connected to the cmos sensor in terface (csi) module. the pre-processor can apply frame rate control on the live video stream from th e csi module to adjust for different processing load conditions. the pre-processor?s two output channels are used to output rgb data for display of the local camera view and to output image data for compression by the hardware encoder or a software encoder (still image or video encode). figure 1-5 shows the image pre-processor. figure 1-5. pre-processor data flow pre-processor features: ? data input: ? system memory ? private dma between cmos sensor interface module and pre-processor ip bus interface bus arbitration ip bus ahb bus post processing pre- processing sensor data from csi frame buffer (rgb/yuv) cmos sensor rgb display buffer pre-processor interface yuv 4:2:2,4:2:0, optional data paths using dumb cmos sensors viewfinder compression system memory color space resize conversion 4:4:4 or video encode resize main second introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-21 ? data input formats: ? arbitrarily unpacked rgb input ? yuv 4:2:2 (interleaved) ? yuv 4:2:0 (planar) ? input image size: 2044 2044 ? image scaling: ? main resize ratio: 8:1?1:1 in integral steps, horizontal 9:8/vertical 6:5 and horizontal 9:8/vertical 1:1 ? secondary resize ratio for viewfinder: 8:1 ? 1:1 in integral steps ? output data format: ? rgb565 ? yuv 4:2:2 (interleaved) ? yuv 4:2:0 (planar) ? rgb data and one yuv data form at can be generated concurrently 1.2.10.2.2 post-processor (pp) the post-processor performs deblock, dering, imag e resize, and color space conversion (csc) functions on the input image data. these functions provide flexibility to meet various rgb formats and yuv formats for display. in addition to working in tandem with the decoder s ub-block in the emma_lt, the post-processor can also be used by software decoders (other than mpeg-4) to touch up the final output before display. the sub-blocks that perform deblock, dering, resize, and csc operations can be selectively bypassed through software configuration. figure 1-6 shows the flow for video postprocessing. figure 1-6. post-processor post-processor features: ? input data: ? from system memory ? input format: ? yuv 4:2:0 (planar) ? output format: ? yuv422 current/ ref frame current/ ref frame deblock dering image color resize conversion rgb display buffer post-processor mpeg-4 decoder introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-22 freescale semiconductor ? rgb444 ? rgb565 ? rgb666 ? rgb888 (unpacked) ? input size: maximum size of 2044 2044 ? image resize: ? upscaling ratios ranging from 1:1 to 1:4 in fractional steps ? downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 ? ratios provide scaling between qcif, cif, qvga (320 240) and qvga (240 320) 1.2.10.3 digital audio multiplexer (audmux) the digital audio multiplexer (aud mux) provides a programmable inte rconnect fabric for voice, audio, and synchronous data routing between the i.mx27 proc essor?s ssi modules and external ssi, audio, and voice codecs. the audmux is designed so that resource configurations do not need to be hard-wired, but instead, can be shared in many different configur ations. the audmux interconnections allow multiple simultaneous separate audio/voice/dat a flows between the ports in a point-to-point or point-to-multipoint configuration(s). in a typical scenario, the audmux and two ssi/i 2 s modules provide interfaces to the serial audio port of the cellular baseband (bb), narrowband (nb), and wideband (wb) audio ports of the external audio ad/da, and to the audio port of the bluetooth wireless technology on-board peripheral. see figure 1-7 . figure 1-7. typical audmux application wb nb bb i.mx31/i.mx31l mp3 baseband ic voice bluetooth tm ic voice adc/dac audio adc/dac voice voice codec audmux option stereo dac blue tooth ssi1 port 1 port 2 port 3 io mux port 4 (external) port 5 (external) port 6 (external) port 7 (external) port 4 (external) port 5 (external) port 6 (external) port 7 (external) power management ic voice call alert tone port 4 (external) port 5 (external) port 6 (external) port 7 (external) port 4 (external) port 5 (external) port 6 (external) port 4 (external) port 7 (external) port 5 (external) port 6 (external) port 4 (external) ssi2 sap i.mx31/i.mx31l voice notes i.mx27 mp3 i.mx27 voice notes introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-23 1.2.11 multimedia interface the cmos sensor interface (csi) provides multimedia interfacing. 1.2.11.1 cmos sensor interface (csi) the cmos sensor interface (csi) is a logic interface that enables the i.mx27 device to connect directly to external cmos sensors and a ccir656 video source. the sensor port provides a connection to either one or two image sensors, of which only one sensor can be active at any given time. the sensor port supports a di rect parallel interface to either cmos or ccd sensor controllers using a parallel interface with widths of 12 bits, 10 bits, 8 bits, or 4 bits at data bus rates up to 60 mhz. the sensor port may be configured to pe rform outputs of a still image to a non-contiguous memory buffer, enabling efficient memory use under an open os. the capabilities of the csi include: ? configurable interface logic to support common available cmos sensors in the market ? support traditional sensor timing interface ? support ccir656 video interface, progressive mode for smart sensor, interlace mode for pal and ntsc input ? 8-bit input port for ycc, yuv, bayer, or rgb data ?32 32 fifo storing image da ta supporting core data read and dma data burst transfer to system memory ? full control of 8-bit and 16-bi t data to 32-bit fifo packing ? direct interface to the emma_lt pre-processing block (prp) ? single interrupt source to the interrupt controller from maskable sensor interrupt sources: start of frame, end of frame, change of field, fifo full ? configurable master clock frequency output to sensor ? asynchronous input logic design. sensor master clock can be driven by either the i.mx27 processor or by an external clock source. ? statistic data generation for auto exposure (ae) and auto white balance (awb) control of the camera (for bayer data only) 1.2.12 human interface the i.mx27 processor can connect to a wide variety of popular display devices, such as: ? ram-less lcd panels?up to 40 mpix/s (for example, svga @ 80 fps), 262k colors. results are dependent on end application. ? lcd panels with integrated frame buffer?up to 1024 1024, 14m colors. results are dependent on end application. ? graphics accelerators ? tv encoders introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-24 freescale semiconductor the i.mx27 processor?s display ports enable simulta neous connectivity of up to two displays?an lcd without memory and a tv encoder?as well as provides connectivity to three interface types: ? synchronous parallel (18-bit) ? asynchronous parallel (18-bit) ? asynchronous serial (spi-like) at a bus rate of up to 100 mhz 1.2.12.1 liquid crystal display controller (lcdc) the liquid crystal display controller (lcdc) provides di splay data for external gray-scale or color lcd panels. the lcdc features include the following: ? software programmable screen size (up to 800 600) to support single (non-split) monochrome, color stn panels, and color tft panels ? support for color depth for cstn panels: 4- or 8-bit mapping from 256 18 table, 12-bit true color ? support for color depth for tft panels: 4- or 8-bit mapping from 256 18 table, 16-bit/18-bit/24-bit true color ? up to 16 grey levels out of 16 palettes ? capable of directly driving popular lcd driver s from manufacturers including motorola, sharp, hitachi, and toshiba ? support for data bus width of 16-bit or 18-bit tft panels ? support for the auo panel in 16 bpp and 24 bpp pixel modes ? support for data bus widths of 8-bit, 4-b it, 2-bit, and 1-bit monochrome lcd panels ? direct interface to sharp ? 320 240 and 240 320 hr-tft panels and other generic panels ? support for logical operation between color hardware cursor and background ? lcd contrast control using 8-bit pwm ? support for self-refresh lcd modules ? hardware panning (soft horizontal scrolling) ? windowing support for one graphic or text overlay 1.2.12.2 smart liquid crystal display controller (slcdc) the smart liquid crystal display controller (slcdc) transparently and efficiently transfers image data from system memory to an external lcd controller. the slcdc module contains a dma controller that transfers image and control data from system memory to the slcdc fifo, where it is formatted and sent out to the external lcd controller. the slcdc can be configured to writ e image data to an external lcd controller via a 4-line serial, 3-line serial, or 8- or 16-bit pa rallel interface. the slcdc has two fifos where command and display data are loaded via dma. the display data is tagged with commands that are used by the slcdc to communicate display information and data to the smart lcd panel. the command tagged data format of the slcdc provid es flexibility and ease of connection to existing and new smart lcd panels. introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1-25 1.2.12.3 keypad port (kpp) the keypad port (kpp) is used for key pad matrix sc anning or as a general pur pose i/o. this peripheral simplifies the software task of sca nning a keypad matrix. features include: ? up to 8 8 external key pad matrix support ? open drain design ? glitch suppression circuit prev ents erroneous key detection ? multiple keys detection ? standby key press detection 1.2.13 packaging information the i.mx27 processor is offered in the 404 mapbga package option. this package brings out all the new interfaces, and supplies more flexible multiplexing. ? type: 0.65 mm pitch ? dimensions: 17 mm 17 mm ? balls: 404 introduction to the i.mx27 multimedia applications processor MCIMX27 multimedia applications processor reference manual, rev. 0.2 1-26 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-1 chapter 2 system memory and register map 2.1 introduction this chapter provides the i.mx27 multimedia applications processor?s memory maps and chip configuration registers. 2.2 memory space the i.mx27 multimedia applications processor, with a 32-bit address bus, is capable of addressing a 4-gbyte physical address space. this space is divide d into sections of 512-mbyte regions within which various memories and peripherals are mapped. table 2-1 shows a simplified breakdown of the eight 512- mbyte regions decoded within the 4-gbyte address space. 2.2.1 detailed memory map figure 2-2 shows the memory space breakout view for the i.mx27 processor. the left-most column shows the eight 512-mbyte regions. the middle column s hows the breakout of primary and secondary ahb slaves, and the right-most column shows the br eakout of the aipi1 and aipi2 address spaces. table 2-2 through table 2-5 show the detailed breakdown of the co mplete memory map according to the 512-mbyte regions. table 2-6 and table 2-7 show the detailed breakdown of the aipi1 and aipi2 modules and the different ip peripherals accessed over the aipi1 and aipi2. table 2-1. 4 gbyte memory map breakdown address size usage 0x0000_0000 512 mbyte rom, primary ahb slaves, and peripherals 0x2000_0000 512 mbyte reserved 0x4000_0000 512 mbyte reserved 0x6000_0000 512 mbyte reserved 0x8000_0000 512 mbyte secondary ahb slave port 1 0xa000_0000 1 gbyte secondary ahb slave port 2 0xe000_0000 512 mbyte primary ahb (ram) system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-2 freescale semiconductor figure 2-1. detailed block diagram for the i.mx27 processor nand flash nor-flash sdram (sdr and ddr) emi 0 1 2 3 4 5 6 7 pcmcia/cf nfc weim wb audio voice bt ce ssi 1 gpio kpp 8x8 keypad mu pulse width mod. in/out owire i2c1 wdog wdog interrupt camera iim scc, crm, sahara2 uart 6 ipc mu scc crm rtc ram iim slid mcu m2 internal memory 45 kbyte ram 24 kbyte rom cspi 1 mu gpio pwm ssi 2 csi cspi 2 mu gpt 1 gpt 2 gpt 3 gpt 3 gpt 4 cspi 3 mu jtagc mu mu mu srouter tcu mpll audmux 210 mshc mmc/sd card memory stick ms/pro 10/100baset phy lcd display 1 lcd display 2 abcd uart1 irda/wlan bb + rf uart2 irda uart3 irda i.mx27 uart4 irda mu battery ctl mu sdhc1 mmc/sd card uart 5 irda mu mu mu mu ip bus 1 ip bus 2 mu sdhc3 mmc/sd card arm926ej-s rompatch 6x3 max mctl aipi 1 aipi 2 pahbmux etm9 aitc m0 m1 m2 m3 m4 m5 s0 s1 s2 to crm i-ahb d-ahb etm i-ahb patch d-ahb patch etb arm926 platform primary ahb clkctl jtag sync ip bus jam ip bus ip bus spll osc32k osc26m arm926ej-s platform esdctl pcmcia m3if [12,13] [7] [11] [3] [6] [5] [2] [1] [4] [1] [22] [17] [16] [9] [14] [15] [23] [21] [2] [24] [18] [6] [8] [19] [20] [30] sdhc2 [7] [10] [11] [12] [13] [27] [28] [3] [5] [4] [25] ata hard drive mu d-$ i-$ usb2.0 [8] gpt 5 mu [26] usb ctl i2c2 mu [29] gpt 6 mu [31] color legend mcu memory- mapped module other modules like test, plls or memories (all sizes in kbyte) dma legend module without dma module with internal dma module with dma-req to dma module with internal dma and dma-req to dma pad-mux legend mux functional pad muxing with other peripherals in some modes video codec [10] rtic sahara2 dma tmax slcdc ipmux ipmux tmax emma_lt lcdc 64-bit tmax tmax fec system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-3 note accesses to locations defi ned as reserved (other than aliased ram space) result in an ahb error response. accesses to unimplemented locations within the aitc register spaces will be terminated, write accesses will have no effect, and read accesses will return all zeros. table 2-2 shows the memory map of the primary ahb address space in the first 512-mbyte region. table 2-3 shows the memory map of the csi and ata modules when connected to the secondary ahb ports 1 via the abcd. the brom (hole) is split into two sections of 16 kbytes and 8 kbytes. the brom (hole) indicates that there is no brom code presen t in this region. the aipi1 and aipi2 address space contains aipi control registers and the ip slave registers. the aipi1 and aipi2 maps are shown in table 2-6 and table 2-7 , respectively. figure 2-2 shows the i.mx27 processor?s physical memory map (4 gbytes). table 2-2. primary ahb memory map (lower) address secondary ahb slave port 1 size 0x0000_0000?0x0000_3fff brom 16 kbyte 0x0000_4000?0x0040_3fff reserved 4 mbyte 0x0040_4000?0x0040_5fff brom 8 kbyte 0x0040_6000? 0x007f_ffff brom (hole) 3 mbyte + 1000 kbyte 0x0080_0000?0x0fff_ffff reserved 248 mbyte 0x1000_0000?0x1001_ffff aipi1 128 kbyte 0x1002_0000?0x1003_ffff aipi2 128 kbyte 0x1004_0000?0x1004_0fff aitc 4 kbyte 0x1004_1000? 0x1004_1fff rom patch 4 kbyte 0x1004_2000?0x7fff_ffff reserved 255 mbyte + 752 kbyte table 2-3. secondary ahb port 1 memory map address secondary ahb port 1 size 0x8000_0000?0x8000_0fff csi 4 kbyte 0x8000_1000?0x8000_1fff ata 4 kbyte 0x8000_2000?0x9fff_ffff reserved 512 mbyte?8 kbyte system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-4 freescale semiconductor figure 2-2. i.mx27 processor?s physical memory map (4 gbytes) vram (45 kbyte) rom patch aitc reserved 36 k 72 k byte 20 k byte aipi2 reserved reserved external memory reserved (960 mbyte) reserved emi (20 kbyte) csi (4kb) reserved ata(4kb) pcmcia/cf emi modules 5x4 kbyte reserved 0x7fff ffff 0x1004 2000 1536 mb 256 mbyte - 280 kbyte 0x1fff ffff 0x2000 0000 internal registers cs5 (spare) active low cs5 (spare) active low cs4 (spare) active low gpt6 sdhc3 i2c2 uart6 uart5 gpt5 gpt4 mshc cspi3 audmux gpio sdhc2 sdhc1 i2c1 ssi2 ssi1 cspi2 cspi1 uart4 uart3 uart2 uart1 owire kpp rtc pwm gpt3 0x0000 0000 0xa000 0000 base address 0xa000 0000 0x0080 0000 0xafff ffff 0x0000 3fff 0x1002 0000 0x1003 1fff 0x007f ffff 0x0040 4000 0x1000 0000 0x1004 1fff 0x0fff ffff 0x9fff ffff 0x8000 0000 0xe000 0000 0xffef ffff 0x1000 0000 0x1000 0fff 0x1000 1000 0x1000 1fff 0x1000 2000 0x1000 2fff 0x1000 3000 0x1000 3fff 0x1000 4000 0x1000 4fff 0x1000 5000 0x1000 5fff 0x1000 6000 0x1000 6fff 0x1000 7000 0x1000 7fff 0x1000 8000 0x1000 8fff 0x1000 9000 0x1000 9fff 0x1000 a000 0x1000 afff 0x1000 b000 0x1000 bfff 0x1000 c000 0x1000 cfff 0x1000 d000 0x1000 dfff 0x1000 e000 0x1000 efff 0x1000 f000 0x1000 ffff 0x1002 0000 0x1002 0fff 0x1002 1000 0x1002 1fff 0x1002 2000 0x1002 2fff 0x1002 3000 0x1002 3fff 0x1002 4000 0x1002 4fff 0x1002 5000 0x1002 5fff 0x1002 6000 0x1002 6fff 0x1002 7000 0x1002 7fff 0x1002 8000 0x1002 8fff 0x1002 9000 0x1002 9fff 0x1002 d000 0x1002 dfff 0x1002 e000 0x1002 efff 0x1002 f000 0x1002 ffff 16 kbyte 0x1004 1000 0x1004 1fff 0xb000 0000 0xbfff ffff 0xc000 0000 0xc7ff ffff 0xc800 0000 0xcfff ffff 0xd000 0000 0xd1ff ffff 0xd200 0000 0xd3ff ffff 0xd400 0000 0xd5ff ffff 0xd600 0000 0xd7ff ffff 4 mbyte 248 mbyte 4 mbyte - 16 kbyte 264 kbyte 512 mbyte 128 kbyte 128 kbyte 4 kbyte 0x0040 3fff 0x0000 4000 max jam etb ram etb ram etb regs reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x1003 0000 0x1003 0fff 0x1003 1000 0x1003 1fff 0x1003 2000 0x1003 2fff 0x1003 3000 0x1003 3fff 0x1003 4000 0x1003 4fff 0x1003 5000 0x1003 5fff 0x1003 6000 0x1003 6fff 0x1003 7000 0x1003 7fff 0x1003 8000 0x1003 8fff 0x1003 9000 0x1003 9fff 0x1003 a000 0x1003 afff 0x1003 b000 0x1003 bfff 0x1003 c000 0x1003 cfff 0x1003 d000 0x1003 dfff 0x1003 e000 0x1003 efff 0x1003 f000 0x1003 ffff reserved reserved scc scc fec rtic reserved iim crm 0x1001 0000 0x1001 0fff 0x1001 1000 0x1001 1fff 0x1001 2000 0x1001 2fff 0x1001 3000 0x1001 3fff 0x1001 4000 0x1001 4fff 0x1001 5000 0x1001 5fff 0x1001 6000 0x1001 6fff 0x1001 7000 0x1001 7fff 0x1001 8000 0x1001 8fff 0x1001 9000 0x1001 9fff 0x1001 a000 0x1001 afff 0x1001 b000 0x1001 bfff 0x1001 c000 0x1001 cfff 0x1001 d000 0x1001 dfff 0x1001 e000 0x1001 efff 0x1001 f000 0x1001 ffff 0x1004 0000 0x1004 0fff gpt2 gpt1 wdog dma aipi1 emma_lt cs3 (spare) active low cs2 (ext sram) active low cs1 (flash) active low cs0 (flash) active low csd1 (sdram) active low csd0 (sdram) active low 256 mbyte 256 mbyte 128 mbyte 128 mbyte 32 mbyte 32 mbyte 32 mbyte 32 mbyte sahara2 usb2.0 h.264 slcdc lcdc aipi2 0x1000 0000 0x1001 ffff 0x1002 a000 0x1002 afff 0x1002 b000 0x1002 bfff 0x1002 c000 0x1002 cfff reserved brom reserved brom 4 kbyte 64 mbyte 0xd800 0000 0xdbff ffff reserved reserved 0xdfff ffff 0xdc00 0000 64 mbyte 1 gbyte 511 mbyte 0xdfff ffff aipi1 0xffff 4bff 0xfff0 0000 979 kbyte 45 kbyte 0xffff 4c00 0xffff ffff system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-5 table 2-4 shows the memory map breakdown for the secondary ahb port 3. the sdramc, weim, pcmcia, and nfc module control registers and exte rnal memory are addressed via this region. the external memory regions (memory or external periphe rals) are accessed via the respective chip selects. csd1 and csd0 are sdramc chip selects, and cs5 to cs0 are weim chip selects. csd1 and cs0 chip select spaces are available for external boot. 0xb c000 0000 to 0xdfff_ffff is allocated for pcmcia io and memory space. table 2-5 shows the last region of address space that is part of the primary ahb memory map. the vector-ram is mapped into this region and the i.mx27 device uses the high memory (0xffff ff00?0xffff ffff) to store the interrupt vector table (64 words). this region is aliased on a 128-kbyte boundary. table 2-6 and table 2-7 show the detailed breakdown of the addr ess space controlled by aipi1 and aipi2. more details on the aipi can be found in chapter 35, ?ahb-lite ip interface (aipi) module .? table 2-4. secondary ahb port 2 memory map address secondary ahb port 3 size 0xa000_0000?0xafff_ffff external sdram/mddr (csd0 )256 mbyte 0xb000_0000?0xbfff_ffff external sdram/mddr (csd1 )256 mbyte 0xc000_0000?0xc7ff_ffff weim external memory (cs0 )128 mbyte 0xc800_0000?0xcfff_ffff weim external memory (cs1 )128 mbyte 0xd000_0000?0xd1ff_ffff weim external memory (cs2 )32 mbyte 0xd200_0000?0xd3ff_ffff weim external memory (cs3 )32 mbyte 0xd400_0000?0xd5ff_ffff weim external memory (cs4 )32 mbyte 0xd600_0000?0xd7ff_ffff weim external memory (cs5 )32 mbyte 0xd800_0000?0xd800_0fff nfc registers and internal ram 4 kbyte 0xd800_1000?0xd800_1fff sdramc registers 4 kbyte 0xd800_2000?0xd800_2fff weim registers 4 kbyte 0xd800_3000?0xd800_3fff m3if registers 4 kbyte 0xd800_4000?0xd800_4fff pcmcia registers 4 kbyte 0xd800_5000?0xdbff_ffff reserved 64 mbyte?20 kbyte 0xdc00_0000?0xdfff_ffff pcmcia memory space 64 mbyte table 2-5. primary ahb memory map (upper) address primary ahb size 0xe000_0000?0xffef_ffff reserved (aliased) 511 mbyte 0xfff0_0000?0xffff_4bff vram space not use 979 kbyte 0xffff_4c00?0xffff_ffff 45 kbyte vram 45 kbyte system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-6 freescale semiconductor table 2-6. aipi1 memory map address aipi1 memory map size 0 0x1000_0000?0x1000_0fff aipi1 (slot 0) 4 kbyte 1 0x1000_1000?0x1000_1fff dma 4 kbyte 2 0x1000_2000?0x1000_2fff wdog 4 kbyte 3 0x1000_3000?0x1000_3fff gpt1 4 kbyte 4 0x1000_4000?0x1000_4fff gpt2 4 kbyte 5 0x1000_5000?0x1000_5fff gpt3 4 kbyte 6 0x1000_6000?0x1000_6fff pwm 4 kbyte 7 0x1000_7000?0x1000_7fff rtc 4 kbyte 8 0x1000_8000?0x1000_8fff kpp 4 kbyte 9 0x1000_9000?0x1000_9fff owire 4 kbyte 10 0x1000_a000?0x1000_afff uart1 4 kbyte 11 0x1000_b000?0x1000_bfff uart2 4 kbyte 12 0x1000_c000?0x1000_cfff uart3 4 kbyte 13 0x1000_d000?0x1000_dfff uart4 4 kbyte 14 0x1000_e000?0x1000_efff cspi1 4 kbyte 15 0x1000_f000?0x1000_ffff cspi2 4 kbyte 16 0x1001_0000?0x1001_0fff ssi1 4 kbyte 17 0x1001_1000?0x1001_1fff ssi2 4 kbyte 18 0x1001_2000?0x1001_2fff i2c1 4 kbyte 19 0x1001_3000?0x1001_3fff sdhc1 4 kbyte 20 0x1001_4000?0x1001_4fff sdhc2 4 kbyte 21 0x1001_5000?0x1001_5fff gpio 4 kbyte 22 0x1001_6000?0x1001_6fff audmux 4 kbyte 23 0x1001_7000?0x1001_7fff cspi3 4 kbyte 24 0x1001_8000?0x1001_8fff mshc 4 kbyte 25 0x1001_9000?0x1001_9fff gpt4 4 kbyte 26 0x1001_a000?0x1001_afff gpt5 4 kbyte 27 0x1001_b000?0x1001_bfff uart5 4 kbyte 28 0x1001_c000?0x1001_cfff uart6 4 kbyte 29 0x1001_d000?0x1001_dfff i2c2 4 kbyte 30 0x1001_e000?0x1001_efff sdhc3 4 kbyte 31 0x1001_f000?0x1001_ffff gpt6 4 kbyte system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-7 2.3 register map the internal registers in the i.mx27 processor are listed in table 2-8 . table 2-7. aipi2 memory map address aipi2 memory map size 0 0x1002_0000?0x1002_0fff aipi2 (slot 0) 4 kbyte 1 0x1002_1000?0x1002_1fff lcdc 4 kbyte 2 0x1002_2000?0x1002_2fff slcdc 4 kbyte 3 0x1002_3000?0x1002_3fff reserved 4 kbyte 4 0x1002_4000?0x1002_4fff usb2.0 4 kbyte 5 0x1002_5000?0x1002_5fff sahara2 4 kbyte 6 0x1002_6000?0x1002_6fff emma_lt 4 kbyte 7 0x1002_7000?0x1002_7fff crm 4 kbyte 8 0x1002_8000?0x1002_8fff iim 4 kbyte 9 0x1002_9000?0x1002_9fff reserved 4 kbyte 10 0x1002_a000?0x1002_afff rtic 4 kbyte 11 0x1002_b000?0x1002_bfff fec 4 kbyte 12 0x1002_c000?0x1002_cfff scc 4 kbyte 13 0x1002_d000?0x1002_dfff scc 4 kbyte 14?26 0x1002_e000?0x1003_afff reserved (slots 14?26) 52 kbyte 27 0x1003_b000?0x1003_bfff etb regs 4 kbyte 28 0x1003_c000?0x1003_cfff etb ram 4 kbyte 29 0x1003_d000?0x1003_dfff etb ram 4 kbyte 30 0x1003_e000?0x1003_efff jam 4 kbyte 31 0x1003_f000?0x1003_ffff max 4 kbyte table 2-8. register map module name address register name description aipi1 0x1000_0000 psr0 peripheral size register 0 aipi1 0x1000_0004 psr1 peripheral size register 1 aipi1 0x1000_0008 par peripheral access register aipi1 0x1000_000c aaor atomic access only register dmac 0x1000_1000 dcr dma control register dmac 0x1000_1004 disr dma interrupt status register dmac 0x1000_1008 dimr dma interrupt mask register system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-8 freescale semiconductor dmac 0x1000_100c dbtosr dma burst time-out status register dmac 0x1000_1010 drtosr dma request time-out status register dmac 0x1000_1014 dsesr dma transfer error status register dmac 0x1000_1018 dbosr dma buffer overflow status register dmac 0x1000_101c dbtocr dma burst time-out control register dmac 0x1000_1040 wsra w-size register a dmac 0x1000_1044 xsra x-size register a dmac 0x1000_1048 ysra y-size register a dmac 0x1000_104c wsrb w-size register b dmac 0x1000_1050 xsrb x-size register b dmac 0x1000_1054 ysrb y-size register b dmac 0x1000_1080 sar0 channel 0 source address register dmac 0x1000_1084 dar0 channel 0 destination address register dmac 0x1000_1088 cntr0 channel 0 count register dmac 0x1000_108c ccr0 channel 0 control register dmac 0x1000_1090 rssr0 channel 0 request source select register dmac 0x1000_1094 blr0 channel 0 burst length register dmac 0x1000_1098 rtor0 bucr0 channel 0 request time-out register channel 0 bus utilization control register dmac 0x1000_109c ccnr0 channel 0 channel counter register dmac 0x1000_10c0 sar1 channel 1 source address register dmac 0x1000_10c4 dar1 channel 1 destination address register dmac 0x1000_10c8 cntr1 channel 1 count register dmac 0x1000_10cc ccr1 channel 1 control register dmac 0x1000_10d0 rssr1 channel 1 request source select register dmac 0x1000_10d4 blr1 channel 1 burst length register dmac 0x1000_10d8 rtor1 bucr1 channel 1 request time-out register channel 1 bus utilization control register dmac 0x1000_10dc ccnr1 channel 1 channel counter register dmac 0x1000_1100 sar2 channel 2 source address register dmac 0x1000_1104 dar2 channel 2 destination address register dmac 0x1000_1108 cntr2 channel 2 count register dmac 0x1000_110c ccr2 channel 2 control register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-9 dmac 0x1000 1110 rssr2 channel 2 request source select register dmac 0x1000 1114 blr2 channel 2 burst length register dmac 0x1000 1118 rtor2 bucr2 channel 2 request time-out register channel 2 bus utilization control register dmac 0x1000 111c ccnr2 channel 2 channel counter register dmac 0x1000 1140 sar3 channel 3 source address register dmac 0x1000 1144 dar3 channel 3 destination address register dmac 0x1000 1148 cntr3 channel 3 count register dmac 0x1000 114c ccr3 channel 3 control register dmac 0x1000 1150 rssr3 channel 3 request source select register dmac 0x1000 1154 blr3 channel 3 burst length register dmac 0x1000 1158 rtor3 bucr3 channel 3 request time-out register channel 3 bus utilization control register dmac 0x1000 115c ccnr3 channel 3 channel counter register dmac 0x1000 1180 sar4 channel 4 source address register dmac 0x1000 1184 dar4 channel 4 destination address register dmac 0x1000 1188 cntr4 channel 4 count register dmac 0x1000 118c ccr4 channel 4 control register dmac 0x1000 1190 rssr4 channel 4 request source select register dmac 0x1000 1194 blr4 channel 4 burst length register dmac 0x1000 1198 rtor4 bucr4 channel 4 request time-out register channel 4 bus utilization control register dmac 0x1000 119c ccnr 4 channel 4 channel counter register dmac 0x1000 11c0 sar5 channel 5 source address register dmac 0x1000 11c4 dar5 channel 5 destination address register dmac 0x1000 11c8 cntr5 channel 5 count register dmac 0x1000 11cc ccr5 channel 5 control register dmac 0x1000 11d0 rssr5 channel 5 request source select register dmac 0x1000 11d4 blr5 channel 5 burst length register dmac 0x1000 11d8 rtor5 bucr5 channel 5 request time-out register channel 5 bus utilization control register dmac 0x1000 11dc ccnr5 channel 5 channel counter register dmac 0x1000 1200 sar6 channel 6 source address register dmac 0x1000 1204 dar6 channel 6 destination address register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-10 freescale semiconductor dmac 0x1000 1208 cntr6 channel 6 count register dmac 0x1000 120c ccr6 channel 6 control register dmac 0x1000 1210 rssr6 channel 6 request source select register dmac 0x1000 1214 blr6 channel 6 burst length register dmac 0x1000 1218 rtor6 bucr6 channel 6 request time-out register channel 6 bus utilization control register dmac 0x1000 121c ccnr6 channel 6 channel counter register dmac 0x1000 1240 sar7 channel 7 source address register dmac 0x1000 1244 dar7 channel 7 destination address register dmac 0x1000 1248 cntr7 channel 7 count register dmac 0x1000 124c ccr7 channel 7 control register dmac 0x1000 1250 rssr7 channel 7 request source select register dmac 0x1000 1254 blr7 channel 7 burst length register dmac 0x1000 1258 rtor7 bucr7 channel 7 request time-out register channel 7 bus utilization control register dmac 0x1000 125c ccnr7 channel 7 channel counter register dmac 0x1000 1280 sar8 channel 8 source address register dmac 0x1000 1284 dar8 channel 8 destination address register dmac 0x1000 1288 cntr8 channel 8 count register dmac 0x1000 128c ccr8 channel 8 control register dmac 0x1000 1290 rssr8 channel 8 request source select register dmac 0x1000 1294 blr8 channel 8 burst length register dmac 0x1000 1298 rtor8 bucr8 channel 8 request time-out register channel 8 bus utilization control register dmac 0x1000 129c ccnr8 channel 8 channel counter register dmac 0x1000 12c0 sar9 channel 9 source address register dmac 0x1000 12c4 dar9 channel 9 destination address register dmac 0x1000 12c8 cntr9 channel 9 count register dmac 0x1000 12cc ccr9 channel 9 control register dmac 0x1000 12d0 rssr9 channel 9 request source select register dmac 0x1000 12d4 blr9 channel 9 burst length register dmac 0x1000 12d8 rtor9 bucr9 channel 9 request time-out register channel 9 bus utilization control register dmac 0x1000 12dc ccnr9 channel 9 channel counter register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-11 dmac 0x1000 1300 sar10 channel 10 source address register dmac 0x1000 1304 dar10 channel 10 destination address register dmac 0x1000 1308 cntr10 channel 10 count register dmac 0x1000 130c ccr10 channel 10 control register dmac 0x1000 1310 rssr10 channel 10 request source select register dmac 0x1000 1314 blr10 channel 10 burst length register dmac 0x1000 1318 rtor10 bucr10 channel 10 request time-out register channel 10 bus utilization control register dmac 0x1000 131c ccnr10 channel 10 channel counter register dmac 0x1000 1340 sar11 channel 11 source address register dmac 0x1000 1344 dar11 channel 11 destination address register dmac 0x1000 1348 cntr11 channel 11 count register dmac 0x1000 134c ccr11 channel 11 control register dmac 0x1000 1350 rssr11 channel 11 request source select register dmac 0x1000 1354 blr11 channel 11 burst length register dmac 0x1000 1358 rtor11 bucr11 channel 11 request time-out register channel 11 bus utilization control register dmac 0x1000 135c ccnr11 channel 11 channel counter register dmac 0x1000 1380 sar12 channel 12 source address register dmac 0x1000 1384 dar12 channel 12 destination address register dmac 0x1000 1388 cntr12 channel 12 count register dmac 0x1000 138c ccr12 channel 12 control register dmac 0x1000 1390 rssr12 channel 12 request source select register dmac 0x1000 1394 blr12 channel 12 burst length register dmac 0x1000 1398 rtor12 bucr12 channel 12 request time-out register channel 12 bus utilization control register dmac 0x1000 139c ccnr12 channel 14 channel counter register dmac 0x1000 13c0 sar13 channel 13 source address register dmac 0x1000 13c4 dar13 channel 13 destination address register dmac 0x1000 13c8 cntr13 channel 13 count register dmac 0x1000 13cc ccr13 channel 13 control register dmac 0x1000 13d0 rssr13 channel 13 request source select register dmac 0x1000 13d4 blr13 channel 13 burst length register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-12 freescale semiconductor dmac 0x1000 13d8 rtor13 bucr13 channel 13 request time-out register channel 13 bus utilization control register dmac 0x1000 13dc ccnr13 channel 13 channel counter register dmac 0x1000 1400 sar14 channel 14 source address register dmac 0x1000 1404 dar14 channel 14 destination address register dmac 0x1000 1408 cntr14 channel 14 count register dmac 0x1000 140c ccr14 channel 14 control register dmac 0x1000 1410 rssr14 channel 14 request source select register dmac 0x1000 1414 blr14 channel 14 burst length register dmac 0x1000 1418 rtor14 bucr14 channel 14 request time-out register channel 14 bus utilization control register dmac 0x1000 141c ccnr14 channel 14 channel counter register dmac 0x1000 1440 sar15 channel 15 source address register dmac 0x1000 1444 dar15 channel 15 destination address register dmac 0x1000 1448 cntr15 channel 15 count register dmac 0x1000 144c ccr15 channel 15 control register dmac 0x1000 1450 rssr15 channel 15 request source select register dmac 0x1000 1454 blr15 channel 15 burst length register dmac 0x1000 1458 rtor15 bucr15 channel 15 request time-out register channel 15 bus utilization control register dmac 0x1000 145c ccnr15 channel 15 channel counter register dmac 0x1000 1480 tcr test control register dmac 0x1000 1484 tfifoar test fifo a register dmac 0x1000 148c tdipr test dma in progress register dmac 0x1000 1490 tfifobr test fifo b register dmac 0x1000 1498 tdrr_l low 32 dma request register dmac 0x1000 149c tdrr_h high 32 dma request register wdog 0x1000 2000 wcr watchdog control register wdog 0x1000 2002 wsr watchdog service register wdog 0x1000 2004 wrsr watchdog reset status register gpt1 0x1000 3000 tctl1 gpt control register 1 gpt1 0x1000 3004 tprer1 gpt prescaler register 1 gpt1 0x1000 3008 tcmp1 gpt compare register 1 gpt1 0x1000 300c tcr1 gpt capture register 1 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-13 gpt1 0x1000 3010 tcn1 gpt counter register 1 gpt1 0x1000 3014 tstat1 gpt status register 1 gpt2 0x1000 4000 tctl2 gpt control register 2 gpt2 0x1000 4004 tprer2 gpt prescaler register 2 gpt2 0x1000 4008 tcmp2 gpt compare register 2 gpt2 0x1000 400c tcr2 gpt capture register 2 gpt2 0x1000 4010 tcn2 gpt counter register 2 gpt2 0x1000 4014 tstat2 gpt status register 2 gpt3 0x1000 5000 tctl3 gpt control register 3 gpt3 0x1000 5004 tprer3 gpt prescaler register 3 gpt3 0x1000 5008 tcmp3 gpt compare register 3 gpt3 0x1000 500c tcr3 gpt capture register 3 gpt3 0x1000 5010 tcn3 gpt counter register 3 gpt3 0x1000 5014 tstat3 gpt status register 3 pwm 0x1000 6000 pwmcr pwm control register pwm 0x1000 6004 pwmsr pwm status register pwm 0x1000 6008 pwmir pwm interrupt register pwm 0x1000 600c pwmsar pwm sample register pwm 0x1000 6010 pwmpr pwm period register pwm 0x1000 6014 pwmcnr pwm counter register rtc 0x1000 7000 hourmin rtc hours and minutes counter register rtc 0x1000 7004 seconds rtc seconds counter register rtc 0x1000 7008 alrm_hm rtc hours and minutes alarm register rtc 0x1000 700c alrm_sec rtc seconds alarm register rtc 0x1000 7010 rcctl rtc control register rtc 0x1000 7014 rtcisr rtc interrupt status register rtc 0x1000 7018 rtcienr rtc interrupt enable register rtc 0x1000 701c stpwch stopwatch minutes register rtc 0x1000 7020 dayr rtc days counter register rtc 0x1000 7024 dayalarm rtc day alarm register kpp 0x1000_8000 kpcr keypad control register kpp 0x1000_8002 kpsr keypad status register kpp 0x1000_8004 kddr keypad data direction register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-14 freescale semiconductor kpp 0x1000_8006 kpdr keypad data register o-wire 0x1000 9000 control 1-wire control register o-wire 0x1000 9002 time_divider 1-wire time divider register o-wire 0x1000 9004 reset 1-wire reset register uart1 0x1000_a000 uxrd_1 uart1 receiver register uart1 0x1000_a040 utxd_1 uart1 transmitter register uart1 0x1000_a080 ucr1_1 uart1 control register uart1 0x1000_a084 ucr2_1 uart1 control register 2 uart1 0x1000_a088 ucr3_1 uart1 control register 3 uart1 0x1000_a08c ucr4_1 uart1 control register 4 uart1 0x1000_a090 ufcr_1 uart1 fifo control register uart1 0x1000_a094 usr1_1 uart1 status register 1 uart1 0x1000_a098 usr2_1 uart1 status register 2 uart1 0x1000_a09c uesc_1 uart1 escape character register uart1 0x1000_a0a0 utim_1 uart1 escape timer register uart1 0x1000_a0a4 ubir_1 uart1 brm incremental register uart1 0x1000_a0a8 ubmr_1 uart1 brm modulator register uart1 0x1000_a0ac ubrc_1 uart1 baud rate count register uart1 0x1000_a0b0 onems_1 uart1 one millisecond register uart1 0x1000_a0b4 uts_1 uart1 test register 1 uart2 0x1000_b000 uxrd_2 uart2 receiver register uart2 0x1000_b040 utxd_2 uart2 transmitter register uart2 0x1000_b080 ucr1_2 uart2 control register uart2 0x1000_b084 ucr2_2 uart2 control register 2 uart2 0x1000_b088 ucr3_2 uart2 control register 3 uart2 0x1000_b08c ucr4_2 uart2 control register 4 uart2 0x1000_b090 ufcr_2 uart2 fifo control register uart2 0x1000_b094 usr1_2 uart2 status register 1 uart2 0x1000_b098 usr2_2 uart2 status register 2 uart2 0x1000_b09c uesc_2 uart2 escape character register uart2 0x1000_b0a0 utim_2 uart2 escape timer register uart2 0x1000_b0a4 ubir_2 uart2 brm incremental register uart2 0x1000_b0a8 ubmr_2 uart2 brm modulator register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-15 uart2 0x1000_b0ac ubrc_2 uart2 baud rate count register uart2 0x1000_b0b0 onems_2 uart2 one millisecond register uart2 0x1000_b0b4 uts_2 uart2 test register 1 uart3 0x1000_c000 uxrd_3 uart3 receiver register uart3 0x1000_c040 utxd_3 uart3 transmitter register uart3 0x1000_c080 ucr1_3 uart3 control register uart3 0x1000_c084 ucr2_3 uart3 control register 2 uart3 0x1000_c088 ucr3_3 uart3 control register 3 uart3 0x1000_c08c ucr4_3 uart3 control register 4 uart3 0x1000_c090 ufcr_3 uart3 fifo control register uart3 0x1000_c094 usr1_3 uart3 status register 1 uart3 0x1000_c098 usr2_3 uart3 status register 2 uart3 0x1000_c09c uesc_3 uart3 escape character register uart3 0x1000_c0a0 utim_3 uart3 escape timer register uart3 0x1000_c0a4 ubir_3 uart3 brm incremental register uart3 0x1000_c0a8 ubmr_3 uart3 brm modulator register uart3 0x1000_c0ac ubrc_3 uart3 baud rate count register uart3 0x1000_c0b0 onems_3 uart3 one millisecond register uart3 0x1000_c0b4 uts_3 uart3 test register 1 uart4 0x1000_d000 uxrd_4 uart4 receiver register uart4 0x1000_d040 utxd_4 uart4 transmitter register uart4 0x1000_d080 ucr1_4 uart4 control register uart4 0x1000_d084 ucr2_4 uart4 control register 2 uart4 0x1000_d088 ucr3_4 uart4 control register 3 uart4 0x1000_d08c ucr4_4 uart4 control register 4 uart4 0x1000_d090 ufcr_4 uart4 fifo control register uart4 0x1000_d094 usr1_4 uart4 status register 1 uart4 0x1000_d098 usr2_4 uart4 status register 2 uart4 0x1000_d09c uesc_4 uart4 escape character register uart4 0x1000_d0a0 utim_4 uart4 escape timer register uart4 0x1000_d0a4 ubir_4 uart4 brm incremental register uart4 0x1000_d0a8 ubmr_4 uart4 brm modulator register uart4 0x1000_d0ac ubrc_4 uart4 baud rate count register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-16 freescale semiconductor uart4 0x1000_d0b0 onems_4 uart4 one millisecond register uart4 0x1000_d0b4 uts_4 uart4 test register 1 cspi1 0x1000 e000 rxdata1 receive data register 1 cspi1 0x1000 e004 txdata1 transmit data register 1 cspi1 0x1000 e008 control_reg1 cspi control register 1 cspi1 0x1000 e00c int_reg1 interrupt control/status register 1 cspi1 0x1000 e010 test_reg cspi test register 1 cspi1 0x1000 e014 period1 cspi sample period control register 1 cspi1 0x1000 e018 cspi_dma1 cspi dma register 1 cspi1 0x1000 e01c cspi_reset1 cspi 1 soft reset register cspi2 0x1000 f000 rxdata2 receive data register 2 cspi2 0x1000 f004 txdata2 transmit data register 2 cspi2 0x1000 f008 control_reg2 cspi control register 2 cspi2 0x1000 f00c int_reg2 interrupt control/status register 2 cspi2 0x1000 f010 test_reg 2 cspi test register 2 cspi2 0x1000 f014 period2 cspi sample period control register 2 cspi2 0x1000 f018 cspi_dma2 cspi dma register 2 cspi2 0x1000 f01c cspi_reset2 cspi 2 soft reset register ssi 1 0x1001 0000 stx0 ssi transmit data register 0 ssi 1 0x1001 0004 stx1 ssi transmit data register 1 ssi 1 0x1001 0008 srx0 ssi receive data register 0 ssi 1 0x1001 000c srx1 ssi receive data register 1 ssi 1 0x1001 0010 scr ssi control register ssi 1 0x1001 0014 sisr ssi interrupt status register ssi 1 0x1001 0018 sier ssi interrupt enable register ssi 1 0x1001 001c stcr ssi transmit configuration register ssi 1 0x1001 0020 srcr ssi receive configuration register ssi 1 0x1001 0024 stccr ssi transmit clock control register ssi 1 0x1001 0028 srccr ssi receive clock control register ssi 1 0x1001 002c sfcsr ssi fifo control/status register ssi 1 0x1001 0030 str ssi test register ssi 1 0x1001 0034 sor ssi option register ssi 1 0x1001 0038 sacnt ssi ac97 control register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-17 ssi 1 0x1001 003c sacadd ssi ac97 command address register ssi 1 0x1001 0040 sacdat ssi ac97 command data register ssi 1 0x1001 0044 satag ssi ac97 tag register ssi 1 0x1001 0048 stmsk ssi transmit time slot mask register ssi 1 0x1001 004c srmsk ssi receive time slot mask register ssi 1 0x1001 0050 saccst ssi ac97 channel status register ssi 1 0x1001 0054 saccen ssi ac97 channel enable register ssi 1 0x1001 0058 saccdis ssi ac97 channel disable register ssi 2 0x1001 1000 stx0 ssi transmit data register 0 ssi 2 0x1001 1004 stx1 ssi transmit data register 1 ssi 2 0x1001 1008 srx0 ssi receive data register 0 ssi 2 0x1001 100c srx1 ssi receive data register 1 ssi 2 0x1001 1010 scr ssi control register ssi 2 0x1001 1014 sisr ssi interrupt status register ssi 2 0x1001 1018 sier ssi interrupt enable register ssi 2 0x1001 101c stcr ssi transmit configuration register ssi 2 0x1001 1020 srcr ssi receive configuration register ssi 2 0x1001 1024 stccr ssi transmit clock control register ssi 2 0x1001 1028 srccr ssi receive clock control register ssi 2 0x1001 102c sfcsr ssi fifo control/status register ssi 2 0x1001 1030 str ssi test register ssi 2 0x1001 1034 sor ssi option register ssi 2 0x1001 1038 sacnt ssi ac97 control register ssi 2 0x1001 103c sacadd ssi ac97 command address register ssi 2 0x1001 1040 sacdat ssi ac97 command data register ssi 2 0x1001 1044 satag ssi ac97 tag register ssi 2 0x1001 1048 stmsk ssi transmit time slot mask register ssi 2 0x1001 104c srmsk ssi receive time slot mask register ssi 2 0x1001 1050 saccst ssi ac97 channel status register ssi 2 0x1001 1054 saccen ssi ac97 channel enable register ssi 2 0x1001 1058 saccdis ssi ac97 channel disable register i2c 1 0x1001 2000 iadr i2c address register i2c 1 0x1001 2004 ifdr i2c frequency divider register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-18 freescale semiconductor i2c 1 0x1001 2008 i2cr i2c control register i2c 1 0x1001 200c i2sr i2c status register i2c 1 0x1001 2010 i2dr i2c data i/o register sdhc1 0x1001 3000 str_stp_clk mmc/sd1 clock control register sdhc1 0x1001 3004 status (read only) mmc/sd1 status register sdhc1 0x1001 3008 clk_rate mmc/sd1 clock rate register sdhc1 0x1001 300c cmd_dat_cont mmc/sd1 command and data control register sdhc1 0x1001 3010 response_to mmc/sd1 response time out register sdhc1 0x1001 3014 read_to mmc/sd1 read time out register sdhc1 0x1001 3018 blk_len mmc/sd1 block length register sdhc1 0x1001 301c nob mmc/sd1 number of block register sdhc1 0x1001 3020 rev_no mmc/sd1 revision number register sdhc1 0x1001 3024 int_cntl mmc/sd1 interrupt control register sdhc1 0x1001 3028 cmd mmc/sd1 command number register sdhc1 0x1001 302c argh mmc/sd1 higher argument register sdhc1 0x1001 3030 argl mmc/sd1 lower argument register sdhc1 0x1001 3034 res_fifo (read only) mmc/sd1 response fifo register sdhc1 0x1001 3038 buffer_access mmc/sd1 buffer access register sdhc2 0x1001 4000 str_stp_clk mmc/sd2 clock control register sdhc2 0x1001 4004 status (read only) mmc/sd2 status register sdhc2 0x1001 4008 clk_rate mmc/sd2 clock rate register sdhc2 0x1001 400c cmd_dat_cont mmc/sd2 command and data control register sdhc2 0x1001 4010 response_to mmc/sd2 response time out register sdhc2 0x1001 4014 read_to mmc/sd2 read time out register sdhc2 0x1001 4018 blk_len mmc/sd2 block length register sdhc2 0x1001 401c nob mmc/sd2 number of block register sdhc2 0x1001 4020 rev_no mmc/sd2 revision number register sdhc2 0x1001 4024 int_cntl mmc/sd2 interrupt control register sdhc2 0x1001 4028 cmd mmc/sd2 command number register sdhc2 0x1001 402c argh mmc/sd2 higher argument register sdhc2 0x1001 4030 argl mmc/sd2 lower argument register sdhc2 0x1001 4034 res_fifo (read only) mmc/sd2 response fifo register sdhc2 0x1001 4038 buffer_access mmc/sd2 buffer access register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-19 gpio 0x1001 5000 pta_ddir data direction register, port a gpio 0x1001 5004 pta_ocr1 output configuration register 1 (ocr1), port a gpio 0x1001 5008 pta_ocr2 output configuration register 2 (ocr2), port a gpio 0x1001 500c pta_iconfa1 input configuration register a1 (iconfa1), port a gpio 0x1001 5010 pta_iconfa2 input configuration register a1 (iconfa2), port a gpio 0x1001 5014 pta_iconfb1 input configuration register b1 (iconfb1), port a gpio 0x1001 5018 pta_iconfb2 input configuration register b2 (iconfb2), port a gpio 0x1001 501c pta_dr data register, port a gpio 0x1001 5020 pta_gius gpio in use register, port a gpio 0x1001 5024 pta_ssr sample status register, port a gpio 0x1001 5028 pta_icr1 interrupt configuration register 1, port a gpio 0x1001 502c pta_icr2 interrupt configuration register 2, port a gpio 0x1001 5030 pta_imr interrupt mask register, port a gpio 0x1001 5034 pta_isr interrupt status register, port a gpio 0x1001 5038 pta_gpr general purpose register, port a gpio 0x1001 503c pta_swr software reset register, port a gpio 0x1001 5040 pta_puen pull_up enable register, port a gpio 0x1001_5100 ptb_ddir data direction register, port b gpio 0x1001 5104 ptb_ocr1 output configuration register 1 (ocr1), port b gpio 0x1001 5108 ptb_ocr2 output configuration register 2 (ocr2), port b gpio 0x1001 510c ptb_iconfa1 input configuration register a1 (iconfa1), port b gpio 0x1001 5110 ptb_iconfa2 input configuration register a1 (iconfa2), port b gpio 0x1001 5114 ptb_iconfb1 input configuration register b1 (iconfb1), port b gpio 0x1001 5118 ptb_iconfb2 input configuration register b2 (iconfb2), port b gpio 0x1001 511c ptb_dr data register, port b gpio 0x1001 5120 ptb_gius gpio in use register, port b gpio 0x1001 5124 ptb_ssr sample status register, port b gpio 0x1001 5128 ptb_icr1 interrupt configuration register 1, port b gpio 0x1001 512c ptb_icr2 interrupt configuration register 2, port b gpio 0x1001 5130 ptb_imr interrupt mask register, port b gpio 0x1001 5134 ptb_isr interrupt status register, port b gpio 0x1001 5138 ptb_gpr general purpose register, port b gpio 0x1001 513c ptb_swr software reset register, port b table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-20 freescale semiconductor gpio 0x1001 5140 ptb_puen pull_up enable register, port b gpio 0x1001_5200 ptc_ddir data direction register, port c gpio 0x1001 5204 ptc_ocr1 output configuration register 1 (ocr1), port c gpio 0x1001 5208 ptc_ocr2 output configuration register 2 (ocr2), port c gpio 0x1001 520c ptc_iconfa1 input configuration register a1 (iconfa1), port c gpio 0x1001 5210 ptc_iconfa2 input configuration register a1 (iconfa2), port c gpio 0x1001 5214 ptc_iconfb1 input configuration register b1 (iconfb1), port c gpio 0x1001 5218 ptc_iconfb2 input configuration register b2 (iconfb2), port c gpio 0x1001 521c ptc_dr data register, port c gpio 0x1001 5220 ptc_gius gpio in use register, port c gpio 0x1001 5224 ptc_ssr sample status register, port c gpio 0x1001 5228 ptc_icr1 interrupt configuration register 1, port c gpio 0x1001 522c ptc_icr2 interrupt configuration register 2, port c gpio 0x1001 5230 ptc_imr interrupt mask register, port c gpio 0x1001 5234 ptc_isr interrupt status register, port c gpio 0x1001 5238 ptc_gpr general purpose register, port c gpio 0x1001 523c ptc_swr software reset register, port c gpio 0x1001 5240 ptc_puen pull_up enable register, port c gpio 0x1001 5300 ptd_ddir data direction register, port d gpio 0x1001 5304 ptd_ocr1 output configuration register 1 (ocr1), port d gpio 0x1001 5308 ptd_ocr2 output configuration register 2 (ocr2), port d gpio 0x1001 530c ptd_iconfa1 input configuration register a1 (iconfa1), port d gpio 0x1001 5310 ptd_iconfa2 input configuration register a1 (iconfa2), port d gpio 0x1001 5314 ptd_iconfb1 input configuration register b1 (iconfb1), port d gpio 0x1001 5318 ptd_iconfb2 input configuration register b2 (iconfb2), port d gpio 0x1001 531c ptd_dr data register, port d gpio 0x1001 5320 ptd_gius gpio in use register, port d gpio 0x1001 5324 ptd_ssr sample status register, port d gpio 0x1001 5328 ptd_icr1 interrupt configuration register 1, port d gpio 0x1001 532c ptd_icr2 interrupt configuration register 2, port d gpio 0x1001 5330 ptd_imr interrupt mask register, port d gpio 0x1001 5334 ptd_isr interrupt status register, port d gpio 0x1001 5338 ptd_gpr general purpose register, port d table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-21 gpio 0x1001 533c ptd_swr software reset register, port d gpio 0x1001 5340 ptd_puen pull_up enable register, port d gpio 0x1001 5400 pte_ddir data direction register, port e gpio 0x1001 5404 pte_ocr1 output configuration register 1 (ocr1), port e gpio 0x1001 5408 pte_ocr2 output configuration register 2 (ocr2), port e gpio 0x1001 540c pte_iconfa1 input configuration register a1 (iconfa1), port e gpio 0x1001 5410 pte_iconfa2 input configuration register a1 (iconfa2), port e gpio 0x1001 5414 pte_iconfb1 input configuration register b1 (iconfb1), port e gpio 0x1001 5418 pte_iconfb2 input configuration register b2 (iconfb2), port e gpio 0x1001 541c pte_dr data register, port e gpio 0x1001 5420 pte_gius gpio in use register, port e gpio 0x1001 5424 pte_ssr sample status register, port e gpio 0x1001 5428 pte_icr1 interrupt configuration register 1, port e gpio 0x1001 542c pte_icr2 interrupt configuration register 2, port e gpio 0x1001 5430 pte_imr interrupt mask register, port e gpio 0x1001 5434 pte_isr interrupt status register, port e gpio 0x1001 5438 pte_gpr general purpose register, port e gpio 0x1001 543c pte_swr software reset register, port e gpio 0x1001 5440 pte_puen pull_up enable register, port e gpio 0x1001 5500 ptf_ddir data direction register, port f gpio 0x1001 5504 ptf_ocr1 output configuration register 1 (ocr1), port f gpio 0x1001 5508 ptf_ocr2 output configuration register 2 (ocr2), port f gpio 0x1001 550c ptf_iconfa1 input configuration register a1 (iconfa1), port f gpio 0x1001 5510 ptf_iconfa2 input configuration register a1 (iconfa2), port f gpio 0x1001 5514 ptf_iconfb1 input configuration register b1 (iconfb1), port f gpio 0x1001 5518 ptf_iconfb2 input configuration register b2 (iconfb2), port f gpio 0x1001 551c ptf_dr data register, port f gpio 0x1001 5520 ptf_gius gpio in use register, port f gpio 0x1001 5524 ptf_ssr sample status register, port f gpio 0x1001 5528 ptf_icr1 interrupt configuration register 1, port f gpio 0x1001 552c ptf_icr2 interrupt configuration register 2, port f gpio 0x1001 5530 ptf_imr interrupt mask register, port f gpio 0x1001 5534 ptf_isr interrupt status register, port f table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-22 freescale semiconductor gpio 0x1001 5538 ptf_gpr general purpose register, port f gpio 0x1001 553c ptf_swr software reset register, port f gpio 0x1001 5540 ptf_puen pull_up enable register, port f gpio 0x1001 5600 pmask gpio port interrupt mask audmux 0x1001 6000 hpcr1 host port configuration register 1 audmux 0x1001 6004 hpcr2 host port configuration register 2 audmux 0x1001 6008 hpcr3 host port configuration register 3 audmux 0x1001 6010 ppcr1 peripheral port configuration register 1 audmux 0x1001 6014 ppcr2 peripheral port configuration register 2 audmux 0x1001 601c ppcr3 peripheral port configuration register 3 cspi3 0x1001 7000 rxdata3 receive data register 3 cspi3 0x1001 7004 txdata3 transmit data register 3 cspi3 0x1001 7008 control_reg3 cspi control register 3 cspi3 0x1001 700c int_reg3 interrupt control/status register 3 cspi3 0x1001 7010 test_reg3 cspi test register 3 cspi3 0x1001 7014 period3 cspi sample period control register 3 cspi3 0x1001 7018 cspi_dma3 cspi dma register 3 cspi3 0x1001 701c cspi_reset3 cspi soft reset register 3 mshc 0x1001 8000 command_reg mshc command register mshc 0x1001 8008 data_reg mshc data register mshc 0x1001 8010 status_reg mshc status register mshc 0x1001 8018 system_reg mshc system register gpt4 0x1001 9000 tctl4 gpt control register 4 gpt4 0x1001 9004 tprer4 gpt prescaler register 4 gpt4 0x1001 9008 tcmp4 gpt compare register 4 gpt4 0x1001 900c tcr4 gpt capture register 4 gpt4 0x1001 9010 tcn4 gpt counter register 4 gpt4 0x1001 9014 tstat4 gpt status register 4 gpt5 0x1001 a000 tctl5 gpt control register 5 gpt5 0x1001 a004 tprer5 gpt prescaler register 5 gpt5 0x1001 a008 tcmp5 gpt compare register 5 gpt5 0x1001 a00c tcr5 gpt capture register 5 gpt5 0x1001 a010 tcn5 gpt counter register 5 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-23 gpt5 0x1001 a014 tstat5 gpt status register 5 uart5 0x1001_b000 uxrd_5 uart5 receiver register uart5 0x1001_b040 utxd_5 uart5 transmitter register uart5 0x1001_b080 ucr1_5 uart5 control register uart5 0x1001_b084 ucr2_5 uart5 control register 2 uart5 0x1001_b088 ucr3_5 uart5 control register 3 uart5 0x1001_b08c ucr4_5 uart5 control register 4 uart5 0x1001_b090 ufcr_5 uart5 fifo control register uart5 0x1001_b094 usr1_5 uart5 status register 1 uart5 0x1001_b098 usr2_5 uart5 status register 2 uart5 0x1001_b09c uesc_5 uart5 escape character register uart5 0x1001_b0a0 utim_5 uart5 escape timer register uart5 0x1001_b0a4 ubir_5 uart5 brm incremental register uart5 0x1001_b0a8 ubmr_5 uart5 brm modulator register uart5 0x1001_b0ac ubrc_5 uart5 baud rate count register uart5 0x1001_b0b0 onems_5 uart5 one millisecond register uart5 0x1001_b0b4 uts_5 uart5 test register 1 uart6 0x1001_c000 uxrd_6 uart6 receiver register uart6 0x1001_c040 utxd_6 uart6 transmitter register uart6 0x1001_c080 ucr1_6 uart6 control register uart6 0x1001_c084 ucr2_6 uart6 control register 2 uart6 0x1001_c088 ucr3_6 uart6 control register 3 uart6 0x1001_c08c ucr4_6 uart6 control register 4 uart6 0x1001_c090 ufcr_6 uart6 fifo control register uart6 0x1001_c094 usr1_6 uart6 status register 1 uart6 0x1001_c098 usr2_6 uart6 status register 2 uart6 0x1001_c09c uesc_6 uart6 escape character register uart6 0x1001_c0a0 utim_6 uart6 escape timer register uart6 0x1001_c0a4 ubir_6 uart6 brm incremental register uart6 0x1001_c0a8 ubmr_6 uart6 brm modulator register uart6 0x1001_c0ac ubrc_6 uart6 baud rate count register uart6 0x1001_c0b0 onems_6 uart6 one millisecond register uart6 0x1001_c0b4 uts_6 uart6 test register 1 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-24 freescale semiconductor i2c 2 0x1001 d000 iadr i2c address register i2c 2 0x1001 d004 ifdr i2c frequency divider register i2c 2 0x1001 d008 i2cr i2c control register i2c 2 0x1001 d00c i2sr i2c status register i2c 2 0x1001 d010 i2dr i2c data i/o register sdhc3 0x1001 e000 str_stp_clk mmc/sd2 clock control register sdhc3 0x1001 e004 status (read only) mmc/sd2 status register sdhc3 0x1001 e008 clk_rate mmc/sd2 clock rate register sdhc3 0x1001 e00c cmd_dat_cont mmc/sd2 command and data control register sdhc3 0x1001 e010 response_to mmc/sd2 response time out register sdhc3 0x1001 e014 read_to mmc/sd2 read time out register sdhc3 0x1001 e018 blk_len mmc/sd2 block length register sdhc3 0x1001 e01c nob mmc/sd2 number of block register sdhc3 0x1001 e020 rev_no mmc/sd2 revision number register sdhc3 0x1001 e024 int_cntl mmc/sd2 interrupt control register sdhc3 0x1001 e028 cmd mmc/sd2 command number register sdhc3 0x1001 e02c argh mmc/sd2 higher argument register sdhc3 0x1001 e030 argl mmc/sd2 lower argument register sdhc3 0x1001 e034 res_fifo (read only) mmc/sd2 response fifo register sdhc3 0x1001 e038 buffer_access mmc/sd2 buffer access register gpt6 0x1001 f000 tctl6 gpt control register 6 gpt6 0x1001 f004 tprer6 gpt prescaler register 6 gpt6 0x1001 f008 tcmp6 gpt compare register 6 gpt6 0x1001 f00c tcr6 gpt capture register 6 gpt6 0x1001 f010 tcn6 gpt counter register 6 gpt6 0x1001 f014 tstat6 gpt status register 6 aipi2 0x1002 0000 psr0 peripheral size register0 aipi2 0x1002 0004 psr1 peripheral size register1 aipi2 0x1002 0008 par peripheral access register aipi2 0x1002 000c aaor atomic access only register lcdc 0x1002 1000 lssar lcdc screen start address register lcdc 0x1002 1004 lsr lcdc size register lcdc 0x1002 1008 lvpwr lcdc virtual page width register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-25 lcdc 0x1002 100c lcpr lcdc cursor position register lcdc 0x1002 1010 lcwhbr lcdc cursor width height and blink register lcdc 0x1002 1014 lccmr lcdc color cursor mapping register lcdc 0x1002 1018 lpcr lcdc panel configuration register lcdc 0x1002 101c lhcr lcdc horizontal configuration register lcdc 0x1002 1020 lvcr lcdc vertical configuration register lcdc 0x1002 1024 lpor lcdc panning offset register lcdc 0x1002 1028 lscr lcdc sharp configuration register lcdc 0x1002 102c lpccr lcdc pwm contrast control register lcdc 0x1002 1030 ldcr lcdc dma control register lcdc 0x1002 1034 lrmcr lcdc refresh mode control register lcdc 0x1002 1038 licr lcdc interrupt configuration register lcdc 0x1002 103c lier lcdc interrupt enable register lcdc 0x1002 1040 lisr lcdc interrupt status register lcdc 0x1002 1050 lgwsar lcdc graphic window start address register lcdc 0x1002 1054 lgwsr lcdc graphic window size register lcdc 0x1002 1058 lgwvpwr lcdc graphic window virtual page width register lcdc 0x1002 105c lgwpor lcdc graphic window panning offset register lcdc 0x1002 1060 lgwpr lcdc graphic window position register lcdc 0x1002 1064 lgwcr lcdc graphic window control register lcdc 0x1002 1068 lgwdcr lcdc graphic window dma control register lcdc 0x1002 1080 lauscr lcdc aus mode control register lcdc 0x1002 1084 lausccr lcdc aus mode cursor control register slcdc 0x1002 2000 data_base_addr slcd data base address register slcdc 0x1002 2004 data_buff_size slcd data buffer size register slcdc 0x1002 2008 cmd_base_addr slcd command buffer base address register slcdc 0x1002 200c cmd_buff_size slcd command buffer size register slcdc 0x1002 2010 cmd_str_size slcd command string size register slcdc 0x1002 2014 fifo_config slcd fifo configuration register slcdc 0x1002 2018 lcd_config slcd configuration register slcdc 0x1002 201c lcd_xfer_config slcd transfer configuration register slcdc 0x1002 2020 dma_ctrl_stat slcd dma control/status register slcdc 0x1002 2024 lcd_clk_config slcd clock configuration register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-26 freescale semiconductor slcdc 0x1002 2028 lcd_write_data slcd write data register video codec 0x1002 3000 coderun bit run start video codec 0x1002 3004 codedownload code download data register video codec 0x1002 3008 hostintreq host interrupt request to bi video codec 0x1002 300c bitintclear bit interrupt clear video codec 0x1002 3010 bitintsts bit interrupt status video codec 0x1002 3100 workbufaddr working buffer address in external memory video codec 0x1002 3104 codebufaddr code table size in external memory video codec 0x1002 3108 bitstreamctrl bit stream control video codec 0x1002 310c framememctrl frame memory control video codec 0x1002 3110 sramaddr internal sram base address video codec 0x1002 3114 sramsize internal sram size video codec 0x1002 3140 bitstreamrdptr bit stream buffer read address video codec 0x1002 3144 bitstreamwrptr bit stream buffer write address video codec 0x1002 3148 framenum encoded/decoded frame number video codec 0x1002 3160 busyflag processing busy flag video codec 0x1002 3164 runcommand start/stop codec run command video codec 0x1002 3168 runindex run process index video codec 0x1002 316c runcodstd run codec standard video codec 0x1002 3180 bitbufaddr parameter registers in sequence initialization. bitstream buffer address video codec 0x1002 3184 bitbufsize parameter registers in sequence initialization. bitstream buffer size video codec 0x1002 3188 frameintaddry parameter registers in sequence initialization. temporal frame y address video codec 0x1002 318c frameintaddrcb parameter registers in sequence initialization. temporal frame cb address video codec 0x1002 3190 frameintaddrcr parameter registers in sequence initialization. temporal frame cr address video codec 0x1002 3194 enccodstd parameter registers in sequence initialization. encode coding standard video codec 0x1002 3198 encsrcformat parameter registers in sequence initialization. encode source frame format video codec 0x1002 319c encmp4para parameter registers in sequence initialization. encode mpeg4 parameter table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-27 video codec 0x1002 31a0 enc263para parameter registers in sequence initialization. encode h.263 parameter video codec 0x1002 31a4 enc264para parameter registers in sequence initialization. encode h.264 parameter video codec 0x1002 31a8 encslicemode parameter registers in sequence initialization. encode slice mode video codec 0x1002 31ac encgopnum parameter registers in sequence initialization. encode gop number video codec 0x1002 31b0 encpictureqs parameter registers in sequence initialization. encode picture quantize step video codec 0x1002 31c0 retstatus parameter registers in sequence initialization. command executing result status video codec 0x1002 31c4 retsrcformat parameter registers in sequence initialization. decoded source format video codec 0x1002 31c8 retmp4info parameter registers in sequence initialization. decoded mpeg4 sequence information video codec 0x1002 31cc ret263info parameter registers in sequence initialization. decoded h.263 sequence information video codec 0x1002 31d0 ret264info parameter registers in sequence initialization. decoded h.264 sequence information video codec 0x1002 3180 framesrcaddry parameter register in processing running. source frame y address video codec 0x1002 3184 framesrcaddrcb parameter register in processing running. source frame cb address video codec 0x1002 3188 framesrcaddrcr parameter register in processing running. source frame cr address video codec 0x1002 318c framedecaddry parameter register in processing running. decode frame y address video codec 0x1002 3190 framedecaddrcb parameter register in processing running. decode frame cb address video codec 0x1002 3194 framedecaddrcr parameter register in processing running. decode frame cr address video codec 0x1002 31c0 retstatus parameter register in processing running. command executing result status usbotg 0x1002 4000 uog_id id (uog_id) usbotg 0x1002 4004 uog_hwgeneral hardware general (uog_hwgeneral) usbotg 0x1002 4008 uog_hwhost host hardware parameters (uog_hwhost) usbotg 0x1002 400c uog_hwdevice device hardware parameters (uog_hwdevice) usbotg 0x1002 4010 uog_hwtxbuf tx buffer hardware parameters (uog_hwtxbuf) table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-28 freescale semiconductor usbotg 0x1002 4014 uog_hwrxbuf rx buffer hardware parameters (uog_hwrxbuf) usbotg 0x1002 4080 gptimer0ld general purpose timer #0 load (gptimer0ld) usbotg 0x1002 4084 gptimer0ctrl general purpose timer #0 controller (gptimer0ctrl) usbotg 0x1002 4088 gptimer0ld general purpose timer #1 load (gptimer0ld) usbotg 0x1002 408c gptimer0ctrl general purpose timer #1 controller (gptimer0ctrl) usbotg 0x1002 4100 uog_caplength capability register length (uog_caplength) usbotg 0x1002 4102 uog_hciversion host interface version (uog_hciversion) usbotg 0x1002 4104 uog_hcsparams host control structural parameters (uog_hcsparams) usbotg 0x1002 4108 uog_hccparams control ca pability parameters (uog_hccparams) usbotg 0x1002 4120 uog_dciversion device interface version (uog_dciversion) usbotg 0x1002 4124 uog_dccparams device controller capability parameters (uog_dccparams) usbotg 0x1002 4140 uog_usbcmd usb command register (uog_usbcmd) usbotg 0x1002 4144 uog_usbsts usb status register (uog_usbsts) usbotg 0x1002 4148 uog_usbintr interrupt enable register (uog_usbintr) usbotg 0x1002 414c uog_frindex usb frame index (uog_frindex) usbotg 0x1002 4154 uog_periodiclistbase host controller frame list base address (uog_periodiclistbase) usbotg 0x1002 4158 uog_asynclistaddr host controller next asynch. address (uog_asynclistaddr) usbotg 0x1002 4160 uog_burstsize host controller embedded tt asynch. buffer status (uog_burstsize) usbotg 0x1002 4164 uog_txfilltuning tx fifo fill tuning (uog_txfilltuning) usbotg 0x1002 4170 ulpiview ulpi viewport (ulpiview) usbotg 0x1002 4180 uog_cfgflag config flag (uog_cfgflag) usbotg 0x1002 4184 uog_portsc1 port status and control (uog_portsc1) usbotg 0x1002 41a4 uog_otgsc on-the-go status and control (uog_otgsc) usbotg 0x1002 41a8 uog_usbmode usb device mode (uog_usbmode) usbotg 0x1002 41ac uog_endptsetupstat endpoi nt setup status (uog_endptsetupstat) usbotg 0x1002 41b0 uog_endptprime endpoint initialization (uog_endptprime) usbotg 0x1002 41b4 uog_endptflush endpoint de-initialize (uog_endptflush) usbotg 0x1002 41b8 uog_endptstat endpoint status (uog_endptstat) table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-29 usbotg 0x1002 41bc uog_endptcomplete endpoint complete (uog_endptcomplete) usbotg 0x1002 41c0 endptctrl0 endpoint control 0 (endptctrl0) usbotg 0x1002 41c4 endptctrl1 endpoint control 1 (endptctrl1) usbotg 0x1002 41c8 endptctrl2 endpoint control 2 (endptctrl2) usbotg 0x1002 41cc endptctrl3 endpoint control 3 (endptctrl3) usbotg 0x1002 41d0 endptctrl4 endpoint control 4 (endptctrl4) usb otg 0x1002 41d4 endptctrl5 endpoint control 5 (endptctrl5) usb otg 0x1002 41d8 endptctrl6 endpoint control 6 (endptctrl6) usbotg 0x1002 41dc endptctrl7 endpoint control 7 (endptctrl7) usbotg 0x1002 4200 uh1_id host 1 id (uh1_id) usbotg 0x1002 4204 uh1_hwgeneral hardware general (uh1_hwgeneral) usbotg 0x1002 4208 uh1_hwhost host hardware parameters (uh1_hwhost) usbotg 0x1002 4210 uh1_hwtxbuf tx buffer hardware parameters (uh1_hwtxbuf) usbotg 0x1002 4214 uh1_hwrxbuf rx buffer hardware parameters (uh1_hwrxbuf) usbotg 0x1002 4280 gptimer0ld general purpose timer #0 load (gptimer0ld) usbotg 0x1002 4284 gptimer0ctrl general purpose timer #0 controller (gptimer0ctrl) usbotg 0x1002 4288 gptimer0ld general purpose timer #1 load (gptimer0ld) usbotg 0x1002 428c gptimer0ctrl general purpose timer #1 controller (gptimer0ctrl) usbotg 0x1002 4300 uh1_caplength capability register length (uh1_caplength) usbotg 0x1002 4302 uh1_hciversion host interface version (uh1_hciversion) usbotg 0x1002 4304 uh1_hcsparams host control structural parameters (uh1_hcsparams) usbotg 0x1002 4308 uh1_hccparams control c apability parameters (uh1_hccparams) usbotg 0x1002 4340 uh1_usbcmd usb command register (uh1_usbcmd) usbotg 0x1002 4344 uh1_usbsts usb status register (uh1_usbsts) usbotg 0x1002 4348 uh1_usbintr interrupt enable register (uh1_usbintr) usbotg 0x1002 434c uh1_frindex usb frame index (uh1_frindex) usbotg 0x1002 4354 uh1_periodiclistbase host controller frame list base address (uh1_periodiclistbase) usbotg 0x1002 4358 uh1_asynclistaddr host controller next asynch. address (uh1_asynclistaddr) usbotg 0x1002 4360 uh1_burstsize host controller embedded tt asynch. buffer status (uh1_burstsize) table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-30 freescale semiconductor usbotg 0x1002 4364 uh1_txfilltuning tx fifo fill tuning (uh1_txfilltuning) usbotg 0x1002 4380 reserved usbotg 0x1002 4838 reserved port status and control (uh1_portsc1) usbotg 0x1002 4384 uh1_portsc1 port status and control (uh1_portsc1) usbotg 0x1002 483c reserved reserved usbotg 0x1002 43a8 uh1_usbmode usb device mode (uh1_usbmode) usbotg 0x1002 4400 uh2_id id (uh2_id) usbotg 0x1002 4404 uh2_hwgeneral hardware general (uh2_hwgeneral) usbotg 0x1002 4408 uh2_hwhost host hardware parameters (uh2_hwhost) usbotg 0x1002 4410 uh2_hwtxbuf tx buffer hardware parameters (uh2_hwtxbuf) usbotg 0x1002 4414 uh2_hwrxbuf rx buffer hardware parameters (uh2_hwrxbuf) usbotg 0x1002 4480 gptimer0ld general purpose timer #0 load (gptimer0ld) usbotg 0x1002 4484 gptimer0ctrl general purpose timer #0 controller (gptimer0ctrl) usbotg 0x1002 4488 gptimer0ld general purpose timer #1 load (gptimer0ld) usbotg 0x1002 448c gptimer0ctrl general purpose timer #1 controller (gptimer0ctrl) usbotg 0x1002 4500 uh2_caplength capability register length (uh2_caplength) usbotg 0x1002 4502 uh2_hciversion host interface version (uh2_hciversion) usbotg 0x1002 4504 uh2_hcsparams host control structural parameters (uh2_hcsparams) usbotg 0x1002 4508 uh2_hccparams control capability parameters (uh2_hccparams) usbotg 0x1002 4540 uh2_usbcmd usb command register (uh2_usbcmd) usbotg 0x1002 4544 uh2_usbsts usb status register (uh2_usbsts) usbotg 0x1002 4548 uh2_usbintr interrupt enable register (uh2_usbintr) usbotg 0x1002 454c uh2_frindex usb frame index (uh2_frindex) usbotg 0x1002 4554 uh2_periodiclistbase host controller frame list base address (uh2_periodiclistbase) usbotg 0x1002 4558 uh2_asynclistaddr host controller next asynch. address (uh2_asynclistaddr) usbotg 0x1002 4560 uh2_burstsize host controller embedded tt asynch. buffer status (uh2_burstsize) usbotg 0x1002 4564 uh2_txfilltuning tx fifo fill tuning (uh2_txfilltuning) usbotg 0x1002 4570 ulpiview ulpi viewport (ulpiview) usbotg 0x1002 4580 reserved table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-31 usbotg 0x1002 4584 uh2_portsc1 port status and control (uh2_portsc1) usbotg 0x1002 45a8 uh2_usbmode usb device mode (uh2_usbmode) usbotg 0x1002 4600 usb_ctrl usb control register (usb_ctrl) usbotg 0x1002 4604 usb_otg_mirror usb otg mirror register (usb_otg_mirror) sahara2 0x1002 5000 ver_id sahara2 version id register sahara2 0x1002 5004 dsc_adr sahara2 descriptor address register sahara2 0x1002 5008 control sahara2 control register sahara2 0x1002 500c command sahara2 command register sahara2 0x1002 5010 stat sahara2 status register sahara2 0x1002 5014 err_stat sahara2 error status register sahara2 0x1002 5018 fault_adr sahara2 fault address register sahara2 0x1002 501c c_dsc_adr sahara2 current descriptor address register sahara2 0x1002 5020 i_dsc_adr sahara2 initial descriptor address register sahara2 0x1002 5024 buff_lvl sahara2 buffer level register sahara2 0x1002 5080 dsc_a location to store descriptor sahara2 0x1002 5084 dsc_b location to store descriptor sahara2 0x1002 5088 dsc_c location to store descriptor sahara2 0x1002 508c dsc_d location to store descriptor sahara2 0x1002 5090 dsc_e location to store descriptor sahara2 0x1002 5094 dsc_f location to store descriptor sahara2 0x1002 50a0 lnk_1_a location to store link data sahara2 0x1002 50a4 lnk_1_b location to store link data sahara2 0x1002 50a8 lnk_1_c location to store link data sahara2 0x1002 50b0 lnk_2_a location to store link data sahara2 0x1002 50b4 lnk_2_b location to store link data sahara2 0x1002 50b8 lnk_2_c location to store link data sahara2 0x1002 50c0 flow_ctrl sahara2 internal buffer and data-paths control register sahara2 0x1002 5100 skha_mode skha mode register sahara2 0x1002 5104 skha_key_size skha key size register sahara2 0x1002 5108 skha_data_size skha data size register sahara2 0x1002 510c skha_stat skha status register sahara2 0x1002 5110 skha_err_stat skha error status register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-32 freescale semiconductor sahara2 0x1002 5114 skha_end-of-message skha end-of-message register sahara2 0x1002 5140? 0x1002 517f skha_cxt skha context register sahara2 0x1002 5180? 0x1002 51ff skha key skha key register sahara2 0x1002 5200 mdha_mode mdha mode register sahara2 0x1002 5204 mdha_key_size mdha key size register sahara2 0x1002 5208 mdha_data_size mdha data size register sahara2 0x1002 520c mdha_stat mdha status register sahara2 0x1002 5210 mdha_err_stat mdha error status register sahara2 0x1002 5214 mdha_end-of-message mdha end-of-message register sahara2 0x1002 5240? 0x1002 5254 mdha_digest and length mdha message digest and length register sahara2 0x1002 5280? 0x1002 52ff mdha_key mdha keys sahara2 0x1002 5300 rng_mode rng mode register sahara2 0x1002 5308 rng_data_size rng data size register sahara2 0x1002 530c rng_stat rng status register sahara2 0x1002 5310 rng_error_stat rng error status register sahara2 0x1002 5314 rng_end-of-message rng end-of-message register sahara2 0x1002 5340? 0x1002 537f rng_verification rng verification register sahara2 0x1002 5380 rng_entropy rng entropy register sahara2 0x1002 5400? 0x1002 54ff data input buffer data input buffers sahara2 0x1002 5500? 0x1002 55ff data output buffer data output buffers sahara2 0x1002 5600? 0x1002 57ff sbox context sbox context emma_lt 0x1002 6000 pp_cntl pp control register emma_lt 0x1002 6004 pp_intrcntl pp interrupt control register emma_lt 0x1002 6008 pp_intrstatus pp interrupt status register emma_lt 0x1002 600c pp_source_y_ptr pp source ?y? frame data pointer register emma_lt 0x1002 6010 pp_source_cb_ptr pp source ?cb? frame data pointer register emma_lt 0x1002 6014 pp_source_cr_ptr pp source ?cr? frame data pointer register emma_lt 0x1002 6018 pp_dest_rgb_ptr pp destination ?rgb? frame start address register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-33 emma_lt 0x1002 601c pp_quantizer_ptr pp quantizer start address register emma_lt 0x1002 6020 pp_process_frame_para pp process frame parameter, width and height register emma_lt 0x1002 6024 pp_source_frame_width pp source frame width register emma_lt 0x1002 6028 pp_dest_display_width pp destination display width register emma_lt 0x1002 602c pp_dest_image_size pp destination image size register emma_lt 0x1002 6030 pp_dest_frame_fmt_cntl pp destination frame format control register emma_lt 0x1002 6034 pp resize table index reg pp resize table index register emma_lt 0x1002 6038 pp_csc_coeff_012 pp csc coefficient 0, 1, and 2 register emma_lt 0x1002 603c pp_csc_coeff_34 pp csc coefficient 3 and 4 register emma_lt 0x1002 6100? 0x1002 617c pp_resize_coef_tbl pp resize coefficient table register emma_lt 0x1002 6400 prp_cntl prp control register emma_lt 0x1002 6404 prp_intrcntl prp interrupt control register emma_lt 0x1002 6408 prp_intrstatus prp interrupt status register emma_lt 0x1002 640c prp_source_y_ptr prp source ?y? frame start address register emma_lt 0x1002 6410 prp_source_cb_ptr prp source ?cb? frame start address register emma_lt 0x1002 6414 prp_source_cr_ptr prp source ?cr? frame start address register emma_lt 0x1002 6418 prp_dest_rgb1_ptr prp de stination ?rgb? frame-1 start address register emma_lt 0x1002 641c prp_dest_rgb2_ptr prp destination ?rgb? frame-2 start address register emma_lt 0x1002 6420 prp_dest_y_ptr prp destination ?y? frame start address register emma_lt 0x1002 6424 prp_dest_cb_ptr prp destination ?cb? frame start address register emma_lt 0x1002 6428 prp_dest_cr_ptr prp destination ?cr? frame start address register emma_lt 0x1002 642c prp_source_frame_size prp source frame size register emma_lt 0x1002 6430 prp_ch1_line_stride prp channel-1 line stride register emma_lt 0x1002 6434 prp_src_pixel_format_cntl prp source pixel format control register emma_lt 0x1002 6438 prp_ch1_pixel_format_cntl prp ch1 pixel format control register emma_lt 0x1002 643c prp_ch1_out_image_size prp ch1 output image size register emma_lt 0x1002 6440 prp_ch2_out_image_size prp ch2 output image size register emma_lt 0x1002 6444 prp_source_line_stride prp source line stride register emma_lt 0x1002 6448 prp_csc_coeff_012 prp csc coefficients 0, 1, and 2 register emma_lt 0x1002 644c prp_csc_coeff_345 prp csc coefficients 3, 4, and 5 register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-34 freescale semiconductor emma_lt 0x1002 6450 prp_csc_coeff_678 prp csc coefficients 6, 7, and 8 register emma_lt 0x1002 6454 prp_ch1_hresize_coeff1 prp ch1 horizontal resize coefficients register emma_lt 0x1002 6458 prp_ch1_hresize_coeff2 prp ch1 horizontal resize coefficients register emma_lt 0x1002 645c prp_ch1_hresize_valid prp ch1 horizontal resize valid register emma_lt 0x1002 6460 prp_ch1_vresize_coeff1 prp ch1 vertical resize coefficients register emma_lt 0x1002 6464 prp_ch1_vresize_coeff2 prp ch1 vertical resize coefficients register emma_lt 0x1002 6468 prp_ch1_vresize_valid prp ch1 vertical resize valid register emma_lt 0x1002 646c prp_ch2_hresize_coeff1 prp ch2 horizontal resize coefficients register emma_lt 0x1002 6470 prp_ch2_hresize_coeff2 prp ch2 horizontal resize coefficients register emma_lt 0x1002 6474 prp_ch2_hresize_valid prp ch2 horizontal resize valid register emma_lt 0x1002 6478 prp_ch2_vresize_coeff1 prp ch2 vertical resize coefficients register emma_lt 0x1002 647c prp_ch2_vresize_coeff2 prp ch2 vertical resize coefficients register emma_lt 0x1002 6480 prp_ch2_vresize_valid prp ch2 vertical resize valid register pllclk 0x1002 7000 cscr clock source control register pllclk 0x1002 7004 mpctl0 mpll control register 0 pllclk 0x10027008 mpctl1 mpll control register 1 pllclk 0x1002700c spctl0 spll control register 0 pllclk 0x10027010 spctl1 spll control register 1 pllclk 0x10027014 osc26mctl oscillator 26m register pllclk 0x10027018 pcdr0 peripheral clock divider register 0 pllclk 0x1002701c pcdr1 peripheral clock divider register 1 pllclk 0x10027020 pccr0 peripheral clock control register 0 pllclk 0x10027024 pccr1 peripheral clock control register 1 pllclk 0x10027028 ccsr clock control status register pllclk 0x1002702c pmctl pmos switch control register pllclk 0x10027030 pmcount pmos switch counter register pllclk 0x10027034 wkgdctl wakeup guard mode control register sysctrl 0x10027800 cid chip id register sysctrl 0x10027814 fmcr function multiplexing control register sysctrl 0x10027818 gpcr global peripheral control register sysctrl 0x1002781c wbcr well bias control register sysctrl 0x10027820 dscr1 driving strength control register 1 sysctrl 0x10027824 dscr2 driving strength control register 2 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-35 sysctrl 0x10027828 dscr3 driving strength control register 3 sysctrl 0x1002782c dscr4 driving strength control register 4 sysctrl 0x10027830 dscr5 driving strength control register 5 sysctrl 0x10027834 dscr6 driving strength control register 6 sysctrl 0x10027838 dscr7 driving strength control register 7 sysctrl 0x1002783c dscr8 driving strength control register 8 sysctrl 0x10027840 dscr9 driving strength control register 9 sysctrl 0x1002 7844 dscr10 driving strength control register 10 sysctrl 0x1002 7848 dscr11 driving strength control register 11 sysctrl 0x1002 784c dscr12 driving strength control register 12 sysctrl 0x1002 7850 dscr13 driving strength control register 13 sysctrl 0x1002 7854 pscr pull strength control register sysctrl 0x1002 7858 pcsr priority control and select register sysctrl 0x1002 7860 pmcr power management control register sysctrl 0x1002 7864 dcvr0 dptc comparator value register 0 sysctrl 0x1002 7868 dcvr? dptc comparator value register 1 sysctrl 0x1002 786c dcvr2 dptc comparator value register 2 sysctrl 0x1002 7870 dcvr3 dptc comparator value register 3 iim 0x1002_8000 stat status register iim 0x1002_8004 statm status irq mask register iim 0x1002_8008 err module errors register iim 0x1002_800c emask error irq mask register iim 0x1002_8010 fctl fuse control register iim 0x1002_8014 ua upper address register iim 0x1002_8018 la lower address register iim 0x1002_801c sdat explicit sense data register iim 0x1002_8020 prev product revision register iim 0x1002_8024 srev silicon revision register iim 0x1002_8028 prog_p program protection register iim 0x1002_802c scs0 software_controllable signals register 0 iim 0x1002_8030 scs1 software_controllable volatile hardware?visible signals register (1?3) iim 0x1002_8034 scs2 iim 0x1002_8038 scs3 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-36 freescale semiconductor iim 0x1002_803c fbac0 fuse bank 0 access protection register iim 0x1002_8804 word1_bank0 word 1 of fusebank 0 iim 0x1002_8808 word2_bank0 word 2 of fusebank 0 iim 0x1002_880c word3_bank0 word 3 of fusebank 0 iim 0x1002_8810 word4_bank0 word 4 of fusebank 0 iim 0x1002_8814? 0x1002_8828 suid silicon_unique_id[47:0] iim 0x1002_882c? 0x1002_887c scc_key scc_key[167:0] iim 0x1002_8c00 fbac1 fuse bank 0 access protection register iim 0x1002_8c04? 0x1002_8c18 mac_addr mac address of ethernet iim 0x1002_8c1c? 0x1002_8c7c reserved reserved for future use rtic 0x1002 a000 rticsr rtic status register rtic 0x1002 a004 rticcmdr rtic command register rtic 0x1002 a008 rticcntlr rtic control register rtic 0x1002 a00c rtictr rtic throttle register rtic 0x1002 a010 rticamsar1 rtic memory a start address register 1 rtic 0x1002 a014 rticamlr1 rtic memory a len register 1 rtic 0x1002 a0018 rticamsar2 rtic memory a start address register 2 rtic 0x1002 a01c rticamlr2 rtic memory a len register 2 rtic 0x1002 a030 rticbmsar1 rtic memory b start address register 1 rtic 0x1002 a034 rticbmlr1 rtic memory b len register 1 rtic 0x1002 a038 rticbmsar2 rtic memory b start address register 2 rtic 0x1002 a003c rticbmlr2 rtic memory b len register 2 rtic 0x1002 a050 rticcmsar1 rtic memory c start address register 1 rtic 0x1002 a054 rticcmlr1 rtic memory c len register 1 rtic 0x1002 a058 rticcmsar2 rtic memory c start address register 2 rtic 0x1002 a05c rticcmlr2 rtic memory c len register 2 rtic 0x1002 a070 rticdmsar1 rtic memory d start address register 1 rtic 0x1002 a074 rticdmlr1 rtic memory d len register 1 rtic 0x1002 a078 rticdmsar2 rtic memory d start address register 2 rtic 0x1002 a07c rticdmlr2 rtic memory d len register 2 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-37 rtic 0x1002 a090 rticfar rtic fault address register rtic 0x1002 a094 rticwr rtic watchdog register rtic 0x1002 a0a0 rticamhr1 rtic memory a hash result [159:128] rtic 0x1002 a0a4 rticamhr2 rtic memory a hash result [127:96] rtic 0x1002 a0a8 rticamhr3 rtic memory a hash result [95:64] rtic 0x1002 a0ac rticamhr4 rtic memory a hash result [63:32] rtic 0x1002 a0b0 rticamhr5 rtic memory a hash result [31:0] rtic 0x1002 a0c0 rticbmhr1 rtic memory b hash result [159:128] rtic 0x1002 a0c4 rticbmhr2 rtic memory b hash result [127:96] rtic 0x1002 a0c8 rticbmhr3 rtic memory b hash result [95:64] rtic 0x1002 a0cc rticbmhr4 rtic memory b hash result [63:32 rtic 0x1002 a0d0 rticbmhr5 rtic memory b hash result [31:0] rtic 0x1002 a0e0 rticcmhr1 rtic memory c hash result [159:128] rtic 0x1002 a0e4 rticcmhr2 rtic memory c hash result [127:96] rtic 0x1002 a0e8 rticcmhr3 rtic memory c hash result [95:64] rtic 0x1002 a0ec rticcmhr4 rtic memory c hash result [63:32] rtic 0x1002 a0f0 rticcmhr5 rtic memory c hash result [31:0] rtic 0x1002 a100 rticdmhr1 rtic memory d hash result [159:128] rtic 0x1002 a104 rticdmhr2 rtic memory d hash result [127:96] rtic 0x1002 a108 rticdmhr3 rtic memory d hash result [95:64] rtic 0x1002 a10c rticdmhr4 rtic memory d hash result [63:32] rtic 0x1002 a110 rticdmhr5 rtic memory d hash result [31:0] fec 0x1002_b004 eir interrupt event register fec 0x1002_b008 eimr interrupt mask register fec 0x1002_b010 rdar receive descriptor active register fec 0x1002_b014 tdar transmit descriptor active register fec 0x1002_b024 ecr ethernet control register fec 0x1002_b040 mmfr mii management frame register fec 0x1002_b044 mscr mii speed control register fec 0x1002_b064 mibc mib control/status register fec 0x1002_b084 rcr receive control register fec 0x1002_b0c4 tcr transmit control register fec 0x1002_b0e4 palr physical address low register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-38 freescale semiconductor fec 0x1002_b0e8 paur physical address high+ type field fec 0x1002_b0ec opd opcode + pause duration fec 0x1002_b118 iaur upper 32 bits of individual hash table fec 0x1002_b11c ialr lower 32 bits of individual hash table fec 0x1002_b120 gaur upper 32 bits of group hash table fec 0x1002_b124 galr lower 32 bits of group hash table fec 0x1002_b144 tfwr transmit fifo watermark fec 0x1002_b14c frbr fifo receive bound register fec 0x1002_b150 frsr fifo receive fifo start registers fec 0x1002_b180 erdsr pointer to receive descriptor ring fec 0x1002_b184 etdsr pointer to transmit descriptor ring fec 0x1002_b188 emrbr maximum receive buffer size fec 0x1002_b200 rmon_t_drop count of frames not counted correctly fec 0x1002_b204 rmon_t_packets rmon tx packet count fec 0x1002_b208 rmon_t_bc_pkt rmon tx broadcast packets fec 0x1002_b20c rmon_t_mc_pkt rmon tx multicast packets fec 0x1002_b210 rmon_t_crc_align rmon tx packets w crc/align error fec 0x1002_b214 rmon_t_undersize rmon tx packets < 64 bytes, good crc fec 0x1002_b218 rmon_t_oversize rmon tx packets > max_fl bytes, good crc fec 0x1002_b21c rmon_t_frag rmon tx packets < 64 bytes, bad crc fec 0x1002_b220 rmon_t_jab rmon tx packets > max_fl bytes, bad crc fec 0x1002_b224 rmon_t_col rmon tx collision count fec 0x1002_b228 rmon_t_p64 rmon tx 64 byte packets fec 0x1002_ 22c rmon_t_p65to127 rmon tx 65 to 127 byte packets fec 0x1002_b230 rmon_t_p128to255 rmon tx 128 to 255 byte packets fec 0x1002_b234 rmon_t_p256to511 rmon tx 256 to 511 byte packets fec 0x1002_b238 rmon_t_p512to1023 rmon tx 512 to 1023 byte packets fec 0x1002_b23c rmon_t_p1024to2047 rmon tx 1024 to 2047 byte packets fec 0x1002_b240 rmon_t_p_gte2048 rmon tx packets w > 2048 bytes fec 0x1002_b244 rmon_t_octets rmon tx octets fec 0x1002_b248 ieee_t_drop count of frames not counted correctly fec 0x1002_b24c ieee_t_frame_ok frames transmitted ok fec 0x1002_b250 ieee_t_1col frames transmitted with single collision table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-39 fec 0x1002_b254 ieee_t_mcol frames transmitted with multiple collisions fec 0x1002_b258 ieee_t_def frames transmitted after deferral delay fec 0x1002_b25c ieee_t_lcol frames transmitted with late collision fec 0x1002_b260 ieee_t_excol frames transmitted with excessive collisions fec 0x1002_b264 ieee_t_macerr frames transmitted with tx fifo underrun fec 0x1002_b268 ieee_t_cserr frames transmitted with carrier sense error fec 0x1002_b26c ieee_t_sqe frames transmitted with sqe error fec 0x1002_b270 ieee_t_fdxfc flow control pause frames transmitted fec 0x1002_b274 ieee_t_octets_ok octet count for frames transmitted w/o error fec 0x1002_b284 rmon_r_packets rmon rx packet count fec 0x1002_b288 rmon_r_bc_pkt rmon rx broadcast packets fec 0x1002_b28c rmon_r_mc_pkt rmon rx multicast packets fec 0x1002_b290 rmon_r_crc_align rmon rx packets w crc/align error fec 0x1002_b294 rmon_r_undersize rmon rx packets < 64 bytes, good crc fec 0x1002_b298 rmon_r_oversize rmon rx packets > max_fl bytes, good crc fec 0x1002_b29c rmon_r_frag rmon rx packets < 64 bytes, bad crc fec 0x1002_b2a0 rmon_r_jab rmon rx packets > max_fl bytes, bad crc fec 0x1002_b2a4 rmon_r_resvd_0 reserved fec 0x1002_b2a8 rmon_r_p64 rmon rx 64 byte packets fec 0x1002_b2ac rmon_r_p65to127 rmon rx 65 to 127 byte packets fec 0x1002_b2b0 rmon_r_p128to255 rmon rx 128 to 255 byte packets fec 0x1002_b2b4 rmon_r_p256to511 rmon rx 256 to 511 byte packets fec 0x1002_b2b8 rmon_r_p512to1023 rmon rx 512 to 1023 byte packets fec 0x1002_b2bc rmon_r_p1024to2047 rmon rx 1024 to 2047 byte packets fec 0x1002_b2c0 rmon_r_p_gte2048 rmon rx packets w > 2048 bytes fec 0x1002_b2c4 rmon_r_octets rmon rx octets fec 0x1002_b2c8 ieee_r_drop count of frames not counted correctly fec 0x1002_b2cc ieee_r_frame_ok frames received ok fec 0x1002_b2d0 ieee_r_crc frames received with crc error fec 0x1002_b2d4 ieee_r_align frames received with alignment error fec 0x1002_b2d8 ieee_r_macerr receive fifo overflow count fec 0x1002_b2dc ieee_r_fdxfc flow control pause frames received fec 0x1002_b2e0 ieee_r_octets_ok octet count for frames rcvd w/o error table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-40 freescale semiconductor scc 0x1002_c000 red_start scm red memory start addr register scc 0x1002_c004 black_start scm black memory start addr register scc 0x1002_c008 length scm encrypt/decrypt data length register scc 0x1002_c010 scm_stat scm status register scc 0x1002_c014 scm_error scc error status register scc 0x1002_c018 interrupt_control scc interrupt control register scc 0x1002_c01c configuration scc configuration register scc 0x1002_c020 init_vector 0 initial vector 0 register scc 0x1002_c024 init_vector1 initial vector 1 register scc 0x1002_c400 ? 0x1002_c7ff scm_red_mem scm red memory scc 0x1002_c800 ? 0x1002_cbff scm_black_mem scm black memory scc 0x1002_d000 smn_stat smn status register scc 0x1002_d004 smn_command smn command register scc 0x1002_d008 seq_start sequence start value register scc 0x1002_d00c seq_end sequence end value register scc 0x1002_d010 seq_check sequence check register scc 0x1002_d014 bit_count bit count register scc 0x1002_d018 bit_bank_inc_size bit bank increment size register scc 0x1002_d01c bit_bank_dec bit bank decrement scc 0x1002_d020 cmp_size compare size register scc 0x1002_d024 plaintext_check plaintext check register scc 0x1002_d028 cipher check ciphertext check register scc 0x1002_d02c timer iv timer initial vector register scc 0x1002_d030 timer control timer control register scc 0x1002_d034 debug detector status debug port detection status register scc 0x1002_d038 timer timer register etb reg 0x1003_b000 etb_id etb identify register etb reg 0x1003_b004 etb_ram_depth etb ram depth register etb reg 0x1003_b008 etb_ram_width etb ram width register etb reg 0x1003_b00c etb_status etb status register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-41 etb reg 0x1003_b010 etb_data etb data register etb reg 0x1003_b014 etb_read_pointer etb read pointer register etb reg 0x1003_b018 etb_write_pointer etb write pointer register etb reg 0x1003_b01c etb_trigger_counter etb trigger counter register etb reg 0x1003_b020 etb_control etb control register jam 0x1003_e000 jam_arm9p_gpr0 jam arm9p general purpose register 0 jam 0x1003_e010 jam_arm9p_gpr4 jam arm9p general purpose register 4 max 0x1003_f000 mpr0 master priority register for slave port 0 max 0x1003_f100 mpr1 master priority register for slave port 1 max 0x1003_f200 mpr2 master priority register for slave port 2 max 0x1003_f004 ampr0 alternate master priority register for slave port 0 max 0x1003_f104 ampr1 alternate master priority register for slave port 1 max 0x1003_f204 ampr2 alternate master priority register for slave port 2 max 0x1003_f010 sgpcr0 general purpose control register for slave port 0 max 0x1003_f110 sgpcr1 general purpose control register for slave port 1 max 0x1003_f210 sgpcr2 general purpose control register for slave port 2 max 0x1003_f014 asgpcr0 alternate sgpcr for slave port 0 max 0x1003_f114 asgpcr1 alternate sgpcr for slave port 1 max 0x1003_f214 asgpcr2 alternate sgpcr for slave port 2 max 0x1003_f800 mgpcr0 general purpose control register for master port 0 max 0x1003_f900 mgpcr1 general purpose control register for master port 1 max 0x1003_fa00 mgpcr2 general purpose control register for master port 2 max 0x1003_fb00 mgpcr3 general purpose control register for master port 3 max 0x1003_fc00 mgpcr4 general purpose control register for master port 4 max 0x1003_fd00 mgpcr5 general purpose control register for master port 5 aitc 0x1004_0000 intcntl interrupt control register aitc 0x1004_0004 nimask normal interrupt mask register aitc 0x1004_0008 intennum interrupt enable number register aitc 0x1004_000c intdisnum interrupt disable number register aitc 0x1004_0010 intenableh interrupt enable register high aitc 0x1004_0014 intenablel interrupt enable register low aitc 0x1004_0018 inttypeh interrupt type register high aitc 0x1004_001c inttypel interrupt type register low table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-42 freescale semiconductor aitc 0x1004_0020 nipriority7 normal interrupt priority level register 7 aitc 0x1004_0024 nipriority6 normal interrupt priority level register 6 aitc 0x1004_0028 nipriority5 normal interrupt priority level register 5 aitc 0x1004_002c nipriority4 normal interrupt priority level register 4 aitc 0x1004_0030 nipriority3 normal interrupt priority level register 3 aitc 0x1004_0034 nipriority2 normal interrupt priority level register 2 aitc 0x1004_0038 nipriority1 normal interrupt priority level register 1 aitc 0x1004_003c nipriority0 normal interrupt priority level register 0 aitc 0x1004_0040 nivecsr normal interrupt vector and status register aitc 0x1004_0044 fivecsr fast interrupt vector and status register aitc 0x1004_0048 intsrch interrupt source register high aitc 0x1004_004c intsrcl interrupt source register low aitc 0x1004_0050 intfrch interrupt force register high aitc 0x1004_0054 intfrcl interrupt force register low aitc 0x1004_0058 nipndh normal interrupt pending register high aitc 0x1004_005c nipndl normal interrupt pending register low aitc 0x1004_0060 fipndh fast interrupt pending register high aitc 0x1004_0064 fipndl fast interrupt pending register low csi 0x8000_0000 csicr1 csi control register 1 csi 0x8000_0004 csicr2 csi control register 2 csi 0x8000_0008 csisr csi status register csi 0x8000_000c csistatr csi statistic fifo register csi 0x8000_0010 csirxr csi rxfifo register csi 0x8000_0014 csirxcnt csi rx count register csi 0x8000_0018 csidebug csi debug register csi 0x8000_001c csicr3 csi control register 3 ata 0x8000_1000 time_config0 ata timing parameter 0. ata 0x8000_1004 time_config1 ata timing parameter 1. ata 0x8000_1008 time_config2 ata timing parameter 2. ata 0x8000_100c time_config3 ata timing parameter 3. ata 0x8000_1010 time_config4 ata timing parameter 4. ata 0x8000_1014 time_config5 ata timing parameter 5. ata 0x8000_1018 fifo_data_32 32-bit wide data port to/from fifo table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-43 ata 0x8000_101c fifo_data_16 16-bit wide data port to/from fifo ata 0x8000_1020 fifo_fill fifo filling in halfwords ata 0x8000_1024 ata_control ata interface control register ata 0x8000_1028 int_pending interrupt pending register ata 0x8000_102c int_enable interrupt enable register ata 0x8000_1030 int_clear interrupt clear register ata 0x8000_1034 fifo_alarm fifo alarm threshold ata 0x8000_10a0 dctr drive data register ata 0x8000_10a4 ddtr drive features register ata 0x8000_10a8 dftr drive sector count register ata 0x8000_10ac dscr drive sector number register ata 0x8000_10b0 dsnr drive cylinder low register ata 0x8000_10b4 dclr drive cylinder high register ata 0x8000_10b8 dchr drive device head register ata 0x8000_10bc ddhr drive command register (w)/ drive status register (r) ata 0x8000_10d8 dcdr drive alternate status register (w)/ drive control register (r) nfc 0xd800_0e00 nfc_bufsize internal sram size nfc 0xd800_0e02 reserved reserved nfc 0xd800_0e04 ram_buffer_address buffer number for page data transfer to/ from flash memory nfc 0xd800_0e06 nand_flash_add nand flash address nfc 0xd800_0e08 nand_flash_cmd nand flash command nfc 0xd800_0e0a nfc_configuration nfc internal buffer lock control nfc 0xd800_0e0c ecc_status_result controller status/result of flash operation nfc 0xd800_0e0e ecc_rslt_main_area ecc error position of main area data error nfc 0xd800_0e10 ecc_rslt_spare_area ecc error position of spare area data error nfc 0xd800_0e12 nf_wr_prot nand flash write protection nfc 0xd800_0e14 unlock_start_blk_add start address for write protection unlock nfc 0xd800_0e16 unlock_end_blk_add end address for write protection unlock nfc 0xd800_0e18 nand_flash_wr_pr_st current nand flash write protection status nfc 0xd800_0e1a nand_flash_config1 nand flash operation configuration 1 nfc 0xd800_0e1c nand_flash_config2 nand flash operation configuration 2 table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-44 freescale semiconductor esdctl 0xd800_1000 esd_esdctl0 sdram/mddr 0 control register esdctl 0xd800_1004 esd_esdcfg0 sdram/mddr 0 timing config register esdctl 0xd800_1008 esd_esdctl1 sdram/mddr 1 control register esdctl 0xd800_100c esd_esdcfg1 sdram/mddr 1 timing config register esdctl 0xd800_1010 esd_esdmisc sdram/mddr miscellaneous register weim 0xd800_2000 cs0u chip select 0 upper control register weim 0xd800_2004 cs0l chip select 0 lower control register weim 0xd800_2008 cs0a chip select 0 addition control register weim 0xd800 2010 cs1u chip select 1 upper control register weim 0xd800_2014 cs1l chip select 1 lower control register weim 0xd800_2018 cs1a chip select 1 addition control register weim 0xd800_2020 cs2u chip select 2 upper control register weim 0xd800_2024 cs2l chip select 2 lower control register weim 0xd800_2028 cs2a chip select 2 addition control register weim 0xd800_2030 cs3u chip select 3 upper control register weim 0xd800_2034 cs3l chip select 3 lower control register weim 0xd800_2038 cs3a chip select 3 addition control register weim 0xd800_2040 cs4u chip select 4 upper control register weim 0xd800_2044 cs4l chip select 4 lower control register weim 0xd800_2048 cs4a chip select 4 addition control register weim 0xd800_2050 cs5u chip select 5 upper control register weim 0xd800_2054 cs5l chip select 5 lower control register weim 0xd800_2058 cs5a chip select 5 addition control register weim 0xd800_2060 eim eim configuration register m3if 0xd800_3000 m3if_ctl m3if control register m3if 0xd800_3028 m3if_scfg0 m3if snooping configuration register 0 m3if 0xd800_302c m3if_scfg1 m3if snooping configuration register 1 m3if 0xd800_3030 m3if_scfg2 m3if snooping configuration register 2 m3if 0xd800_3034 m3if_ssr0 m3if snooping status register 0 m3if 0xd800_3038 m3if_ssr1 m3if snooping status register 1 m3if 0xd800_3040 m3ifmlwe0 m3if master lock weim cs0 register m3if 0xd800_3044 m3ifmlwe1 m3if master lock weim cs1 register m3if 0xd800_3048 m3ifmlwe2 m3if master lock weim cs2 register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 2-45 m3if 0xd800_304c m3ifmlwe3 m3if master lock weim cs3 register m3if 0xd800_3050 m3ifmlwe4 m3if master lock weim cs4 register m3if 0xd800_3054 m3ifmlwe5 m3if master lock weim cs5 register pcmcia 0xd800_4000 pcmcia_pipr pcmcia input pins register pcmcia 0xd800_4004 pcmcia_pscr pcmcia status changed register pcmcia 0xd800_4008 pcmcia_per pcmcia enable register pcmcia 0xd800_400c pcmcia_pbr0 pcmcia base register 0 pcmcia 0xd800_4010 pcmcia_pbr1 pcmcia base register 1 pcmcia 0xd800_4014 pcmcia_pbr2 pcmcia base register 2 pcmcia 0xd800_4018 pcmcia_pbr3 pcmcia base register 3 pcmcia 0xd800_401c pcmcia_pbr4 pcmcia base register 4 pcmcia 0xd800_4020 pcmcia_pbr5 pcmcia base register 5 pcmcia 0xd800_4024 pcmcia_pbr6 pcmcia base register 6 pcmcia 0xd800_4028 pcmcia_por0 pcmcia option register 0 pcmcia 0xd800_402c pcmcia_por1 pcmcia option register 1 pcmcia 0xd800_4030 pcmcia_por2 pcmcia option register 2 pcmcia 0xd800_4034 pcmcia_por3 pcmcia option register 3 pcmcia 0xd800_4038 pcmcia_por4 pcmcia option register 4 pcmcia 0xd800_403c pcmcia_por5 pcmcia option register 5 pcmcia 0xd800_4040 pcmcia_por6 pcmcia option register 6 pcmcia 0xd800_4044 pcmcia_pofr0 pcmcia offset register 0 pcmcia 0xd800_4048 pcmcia_pofr1 pcmcia offset register 1 pcmcia 0xd800_404c pcmcia_pofr2 pcmcia offset register 2 pcmcia 0xd800_4050 pcmcia_pofr3 pcmcia offset register 3 pcmcia 0xd800_4054 pcmcia_pofr4 pcmcia offset register 4 pcmcia 0xd800_4058 pcmcia_pofr5 pcmcia offset register 5 pcmcia 0xd800_405c pcmcia_pofr6 pcmcia offset register 6 pcmcia 0xd800_4060 pcmcia_pgcr pcmcia general control register pcmcia 0xd800_4064 pcmcia_pgsr pcmcia general status register table 2-8. register map (continued) module name address register name description system memory and register map MCIMX27 multimedia applications processor reference manual, rev. 0.2 2-46 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-1 chapter 3 clocks, power management, and reset control 3.1 introduction there are two clock controller modules in the i. mx27 multimedia applications processor: the arm9 platform clock controller and the pll clock controll er module (ccm), which produces the clock signals used and distributed by the arm9 platform clock controller. ? arm9 platform clock controller?the primary f unction of the arm9 platform clock controller is to take the clock signals from the pll clock controller and distribute them to various peripherals on the arm9 platform. the clock contro l module contains the logic to turn clocks on or off and to determine when the arm9 platform?s clock can be turned off. this module also synchronizes the jtag interface to the clk domain. ? pll clock controller?this module generates clock signals used throughout the i.mx27 chip and external peripherals. the pll clock controller al so serves as the interface between the arm9 platform and the peripherals on the i.mx27 device. the arm9 platform clock controller is not a user-programmable or accessible module, whereas the pll clock controller is accessible?therefore, only the p ll clock controller is described in this chapter. 3.2 clock controller architecture block diagram there are two dplls in the pll clock controller ?the mcu/system pll (mpll) and the serial peripheral pll (spll), which uses di gital and mixed analog/digital circ uits to provide clock frequencies for wireless communication and other applications. th e mpll primarily generates the clk signal to the arm9 and hclk (also called system clock) for the sy stem bus and for most of the on-chip peripherals, including the lcdc pixel clock and the nand flash controller clock. the spll produces the primary clock to the clock dividers for usb otg, ssi1, and ssi2. both mpll and spll accept either the output of the fpm or the osc26m as a source from which to generate the required frequencies for the arm9 platfo rm and/or peripherals us ing a fractional frequency multiplication method. detailed information about th e calculation of the dpll settings is shown in section 3.2.2, ?output frequency calculations .? to produce the wide range of on-chip clock frequenc ies required by the i.mx27 processor, the core clock generator uses a two-stage phase locked loop. the fi rst stage is a frequency pre-multiplier pll (fpm), which multiplies the input frequency by a factor of 1024. if the input crystal frequency is 32.768 khz, the premultiplier multiplies it by a factor of 1024 to 33.554 mhz (32.768 mhz for a 32.0 khz crystal). the output of the fpm is one of the clock sources for the mpll and spll. power management in the i.mx27 device is accomplished by controlling the clock output of the mpll and spll units. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-2 freescale semiconductor the distribution of clocks in the i.mx27 proce ssor is shown in the general block diagram, figure 3-1 . there are two external clock sources to the pll clock controller, as follows: ? 32 khz external crystal ? 26 mhz external source/crystal settings in the clock source control register (cscr) are used to independently configure the external clock sources applied to the mpll and spll. figure 3-1. i.mx27 clock distribution block diagram (1 of 2) osc 32k fpm clk 32k fpm en bypass[1] osc 26m osc26m dis bypass[0] 1 0 0 1 div 1p5 bypass[0] osc26m div1p5 1 0 mpllclk sel bypass[1] mpll 1 0 upllclk sel bypass[1] upll upll clk 1 0 bypass[2] ext 60m mpll clk spll spll clk clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-3 figure 3-2. i.mx27 clock distribution block diagram (2 of 2) table 3-1. pll clock controller signal descriptions signal names description clk fast clock used only by arm9 platform for internal operations, such as executing instructions from the cache. can be gated during doze and sleep mode when all the criteria are met to enter a low power. hclk system clock. appears as the bclk input to the cpu and the hclk to the system. this is a continuous clock (when the system is not in sleep mode). it can be gated during doze and sleep mode when all the criteria are met to enter a low power. hclken used to signify the rising edge of clk that corresponds to the rising edge of hclk. it is used by the arm9 platform only. clk60m 60 mhz clock for the usb otg module ssi1clk divided clock output for the ssi1 module ssi2clk divided clock output for the ssi2 module nfcclk divided clock output for the nand flash controller module h264cclk divided clock output for the h264 module mshcclk divided clock output for the mshc module mcu dpll ref cloc k 2x clock port div3 div2 ahbdiv ip g d iv 0 1 armdiv arm src per1div per2div per3div per4div arm div: ahb div: per 1 div : per2 div: per3 d iv : per4 div : per2div per3div per4div ssi1div ssi1 d iv : ssi2 d iv : mshc div: ssi2div h264div usb dpll 0 1 0 1 mshcdiv nfc div: nfcdiv h2 6 4 d iv : 0 1 0 1 usbdiv usb div: arm clk ahb clk ip g c l k uart/gpt/pw m lcdc sdhc/cspi csi nfc ssi1 ssi2 mshc h264 usb 1 0 ext 266m 0 1 by pa ss[2] ext 266m by pa ss[2] mpll spll clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-4 freescale semiconductor 3.2.1 high frequency clock source and distribution two dplls?mpll and spll?on the i.mx27 device ar e used to generate two separate clock frequencies from either the fre quency pre-multiplier (fpm) or an external high frequency source (clk26m). the clock source for each dpll is indivi dually selected using bits in the clock source control register (cscr). the mcu/system pll (mpll) is configured by the mpctl registers (mpc tl0, mpctl1) to produce system clock signals that are divided down to output the fclk (for example 266 mhz) and the hclk (for example, 133 mhz) clock signals. mpll serves as the clock source for the perclk4, perdiv3, perdiv2, and perdiv1. fclk serves as the clock source for the nfcdiv divider. these dividers produce the clock signals for the following: ? nand flash controller (nfc) ? peripheral set 1 (perclk1): uart, timer, and pwm ? peripheral set 2 (perclk2): sdhc and cspi ? lcdc pixel clock (perclk3) ? csi (perclk4) serial peripheral pll (spll) is configured by sp ctl registers (spctl0, spctl1) and produces input signals for the usbdiv, ssi1div, ssi2div, h264d iv, and mshcdiv dividers, which generate clock signals for serial peripherals that require special clock frequencies: ? clk60m?for the usb otg ? ssi1clk?clock signal for ssi1 ? ssi2clk?clock signal for ssi2 ? h264cclk?clock signal for h264 ? mshcclk?clock signal for mshc the clock source for the ssi1div and ssi2div dividers can be the mpll or spll. source selection is controlled by the respective bits in the clock source control register (cscr). perclk1 divided clock output for peripheral set 1 (uart, timer, pwm) perclk2 divided clock output for peripheral set 2 (sdhc, cspi) perclk3 divided clock output for the lcdc perclk4 divided clock output for the csi clko selected internal clock output to the clko pin a9p_clk_off control signal from the arm9 platform clock controller table 3-1. pll clock controller signal descriptions (continued) signal names description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-5 3.2.2 output frequency calculations both dplls produce a high frequency clock that exhi bits a low frequency jitter and a low phase jitter. the dpll output clock frequency (f dpll ) is determined by the equation 3-1 : f dpll = 2f ref mfi + mfn / (mfd+1) pd+1 eqn. 3-1 where: ?f ref is the reference frequency (1024 32.768 khz, 1024 32.0 khz, or 26 mhz). ? mfi is an integer part of a multiplication factor (mf). ? mfn is the numerator and mfd is the denominator of the mf. ? pd is the predivider factor. note in bootstrap mode, the pll register s assume a source clock of 32.768 khz. if using bootstrap mode, use a 32.768 khz crystal. 3.3 power management the pll clock controller module is designed with cloc k control at various stages of clock supply to achieve optimum power savings. the operation of the pll and clock controller at different stages of power management is described in the following sections. 3.3.1 pll operation at power-up the crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. while system reset remains asserted the pll begins th e lockup sequence and locks 1 ms after the crystal oscillator becomes stable. both dplls are enabled on power-up. the system reset is held asserted by the pll clock controller for 300 ms + 14 cycles of the 32 khz, as shown in figure 3-17 . 3.3.2 pll operation at wake-up when the device is awakened from sleep mode by a wake-up event, the dpll locks within 350 s. the crystal oscillator is always on afte r initial power-up, so crystal startup time is not a factor. the pll output clock starts operating as soon as it achieves lock. 3.3.3 i.mx27 processor low-power modes the i.mx27 processor provides two power saving modes ? doze mode and sleep mode: ? in doze mode, the arm9 executes a wait for inte rrupt (wfi) instruction. system clocks are still active. ? in sleep mode, the arm9 executes a wait for in terrupt (wfi) instruction. the output of the mpll and spll are shut down and only the 32 khz clock is running. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-6 freescale semiconductor these modes are controlled by the clock control logi c and a sequence of cpu instructions. most of the peripheral modules can enable or disable the incomi ng clock signal through clock gating circuitry from the peripheral bus. each module has a module enable bit wh ich, when disabled, disabl es the operational clock to the module. the i.mx27 pll clock controller provides the low- power mode information to the watchdog (wdog) module. 3.3.3.1 doze mode doze mode is defined as when the arm9 executes a wait for an interrupt instruction, after which the buffered clock supply to the mcu is turned off. the sequence of operation to set the system to doze mode is as follows: 1. enable desired interrupts for wake-up from doze mode. 2. disable watchdog timer interrupt. 3. execute wait-for-interrupt instruction. the arm9 executes a wait for interrupt instruction if all required conditions ar e met (no irq, fiq, or debug requests pending), the arm9 platform generates an a9p_clk_off signal to the pll clock controller module. the clk signal to the mcu is immediately turned off when the a9p_clk_off signal goes active. clk_always and system bus (hclk) re main running. hclk is required by the cross bar switch within the arm9 platform for continuous operation of peripheral modules. when an unmasked interrupt event occurs, the clk signal to the arm9 is re-enabled. 3.3.3.2 sleep mode sleep mode is defined as when all the dplls cloc k outputs are disabled. a sequence of operations and criteria must be satisfied before the system turn s off the mpll and spll. the sleep mode sequence is initiated when the mpen bit in the cscr register is cleared disabling the mpll. this action also automatically turns off the spll. the sequence to put the system into sleep mode is as follows: 1. disable ahb peripherals from bus accesses. 2. enable desired interrupts to be used for system wake-up. 3. disable watchdog timer interrupt. 4. set the required value to the sd_cnt (cscr register) for shutdown countdown. 5. disable the mpll by clearing th e mpen bit (cscr register). 6. execute wait-for-interrupt instruction. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-7 the example of programming setup to enter sleep mode is as follows: code example 3-1. programming setup for entering sleep mode mrs r0, cpsr ; enable interrupts and r1, r0, #(enable_irq+enable_fiq+mode_bits) msr cpsr_c, r1 ldr r3, =wdg_baseaddr ; disable wdg timer ldrh r4, [r3, #0x0] orr r4, r4, #0x00000001 strh r4, [r3, #0x0] ldr r1, =crm_baseaddr ; set sdcnt to ?01? ldr r2, [r1, #0x0] orr r2, r2, #0x0100_0000 str r2, [r1, #0x0] bic r2, r2, #0x00000001 ; disable mpen str r2, [r1, #0x0] ldr r1, 0x00000000 mcr p15, 0, r1, c7, c0, 4 ; wfi the mpll and spll are turned off when the countdown value in sd_cnt is satisfied. for the mpll, there are a number of conditions that must be satisfie d before the clock controller module turns off the dpll. the conditions to be satisfied before the pll clock controller actually turns off the mpll are as follows: 1. clock controller module has successfully mastered the system bus. 2. the a9p_clk_off signal from the arm9 platform is active. 3. sdram controller has successfully placed the external sdram into self-refresh mode. 4. after the above conditions are satisfied, the c ountdown based on the value in the sd_cnt field will be initiated. 5. sd_cnt countdown completes. when the conditions listed above are satisfied the mp ll and the spll will be turned off. the frequency premultiplier (fpm) is also disabled in the sleep mode. the fpm_en bit (cscr register) must not be cleared if the fpm is providing the clock source to the dpll. when an unmasked interrupt event occurs, the fpm and then the mpll are re-enabled and the mpll enable bit (mpen) automatically restored to its enable setting. the spll is restored to its original state based on the setting of the spen bit before sleep m ode. if the spll was not enabled before entering sleep mode the spll will not be enabled. the total start-up time from sleep mode is the sum of the fpm lock time and the dpll lock time. in sleep mode, the i.mx27 device retains all ram data and register configuration values. data to output terminals is also maintained and thus wi ll continue to sink/source static current. note system software must ensure that if there are any clocks being sourced by the i.mx27 processor to external peripherals (for example, ssi mclk), then the corresponding pll must not be turned off. in such cases, the i.mx27 processor must remain in doze mode. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-8 freescale semiconductor 3.3.4 sdram power modes when the sdram controller (sdramc) is enabled, the external sdram operates in distributed-refresh mode or in self-refresh mode (as shown in table 3-2 ). the sdram wake-up latency is approximately 20 system clock cycles (hclk). the sdramc can wake up from self-refresh mode when it is in a sdram cycle. in doze and run mode, the power down timers within the sdramc can be enabled to cause the sdram to enter power down mode on detecting no activity. the sdramc still controls the refresh and it takes the sdram out of the power down mode to perform re fresh when needed and then put it back into the power down mode. in power down mode the clock to the sdram is gated off and the cke pin goes low. in addition since the sdram will be in self refresh just when the system get into sleep mode, no bus cycle can access the sdram to cause it to exit the self-refre sh mode. exit from self-refresh mode will happen when the chip will exit the sleep mode and re-enable the mpen. 3.3.5 power management in the pll clock controller the i.mx27 device has a very efficient clock control scheme that enables clocking control of the modules and devices at various stages. power management in the i.mx27 device is achieved by controlling the duty cycles of the clock system efficiently. the clocking control scheme is shown in table 3-3 . most modules in the i.mx27 processor have a module enable bit assigned which must be enabled before the module is active. enabling the module enables the clock source for the module to be provided for its main operations. the clock input to the dividers from the spll is also controlled separately in the same manner. 3.3.6 power management using frequency control the i.mx27 processor has dptc, but does not support the dvfs feature. the i.mx27 device provides a way for software to save power under different operating conditions. ? software determines whether to ch ange the operation frequency or not. ? software uses dptc to determine whethe r to reduce or increase the power supply. table 3-2. sdram operation during power modes sdram run doze stop sdram distributed-refresh, note 1 distributed-refresh, note 1 self-refresh table 3-3. power management in the clock controller device/signal shut-down conditions wake-up conditions mpll when 0 is written to the mpen bit and the pll shut-down count times out (for details see the sd_cnt settings in ta bl e 3 - 6 ). when irq or fiq is asserted spll when 0 is written to the spen bit. when the spen bit is set to 1 fpm when 0 is written to the fpmen bit. when the fpmen bit is set to 1 clk32 continuously running. continuously running clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-9 ? after the power supply has been change d, software can update mpll configuration. ? it restarts the mpll and operates with new frequency. 3.4 memory map and register definition the pll clock controller module includes six user-accessible 32-bit registers. table 3-4 provides the memory map for the pll clock controller. 3.4.1 register summary the conventions in figure 3-3 and table 3-5 serve as a key for the register summary and individual register diagrams. table 3-4. pll clock controller memory map address register access reset value section/page general registers 0x1002_7000 (cscr) clock source control register r/w 0x33f0_1307 3.4.2/3-10 0x1002_7004 (mpctl0) mpll control register 0 r/w 0x0021_1803 3.4.3/3-13 0x1002_7008 (mpctl1) mpll control register 1 r/w 0x0000_8000 3.4.4/3-14 0x1002_700c (spctl0) spll control register 0 r/w 0x8403_1c53 3.4.6/3-16 0x1002_7010 (spctl1) spll control register 1 r/w 0x0000_8000 3.4.7/3-17 0x1002_7014 (osc26mctl) oscillator 26m register r/w 0x0000_3f00 3.4.8/3-18 0x1002_7018 (pcdr0) peripheral clock divider register 0 r/w 0x2008_3403 3.4.9/3-20 0x1002_701c (pcdr1) peripheral clock divider register 1 r/w 0x1204_1303 3.4.10/3-22 0x1002_7020 (pccr0) peripheral clock control register 0 r/w 0x0401_01c0 3.4.11/3-23 0x1002_7024 (pccr1) peripheral clock control register 1 r/w 0xff4b_6848 3.4.12/3-26 0x1002_7028 (ccsr) clock control status register r/w 0x0000_0300 3.4.13/3-29 0x1002_7034 (wkgdctl) wakeup guard mode control register r/w 0x0000_0000 3.4.14/3-31 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 3-3. key to register fields clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-10 freescale semiconductor table 3-5 provides a key for register figures and tables and the register summary. 3.4.2 clock source control register (cscr) the clock source control register controls the vari ous clock sources to the internal modules of the i.mx27 processor. figure 3-4 shows the register and table 3-6 provides the field descriptions. figure 3-4. clock source control register (cscr) table 3-5. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. (previously designated slfclr) reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. 0x1002_7000 (cscr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 usb_div 00 sd_cnt ssi2_ sel ssi1_ sel h264 _sel mshc _sel spll _res ta rt mpll _res ta r t sp_s el mcu _sel w reset00110011111 1 0000 15141312111098765 4 3210 r arm src 0 armdiv 00 ahbdiv 000osc2 6m_di v1p5 osc2 6m_d is fpm_ en spe n mpe n w reset00010011000 0 0111 clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-11 table 3-6. clock source control register field descriptions field description 31 update_dis disable source selection and divider update until next mpll lock. this bit is cleared automatically. when reprogramming the pll and corresponding cscr settings, this bit must first be set before the cscr is updated and dpll is reprogrammed to ensure that erratic clock behavior does not occur. 30?28 usb_div usb clock divider. contains the 3-bit integer divider value for generation of clk60m. 000 spll_clk divided by 1 001 spll_clk divided by 2 ... 111 spll_clk divided by 8 27?26 reserved. these bits are reserved and should read 0. 25?24 sd_cnt shut-down control. contains the value that determines duration of dpll clock output before it goes off after a 0 is written to the mpen or spen bit. note: power controller requests the bus before spll shutdown. any unmasked interrupt event will enable mpll. 00 dpll shuts down after the next rising edge of clk32 is detected and the current bus cycle is completed. a minimum of 16 hclk cycles is occurs after writing 0 to mpen bit. 01 dpll shuts down after second rising edge of clk32 is detected and the current bus cycle is completed. 10 dpll shuts down after third rising edge of clk32 is detected and the current bus cycle is completed. 11 dpll shuts down after forth rising edge of clk32 is detected and the current bus cycle is completed. 23 ssi2_sel ssi2 baud source select. selects the clock source to ssi2 fractional divider (ssi2_div). 0 source clock to ssi2 fractional divider from spll 1 source clock to ssi2 fractional divider from mpll 22 ssi1_sel ssi1 baud source select. selects the clock source to ssi1 fractional divider (ssi1_div). 0 source clock to ssi1 fractional divider from spll 1 source clock to ssi1 fractional divider from mpll 21 h264_sel h264 cclk source select. selects the clock source to h264 divider (h264_div). 0 source clock to h264 divider is from spll 1 source clock to h264 divider is from mpll 20 mshc_sel mshc cclk source select. selects the clock source to mshc divider (mshc_div). 0 source clock to mshc divider is from spll 1 source clock to mshc divider is from mpll 19 spll_restart spll restart. restarts spll at the new assigned frequency. spll_restart self-clears after 1 (min) or 2 (max) cycles of clk32. 0no effect 1 restarts spll at new frequency 18 mpll_restart mpll restart. restarts mpll at the new assigned frequency. mpll_restart self-clears after 1 (min) or 2 (max) cycles of clk32. 0no effect 1 restarts mpll at new frequency 17 sp_sel spll select. selects clock source of spll input. when set, the external high frequency clock input is selected. 0 clock source is the internal premultiplier. register map shows this bit as reserved also conflicts with 1 clock source is the external high frequency clock clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-12 freescale semiconductor note when presc and bclkdiv are modified at the same time, it must be performed in two programming steps: the first step is to change bclkdiv, and then to change presc. 16 mcu_sel mpll select. selects clock source of mpll input. when set, the external high frequency clock input is selected. 0 clock source is the internal premultiplier. 1 clock source is the external high frequency clock. 15 arm src armsrc. it selects the arm clock source. 0 mpll clk * 2 / 3 1mpll clk 13?12 arm_div arm_div. divider value for arm clk. 00 divide by 1 01 divide by 2 10 divide by 3 11 divide by 4 11?10 reserved 9-8 ahb_div ahb_div. divider value for ahb clk. 00 divide by 1 01 divide by 2 10 divide by 3 11 divide by 4 7?5 reserved 4 osc26m_div1p5 oscillator 26m divide enable. divides osc26m output by 1 or 1.5. 0 osc26m output divide by 1 (default) 1 osc26m output divide by 1.5 3 osc26m_dis oscillator disable. disables the internal (on-chip) 26 mhz oscillator circuit when this bit is set to 1. 0 enable the internal 26 mhz oscillator circuit 1 disable the internal 26 mhz oscillator circuit 2 fpm_en frequency premultiplier enable. enables/disables fpm when set/cleared. this bit is set automatically on system reset. when the software writes a 0 to this bit, fpm is shut down immediately. this bit must remain at 1 prior and during sleep mode if fpm is providing the source to the dpll. 0 disable the frequency premultiplier circuit 1 enable the frequency premultiplier circuit 1 spen serial peripheral pll enable. enables/disables the spll. when software writes 0 to spen, spll shuts down after timeout determined by sd_cnt. spen sets automatically when spllen asserts, and on system reset. 0 serial peripheral pll disabled 1 serial peripheral pll enabled 0 mpen mpll enable. enables/disables the mpll. when software writes 0 to mpen, mpll shuts down after sdcnt timeout. mpen sets automatically when mpllen asserts, and on system reset. 0 mcu and serial pll disabled 1 mcu and serial pll enabled table 3-6. clock source control register field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-13 3.4.3 mpll control register 0 (mpctl0) the mcu and system pll control register 0 (mpctl0) is a 32-bit register that controls the operation of the mpll. the mpctl0 control bits are described in the following sections. figure 3-5 shows the register and table 3-7 provides the field descriptions. the following is the recommended procedure for changing the mpll settings: 1. program the desired values of pd, mfd, mfi, and mfn into the mpctl0. 2. set the mpll_restart bit in the cscr (it will self-clear). 3. new mpll settings will take effect. 4. the new pll clock output is valid upon the assertion of the dpll lock flag. 0x1002_7004 (mpctl0) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r cplm 0 pd mfd w reset0000000000100001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 mfi mfn w reset0001100000000011 figure 3-5. mpll control register 0 (mpctl0) table 3-7. mpll register 0 field descriptions field description 31 cplm phase lock mode. dpll operates in the frequency only lock mode (fol) when cplm bit is cleared, and in frequency and phase lock mode (fpl) when the bit is set. fpl mode can be used for both integer and fractional multiplication factor, but phase skew elimination is accomplished only for integer mf. 0fol 1fpl 30 reserved. this bit is reserved and should read 0. 29?26 pd predivider factor. defines the predivider factor (pd) applied to mpll input frequency. pd is an integer between 0 and 15 (inclusive). pd is chosen to ensure that the resulting output frequency remains within the specified range. when a new value is written into pd, mpll loses its lock; and after a time delay, mpll re-locks. mpll output is determined by equation 3-1 . 0000 0 0001 1 ? 1111 15 clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-14 freescale semiconductor the recommended settings for mpll and spll that produce the least amount of signal jitter are shown in table 3-8 . 3.4.4 mcu and system pll control register 1 (mpctl1) the mcu and system pll control register 1 (mpctl1) is a 32-bit register that directs the operation of the on-chip mcu pll. figure 3-6 shows the register and table 3-9 provides the field descriptions. 25?16 mfd multiplication factor (denominator part). defines the denominator part of brm value for mf. when a new value is written into the mfd bits, mpll loses its lock; and after a time delay, mpll re-locks. 000 reserved 001 1 ? 3ff 1023 15?14 reserved. these bits are reserved and should read 0. 13?10 mfi multiplication factor (integer). defines the integer part of brm value for mf. mfi is encoded so that mfi < 5 results in mfi = 5. when a new value is written into the mfi bits, pll loses its lock: and after a time delay, pll re-locks. vco oscillates at a frequency determined by equation 3-1 . where pd is the division factor of the predivider, mfi is the integer part of total mf, mfn is the numerator of the fractional part of mf, and mfd is its denominator part. mf is chosen to ensure that the resulting vco output frequency remains within the specified range. 0000?01015 0110 6 ... 1111 15 9?0 mfn multiplication factor (numerator). defines the numerator of brm value for mf. the mfn is the only part in the dpll configuration that can be changed after the dpll was locked without resetting the dpll (on the fly).the bit 9 is the sign bit. when mfn is zero, the circuitry for fractional division is disabled to save power. 000 0 001 1 ... 1fe 510 1ff reserved ... 3fe ?510 3ff reservoir table 3-8. recommend settings for frequency stability ref frequency targ et frequency mfi mfn mfd pd mpctl0 setting actual calculated frequency 32.768 khz 399 mhz 5 469 495 0 0x01ef15d5 399.000 32.000 khz 399 mhz 6 3 21 0 0x00211803 398.998 26 mhz 399 mhz 7 35 51 0 0x00331c23 399 table 3-7. mpll register 0 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-15 3.4.5 programming the serial peripheral pll (spll) one of the clock frequencies that the spll generates is for the usb otg module (clk60m). its frequency is set to 60 mhz using the spll control re gisters assuming a default input clock frequency 32.768 mhz. this input clock frequency assumes a 32 khz crystal input. the predivider/multiplier output depends on the input clock frequency. recommended se ttings are provided for the serial peripheral pll as shown in table 3-10 . 0x1002_7008 (mpctl1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r lf 00000000 brmo 00000 w reset1000000000000000 figure 3-6. mcu and system pll control register 1 (mpctl1) table 3-9. mcu and system pll control register 1 field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15 lf lock flag. indicates whether mpll is locked or not. when set, mpll clock output is valid. when cleared, mpll clock output remains at logic high. 0 mpll is not locked. 1 mpll is locked. 14?7 reserved. these bits are reserved and should read 0. 6 brmo brm order. controls the brm order which affects jitter performance of mpll. the first order brm is used if a mf fractional part is more than 1/10 and less than 9/10. in other cases, second order brm is used. brmo bit is cleared by a hardware reset. a delay of reference cycles is required between two write accesses to brmo. 0 brm contains first order. 1 brm contains second order. 5?0 reserved. these bits are reserved and should read 0. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-16 freescale semiconductor 3.4.6 spll control register 0 (spctl0) the serial peripheral pll control regi ster 0 (spctl0) is a 32-bit register that controls the operation of the spll. the spctl0 control bits are described in the following sections. figure 3-7 shows the register and table 3-11 provides the field descriptions. the following is a procedure for changi ng the serial peripheral pll settings: 1. program the desired values of pd, mfd, mfi, and mfn into the spctl0. 2. set the spll_restart bit in the cscr (it will self-clear). 3. new pll settings will take effect. 4. the new pll clock output is valid upon the assertion of the dpll lock flag. table 3-10. serial pll multiplier factor ref frequency target frequency mfi mfn mfd pd spctl0 setting actual calculated frequency 32.768 khz 300 mhz 8 111 117 1 0x0475206f 299.99937 mhz 32.768 khz 240 mhz 7 9 58 1 0x043a1c09 239.99950 mhz 32 khz 300 mhz 9 25 160 1 0x04a02419 300.00020 mhz 32 khz 240 mhz 7 83 255 1 0x04ff1c53 240 mhz 26 mhz 300 mhz 11 7 12 1 0x040c2c07 300 mhz 26 mhz 240 mhz 9 3 12 1 0x040c2403 240 mhz 0x1002_700c (spctl0) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r cplm 0 pd mfd w reset1000010011111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 mfi mfn w reset0001110001010011 figure 3-7. spll control register 0 (spctl0) clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-17 3.4.7 spll control register 1 (spctl1) the serial pll control register 1 (spctl1) is a 32-bit read/write register that directs the operation of the spll. the spctl1 control bits are described in this section. figure 3-8 shows the register and table 3-12 provides the field descriptions. table 3-11. spll control register 0 field descriptions field description 31 cplm phase lock mode. dpll operates in the frequency only lock mode (fol) when cplm bit is cleared, and in frequency and phase lock mode (fpl) when the bit is set. fpl mode can be used for both integer and fractional multiplication factor, but phase skew elimination is accomplished only for integer mf. 0fol 1fpl 30 reserved. these bit is reserved and should read 0. 29?26 pd predivider factor. defines the predivider factor (pd) that is applied to the pll input frequency. pd is an integer between 0 and 15 (inclusive). spll oscillates at a frequency determined by equation 3-1 . pd is chosen to ensure that the resulting vco output frequency remains within the specified range. when a new value is written into the pd bits, spll loses its lock: and after a time delay, spll re-locks. 0000 0 0001 1 ? 111115 25?16 mfd multiplication factor (denominator part). defines the denominator part of brm value for the mf. when a new value is written into the mfd9 to mfd0 bits, pll loses its lock: and after a time delay, pll re-locks. 000 reserved 001 1 ? 3ff 1023 15?14 reserved. these bits are reserved and should read 0. 13?10 mfi multiplication factor (integer part). defines the integer part of brm value for mf. mfi is decoded so that mfi < 5 results in mfi = 5. spll oscillates at a frequency determined by equation 3-1 . where pd is the division factor of the predivider, mfi is the integer part of total mf, mfn is the numerator of fractional part of mf, and mfd is the denominator part of mf. mf is chosen to ensure that the resulting vco output frequency remains within the specified range. when a new value is written into the mfi bits, spll loses its lock; and after a time delay, spll re-locks. 0000?01015 0110 6 ... 1111 15 9?0 mfn multiplication factor (numerator). defines the numerator of brm value for mf. the mfn is the only part in the dpll configuration that can be changed after the dpll was locked without resetting the dpll (on the fly).the bit 9 is the sign bit. when mfn is zero, the circuitry for fractional division is disabled to save power. 0x0000 0x0011 ... 0x1fe 510 0x1ff reserved ... 0x3fe-510 0x3ff reserved clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-18 freescale semiconductor 3.4.8 oscillator 26m register this register is use to program the 26 mhz oscillator test modes as well as the gain control. trimming of the oscillator is necessary only on initial power up; the trim may be stored in flash for future reference. figure 3-9 shows the register and table 3-13 provides the field descriptions. 0x1002_7010 (spctl1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r lf 00000000 brmo 00 0 0 00 w reset1000000000000000 figure 3-8. spll control register 1 (spctl1) table 3-12. serial peripheral pll control register 1 field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15 lf lock flag. indicates whether spll is locked or not. when set, spll clock output is valid. when cleared, spll clock output remains at logic high. 0 spll is not locked. 1 spll is locked. 14?7 reserved. these bits are reserved and should read 0. 6 brmo brm order. controls the brm order which affect spll jitter performance. the first order brm is used if a mf fractional part is more than 1/10 and less than 9/10. in other cases, second order brm is used. brmo bit is cleared by a hardware reset. a delay of reference cycles is required between two write accesses to brmo. 0 brm contains first order. 1 brm contains second order. 5?0 reserved. these bits are reserved and should read 0. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-19 3.4.8.1 adjusting the 26 mhz oscillator trim to ensure a proper startup of the 26 mhz oscillator on power-up or system reset use the following steps to determine the optimum trim of the oscillator agc. to ensure proper startup of 26 mhz oscillator on power-up or system reset, use example 3-2 to determine optimum trim. this algorithm must be run to determine optimum agc setting. once done, software must read the trim value from external memory and write it to osc26m_agc[5:0]. example 3-2. 26 mhz oscillator trim programming algorithm 1. at power up or system reset, osc26m_agc[5:0] bits in the osc26mctl register are reset to logic 1 (done in hardware, no so ftware interaction required). 2. read the peak amplitude value in bits os c26m_peak[1:0] in the osc26mctl register. 3. if the amplitude is not in the desired range, adjust by decrementing the osc26m_agc[5:0] by 1 count. 0x1002_7014 (osc26mctl) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 osc26m_ peak w reset0000000000000000 1514131211109876543210 r0 0 agc 00000000 w reset0011111100000000 figure 3-9. oscillator 26m control register (osc26mctl) table 3-13. oscillator 26m control register field descriptions field description 31?18 reserved. these bits are reserved and should read 0. 17?16 osc26m_peak osc26m_peak. these bits indicates the current amplitude status from the oscillator. 00 amplitude in desired operating range 01 amplitude too low; trim higher 10 amplitude too high; trim lower 11 invalid state 13?8 agc automatic gain control. these bits sets the magnitude of crystal oscillations based on osc26m_peak status. optimum settings for these bits is determined using the algorithm in section 3.4.8.1, ?adjusting the 26 mhz oscillator trim .? 7?0 reserved. these bits are reserved and should read 0. reserved bits 7?0 reserved?these bits are reserved and should read 0. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-20 freescale semiconductor 4. wait at least 30.5 us (1 cycle of 32 khz cl ock) for system to update osc26m_peak bits. 5. repeat steps 2 to 4 until trimmed in desired range. 6. decrement 4 additional counts to provide a margin of error for temperature drift. 7. store trim value in an external memory?that is, flash, for future use. it is suggested that the proceeding algorithm be run to determine the optimum agc setting. once this is done on power-up or system reset the software must read the trim value from the external memory and write it to the osc26m_agc[5:0]. 3.4.9 peripheral clock divider register 0 (pcdr0) the peripheral clock divider register 0 (pcdr0) cont ains the divider values for the peripheral clock dividers in the pll clock controller. peripherals in the i.mx27 device require special clock frequency which is divided down from the mpll and the spll clock output. each of these peripheral modules receive their clock input from the respective clock divi der. these modules will still have the clock gating scheme as with other modules for power saving advantages. figure 3-10 shows the register and table 3-14 provides the field descriptions. table 3-16 lists the clock sources associated with the i.mx27 peripherals given in the pcdr0. 0x1002_7018 (pcdr0) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ssi2div clko _en clko_div ssi1div w reset0001001000000100 1514131211109876543210 r h264div nfcdiv mshcdiv w reset0001010011000011 figure 3-10. peripheral clock divider register 0 (pcdr0) clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-21 table 3-14. peripheral clock divider register 0 field descriptions field description 31?26 ssi2div ssi2 baud clock divider. contains 6-bit fractional divider that produces the clock for ssi2clk clock signal for the peripherals. the value of the divider starts from 0. 02 12.5 23 .... 63 33.5 note: formula for all others: clkin / (2 + 0.5 * ssi2div) 25 clko_en clock out enable. enable bit for clko pin. 0 disable clko output 1 enable clko output 24?22 clko_div clock out divider. contains the 3-bit divider that divides output clocks to clko pin. 000 divide by 1 001 divide by 2 ? 111 divide by 8 21?16 ssi1div ssi 1 baud clock divider. contains 6-bit fractional divider that produces the clock for ssi 1 clk clock signal for the peripherals. the value of the divider starts from 0. 02 12.5 23 .... 63 33.5 note: formula for all others: clkin / (2 + 0.5 * ssi 1 div) 15?10 h264div h264 baud clock divider. contains 6-bit fractional divider that produces the clock for h264clk clock signal for the peripherals. the value of the divider starts from 0. 02 12.5 23 .... 63 33.5 note: formula for all others: clkin / (2 + 0.5 * h264div) 9?6 nfcdiv nand flash controller clock divider. contains 4-bit divider that produces the clock for nfcclk clock signal of the nand flash controller. 0000 divide by 1 0001 divide by 2 ? 1111 divide by 16 5?0 mshcdiv mshc clock divider. contains 6-bit divider that produces the clock for mshcclk clock signal of mshc. 000000 divide by 1 000001 divide by 2 ? 111111 divide by 64 clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-22 freescale semiconductor 3.4.10 peripheral clock divider register 1 (pcdr1) the peripheral clock divider register 1 (pcdr1) cont ains the divider values for the peripheral clock dividers in the pll clock controller. peripherals in i.mx27 requires special clock frequency which is divided down from the mpll and the spll clock output. each of these peripheral modules receive their clock input from the respective clock divider. these m odules will still have the clock gating scheme as with other modules for power saving advantages. figure 3-11 shows the register and table 3-15 provides the field descriptions. table 3-16 lists the clock sources associated with the i.mx27 peripherals given in the pcdr1. 0x1002_701c (pcdr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 perdiv4 00 perdiv3 w reset0000001100000011 1514131211109876543210 r0 0 perdiv2 00 perdiv1 w reset0000001100000011 figure 3-11. peripheral clock divider register 1(pcdr1) table 3-15. peripheral clock divider register 1 field descriptions field description 31?30 these are reserved bits and should read 0. 29?24 perdiv4 peripheral clock divider 4. contains 6-bit integer divider that produces perclk4 clock signal for csi mclk clock. 000000 divide by 1 000001 divide by 2 ? 111111 divide by 64 23?22 these are reserved bits and should read 0. 21 ? 16 perdiv3 peripheral clock divider 3. contains 6-bit integer divider that produces perclk3 clock signal for lcdc pixel clock. 000000 divide by 1 000001 divide by 2 ? 111111 divide by 64 15?14 these are reserved bits and should read 0. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-23 3.4.11 peripheral clock control register 0 (pccr0) the peripheral clock control register 0 (pccr0 ) provides additional power saving capabilities by controlling the clocks in the i.mx27 modules. it also controls the clock source for bootstrap mode. the pccr0 allows for gating of hclk to modules or pe ripherals that access the ahb bus and perform ahb bus transfers and also allows for gating of th e ipg clk (perclk) to specific peripherals. figure 3-12 shows the register and table 3-17 provides the field descriptions. 13?8 perdiv2 peripheral clock divider 2. contains 6-bit integer divider that produces perclk2 clock signal for the peripheral 2set (cspi and sdhc). 000000 divide by 1 000001 divide by 2 ? 111111 divide by 64 7?6 these are reserved bits and should read 0. 5 ? 0 perdiv1 peripheral clock divider 1. contains 6-bit integer divider that produces perclk1 clock signal for the peripheral 1 s e t ( ua rt, g p t, p w m ) . 000000 divide by 1 000001 divide by 2 ? 111111 divide by 64 table 3-16. clock sources for i.mx27 peripherals clock source peripherals clock source peripherals ssi1clk ssi1 nfcclk nfc ssi2clk ssi2 mshcclk mshc h264cclc h264 table 3-15. peripheral clock divider register 1 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-24 freescale semiconductor 0x1002_7020 (pccr0) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r cspi1_en cspi2_en cspi3_en dma_en emma_en fec_en gpio_en gpt1_en gpt2_en gpt3_en gpt4_en gpt5_en gpt6_en i2c1_en i2c2_en iim_en w reset0000010000000001 1514131211109876543210 r kpp_en lcdc_en mshc_en owire_en pwm_en 0 rtc_en rtic_en sahara_en scc_en sdhc1_en sdhc2_en sdhc3_en slcdc_en ssi1_en ssi2_en w reset0000000111000000 figure 3-12. peripheral clock control register 0 (pccr0) table 3-17. peripheral clock control register 0 field descriptions field description 31 cspi1_en cspi1 ipg clock enable. enables/disables ipg clock input to cspi1 module. 0 cspi1 ipg clock input is disabled. 1 cspi1 ipg clock input is enabled. 30 cspi2_en cspi2 ipg clock enable. enables/disables ipg clock input to cspi2 module. 0 cspi2 ipg clock input is disabled. 1 cspi2 ipg clock input is enabled. 29 cspi3_en cspi3 ipg clock enable. enables/disables ipg clock input to cspi3 module. 0 cspi3 ipg clock input is disabled. 1 cspi3 ipg clock input is enabled. 28 dma_en dma ipg clock enable. enables/disables ipg clock input to dma module. 0 dma ipg clock input is disabled. 1 dma ipg clock input is enabled. 27 emma_en emma ipg clock enable. enables/disables ipg clock input to emma module. 0 emma ipg clock input is disabled. 1 emma ipg clock input is enabled. 26 fec_en fec ipg clock enable. enables/disables ipg clock input to fec module. 0 fec ipg clock input is disabled. 1 fec ipg clock input is enabled. 25 gpio_en gpio ipg clock enable. enables/disables ipg clock input to gpio module. 0 gpio ipg clock input is disabled. 1 gpio ipg clock input is enabled. 24 gpt1_en gpt1 ipg clock enable. enables/disables ipg clock input to gpt1 module. 0 gpt1 ipg clock input is disabled. 1 gpt1 ipg clock input is enabled. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-25 23 gpt2_en gpt2 ipg clock enable. enables/disables ipg clock input to gpt2 module. 0 gpt2 ipg clock input is disabled. 1 gpt2 ipg clock input is enabled. 22 gpt3_en gpt3 ipg clock enable. enables/disables ipg clock input to gpt3 module. 0 gpt3 ipg clock input is disabled. 1 gpt3 ipg clock input is enabled. 21 gpt4_en gpt4 ipg clock enable. enables/disables ipg clock input to gpt4 module. 0 gpt4 ipg clock input is disabled. 1 gpt4 ipg clock input is enabled. 20 gpt5_en gpt5 ipg clock enable. enables/disables ipg clock input to gpt5 module. 0 gpt5 ipg clock input is disabled. 1 gpt5 ipg clock input is enabled. 19 gpt6_en gpt6 ipg clock enable. enables/disables ipg clock input to gpt6 module. 0 gpt6 ipg clock input is disabled. 1 gpt6 ipg clock input is enabled. 18 i2c1_en i2c1 ipg clock enable. enables/disables ipg clock input to i2c1 module. 0 i2c1 ipg clock input is disabled. 1 i2c1 ipg clock input is enabled. 17 i2c2_en i2c2 ipg clock enable. enables/disables ipg clock input to i2c2 module. 0 i2c2 ipg clock input is disabled. 1 i2c2 ipg clock input is enabled. 16 iim_en iim ipg clock enable. enables/disables ipg clock input to iim module. 0 iim ipg clock input is disabled. 1 iim ipg clock input is enabled. 15 kpp_en kpp ipg clock enable. enables/disables ipg clock input to kpp module. 0 kpp ipg clock input is disabled. 1 kpp ipg clock input is enabled. 14 lcdc_en lcdc ipg clock enable. enables/disables ipg clock input to lcdc module. 0 lcdc ipg clock input is disabled. 1 lcdc ipg clock input is enabled. 13 mshc_en mshc ipg clock enable. enables/disables ipg clock input to mshc module. 0 mshc ipg clock input is disabled. 1 mshc ipg clock input is enabled. 12 owire_en owire ipg clock enable. enables/disables ipg clock input to owire module. 0 owire ipg clock input is disabled. 1 owire ipg clock input is enabled. 11 pwm_en pwm ipg clock enable. enables/disables ipg clock input to pwm module. 0 pwm ipg clock input is disabled. 1 pwm ipg clock input is enabled. 10 reserved. this bit is reserved. 9 rtc_en rtc ipg clock enable. enables/disables ipg clock input to rtc module. 0 rtc ipg clock input is disabled. 1 rtc ipg clock input is enabled. table 3-17. peripheral clock control register 0 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-26 freescale semiconductor 3.4.12 peripheral clock control register 1 (pccr1) the peripheral clock control register 1 (pccr1 ) provides additional power saving capabilities by controlling the clocks in the i.mx27 modules. it also controls the clock source for bootstrap mode. the pccr1 allows for gating of the ipg cl k (perclk) to specific peripherals. figure 3-13 shows the register and table 3-18 provides the field descriptions. 8 rtic_en rtic ipg clock enable. enables/disables ipg clock input to rtic module. 0 rtic ipg clock input is disabled. 1 rtic ipg clock input is enabled. 7 sahara_en sahara ipg clock enable. enables/disables ipg clock input to sahara module. 0 sahara ipg clock input is disabled. 1 sahara ipg clock input is enabled. 6 scc_en scc ipg clock enable. enables/disables ipg clock input to scc_en module. 0 scc_en ipg clock input is disabled. 1 scc_en ipg clock input is enabled. 5 sdhc1_en sdhc1 ipg clock enable. enables/disables ipg clock input to sdhc1 module. 0 sdhc1 ipg clock input is disabled. 1 sdhc1 ipg clock input is enabled. 4 sdhc2_en sdhc2 ipg clock enable. enables/disables ipg clock input to sdhc2 module. 0 sdhc2 ipg clock input is disabled. 1 sdhc2 ipg clock input is enabled. 3 sdhc3_en sdhc3 ipg clock enable. enables/disables ipg clock input to sdhc3 module. 0 sdhc3 ipg clock input is disabled. 1 sdhc3 ipg clock input is enabled. 2 slcdc_en slcdc ipg clock enable. enables/disables ipg clock input to slcdc module. 0 slcdc ipg clock input is disabled. 1 slcdc ipg clock input is enabled. 1 ssi1_en ssi1 ipg clock enable. enables/disables ipg clock input to ssi1 module. 0 ssi1 ipg clock input is disabled. 1 ssi1 ipg clock input is enabled. 0 ssi2_en ssi2 ipg clock enable. enables/disables ipg clock input to ssi2 module. 0 ssi2 ipg clock input is disabled. 1 ssi2 ipg clock input is enabled. table 3-17. peripheral clock control register 0 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-27 0x1002_7024 (pccr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r uart1_en uart2_en uart3_en uart4_en uart5_en uart6_en usb_en wdt_en hclk_ata hclk_brom hclk_csi hclk_dma hclk_emi hclk_emma hclk_fec hclk_h264 w reset1111111101001011 1514131211109876543210 r hclk_lcdc hclk_rtic hclk_sahara hclk_slcdc hclk_usb perclk1_en perclk2_en perclk3_en perclk4_en h264_bauden ssi1_bauden ssi2+bauden nfc_bauden mshc_bauden 00 w reset0110100001001000 figure 3-13. peripheral clock control register 1(pccr1) table 3-18. peripheral clock control register 1 field descriptions field description 31 uart1_en uart1 ipg clock enable. enables/disables ipg clock input to uart1 module. 0 uart1 ipg clock input is disabled. 1 uart1 ipg clock input is enabled. 30 uart2_en uart2 ipg clock enable. enables/disables ipg clock input to uart2 module. 0 uart2 ipg clock input is disabled. 1 uart2 ipg clock input is enabled. 29 uart3_en uart3 ipg clock enable. enables/disables ipg clock input to uart3 module. 0 uart3 ipg clock input is disabled. 1 uart3 ipg clock input is enabled. 28 uart4_en uart4 ipg clock enable. enables/disables ipg clock input to uart4 module. 0 uart4 ipg clock input is disabled. 1 uart4 ipg clock input is enabled. 27 uart5_en uart5 ipg clock enable. enables/disables ipg clock input to uart5 module. 0 uart5 ipg clock input is disabled. 1 uart5 ipg clock input is enabled. 26 uart6_en uart6 ipg clock enable. enables/disables ipg clock input to uart6 module. 0 uart6 ipg clock input is disabled. 1 uart6 ipg clock input is enabled. 25 usb_en usb ipg clock enable. enables/disables ipg clock input to usb module. 0 usb ipg clock input is disabled. 1 usb ipg clock input is enabled. 24 wdt_en wdt ipg clock enable. enables/disables ipg clock input to wdt module. 0 wdt ipg clock input is disabled. 1 wdt ipg clock input is enabled. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-28 freescale semiconductor 23 hclk_ata ata ahb clock enable. enables/disables ahb clock input to ata module. 0 ata ahb clock input is disabled. 1 ata ahb clock input is enabled. 22 hclk_brom brom ahb clock enable. enables/disables ahb clock input to brom module. 0 brom ahb clock input is disabled. 1 brom ahb clock input is enabled. 21 hclk_csi csi ahb clock enable. enables/disables ahb clock input to csi module. 0 csi ahb clock input is disabled. 1 csi ahb clock input is enabled. 20 hclk_dma dma ahb clock enable. enables/disables ahb clock input to dma module. 0 dma ahb clock input is disabled. 1 dma ahb clock input is enabled. 19 hclk_emi emi ahb clock enable. enables/disables ahb clock input to emi module. 0 emi ahb clock input is disabled. 1 emi ahb clock input is enabled. 18 hclk_emma emma ahb clock enable. enables/disables ahb clock input to emma module. 0 emma ahb clock input is disabled. 1 emma ahb clock input is enabled. 17 hclk_fec fec ahb clock enable. enables/disables ahb clock input to fec module. 0 fec ahb clock input is disabled. 1 fec ahb clock input is enabled. 16 hclk_h264 h264 ahb clock enable. enables/disables ahb clock input to h264 module. 0 h264 ahb clock input is disabled. 1 h264 ahb clock input is enabled. 15 hclk_lcdc lcdc ahb clock enable. enables/disables ahb clock input to lcdc module. 0 lcdc ahb clock input is disabled. 1 lcdc ahb clock input is enabled. 14 hclk_rtic rtic ahb clock enable. enables/disabl es ahb clock input to rtic module. 0 rtic ahb clock input is disabled. 1 rtic ahb clock input is enabled. 13 hclk_sahara sahara ahb clock enable. enables/disable s ahb clock input to sahara module. 0 sahara ahb clock input is disabled. 1 sahara ahb clock input is enabled. 12 hclk_slcdc slcdc ahb clock enable. enables/disables ahb clock input to slcdc module. 0 slcdc ahb clock input is disabled. 1 slcdc ahb clock input is enabled. 11 hclk_usb usb ahb clock enable. enables/disables ahb clock input to usb module. 0 usb ahb clock input is disabled. 1 usb ahb clock input is enabled. 10 perclk1_en perclk1 clock enable. enables/disables peripheral clock1. 0 peripheral clock1 is disabled. 1 peripheral clock1 is enabled. table 3-18. peripheral clock control register 1 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-29 3.4.13 clock control status register (ccsr) the clock control status register (ccsr) provides information on the configuration of the analog and digital block. the clocks within the chip ca n also be monitored by the clko_sel programming. figure 3-14 shows the register and table 3-19 provides the field descriptions. 9 perclk2_en perclk2 clock enable. enables/disables peripheral clock2. 0 peripheral clock2 is disabled. 1 peripheral clock2 is enabled. 8 perclk3_en perclk3 clock enable. enables/disables peripheral clock3. 0 peripheral clock3 is disabled. 1 peripheral clock3 is enabled. 7 perclk4_en perclk4 clock enable. enables/disables peripheral clock4. 0 peripheral clock4 is disabled. 1 peripheral clock4 is enabled. 6 h264_bauden h264 baud clock enable. enables/disables baud clock input to h264 module. 0 h264 baud clock input is disabled. 1 h264 baud clock input is enabled. 5 ssi1_bauden ssi1 baud clock enable. enables/disables baud clock input to ssi1 module. 0 ssi1 baud clock input is disabled. 1 ssi1 baud clock input is enabled. 4 ssi2_bauden ssi2 baud clock enable. enables/disables baud clock input to ssi2 module. 0 ssi2 baud clock input is disabled. 1 ssi2 baud clock input is enabled. 3 nfc_bauden nfc baud clock enable. enables/disables baud clock input to nfc module. 0 nfc baud clock input is disabled. 1 nfc baud clock input is enabled. 2 mshc_bauden mshc baud clock enable. enables/disables baud clock input to mshc module. 0 mshc baud clock input is disabled. 1 mshc baud clock input is enabled. 1?0 reserved. these bits are reserved and should read 0. table 3-18. peripheral clock control register 1 field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-30 freescale semiconductor 0x1002_7028 (ccsr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r 32k _sr 00000 clkmode 000 clko_sel w reset0000001100000000 figure 3-14. clock control status register (ccsr) table 3-19. clock control status register field descriptions field description 31?16 reserved. these bit are reserved and should read 0. 15 32k_sr 32k status register. it contains status information of 32 khz clock. it is cleared to zero during the assertion of hard_async_reset signal. the sampled 32khz clock phase is continuously registered into the bit upon the de-assertion of hard_async_reset signal. 0 clk32 in low phase 1 clk32 in high phase 14?12 reserved. these bits are reserved and should read 0. 9?8 clkmode clkmode. determines the configuration of fpm, osc26m and dpll on the chip. its reset value depends on clkmode input signals. 00 dpll, fpm, osc26m bypassed 01 fpm bypassed. 10 fpm and osc26m bypassed 11 fpm and dpll in use (default) clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-31 3.4.14 wakeup guard mode control register (wkgdctl) the wakeup guard mode control register (wkgdctl) provides the configuration of the wakeup guard mode. this is a write once only bit in order to be compatible with the watchdog behavior. after enable/disable, it will not be modifiable. when enabled, the battery detector external to the chip provides a glitch free signal through the tin pin. battery must be intact for the chip to wakeup from sleep. figure 3-15 shows the register and table 3-20 provides the field descriptions. 7?5 reserved. these bits are reserved and should read 0. 4?0 clko_sel clko select. selects which clock signal source is the output of clko pin. 00000 clk32 00001 premclk 00010 clk26m 00011 mpll reference clk 00100 spll reference clk 00101 hclk source (mpll 2x clock output / 3) 00110 spll clk 00111 fclk 01000 hclk 01001 ipg_clk 01010 perclk1 01011 perclk2 01100 perclk3 01101 perclk4 01110 ssi 1 baud 01111 ssi 2 baud 10000 nfc baud 10001 mshc_baud 10010 h264 baud 10011 clk60m always 10100 clk32k always 10101 clk60m 10110 dptc reference clock table 3-19. clock control status register field descriptions (continued) field description clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-32 freescale semiconductor 3.5 functional description of the reset module the reset module controls or distributes all of the system reset signals used by the i.mx27 processor. a simplified block diagram of the reset module is shown in figure 3-16 . the reset module generates two distinct events?a global reset and an arm9 platform reset. 0x1002_7034 (wkgdctl) access: user write-once 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000000 0 w reset000000000000000 0 151413121110987654321 0 r000000000000000 wkgd_en w reset000000000000000 0 figure 3-15. wakeup guard mode control register (wkgdctl) table 3-20. wakeup guard mode control register field descriptions field description 31?1 reserved. these bits are reserved and should read 0. 0 wkdg_en wakeup guard mode enable. enables /disables the wakeup guard logic. write- once-only bit and can only be cleared through system reset. once enabled, battery indicator through tin will be used to qualify the wakeup process. when battery is intact, that is, tin=1, wakeup from sleep proceed as per normal. when wkgd_en=1 and battery is removed, 32 khz clock to watchdog module is gated off. clock resumes when battery is back in place. 0 wakeup guard mode is disabled. 1 wakeup guard mode is enabled. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-33 figure 3-16. reset module clock diagram 3.5.1 global reset a global reset is produced by the simultane ous assertion of the following resets: ? reset_dram ?hreset ? hard_async_reset ? reset_por there is one source capable of generating a global reset: a low condition on the por pin when the 32 khz crystal oscillator is running. the hreset and hard_async_reset are armed simultaneously; they remain in that state for 14 clk32 cycles. reset_dram is deasserted seven clk32 cycles before hreset and hard_async_reset are deasserted. the sdram executes the necessary self refresh operations during this time. the timing diagram in figure 3-16 shows the relationship of the reset signal timings. see table 3-21 for reset module signal and pin definitions. hreset reset_dram por reset wdog_reset clk32 300 ms por_timeout 4-cycle qualifier rsr rising edge detector reset_por ip bus 14-cycle stretcher 7-cycle stretcher clk32 clk32 clk32 counter syn logic hard_async_reset hclk global_reset reset_por ext_reset (programmed values) 3-cycle stretcher syn logic fuse_latch clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-34 freescale semiconductor the following signal conditions are not capable of gene rating a global reset, however their assertion will reset the arm9 platform: ? an external qualified low condition on the reset_in pin ? a low condition on wdog_reset furthermore, these reset conditions will not reset the sdramc, real time clock, watchdog module, or allow a change in boot mode?that is, changes made to boot[3:0] during these resets conditions will not take effect. only the global reset is capable of this. the source of the last hardware reset can be determined in the watchdog status register. note due to the asynchronous nature of the reset_in signal, the time period required to qualify the signal may vary, and the hreset timing relative to the rising edge of the reset_in is also affected. a reset_in signal shorter than three clk32 cycles will not be qualified, a reset_in signal equal to or longer than four clk32 cy cles will always be qualified, and any period length that is more than three and less than four clk32 cycles is undefined. por is the reset signal for all the reset module flip-flops. for this reason, an external reset signal is qualified if it lasts more than four clk32 cycles when por is deasserted. during power on the user must ensure that por stay asserted (low) long enough for the 32khz crystal to stabilize. the time it takes for the crystal to stabilize depends upon on the crystal used. consult the crystal?s specification for details about its stabilization timing. note refer to the i.mx27 multimedia applications processor data sheet for power-up and power-down sequence requirements. clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3-35 figure 3-17. dram and intern al reset timing diagram 3.5.2 arm9 platform reset any qualified global reset signal resets the arm9 platform and all related peripherals to their default state. after the internal reset is deasserted, the arm9 proc essor begins fetching code from the internal bootstrap rom or cs0 space. the memory location of the fetch depends on the configuration of the boot pins and the value of the test pin on the rising edge of the hreset . table 3-21. reset module pin and signal descriptions signal name direction signal description clk32 in 32 khz clock?a 32 khz clock signal derived from the 32.768 khz or 32.0 khz crystal oscillator circuit in the pll clock controller. por in power-on reset?an internal active schmitt trigger signal from the por pin. the por signal is normally generated by an external rc circuit designed to detect a power-up event. reset_in in reset?an external active low schmitt trigger signal from the reset_in pin. when this signal goes active, all modules (except the sdramc, real time clock, watchdog, and the boot[3:0] signals) are reset. wdog_reset in watchdog timer reset?an active low signal generated by the watchdog timer when a time-out period has expired. resets the same modules as reset_in . hard_asyn_reset out hard asynchronous reset?an active low signal that resets all peripheral modules except the watchdog module?s status register. the rising edge of this signal is synchronous with ipg_clk. u n d e f i n e d 14 cycles @ clk32 7 cycles @ clk32 300 ms por reset_por reset_dram reset_cpu clk32 hclk reset_sys clocks, power management, and reset control MCIMX27 multimedia applications processor reference manual, rev. 0.2 3-36 freescale semiconductor hreset out hard reset?an active low signal that resets the arm9 platform. this signal is deasserted during the low phase of hclk. this signal also appears on the reset_out pin of the i.mx27. reset_dram out dram reset?an active low signal that resets the sdram controller. table 3-21. reset module pin and signal descriptions (continued) signal name direction signal description MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-1 chapter 4 system control 4.1 introduction this chapter describes the system control module of the i.mx27 microprocessor. the system control module enables system software to control, customize, or read the status of the following functions: ? chip id ? multiplexing of i/o signals ? i/o drive strength ? i/o pull enable control ? well bias control ? system boot mode selection ? dptc control 4.2 memory map and register definition the system control module includes one 32-bit silicon id and twenty-four user-accessible 32-bit registers. table 4-1 summarizes these registers and their addresses. table 4-1. block memory map address register access reset value section/page general registers 0x1002_7800 (cid) chip id register r/w 0x1882_181d 4.2.1/4-3 0x1002_7814 (fmcr) function multiplexing control register r/w 0xffff_ffcb 4.2.2/4-4 0x1002_7818 (gpcr) global peripheral control register r/w 0x0000_0808 4.2.3/4-6 0x1002_781c (wbcr) well bias control register r/w 0x0000_0000 4.2.5/4-8 0x1002_7820 (dscr1) drive strength control register 1 r/w 0x0000_0000 4.2.6/4-10 0x1002_7824 (dscr2) drive strength control register 2 r/w 0x0000_0000 4.2.7/4-12 0x1002_7828 (dscr3) drive strength control register 3 r/w 0x0000_0000 4.2.8/4-14 0x1002_782c (dscr4) drive strength control register 4 r/w 0x0000_0000 4.2.9/4-17 system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-2 freescale semiconductor the conventions in figure 4-1 and table 4-2 serve as a key for the register summary and individual register diagrams. table 4-2 provides a key for register figures and tables and the register summary. 0x1002_7830 (dscr5) drive strength control register 5 r/w 0x0000_0000 4.2.10/4-18 0x1002_7834 (dscr6) drive strength control register 6 r/w 0x0000_0000 4.2.11/4-21 0x1002_7838 (dscr7) drive strength control register 7 r/w 0x0000_0000 4.2.12/4-23 0x1002_783c (dscr8) drive strength control register 8 r/w 0x0000_0000 4.2.13/4-25 0x1002_7840 (dscr9) drive strength control register 9 r/w 0x0000_0000 4.2.14/4-28 0x1002_7844 (dscr10) drive strength control register 10 r/w 0x0000_0000 4.2.15/4-30 0x1002_7848 (dscr11) drive strength control register 11 r/w 0x0000_0000 4.2.16/4-32 0x1002_784c (dscr12) drive strength control register 12 r/w 0x0000_0000 4.2.17/4-34 0x1002_7850 (dscr13) drive strength control register 13 r/w 0x0000_0000 4.2.18/4-36 0x1002_7854 (pscr) pull strength control register r/w 0x0000_0000 4.2.19/4-38 0x1002_7858 (pcsr) priority control and select register r/w 0x0000_0003 4.2.20/4-40 0x1002_7860 (pmcr) power management control register r/w 0x0000_0000 4.2.21/4-41 0x1002_7864 (dcvr0) dptc comparator value register 0 r/w 0x0000_0000 4.2.22/4-43 0x1002_7868 (dcvr1) dptc comparator value register 1 r/w 0x0000_0000 4.2.23/4-43 0x1002_786c (dcvr2) dptc comparator value register 2 r/w 0x0000_0000 4.2.24/4-44 0x1002_7870 (dcvr3) dptc comparator value register 3 r/w 0x0000_0000 4.2.25/4-45 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 4-1. key to register fields table 4-1. block memory map (continued) address register access reset value section/page system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-3 4.2.1 chip id register (cid) the chip id register contains the chip identification number. figure 4-2 shows the register and table 4-3 provides its field descriptions. table 4-2. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. (previously designated slfclr) reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. 0x1002_7800 (cid) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r version id part number w reset0001100010000010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r part number manufacturer id w reset0001000000011101 figure 4-2. chip id register (cid) system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-4 freescale semiconductor 4.2.2 function multiplexing control register (fmcr) the fmcr controls the multiplexing of the signal lines shared by the slcdc module, uart module, and keypad module as well as the sdram chip select lines. the fmcr also allows control or indicates the boot status of the nand flash page size and data port size. figure 4-3 shows the register and table 4-4 provides its field descriptions. table 4-3. chip id register field descriptions field description 31?28 version id version id. this field contains the 4-bit version id number. 27?12 part number part number. this field contains the 16-bit part number of the chip. 11?0 manufacturer id manufacturer id. this field contains the 12-bit manufacturer id number of the chip. 0x1002_7814 (fmcr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r111111 uart4_rxd_ctl uart4_rts_ctl 11111 kp_col6_ctl kp_row7_ctl kp_row6_ctl w reset1111111111111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r1 pc_wait_b_ctl pc_ready_ctl pc_vs1_ctl pc_vs2_ctl pc_bvd1_ctl pc_bvd2_ctl iois16_ctl 11 nf_fms nf_16bit_sel 1 slcdc_sel sdcs1_sel sdcs0_sel w reset1111111111001011 figure 4-3. function multiplexing control register (fmcr) table 4-4. function multiplexing control register description field description 31?26 reserved. these bits are reserved and should read 1. 25 uart4_rxd_ctl uart4 rxd control. when set, the alternate signal of usbh1_rxdp (pb31) is input to rxd of uart4. when 0, the usbh1_txdp (pb29) gpio?s aout is input to rxd of uart4. with either setting, the user must also ensure that the proper gpio registers have been programmed to select the desired multiplexing. 0 the usbh1_txdp (pb29) gpio?s aout is input to rxd of uart4. 1 the alternate signal of usbh1_rxdp (pb31) is input to rxd of uart4. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-5 24 uart4_rts_ctl uart4 rts control. when set, the alternate signal of usbh1_fs (pb26) is input to rts of uart4. when 0, the usbh1_rxdp (pb31) gpio?s aout is input to rts of uart4. with either setting, the user must also ensure that the proper gpio registers have been programmed to select the desired multiplexing. 0 the usbh1_rxdp (pb31) gpio?s aout is input to rts of uart4. 1 the alternate signal of usbh1_fs (pb26) is input to rts of uart4. 23?19 reserved. these bits are reserved and should read 1. 18 kp_col6_ctl keypad column 6 control. when set, the alternate signal of uart2_txd (pe6) is input to column 6 of keypad. when 0, the alternate signal of test_wb2 (pe0) is input to column 6 of keypad. with either setting, the user must also ensure that the proper gpio registers have been programmed to select the desired multiplexing. 0 the alternate signal of test_wb2 (pe0) is input to column 6 of keypad. 1 the alternate signal of uart2_txd (pe6) is input to column 6 of keypad. 17 kp_row7_ctl keypad row 7 control. when set, the alternate signal of uart2_rts (pe4) is input to row 7of keypad. when 0, the alternate signal of test_wb0 (pe2) is input to row 7 of keypad. with either setting, the user must also ensure that the proper gpio registers have been programmed to select the desired multiplexing. 0 the alternate signal of test_wb0 (pe2) is input to row 7 of keypad. 1 the alternate signal of uart2_rts (pe4) is input to row 7of keypad. 16 kp_row6_ctl keypad row 6 control. when set, the alternate signal of uart2_rxd (pe7) is input to row 6 of keypad. when 0, the alternate signal of test_wb1 (pe1) is input to row 6 of keypad. with either setting, the user must also ensure that the proper gpio registers have been programmed to select the desired multiplexing. 0 the alternate signal of test_wb1 (pe1) is input to row 6 of keypad. 1 the alternate signal of uart2_rxd (pe7) is input to row 6 of keypad. 15 reserved. these bits are reserved and should read 1. 14 pc_wait_b_ctl pc_wait_b control. when set, signal pc_wait_b of pcmcia is input from pc_wait_b. when 0, it is input from bout of gpio port c[31]. 0 the signal pc_wait_b of pcmcia is input from bout of gpio port c[31]. 1 the signal pc_wait_b of pcmcia is input from pc_wait_b. 13 pc_ready_ctl pc_ready control. when set, signal pc_ready of pcmcia is input from pc_ready. when 0, it is input from bout of gpio port c[30]. 0 the signal pc_ready of pcmcia is input from bout of gpio port c[30]. 1 the signal pc_ready of pcmcia is input from pc_ready. 12 pc_vs1_ctl pc_vs1 control. when set, signal pc_vs1 of pcmcia is input from pc_vs1. when 0, it is input from bout of gpio port c[29]. 0 the signal pc_vs1 of pcmcia is input from bout of gpio port c[29]. 1 the signal pc_vs1 of pcmcia is input from pc_vs1. 11 pc_vs2_ctl pc_vs2 control. when set, signal pc_vs2 of pcmcia is input from pc_vs2. when 0, it is input from bout of gpio port c[28]. 0 the signal pc_vs2 of pcmcia is input from bout of gpio port c[28]. 1 the signal pc_vs2 of pcmcia is input from pc_vs2. 10 pc_bvd1_ctl pc_bvd1 control. when set, signal pc_bvd1 of pcmcia is input from pc_bvd1. when 0, it is input from bout of gpio port c[19]. 0 the signal pc_bvd1 of pcmcia is input from bout of gpio port c[19]. 1 the signal pc_bvd1 of pcmcia is input from pc_bvd1. table 4-4. function multiplexing control register description (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-6 freescale semiconductor 4.2.3 global peripheral control register (gpcr) the global peripheral control register (gpcr) displays the current boot mode of the i.mx27 device. the clock gating to the processor?s modules is also controlled by this register. figure 4-4 shows the register and table 4-5 provides its field descriptions. 9 pc_bvd2_ctl pc_bvd2 control. when set, signal pc_bvd2 of pcmcia is input from pc_bvd2. when 0, it is input from bout of gpio port c[18]. 0 the signal pc_bvd2 of pcmcia is input from bout of gpio port c[18]. 1 the signal pc_bvd2 of pcmcia is input from pc_bvd2. 8 iois16_ctl iois16 control. when set, signal iois16 of pcmcia is input from iois16. when 0, it is input from bout of gpio port c[17]. 0 the signal iois16 of pcmcia is input from bout of gpio port c[17]. 1 the signal iois16 of pcmcia is input from iois16. 7?6 reserved. these bits are reserved and should read 1. 5 nf_fms flash memory select. when boot[3:0] = 0010 or 0011, the nf_fms will be set, otherwise it will be 0. after boot up, this bit is user programmable. 0 nand flash with 512b page size (64mb/128mb/256mb/512mbyte/ 1gbyte ddp) 1 nand flash with 2 kbyte page size (1gbyte/2gbyte ddp/2gbyte) note: ddp means double density package. 4 nf_16bit_sel nand flash 16-bit select. selects 16-bit nf operation. setting this bit forces the nand flash into 16-bit operation and the nand flash upper data is available to the pins. clearing this bit forces the nf to 8-bit operation and the a[25:21]signals become the function pins. the muxing is done in the emi module, not i/o mux module. during system boot up, if the boot[3:0] input pins are configured to select 16-bit mode, this nf_16bit_sel bit is set. 0 nand flash 8-bit operation 1 nand flash 16-bit operation 3 reserved. this bit is reserved and should read 0. 2 slcdc_sel slcdc select. selects whether a baseband chip (bb) or the i.mx27 processor drives the slcdc display port in serial mode. 0 on chip slcdc drives the slcdc port. 1 bb can write directly to the slcdc port. 1 sdcs1_sel sdram chip select. selects the function of the cs3/csd1 pin. 0cs3 is selected. 1csd1 is selected. 0 sdcs0_sel sdram chip select. selects the function of the cs2/csd0 pin. 0cs2 is selected. 1csd0 is selected. table 4-4. function multiplexing control register description (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-7 0x1002_7818 (gpcr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0 0 0 0 0000 boot w reset0000 0 0 0 0 0000 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 000 etm9 _pad _en usb_ burst _over ride pp_ burst _over ride dma_ burst _over ride 0 0 0 0cloc k_ga ting_ en ddr_ mode clk_ ddr_ mode ddr_ input w reset0000 1 0 0 0 0000 1 0 0 0 figure 4-4. global peripheral control register (gpcr) table 4-5. global peripheral control register descriptions field description 31?20 reserved. these bits are reserved and should read 0. 19?16 boot boot mode. these are 4-bit system boot mode for the i.mx27 device. 0000 bootstrap from uart/usb 0001 reserved 0010 8-bit nand flash (2 kbyte per page) 0011 16-bit nand flash (2 kbyte per page) 0100 16-bit nand flash (512 bytes per page) 0101 16-bit cs0 0110 32-bit cs0 0111 8 bit nand flash (512 bytes per page) 1xxx reserved 15?12 reserved. these bits are reserved and should read 0. 11 etm9_pad_en etm9 pad enable. when this bit is set, pads for etm9 are enabled. 0 disable etm9 pads 1 enable etm9 pads 10 usb_burst_override usb burst override control. when this bit is set, the burst type of usb will be forced to incr8. 0 bypass. the burst type will not be forced. 1 burst type of usb is incr8 9 pp_burst_override emma pp burst override control. when this bit is set, the burst type of emma pp will be forced to incr4 or incr8. 0 bypass. the burst type will not be forced. 1 burst type of emma pp is incr4 or incr8. 8 dma_burst_override dma burst override control. when this bit is set, the burst type of dma wi ll be forced to incr4 or incr8. 0 bypass. the burst type will not be forced. 1 burst type of dma is incr4 or incr8. 7?4 reserved. these bits are reserved and should read 0. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-8 freescale semiconductor 4.2.4 well bias system the i.mx27 processor employs an innovative system feat ure to help reduce leakage current called well biasing. the well bias system reduces the leakage current of the qvddx sub-system during low-power mode by increasing the threshold voltage of the qvddx sub-system transistors. the i.mx27 contains two well biasing system, one for arm core logic and one for emi module. the following section describes how to enable and take advantage of this power saving feature. 4.2.5 well bias control register (wbcr) the well bias control register (wbcr) allows the user to enable the a926p well biasing system and emi well biasing system. the default setting is bot h well biasing systems are disabled. a926p well biasing system can operate under both doze mode a nd sleep mode, while emi well biasing system can operate under sleep mode only. to enable well biasi ng systems and take advant age of this power saving feature, crm_wbfa or crm_wbfa_emi bit must be set to 1. figure 4-5 shows the register and table 4-6 provides its field descriptions. 3 clock_gating_en clock gating enable. when set to 1, the peripheral register access clocks are gated by the aipi modules. for example, when there is a register read or write access to the peripherals of aipi1, the ipg_clk_s1 clock will be running, otherwise if no access is taking place the clock will shut off and when there is a register read or write access to the peripherals of aipi2. the clock is running, otherwise if no access is taking place the clock shuts off. when this bit is cleared to 0 then the aipi clocks become a continuous clock, regardless of peripheral accesses. it is recommended for maximum power savings to ensure this bit is set to 1. 2 ddr_mode ddr drive strength control. used to select ddr drive strength of all ddr pads except the sdclk pad. 0 drive strength is selected by associated fields in the dscrx registers. 1 drive strength of about 20 ma, as defined in sstl_18 1 clk_ddr_mode clk ddr mode. used to select ddr drive strength of sdclk pad. 0 drive strength is selected by associated fields in the dscr8 registers. 1 drive strength of about 20 ma, as defined in sstl_18 0 ddr_input ddr_input. used to force input mode of ddr pads to cmos input mode. 0 no force on input mode of ddr pads 1 ddr pads will be forced to cmos input mode. table 4-5. global peripheral control register descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-9 0x1002_781c (wbcr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 crm_spa_emi 0000 crm_wbfa _emi crm_wbm_ emi w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000 crm_spa 0000 crm_wbfa crm_wbm w reset0000000000000000 figure 4-5. well bias control register (wbcr) table 4-6. well bias control register field descriptions field description 31?28 reserved. these bits are reserved and should read 0. 27?26 crm_spa_emi emi pwell set point adjust. describe the configuration of the emi pwell bias circuit?s set point or regulation level. 00 minimum back bias applied to the pwells. 01 decreased back bias applied to the pwells. 10 moderate back bias applied to the pwells. 11 increased back bias applied to the pwells. 25?24 crm_spa_emi emi nwell set point adjust. describe the configuration of the emi nwell bias circuit?s set point or regulation level. 00 minimum back bias applied to the nwells. 01 decreased back bias applied to the nwells. 10 moderate back bias applied to the nwells. 11 increased back bias applied to the nwells. 23?20 reserved. these bits are reserved and should read 0. 19 crm_wbfa_emi well bias frequency adjust. for optimal power savings, the user should set this bit to 1 when emi well bias is enabled. 0 standard 1 adjusted suggested setting for optimal power savings when well bias is enabled. note: this bit has no effect when well bias is disabled. 18?16 crm_wbm_emi crm_wbm. enables or disables emi well bias system during sleep mode. to enable well bias during sleep mode, these bits must be set to 001. to disable well bias, these bits must be set to 000. all other bit settings are reserved. 000 well bias not applied 001 well bias @ sleep 010?111well bias not applied 15?12 reserved. these bits are reserved and should read 0. 11?10 crm_spa a926p pwell set point adjust. describes the configuration of the a926p pwell bias circuit?s set point or regulation level. 00 minimum back bias applied to the pwells. 01 decreased back bias applied to the pwells. 10 moderate back bias applied to the pwells. 11 increased back bias applied to the pwells. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-10 freescale semiconductor 4.2.6 drive strength control register 1 (dscr1) the drive strength control register 1 (dscr1) contro ls the driving force parameters of all slow i/o signals in the i.mx27 device. figure 4-6 shows the register and table 4-7 provides its field descriptions. 9?8 crm_spa a926p nwell set point adjust. describe the configuration of the a926p nwell bias circuit?s set point or regulation level. 00 minimum back bias applied to the nwells. 01 decreased back bias applied to the nwells. 10 moderate back bias applied to the nwells. 11 increased back bias applied to the nwells. 7?4 reserved. these bits are reserved and should read 0. 3 crm_wbfa well bias frequency adjust. for optimal power savings, the user should set this bit to 1 when a926p well bias is enabled. 0 standard. 1 adjusted suggested setting for optimal power savings when well bias is enabled this bit has no effect when well bias is disabled. 2?0 crm_wbm crm_wbm. controls when the a926p well bias will be applied.enables or disables well bias system during sleep mode. to enable well bias during sleep mode, these bits must be set to 001. to disable well bias, these bits must be set to 000. all other bit settings are reserved. 000 well bias not applied 001 well bias @ sleep 010 well bias @ sleep and doze 100?111well bias not applied 0x1002_7820 (dscr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000 ds_slow11 ds_slow10 ds_slow9 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_slow8 ds_slow7 ds_slow6 ds_slow5 ds_slow4 ds_slow3 ds_slow2 ds_slow1 w reset0000000000000000 figure 4-6. drive strength control register (dscr1) table 4-6. well bias control register field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-11 table 4-7. drive strength control register 1 field description field description 31?22 reserved. these bits are reserved and should read 0. 21?20 ds_slow11 drive strength slow i/o. controls the driving strength of slow i/o group 11. (dvs_pmic) 00 normal 01 high 10 max high 11 max high 19?18 ds_slow10 drive strength slow i/o. controls the driving strength of slow i/o group 10. (sdhc1 and cspi3) 00 normal 01 high 10 max high 11 max high 17?16 ds_slow9 drive strength slow i/o. controls the driving strength of slow i/o group 9. (jtag) 00 normal 01 high 10 max high 11 max high 15?14 ds_slow8 drive strength slow i/o. controls the driving strength of slow i/o group 8. (pwm, kpp, uart1, uart2, uart3, and reset_out_b) 00 normal 01 high 10 max high 11 max high 13?12 ds_slow7 drive strength slow i/o. controls the driving strength of slow i/o group 7. (cspi1 and cspi2) 00 normal 01 high 10 max high 11 max high 11?10 ds_slow6 drive strength slow i/o. controls the driving strength of slow i/o group 6. (ssi1, ssi2, sap, ssi3, gpt4, and gpt5) 00 normal 01 high 10 max high 11 max high 9?8 ds_slow5 drive strength slow i/o. controls the driving strength of slow i/o group 5. (gpt1, i2c1, and i2c2) 00 normal 01 high 10 max high 11 max high 7?6 ds_slow4 drive strength slow i/o. controls the driving strength of slow i/o group 4. (usbh1, uart4, and usbg) 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-12 freescale semiconductor 4.2.7 drive strength control register 2 (dscr2) the drive strength control register 2 (dscr2) contro ls the driving force parameters of the fast i/o signals in the i.mx27 processor. figure 4-7 shows the register and table 4-8 provides its field descriptions. 5?4 ds_slow3 drive strength slow i/o. controls the driving strength of slow i/o group 3. (csi, uart5, and uart6) 00 normal 01 high 10 max high 11 max high 3?2 ds_slow2 drive strength slow i/o. controls the driving strength of slow i/o group 2.(sdhc2 and mshc) 00 normal 01 high 10 max high 11 max high 1?0 ds_slow1 drive strength slow i/o. controls the driving strength of slow i/o group 1. (lcdc) 00 normal 01 high 10 max high 11 max high 0x1002_7824 (dscr2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ds_fast16 ds_fast15 ds_fast14 ds_fast13 ds_fast12 ds_fast11 ds_fast10 ds_fast9 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast8 ds_fast7 ds_fast6 ds_fast5 d s_fast4 ds_fast3 ds_fast2 ds_fast1 w reset0000000000000000 figure 4-7. drive strength control register 2 (dscr2) table 4-7. drive strength control register 1 field description (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-13 table 4-8. drive strength control register 2 field descriptions field description 31?30 ds_fast16 drive strength fast i/o. controls the driving strength of fast i/o group 16 (d15). 00 normal 01 high 10 max high 11 max high 29?28 ds_fast15 drive strength fast i/o. controls the driving strength of fast i/o group 15 (d14). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast14 drive strength fast i/o. controls the driving strength of fast i/o group 14 (d13). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast13 drive strength fast i/o. controls the driving strength of fast i/o group 13 (d12). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast12 drive strength fast i/o. controls the driving strength of fast i/o group 12 (d11). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast11 drive strength fast i/o. controls the driving strength of fast i/o group 11(d10). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast10 drive strength fast i/o. controls the driving strength of fast i/o group 10 (d9). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast9 drive strength fast i/o. controls the driving strength of fast i/o group 9 (d8). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast8 drive strength fast i/o. controls the driving strength of fast i/o group 8 (d7). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-14 freescale semiconductor 4.2.8 drive strength control register 3 the drive strength control register 3 (dscr3) contro ls the driving force parameters of the fast i/o signals in the i.mx27. figure 4-8 shows the register and table 4-9 provides its field descriptions. 13?12 ds_fast7 drive strength fast i/o. controls the driving strength of fast i/o group 7 (d6). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast6 drive strength fast i/o. controls the driving strength of fast i/o group 6 (d5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast5 drive strength fast i/o. controls the driving strength of fast i/o group 5 (d4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast4 drive strength fast i/o. controls the driving strength of fast i/o group 4 (d3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast3 drive strength fast i/o. controls the driving strength of fast i/o group 3 (d2). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast2 drive strength fast i/o. controls the driving strength of fast i/o group 2 (d1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast1 drive strength fast i/o. controls the driving strength of fast i/o group 1 (d0). 00 normal 01 high 10 max high 11 max high table 4-8. drive strength control register 2 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-15 0x1002_7828 (dscr3) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ds_fast32 ds_fast31 ds_fast30 ds_fast29 ds_fast28 ds_fast27 ds_fast26 ds_fast25 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast24 ds_fast23 ds_fast22 ds_fast21 ds_fast20 ds_fast19 ds_fast18 ds_fast17 w reset0000000000000000 figure 4-8. drive strength control register 3 (dscr3) table 4-9. drive strength control register 3 field descriptions field description 31?30 ds_fast32 drive strength fast i/o. controls the driving strength of fast i/o group 32 (a15). 00 normal 01 high 10 max high 11 max high 29?28 ds_fast31 drive strength fast i/o. controls the driving strength of fast i/o group 31 (a14). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast30 drive strength fast i/o. controls the driving strength of fast i/o group 30 (a13). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast29 drive strength fast i/o. controls the driving strength of fast i/o group 29 (a12). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast28 drive strength fast i/o. controls the driving strength of fast i/o group 28 (a11). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast27 drive strength fast i/o. controls the driving strength of fast i/o group 27 (a10). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-16 freescale semiconductor 19?18 ds_fast26 drive strength fast i/o. controls the driving strength of fast i/o group 26 (a9). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast25 drive strength fast i/o. controls the driving strength of fast i/o group 25 (a8). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast24 drive strength fast i/o. controls the driving strength of fast i/o group 24 (a7). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast23 drive strength fast i/o. controls the driving strength of fast i/o group 23 (a6). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast22 drive strength fast i/o. controls the driving strength of fast i/o group 22 (a5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast21 drive strength fast i/o. controls the driving strength of fast i/o group 21 (a4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast20 drive strength fast i/o. controls the driving strength of fast i/o group 20 (a3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast19 drive strength fast i/o. controls the driving strength of fast i/o group 19 (a2). 00 normal 01 high 10 max high 11 max high table 4-9. drive strength control register 3 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-17 4.2.9 drive strength control register 4 the drive strength control register 4 (dscr4) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-9 shows the register and table 4-10 provides its field descriptions. 3?2 ds_fast18 drive strength fast i/o. controls the driving strength of fast i/o group 18 (a1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast17 drive strength fast i/o. controls the driving strength of fast i/o group 17 (a0). 00 normal 01 high 10 max high 11 max high 0x1002_782c (dscr4) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 ds_fast42 ds_fast41 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast40 ds_fast39 ds_fast38 ds_fast37 ds_fast36 ds_fast35 ds_fast34 ds_fast33 w reset0000000000000000 figure 4-9. drive strength control register 4 (dscr4) table 4-10. drive strength control register 4 field descriptions field description 31?20 reserved. these bits are reserved and should read 0. 19?18 ds_fast42 drive strength fast i/o. controls the driving strength of fast i/o group 42 (a25). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast41 drive strength fast i/o. controls the driving strength of fast i/o group 41 (a24). 00 normal 01 high 10 max high 11 max high table 4-9. drive strength control register 3 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-18 freescale semiconductor 4.2.10 drive strength control register 5 the drive strength control register 5 (dscr5) contro ls the driving force parameters of the fast i/o signals in the i.mx27 processor. figure 4-10 shows the register and table 4-11 provides its field descriptions. 15?14 ds_fast40 drive strength fast i/o. controls the driving strength of fast i/o group 40 (a23). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast39 drive strength fast i/o. controls the driving strength of fast i/o group 39 (a22). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast38 drive strength fast i/o. controls the driving strength of fast i/o group 38 (a21). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast37 drive strength fast i/o. controls the driving strength of fast i/o group 37 (a20). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast36 drive strength fast i/o. controls the driving strength of fast i/o group 36 (a19). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast35 drive strength fast i/o. controls the driving strength of fast i/o group 35 (a18). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast34 drive strength fast i/o. controls the driving strength of fast i/o group 34 (a17). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast33 drive strength fast i/o. controls the driving strength of fast i/o group 33 (a16). 00 normal 01 high 10 max high 11 max high table 4-10. drive strength control register 4 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-19 0x1002_7830 (dscr5) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ds_fast64 ds_fast63 ds_fast62 ds_fast61 ds_fast60 ds_fast59 ds_fast58 ds_fast57 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast56 ds_fast55 ds_fast54 ds_fast53 ds_fast52 ds_fast51 ds_fast50 ds_fast49 w reset0000000000000000 figure 4-10. drive strength control register 5 (dscr5) table 4-11. drive strength control register 5 field descriptions field description 31?30 ds_fast64 drive strength fast i/o. controls the driving strength of fast i/o group 64 (sd15). 00 normal 01 high 10 max high 11 max high 29?28 ds_fast63 drive strength fast i/o. controls the driving strength of fast i/o group 63 (sd14). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast62 drive strength fast i/o. controls the driving strength of fast i/o group 62 (sd13). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast61 drive strength fast i/o. controls the driving strength of fast i/o group 61 (sd12). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast60 drive strength fast i/o. controls the driving strength of fast i/o group 60 (sd11). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast59 drive strength fast i/o. controls the driving strength of fast i/o group 59 (sd10). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-20 freescale semiconductor 19?18 ds_fast58 drive strength fast i/o. controls the driving strength of fast i/o group 58 (sd9). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast57 drive strength fast i/o. controls the driving strength of fast i/o group 57 (sd8). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast56 drive strength fast i/o. controls the driving strength of fast i/o group 56 (sd7). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast55 drive strength fast i/o. controls the driving strength of fast i/o group 55 (sd6). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast54 drive strength fast i/o. controls the driving strength of fast i/o group 54 (sd5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast53 drive strength fast i/o. controls the driving strength of fast i/o group 53 (sd4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast52 drive strength fast i/o. controls the driving strength of fast i/o group 52 (sd3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast51 drive strength fast i/o. controls the driving strength of fast i/o group 51 (sd2). 00 normal 01 high 10 max high 11 max high table 4-11. drive strength control register 5 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-21 4.2.11 drive strength control register 6 the drive strength control register 6 (dscr6) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-11 shows the register and table 4-12 provides its field descriptions. 3?2 ds_fast50 drive strength fast i/o. controls the driving strength of fast i/o group 50 (sd1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast49 drive strength fast i/o. controls the driving strength of fast i/o group 49 (sd0). 00 normal 01 high 10 max high 11 max high 0x1002_7834 (dscr6) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ds_fast80 ds_fast79 ds_fast78 ds_fast77 ds_fast76 ds_fast75 ds_fast74 ds_fast73 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast72 ds_fast71 ds_fast70 ds_fast69 ds_fast68 ds_fast67 ds_fast66 ds_fast65 w reset0000000000000000 figure 4-11. drive strength control register 6 (dscr6) table 4-12. drive strength control register 6 field descriptions field description 31?30 ds_fast80 drive strength fast i/o. controls the driving strength of fast i/o group 80 (sd31). 00 normal 01 high 10 max high 11 max high 29?28 ds_fast79 drive strength fast i/o. controls the driving strength of fast i/o group 79 (sd30). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast78 drive strength fast i/o. controls the driving strength of fast i/o group 78 (sd29). 00 normal 01 high 10 max high 11 max high table 4-11. drive strength control register 5 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-22 freescale semiconductor 25?24 ds_fast77 drive strength fast i/o. controls the driving strength of fast i/o group 77 (sd28). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast7 drive strength fast i/o. controls the driving strength of fast i/o group 76 (sd27). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast75 drive strength fast i/o. controls the driving strength of fast i/o group 75 (sd26). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast74 drive strength fast i/o. controls the driving strength of fast i/o group 74 (sd25). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast73 drive strength fast i/o. controls the driving strength of fast i/o group 73 (sd24). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast72 drive strength fast i/o. controls the driving strength of fast i/o group 72 (sd23). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast71 drive strength fast i/o. controls the driving strength of fast i/o group 71 (sd22). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast70 drive strength fast i/o. controls the driving strength of fast i/o group 70 (sd21). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast69 drive strength fast i/o. controls the driving strength of fast i/o group 69 (sd20). 00 normal 01 high 10 max high 11 max high table 4-12. drive strength control register 6 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-23 4.2.12 drive strength control register 7 the drive strength control register 7 (dscr7) contro ls the driving force parameters of the fast i/o signals in the i.mx27 processor. figure 4-12 shows the register and table 4-13 provides its field descriptions. 7?6 ds_fast68 drive strength fast i/o. controls the driving strength of fast i/o group 68 (sd19). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast67 drive strength fast i/o. controls the driving strength of fast i/o group 67 (sd18). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast66 drive strength fast i/o. controls the driving strength of fast i/o group 66 (sd17). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast65 drive strength fast i/o. controls the driving strength of fast i/o group 65 (sd16). 00 normal 01 high 10 max high 11 max high 0x1002_7838 (dscr7) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 ds_fast95 ds_fast94 ds_fast93 ds_fast92 ds_fast91 ds_fast90 ds_fast89 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ds_fast88 ds_fast87 ds_fast86 ds_fast85 ds_fast84 ds_fast83 ds_fast82 ds_fast81 w reset0000000000000000 figure 4-12. drive strength control register 7 (dscr7) table 4-12. drive strength control register 6 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-24 freescale semiconductor table 4-13. drive strength control register 7 field descriptions field description 31?30 reserved. these bits are reserved and should read 0. 29?28 ds_fast95 drive strength fast i/o. controls the driving strength of fast i/o group 95 (rw_b). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast94 drive strength fast i/o. controls the driving strength of fast i/o group 94 (bclk). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast93 drive strength fast i/o. controls the driving strength of fast i/o group 93 (lba_b). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast92 drive strength fast i/o. controls the driving strength of fast i/o group 92 (oe_b). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast91 drive strength fast i/o. controls the driving strength of fast i/o group 91 (ecb_b). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast90 drive strength fast i/o. controls the driving strength of fast i/o group 90 (cs5_b). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast89 drive strength fast i/o. controls the driving strength of fast i/o group 89 (cs4_b). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast88 drive strength fast i/o. controls the driving strength of fast i/o group 88 (cs3_b). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast87 drive strength fast i/o. controls the driving strength of fast i/o group 87 (cs2_b). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-25 4.2.13 drive strength control register 8 the drive strength control register 8 (dscr8) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-13 shows the register and table 4-14 provides its field descriptions. 11?10 ds_fast86 drive strength fast i/o. controls the driving strength of fast i/o group 86 (cs1_b). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast85 drive strength fast i/o. controls the driving strength of fast i/o group 85 (cs0_b). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast84 drive strength fast i/o. controls the driving strength of fast i/o group 84 (eb1_b). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast83 drive strength fast i/o. controls the driving strength of fast i/o group 83 (eb0_b). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast82 drive strength fast i/o. controls the driving strength of fast i/o group 82 (sdba1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast81 drive strength fast i/o. controls the driving strength of fast i/o group 81 (sdba0). 00 normal 01 high 10 max high 11 max high table 4-13. drive strength control register 7 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-26 freescale semiconductor 0x1002_783c (dscr8) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 ds_fast111 ds_fast110 ds_fast109 ds_fast108 ds_fast107 ds_fast106 ds_fast105 w reset00 00000000000000 1514 131211109876543210 r ds_fast10 4 ds_fast103 ds_fast102 ds_fast101 ds_fast100 ds_fast99 ds_fast98 ds_fast97 w reset00 00000000000000 figure 4-13. drive strength control register 8 (dscr8) table 4-14. drive strength control register 8 field descriptions field description 31?30 reserved. these bits are reserved and should read 0. 29?28 ds_fast111 drive strength fast i/o. controls the driving strength of fast i/o group 111 (sdqs3). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast110 drive strength fast i/o. controls the driving strength of fast i/o group 110 (sdqs2). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast109 drive strength fast i/o. controls the driving strength of fast i/o group 109 (sdqs1). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast108 drive strength fast i/o. controls the driving strength of fast i/o group 108 (sdqs0). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast107 drive strength fast i/o. controls the driving strength of fast i/o group 107 (sdclk). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast106 drive strength fast i/o. controls the driving strength of fast i/o group 106 (sdcke1). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-27 17?16 ds_fast105 drive strength fast i/o. controls the driving strength of fast i/o group 105 (sdcke0). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast104 drive strength fast i/o. controls the driving strength of fast i/o group 104 (sdwe_b). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast103 drive strength fast i/o. controls the driving strength of fast i/o group 103 (cas_b). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast102 drive strength fast i/o. controls the driving strength of fast i/o group 102 (ras_b). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast101 drive strength fast i/o. controls the driving strength of fast i/o group 101 (ma10). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast100 drive strength fast i/o. controls the driving strength of fast i/o group 100 (dqm3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast99 drive strength fast i/o. controls the driving strength of fast i/o group 99 (dqm2). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast98 drive strength fast i/o. controls the driving strength of fast i/o group 98 (dqm1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast97 drive strength fast i/o. controls the driving strength of fast i/o group 97 (dqm0). 00 normal 01 high 10 max high 11 max high table 4-14. drive strength control register 8 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-28 freescale semiconductor 4.2.14 drive strength control register 9 the drive strength control register 9 (dscr9) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-14 shows the register and table 4-15 provides its field descriptions. 0x1002_7840 (dscr9) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 ds_fast127 ds_fast126 ds_fast125 ds_fast124 ds_fast123 ds_fast122 ds_fast121 w reset00 00000000000000 1514131211109876543210 r ds_fast120 ds_fast119 ds_fast118 ds_fast117 ds_fast116 ds_fast115 ds_fast114 ds_fast113 w reset00 00000000000000 figure 4-14. drive strength control register 9 (dscr9) table 4-15. drive strength control register 9 field descriptions field description 31?30 reserved. these bits are reserved and should read 0. 29?28 ds_fast127 drive strength fast i/o. controls the driving strength of fast i/o group 127 (m_request). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast126 drive strength fast i/o. controls the driving strength of fast i/o group 126 (m_grant). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast125 drive strength fast i/o. controls the driving strength of fast i/o group 125 (iois16). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast124 drive strength fast i/o. controls the driving strength of fast i/o group 124 (pc_poe). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast123 drive strength fast i/o. controls the driving strength of fast i/o group 123 (pc_rw_b). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-29 19?18 ds_fast122 drive strength fast i/o. controls the driving strength of fast i/o group 122 (pc_rst). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast121 drive strength fast i/o. controls the driving strength of fast i/o group 121 (pc_bvd2). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast120 drive strength fast i/o. controls the driving strength of fast i/o group 120 (pc_bvd1). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast119 drive strength fast i/o. controls the driving strength of fast i/o group 119 (pc_vs2). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast118 drive strength fast i/o. controls the driving strength of fast i/o group 118 (pc_vs1). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast117 drive strength fast i/o. controls the driving strength of fast i/o group 117 (pc_pwron). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast116 drive strength fast i/o. controls the driving strength of fast i/o group 116 (pc_ready). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast115 drive strength fast i/o. controls the driving strength of fast i/o group 115 (pc_wait_b). 00 normal 01 high 10 max high 11 max high table 4-15. drive strength control register 9 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-30 freescale semiconductor 4.2.15 drive strength control register 10 the drive strength control register 10 (dscr10) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-15 shows the register and table 4-16 provides its field descriptions. 3?2 ds_fast114 drive strength fast i/o. controls the driving strength of fast i/o group 114 (pc_cd2_b). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast113 drive strength fast i/o. controls the driving strength of fast i/o group 113 (pc_cd1_b). 00 normal 01 high 10 max high 11 max high 0x1002_7844 (dscr10) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 ds_fast143 ds_fast142 ds_fast141 ds_fast140 ds_fast139 ds_fast138 ds_fast137 w reset00 00000000000000 1514131211109876543210 r ds_fast136 ds_fast135 ds_fast134 ds_fast133 ds_fast132 ds_fast131 ds_fast130 ds_fast129 w reset00 00000000000000 figure 4-15. drive strength control register 10 (dscr10) table 4-16. drive strength control register 10 field descriptions field description 31?30 reserved. these bits are reserved and should read 0. 29?28 ds_fast143 drive strength fast i/o. controls the driving strength of fast i/o group 143 (sd3_cmd). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast142 drive strength fast i/o. controls the driving strength of fast i/o group 142 (sd3_clk). 00 normal 01 high 10 max high 11 max high table 4-15. drive strength control register 9 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-31 25?24 ds_fast141 drive strength fast i/o. controls the driving strength of fast i/o group 141 (sd2_clk). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast140 drive strength fast i/o. controls the driving strength of fast i/o group 140 (lsclk). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast139 drive strength fast i/o. controls the driving strength of fast i/o group 139 (csi_mclk). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast138 drive strength fast i/o. controls the driving strength of fast i/o group 138 (csi_pixclk). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast137 drive strength fast i/o. controls the driving strength of fast i/o group 137 (clko). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast136 drive strength fast i/o. controls the driving strength of fast i/o group 136. 00 normal 01 high 10 max high 11 max high 13?12 ds_fast135 drive strength fast i/o. controls the driving strength of fast i/o group 135 (nfwe_b). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast134 drive strength fast i/o. controls the driving strength of fast i/o group 134 (nfre_b). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast133 drive strength fast i/o. controls the driving strength of fast i/o group 133 (nfale). 00 normal 01 high 10 max high 11 max high table 4-16. drive strength control register 10 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-32 freescale semiconductor 4.2.16 drive strength control register 11 the drive strength control register 11 (dscr11) cont rols the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-16 shows the register and table 4-17 provides its field descriptions. 7?6 ds_fast132 drive strength fast i/o. controls the driving strength of fast i/o group 132 (nfcle). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast131 drive strength fast i/o. controls the driving strength of fast i/o group 131 (nfwp_b). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast130 drive strength fast i/o. controls the driving strength of fast i/o group 130 (nfce_b). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast129 drive strength fast i/o. controls the driving strength of fast i/o group 129 (nfrb). 00 normal 01 high 10 max high 11 max high 0x1002_7848 (dscr11) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ds_fast160 ds_fast159 ds_fast158 ds_fast157 ds_fast156 ds_fast155 ds_fast154 ds_fast153 w reset00 00000000000000 1514131211109876543210 r ds_fast152 ds_fast151 ds_fast150 ds_fast149 ds_fast148 ds_fast147 ds_fast146 ds_fast145 w reset00 00000000000000 figure 4-16. drive strength control register 11 (dscr11) table 4-16. drive strength control register 10 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-33 table 4-17. drive strength control register 11 field descriptions field description 31?30 ds_fast160 drive strength fast i/o. controls the driving strength of fast i/o group 160 (ata_data15). 00 normal 01 high 10 max high 11 max high 29?28 ds_fast159 drive strength fast i/o. controls the driving strength of fast i/o group 159 (ata_data14). 00 normal 01 high 10 max high 11 max high 27?26 ds_fast158 drive strength fast i/o. controls the driving strength of fast i/o group 158 (ata_data13). 00 normal 01 high 10 max high 11 max high 25?24 ds_fast157 drive strength fast i/o. controls the driving strength of fast i/o group 157 (ata_data12). 00 normal 01 high 10 max high 11 max high 23?22 ds_fast156 drive strength fast i/o. controls the driving strength of fast i/o group 156 (ata_data11). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast155 drive strength fast i/o. controls the driving strength of fast i/o group 155 (ata_data10). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast154 drive strength fast i/o. controls the driving strength of fast i/o group 154 (ata_data9). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast153 drive strength fast i/o. controls the driving strength of fast i/o group 153 (ata_data8). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast152 drive strength fast i/o. controls the driving strength of fast i/o group 152 (ata_data7). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-34 freescale semiconductor 4.2.17 drive strength control register 12 the drive strength control register 12 (dscr12) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-17 shows the register and table 4-18 provides its field descriptions. 13?12 ds_fast151 drive strength fast i/o. controls the driving strength of fast i/o group 151 (ata_data6). 00 normal 01 high 10 max high 11 max high 11?10 ds_fast150 drive strength fast i/o. controls the driving strength of fast i/o group 150 (ata_data5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast149 drive strength fast i/o. controls the driving strength of fast i/o group 149 (ata_data4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast148 drive strength fast i/o. controls the driving strength of fast i/o group 148 (ata_data3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast147 drive strength fast i/o. controls the driving strength of fast i/o group 147 (ata_data2). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast146 drive strength fast i/o. controls the driving strength of fast i/o group 146 (ata_data1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast145 drive strength fast i/o. controls the driving strength of fast i/o group 145 (ata_data0). 00 normal 01 high 10 max high 11 max high table 4-17. drive strength control register 11 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-35 0x1002_784c (dscr12) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 0 0 0 0 0 ds_fast172 ds_fast171 ds_fast170 ds_fast169 w reset00000000 00000000 15141312111098 76543210 r ds_fast 168 ds_fast 167 ds_fast 166 ds_fast 165 ds_fast164 ds_fast163 ds_fast162 ds_fast161 w reset00000000 00000000 figure 4-17. drive strength control register 12 (dscr12) table 4-18. drive strength control register 12 field descriptions field description 31?24 reserved. these bits are reserved and should read 0. 23?22 ds_fast172 drive strength fast i/o. controls the driving strength of fast i/o group 172 (usbotg_clk). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast171 drive strength fast i/o. controls the driving strength of fast i/o group 171 (usbotg_nxt). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast170 drive strength fast i/o. controls the driving strength of fast i/o group 170 (usbotg_stp). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast169 drive strength fast i/o. controls the driving strength of fast i/o group 169 (usbotg_dir). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast168 drive strength fast i/o. controls the driving strength of fast i/o group 168 (usbotg_data7). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast167 drive strength fast i/o. controls the driving strength of fast i/o group 167 (usbotg_data6). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-36 freescale semiconductor 4.2.18 drive strength control register 13 the drive strength control register 13 (dscr13) contro ls the driving force parameters of the fast i/o signals in the i.mx27 device. figure 4-18 shows the register and table 4-19 provides its field descriptions. 11?10 ds_fast166 drive strength fast i/o. controls the driving strength of fast i/o group 166 (usbotg_data5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast165 drive strength fast i/o. controls the driving strength of fast i/o group 165 (usbotg_data4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast164 drive strength fast i/o. controls the driving strength of fast i/o group 164 (usbotg_data3). 00 normal 01 high 10 max high 11 max high 5?4 ds_fast163 drive strength fast i/o. controls the driving strength of fast i/o group 163 (usbotg_data2). 00 normal 01 high 10 max high 11 max high 3?2 ds_fast162 drive strength fast i/o. controls the driving strength of fast i/o group 162 (usbotg_data1). 00 normal 01 high 10 max high 11 max high 1?0 ds_fast161 drive strength fast i/o. controls the driving strength of fast i/o group 161 (usbotg_data0). 00 normal 01 high 10 max high 11 max high table 4-18. drive strength control register 12 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-37 0x1002_7850 (dscr13) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 0 0000 ds_fast188 ds_fast187 ds_fast186 ds_fast185 w reset0 0 0 0 0000 00000000 15141312 111098 76543210 r ds_fast184 ds_fast183 ds_fast182 ds_fast181 ds_fast180 ds_fast179 ds_fast178 ds_fast177 w reset0 0 0 0 0000 00000000 figure 4-18. drive strength control register 13 (dscr13) table 4-19. drive strength control register 13 field descriptions field description 31?24 reserved. these bits are reserved and should read 0. 23?22 ds_fast188 drive strength fast i/o. controls the driving strength of fast i/o group 188 (usbh2_clk). 00 normal 01 high 10 max high 11 max high 21?20 ds_fast187 drive strength fast i/o. controls the driving strength of fast i/o group 187 (usbh2_dir). 00 normal 01 high 10 max high 11 max high 19?18 ds_fast186 drive strength fast i/o. controls the driving strength of fast i/o group 186 (usbh2_nxt). 00 normal 01 high 10 max high 11 max high 17?16 ds_fast185 drive strength fast i/o. controls the driving strength of fast i/o group 185 (usbh2_stp). 00 normal 01 high 10 max high 11 max high 15?14 ds_fast184 drive strength fast i/o. controls the driving strength of fast i/o group 184 (usbh2_data7). 00 normal 01 high 10 max high 11 max high 13?12 ds_fast183 drive strength fast i/o. controls the driving strength of fast i/o group 183 (usbh2_data6). 00 normal 01 high 10 max high 11 max high system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-38 freescale semiconductor 4.2.19 pull strength control register (pscr) the pull strength control register (pscr) controls the pull strength value and direction for the chip. figure 4-19 shows the register and table 4-20 provides its field descriptions. 11?10 ds_fast182 drive strength fast i/o. controls the driving strength of fast i/o group 182 (usbh2_data5). 00 normal 01 high 10 max high 11 max high 9?8 ds_fast181 drive strength fast i/o. controls the driving strength of fast i/o group 181 (usbh2_data4). 00 normal 01 high 10 max high 11 max high 7?6 ds_fast180 drive strength fast i/o. controls the driving strength of fast i/o group 180.(usbh2_data3) 00 normal 01 high 10 max high 11 max high 5?4 ds_fast179 drive strength fast i/o. controls the driving strength of fast i/o group 179 (usbh2_data2) 00 normal 01 high 10 max high 11 max high 3?2 ds_fast178 drive strength fast i/o. controls the driving strength of fast i/o group 178 (usbh2_data1) 00 normal 01 high 10 max high 11 max high 1?0 ds_fast177 drive strength fast i/o. controls the driving strength of fast i/o group 177 (usbh2_data0) 00 normal 01 high 10 max high 11 max high table 4-19. drive strength control register 13 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-39 0x1002_7854 (pscr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r puencr7 puencr6 puencr5 puencr4 puencr3 puencr2 puencr1 puencr0 w reset0000000000000000 figure 4-19. pull strength control register (pscr) table 4-20. pull strength control register field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?14 puencr puen strength control 7. bit selects direction (up or down) and strength. (sd2_d0_mshc_data0) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 13?12 puencr6 puen strength control 6. bit selects direction (up or down) and strength. (sd2_d1_mshc_data1) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 11?10 puencr5 puen strength control 5. bit selects direction (up or down) and strength. (sd2_d2_mshc_data2) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 9?8 puencr4 puen strength control 4. bit selects direction (up or down) and strength. (sd2_d3_mshc_data3) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 7?6 puencr3 puen strength control 3. bit selects direction (up or down) and strength. (sd2_cmd_mshc_bs) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-40 freescale semiconductor 4.2.20 priority control and select register (pcsr) the priority control and select register (pcsr) cons ist of the master high priority and slave alternate context priority select to the arm9 platform. figure 4-20 shows the register and table 4-21 provides its field descriptions. 5?4 puencr2 puen strength control 2. bit selects direction (up or down) and strength. (sd2_clk_mshc_sclk) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 3?2 puencr1 puen strength control 1. bit selects direction (up or down) and strength. (sd1_d3_cspi3_ss) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 1?0 puencr0 puen strength control 0. bit selects direction (up or down) and strength. (ata_data3_sd3_d3s) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up address 0x1002_7858 (pcsr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 s3_ampr_sel s2_ampr_sel s1_ampr_sel s0_ampr_sel w reset0000000000000000 1514131211109876543210 r0000000000 m5_high_priority m4_high_priority m3_high_priority m2_high_priority m1_high_priority m0_high_priority w reset0000000000000011 figure 4-20. priority control and select register (pcsr) table 4-20. pull strength control register field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-41 4.2.21 power management control register (pmcr) the power management control register (pmcr) controls the dptc function of the chip. figure 4-21 shows the register and table 4-22 provides its field descriptions. table 4-21. priority control and select register field descriptions field description 31?20 reserved. these bits are reserved and should read 0. 19?16 s3_ampr_sel s2_ampr_sel s1_ampr_sel s0_ampr_sel slave alternate context priority select. inputs to the arm9 platform to select the priority determination and control source for the appropriate slave port. (note s0 is the primary ahb and does not come out of the arm9 platform. 0 priority determination and control is made by regular registers. 1 priority determination and control is made by alternate registers set in the crossbar switch. 15?6 reserved. these bits are reserved and should read 0. 5?0 m5_high_priority m4_high_priority m3_high_priority m2_high_priority m1_high_priority m0_high_priority master high priority. inputs to the arm9 platform to elevate to highest appropriate master ports priority level to each slave above all other master ports priority levels which do not have this input asserted. if more than one master has its high priority input asserted, priority level is determined by the software programmed priority assignments inside the crossbar switch. 0 master port low priority 1 master port high priority 0x1002_7860 (pmcr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mc em up lo 0 refcounter w reset000000000000000 0 151413121110987654321 0 r rven 0 vstby 00 dcr rclk on drce 3 drce 2 drce 1 drce 0 dim die dpte n w reset000000000000000 0 figure 4-21. power management control register (pmcr) table 4-22. power management control register field descriptions field description 31 mc mc. measure complete status bit 0 on progress or idle 1 measure completed 30 em em. emergency interrupt state bit 0 no emergency interrupt 1 emergency interrupt is detected. 29 up up. upper_limit interrupt state bit 0 no upper_limit interrupt is detected. 1 upper_limit interrupt is detected. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-42 freescale semiconductor 28 lo lo. lower_limit interrupt state bit. 0 no lower_limit interrupt. 1 lower_limit interrupt is detected. 27 reserved. these bits are reserved and should read 0. 26?16 refcounter reference counter value. these bits contains the value of reference counter in comparison stage. 15 rven reduced voltage mode enable. this bit controls whether enable rv mode when chip is in sleep mode. 0 disable rv mode is in sleep mode. 1 enable rv mode is in sleep mode. 14 reserved. these bits are reserved and should read 0. 13?12 vstby voltage standby control. these two bits will be put on boot1 and boot0 when chip is in sleep mode. and used to inform pmic to change the voltage to the chip. 11?10 reserved. these bits are reserved and should read 0. 9 dcr dptc counting range. this bit sets how many times the system clock may increment and the reference circuits remain active (and their output signals will be counted). value of ?1? causes a 256 system clock count. value of ?0? causes a 128 system clock count. 0 128 system clock count 1 256 system clock count 8 rclkon dptc reference clock monitor on. enable reference clock for debug. 0 normal operation 1 reference clock always on 7 drce3 dptc reference circuit3 enable. this bit defines if reference circuit3 is enabled during dptc operation. 0 dptc reference circuit3 is disabled. 1 dptc reference circuit3 is enabled. 6 drce2 dptc reference circuit2 enable. this bit defines if reference circuit2 is enabled during dptc operation. 0 dptc reference circuit2 is disabled. 1 dptc reference circuit2 is enabled. 5 drce1 dptc reference circuit1 enable. this bit defines if reference circuit1 is enabled during dptc operation. 0 dptc reference circuit1 is disabled. 1 dptc reference circuit1 is enabled. 4 drce0 dptc reference circuit0 enable. this bit defines if reference circuit0 is enabled during dptc operation. 0 dptc reference circuit0 is disabled. 1 dptc reference circuit0 is enabled. 3?2 dim dptc interrupt mask. these bits control how dptc generate its interrupt. 00 dptc will generate an interrupt in all cases. 01 dptc will generate an interrupt only in lower_limit case. 10 dptc will generate an interrupt only in upper_limit case. 11 dptc will generate an interrupt only in emergency case. table 4-22. power management control register field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-43 4.2.22 dptc comparator value register 0 (dcvr0) the dptc comparator value register 0 (dcvr0) contains the dptc comparator value for the dptc in the i.mx27 processor. figure 4-22 shows the register and table 4-23 provides its field descriptions. 4.2.23 dptc comparator value register 1 (dcvr1) the dptc comparator value register 1 (dcvr1) contains the dptc comparator value for the dptc in the i.mx27 processor. figure 4-23 shows the register and table 4-24 provides its field descriptions. 1 die dptc interrupt enable. this bit enables dptc interrupt generation. 0 no interrupt will be generated. 1 enable interrupt generation 0 dpten dptc enable. this bit enables the dptc block and starts the reference circuit clock counting and compares this to look-up table values. 0 dptc is disabled. 1 dptc is enabled. 0x1002_7864 (dcvr0) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ulv llv w reset000000000000000 0 151413121110987654321 0 r llv elv w reset000000000000000 0 figure 4-22. dptc comparator value register 0 (dcvr0) table 4-23. dptc comparator value register 0 field description field description 31?21 ulv upper limit. value for the upper performance limit of the reference circuit 0 clock counter. 20?10 llv lower limit. value for the lower performance limit of the reference circuit 0 clock counter. 9?0 elv emergency limit. value for the lower performance limit of the reference circuit 0 clock counter. this serves as an ?emergency? lower limit, which indicates a critical value. table 4-22. power management control register field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-44 freescale semiconductor 4.2.24 dptc comparator value register 2 the dptc comparator value register 2 (dcvr2) contains the dptc comparator value for the dptc in the i.mx27 processor. figure 4-24 shows the register and table 4-25 provides its field descriptions. 0x1002_7868 (dcvr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ulv llv w reset000000000000000 0 151413121110987654321 0 r llv elv w reset000000000000000 0 figure 4-23. dptc comparator value register 1 (dcvr1) table 4-24. dptc comparator value register 1 field descriptions field description 31?21 ulv upper limit. value for the upper performance limit of the reference circuit 1 clock counter. 20?10 llv lower limit. value for the lower performance limit of the reference circuit 1 clock counter. 9?0 elv emergency limit. value for the lower performance limit of the reference circuit 1 clock counter. this serves as an ?emergency? lower limit, which indicates a critical value 0x1002_786c (dcvr2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ulv llv w reset000000000000000 0 151413121110987654321 0 r llv elv w reset000000000000000 0 figure 4-24. dptc comparator value register 2 (dcvr2) table 4-25. dptc comparator value register 2 field descriptions field description 31?21 ulv upper limit. value for the upper performance limit of the reference circuit 2 clock counter. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-45 4.2.25 dptc comparator value register 3 the dptc comparator value register 3 (dcvr3) contains the dptc comparator value for the dptc in the i.mx27 processor. figure 4-25 shows the register and table 4-26 provides its field descriptions. 4.2.26 pmic pad control register (ppcr) the pmic pad control register (ppcr) contains control bits of boot0 and boot1 pads which used for rv function in low power mode. figure 4-26 shows the register and table 4-27 provides its field descriptions. 20?10 llv lower limit. value for the lower performance limit of the reference circuit 2 clock counter. 9?0 elv emergency limit. value for the lower performance limit of the reference circuit 2 clock counter. this serves as an ?emergency? lower limit, which indicates a critical value. 0x1002_7870 (dcvr3) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ulv llv w reset000000000000000 0 151413121110987654321 0 r llv elv w reset000000000000000 0 figure 4-25. dptc comparator value register 3 (dcvr3) table 4-26. dptc comparator value register 3 description field description 31?21 ulv upper limit. value for the upper performance limit of the reference circuit 3 clock counter. 20?10 llv lower limit. value for the lower performance limit of the reference circuit 3 clock counter. 9?0 elv emergency limit. value for the lower performance limit of the reference circuit 3 clock counter. this serves as an ?emergency? lower limit, which indicates a critical value. table 4-25. dptc comparator value register 2 field descriptions (continued) field description system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-46 freescale semiconductor 4.3 system boot mode selection the operational system boot mode of the i.mx27 processor upon system reset is determined by the configuration of the four external input pins, boot [3:0]. the settings of these pins control where the system is boot from and the memory port size. the i.mx27 processor always begins fetching inst ruction from the address 0x00000000 after reset. the boot[3:0] pins control the memory region that is mapped to the address 0x0. upon power up, if the boot_int is 1, the boot address will always be 0x00000000. if the fuse of the boot_int is blown, the boot address will be generated based on the boot[3:0] information. the boot modes are defined in table 4-28 . these boot modes information are registered dur ing the system reset. when an external chip 0x1002_7874 (ppcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0 0 pus1 pue1 dse1 oe1 00 pus0 pue0 dse0 oe0 w reset0001000000010011 figure 4-26. pmic pad control register (ppcr) table 4-27. pmic pad control register field description field description 31?14 reserved. these bits are reserved and should read 0. 13?12 pus1 pus1. pus control of boot1 pad. only used when rven bit is set. 11 pue1 pue1. pue control of boot1 pad. only used when rven bit is set. 10?9 dse1 dse1. dse control of boot1 pad. only used when rven bit is set. 8 oe1 oe1. oe control of boot1 pad. only used when rven bit is set. 7?16 reserved. these bits are reserved and should read 0. 5?4 pus0 pus0. pus control of boot0 pad. only used when rven bit is set. 3 pue0 pue0. pue control of boot0 pad. only used when rven bit is set. 2?1 dse0 dse0. dse control of boot0 pad. only used when rven bit is set. 0 oe0 oe0. oe control of boot0 pad. only used when rven bit is set. system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 4-47 select is enabled by the boot[3:0] pins, the reset vector 0x0 will jump to the corresponding boot address space. note the boot pins must not change once the i.mx27 device is out of reset. for proper operation, boot[3] must always be tied to vss. table 4-28. system boot mode selection inputs boot[3:0] output signals active device (boot internal) output signals active device (boot external) boot address 0000 irom (bootstrap usb/uart) irom bootstrap usb/uart 0x00000030 0010 irom (8-bit 2 kbyte nand flash) 8-bit 2 kbyte nand flash 0xd8000000 0011 irom (16-bit 2 kbyte nand flash) 16-bit 2 kbyte nand flash 0xd8000000 0100 irom (16-bit 512 byte nand flash) 16-bit 512 kbyte nand flash 0xd8000000 0101 irom (16-bit cs0 at d[15:0] (nor flash)) 16-bit cs0 at d[15:0] (nor flash) 0xc0000000 0110 reserved reserved 0xc0000000 0111 irom (8-bit 512 byte nand flash) 8-bit 512b nand flash 0xd8000000 system control MCIMX27 multimedia applications processor reference manual, rev. 0.2 4-48 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-1 chapter 5 signal descriptions and pin assignments 5.1 introduction this chapter identifies and describes the i.mx27 signals and their pin assignments. 5.2 signal descriptions the i.mx27 signals are described in table 5-1 . most of the signals shown in table 5-1 are multiplexed with other signals. for simplicity, only the primary signal names are shown. see table 5-2 for complete information on the signal multiplexing schemes of these signals. table 5-1. i.mx27 signal descriptions pad name function/notes external bus/chip select (emi) a [13:0] address bus signals, shared with sdram/mddr, weim and pcmcia, a[10] for sdram/mddr is not the address but the pre-charge bank select signal. ma10 address bus signals for sdram/mddr a [25:14] address bus signals, shared with weim and pcmcia sdba[1:0] sdram/mddr bank address signals sd[31:0] data bus signals for sdram, mddr sdqs[3:0] mddr data sample strobe signals dqm0?dqm3 sdram data mask strobe signals eb0 active low external enable byte signal that controls d [15:8], shared with pcmcia pc_reg . eb1 active low external enable byte signal that controls d [7:0], shared with pcmcia pc_iord . oe memory output enable?active low output enables external data bus, shared with pcmcia pc_iowr . cs [5:0] chip select?the chip select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr) in the system control chapter. by default csd [1:0] is selected. dtack is multiplexed with cs4 . cs[5:4] are multiplexed with etmtraceclk and etmtracesync; pf22, 21. ecb active low input signal sent by flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by flash device causing external burst device to latch the starting burst address. signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-2 freescale semiconductor bclk clock signal sent to external synchronous memories (such as burst flash) during burst mode. rw rw signal?indicates whether external access is a read (high) or write (low) cycle. this signal is also shared with the pcmcia pc_we . ras sdram/mddr row address select signal cas sdram/mddr column address select signal sdwe sdram write enable signal sdcke0 sdram clock enable 0 sdcke1 sdram clock enable 1 sdclk sdram clock sdclk_b sdram clock_b nfwe_b nfc write enable signal, multiplexed with etmpipestat2; pf6 nfre_b nfc read enable signal, multiplexed with etmpipestat1; pf5 nfale nfc address latch signal, multiplexed with etmpipestat0; pf4 nfcle nfc command latch signal, multiplexed with etmtracepkt0; pf1 nfwp_b nfc write permit signal, multiplexed with etmtracepkt1; pf2 nfce_b nfc chip enable signal, multiplexed with etmtracepkt2; pf3 nfrb nfc read busy signal, multiplexed with etmtracepkt3; pf0 d[15:0] data bus signal, shared with emi, pcmcia, and nfc pc_cd1_b pcmcia card detect signal, multiplexed with ata ata_dior signal; pf20 pc_cd2_b pcmcia card detect signal, multiplexed with ata ata_diow signal; pf19 pc_wait_b pcmcia wait signal, multiplexed with ata ata_cs1 signal; pf18 pc_ready pcmcia ready/irq signal, multiplexed with ata ata_cs0 signal; pf17 pc_pwron pcmcia signal, multiplexed with ata ata_da2 signal; pf16 pc_vs1 pcmcia voltage sense signal, multiplexed with ata ata_da1 signal; pf14 pc_vs2 pcmcia voltage sense signal, multiplexed with ata ata_da0 signal; pf13 pc_bvd1 pcmcia battery voltage detect signal, multiplexed with ata ata_dmarq signal; pf12 pc_bvd2 pcmcia battery voltage detect signal, multiplexed with ata ata_dmack signalpf11 pc_rst pcmcia card reset signal, multiplexed with ata ata_reset_b signal; pf10 iois16 pcmcia mode signal, multiplexed with ata ata_intrq signal; pf9 pc_rw_b pcmcia read write signal, multiplexed with ata ata_iordy signal; pf8 pc_poe pcmcia output enable signal, multiplexed with ata ata_buffer_en signal; pf7 table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-3 clocks and resets clko clock out signal selected from internal clock signals. refer to the clock controller for internal clock selection; pf15. ext_60m this is a special factory test signal. to ensure proper operation, connect this signal to ground. ext_266m this is a special factory test signal. to ensure proper operation, connect this signal to ground. osc26m_test this is a special factory test signal. to ensure proper operation, leave this signal as a no connect. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module, sdramc module, and the clock control module) are reset. reset_out reset_out?output from the internal hreset_b; and the hreset can be caused by all reset source: power on reset, system reset (reset_in), and watchdog reset. por power on reset?active low schmitt trigger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. xtal26m oscillator output to external crystal extal26m crystal input (26 mhz), or a 16 mhz to 32 mhz oscillator (or square-wave) input when internal oscillator circuit is shut down. clkmode[1:0] these are special factory test signals. to ensure proper operation, do not connect to these signals. extal32k 32 khz crystal input (note: in the rtc power domain) xtal32k oscillator output to 32 khz crystal (note: in the rtc power domain) power_cut (note: in the rtc power domain) power_on_reset (note: in the rtc power domain) osc32k_bypass the signal for osc32k input bypass (note: in the rtc power domain) bootstrap boot [3:0] system boot mode select?the operational system boot mode of the i.mx27 processor upon system reset is determined by the settings of these pins. boot[1:0] are also used as handshake signals to pmic(vstby). jtag jtag_ctrl jtag controller select signal?jtag_ctrl is sampled during rising edge of trst. must be pulled to logic high for proper jtag interface to debugger. pulling jtag_crtl low is for internal test purposes only. trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and control register access through the jtag port. table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-4 freescale semiconductor tms test mode select to sequence jtag test controller?s state machine. sampled on rising edge of tck. rtck jtag return clock used to enhance stability of jtag debug interface devices. this signal is multiplexed with 1-wire; thus, utilizing 1-wire will render rtck unusable and vice versa; pe16. secure digital interface (x2) sd1_cmd sd command bidirectional signal?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register, a 4. 7k?69 k external pull up resistor must be added. this signal is multiplexed with cspi3_mosi; pe22. sd1_clk sd output clock. this signal is multiplexed with cspi3_sclk; pe23. sd1_d[3:0] sd data bidirectional signals?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register, a 50 k?69 k external pull up resistor must be added. sd1_d[3] is muxed with cspi3_ss while sd1_d[0] is muxed with cspi3_miso pe21?18. sd2_cmd sd command bidirectional signal. this signal is multiplexed with mshc_bs; through gpio multiplexed with slcdc1_cs; pb8. sd2_clk sd output clock signal. this signal is multiplexed with mshc_sclk, through gpio multiplexed with slcdc1_clk; pb9. sd2_d[3:0] sd data bidirectional signals. sd2_d[3:0] multiplexed with mshc_data[0:3], also through gpio sd2_1:0] multiplexed with slcdc1_rs and sldcd1_d0; pb7?pb4. sd3_cmd sd command bidirectional signal. this signal is multiplexed with etmtracepkt15 and also through gpio pd1 multiplexed with fec_txd1. sd3_clk sd output clock signal. this signal is through gpio pd0 multiplexed with fec_txd0. note: sd3_data is multiplexed with ata_data3?0. uarts (x6) uart1_rts request to send input signal; pe15 uart1_cts clear to send output signal; pe14 uart1_rxd receive data input signal; pe13 uart1_txd transmit data output signal, pe12 uart2_rxd receive data input signal. this signal is multiplexed with kp_row6 signal from kpp; pe7. uart2_txd transmit data output signal. this signal is multiplexed with kp_col6 signal from kpp; pe6. uart2_rts request to send input signal. this signal is multiplexed with kp_row7 signal from kpp; pe4. uart2_cts clear to send output signal. this signal is multiplexed with kp_col7 signal from kpp; pe3. uart3_rts request to send input signal, pe11 uart3_cts clear to send output signal; pe10 uart3_rxd receive data input signal; pe9 uart3_txd transmit data output signal; pe8 table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-5 note: uart 4, 5, and 6 are multiplexed with coms sensor interface signals. keypad kp_col[5:0] keypad column selection signals. kp_col[7:6] are multiplexed with uart2_cts and uart2_txd respectively. alternatively, kp_col6 is also available on the internal factory test signal test_wb2. the function multiplexing control register in the system control chapter must be used in conjunction with programming the gpio multiplexing (to select the alternate signal multiplexing) to choose which signal kp_col6 is available. kp_row[5:0] keypad row selection signals. kp_row[7:6] are multiplexed with uart2_rts and uart2_rxd signals respectively. the function multiplexing control register in the system control chapter must be used in conjunction with programming the gpio multiplexing (to select the alternate signal multiplexing) to choose which signals kp_row6 and kp_row7 are available. note: kp_col[7:6] and kp_row[7:6] are multiplexed with uart2 signals as show above, also see uarts table. pwm pwmo pwm output. this signal is multiplexed with pc_spkout of pcmcia, as well as tout2 and tout3 of the general purpose timer module; pe5. cspi (x3) cspi1_mosi master out/slave in signal, pd31 cspi1_miso master in/slave out signal, pd30 cspi1_ss[2:0] slave select (selectable polarity) signal, the cspi1_ss2 is multiplexed with usbh2_data5/rcv; and cspi1_ss1 is multiplexed with ext_dmagrant ; pd26?28. cspi1_sclk serial clock signal, pd29 cspi1_rdy serial data ready signal, shared with ext_dmareq_b signal; pd25 cspi2_mosi master out/slave in signal, multiplexed with usbh2_data1/txdp; pd24 cspi2_miso master in/slave out signal, multiplexed with usbh2_data2/txdm; pd23 cspi2_ss[2:0] slave select (selectable polarity) signals, multiplexed with usbh2_data4/rxdm, usbh2_data3/rxdp, usbh2_data6/speed; pd19?pd21 cspi2_sclk serial clock signal, multiplexed with usbh2_data0/oen; pd22 note: cspi3 cspi3_mosi, cspi3_miso, cspi3_ss, andcspi3_sclk are multiplexed with sd1 signals. i 2 c i2c2_scl i 2 c2 clock, through gpio, multiplexed with slcdc_data8; pc6 i2c2_sda i 2 c2 data, through gpio, multiplexed with slcdc_data7; pc5 i2c_clk i 2 c1 clock; pd18 i2c_data i 2 c1 data; pd17 cmos sensor interface csi_hsync sensor port horizontal sync, multiplexed with uart5_rtsp; pb21 table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-6 freescale semiconductor csi_vsync sensor port vertical sync, multiplexed with uart5_cts; pb20 csi_d7 sensor port data, multiplexed with uart5_rxd; pb19 csi_d6 sensor port data, multiplexed with uart5_txd; pb18 csi_d5 sensor port data; pb17 csi_pixclk sensor port data latch clock; pb16 csi_mclk sensor port master clock, pb15 csi_d4 sensor port data, pd14 csi_d3 sensor port data, multiplexed with uart6_rts; pb13 csi_d2 sensor port data, multiplexed with uart6_cts; pb12 csi_d1 sensor port data, multiplexed with uart6_rxd; pb11 csi_d0 sensor port data, multiplexed with uart6_txd; pb10 serial audio port?ssi (configurable to i2s protocol and ac97) (2 to 4) ssi1_clk serial clock signal that is output in master or input in slave; pc23 ssi1_txd transmit serial data; pc22 ssi1_rxd receive serial data; pc21 ssi1_fs frame sync signal that is output in master and input in slave; pc20 ssi2_clk serial clock signal that is output in master or input in slave, multiplexed with gpt4_tin. pc27 ssi2_txd transmit serial data signal, multiplexed with gpt4_tout; pc26 ssi2_rxd receive serial data, multiplexed with gpt5_tin; pc25 ssi2_fs frame sync signal which is output in master and input in slave, multiplexed with gpt5_tout: pc24 ssi3_clk serial clock signal which is output in master or input in slave. this signal is multiplexed with slcdc2_clk; through gpio multiplexed with pc_wait_b; pc31. ssi3_txd transmit serial data signal which is multiplexed with slcdc2_cs, through gpio multiplexed with pc_ready; pc30 ssi3_rxd receive serial data which is multiplexed with slcdc2_rs; through gpio multiplexed with pc_vs1; pc29 ssi3_fs frame sync signal which is output in master and input in slave. this signal is multiplexed with slcdc2_d0; through gpio multiplexed with pc_vs1; pc28. ssi4_clk serial clock signal which is output in master or input in slave; through gpio multiplexed with pc_bvd1; pc19 ssi4_txd transmit serial data; through gpio multiplexed with pc_bvd2; pc18 ssi4_rxd receive serial data; through gpio multiplexed with iois16; pc17 ssi4_fs frame sync signal which is output in master and input in slave; pc16 table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-7 general purpose timers (x6) tin timer input capture or timer input clock?the signal on this input is applied to gpt 1?3 simultaneously. this signal is muxed with the walk-up guard mode wkgd signal in the pll, clock, and reset controller module, and is also multiplexed with gpt6_tout; pc15. tout1 timer output signal from general purpose timer1 (gpt1). this signal is multiplexed with ssi1_mclk and ssi2_mclk signal of ssi1 and ssi2. the pin name of this signal is simply tout, and is also multiplexed with gpt6_tin; pc14. note: tout2, tout3 are multiplexed with pwmo pad; gpt4 and gpt5 signals are multiplexed with ssi2 pads. usb2.0 usbotg_dir/txdm usb otg direction/transmit data minus signal, multiplexed with kp_row7a; pe2 usbotg_stp/txdm usb otg stop signal/transmit data minus signal, multiplexed with kp_row6a; pe1 usbotg_nxt/txdm usb otg next/transmit data minus signal, multiplexed with kp_col6a; pe0 usbotg_clk/txdm usb otg clock/transmit data minus signal, pe24 usbotg_data7/suspend usb otg data7/suspend signal, pe25 usbh2_stp/txdm usb host2 stop signal/transmit data minus signal, pa4 usbh2_nxt/txdm usb host2 next/transmit data minus signal, pa3 usbh2_data7/suspend usb host2 data7/suspend signal, pa2 usbh2_dir/txdm usb host2 direction/transmit data minus signal, pa1 usbh2_clk/txdm usb host2 clock/transmit data minus signal; pa0 usbotg_data3/rxdp usb otg data4/receive data plus signal; multiplexed with slcdc1_dat15 through pc13 usbotg_data4/rxdm usb otg data4/receive data minus signal; multiplexed with slcdc1_dat14 through pc12 usbotg_data1/txdp usb otg data1/transmit data plus signal; multiplexed with slcdc1_dat13 through pc11 usbotg_data2/txdm usb otg data2/transmit data minus signal; multiplexed with slcdc1_dat12 through pc10 usbotg_data0/oen usb otg data0/output enable signal; multiplexed with slcdc1_dat11 through pc9 usbotg_data6/speed usb otg data6/suspend signal; multiplexed with slcdc1_dat10 and usbg_txr_int_b through pc8 usbotg_data5/rcv usb otg data5/rcv signal; multiplexed with slcdc1_dat9 through pc7 usbh1_rxdp usb host1 receive data plus signal, multiplexed with uart4_rxd; multiplexed with slcdc1_dat6 and uart4_rts_alt through pb31 usbh1_rxdm usb host1 receive data minus signal; multiplexed with slcdc1_dat5 and uart4_cts through pb30 usbh1_txdp usb host1 transmit data plus signal; multiplexed with uart4_cts, multiplexed with slcdc1_dat4 and uart4_rxd_alt through pb29 usbh1_txdm usb host1 transmit data minus signal; multiplexed with uart4_txd, multiplexed with slcdc1_dat3 through pb28 usbh1_oe_b usb host1 output enable signal; multiplexed with slcdc1_dat2 through pb27 table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-8 freescale semiconductor usbh1_fs usb host1 full speed output signal, multiplexed with uart4_rts, multiplexed with slcdc1_dat1 through pb26 usbh1_rcv usb host1 rcv signal; multiplexed with slcdc1_dat0 through pb25 usb_oc_b usb oc signal. pb24 usb_pwr usb power signal; pb23 usbh1_susp usb host1 suspend signal; pb22 lcd controller and smart lcd controller oe_acd alternate crystal direction/output enable; pa31 contrast this signal is used to control the lcd bias voltage as contrast control; pa30 vsync frame sync or vsync?this signal also serves as the clock signal output for gate; driver (dedicated signal sps for sharp panel hr-tft); pa29. hsync line pulse or hsync; pa28 spl_spr sampling start signal for left and right scanning. through gpio, this signal is multiplexed with the slcdc1_clk; pa27. ps control signal output for source driver (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_cs; pa26. cls start signal output for gate driver. this signal is invert version of ps (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_rs; pa25. rev signal for common electrode driving signal preparation (sharp panel dedicated signal). this signal is multiplexed with slcdc1_d0; pa24. ld [17:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. through gpio, ld[15:0] signals are multiplexed with slcdc1_dat[15:0], slcdc. pa23?pa6. lsclk shift clock; pa5 note: slcdc signals are multiplexed with lcdc signals. ata ata_data15?0 ata data bus, [15:0] are multiplexed with etmtracepkt4?12, fec_mdio, etmtracepkt13?14 sd3_d3?0; through gpio also are multiplexed with slcdc 15?0, and fec signals; pf23, pd16?pd2. noisy i/o supply pins n vdd 1?15, a vdd noisy supply for the i/o pins. there are 16 i/o voltage pads, n vdd 1 through n vdd 15 + a vdd . table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-9 5.3 i/o power supply and signal multiplexing scheme this section describes information about both th e power supply for each i/o pin and its functional multiplexing scheme. section 5.3.3, ?i/o mode and supply level ? provides information on how to configure the power supply scheme for each device in the system (memory and external peripherals). the analog supply pins fpm vdd mpll vdd osc26 vdd upll vdd osc32 vdd supply for analog blocks fpmvss mpllvss osc26vss osc32vss upllvss quiet gnd for analog blocks q vdd internal power supply q vdd power supply pins for silicon internal circuitry qvss gnd pins for silicon internal circuitry fuse vdd for fuse vdd rtc vdd for rtc, scc power supply rtcvss for rtc, scc gnd note: note: both 1-wire and fast ethernet controller signals are multiplexed with other signals. as a result these signal names do not appear in this list. the signals are listed below with the named signal that they are multiplexed. 1-wire signals: the 1-wire input and output signal is multiplexed with jtag rtck pad, pe16. fast ethernet controller (fec) signals: fec_tx_en: transmit enable signal, through gpio multiplexed with ata_data15 pad; pf23 fec_tx_er: transmit data error; through gpio multiplexed with ata_data14 pad; pd16 fec_col: collision signal; through gpio multiplexed with ata_data13 pad; pd15 fec_rx_clk: receive clock signal; through gpio multiplexed with ata_data12 pad; pd14 fec_rx_dv: receive data valid signal; through gpio multiplexed with ata_data11 pad; pd13 fec_rxd0: receive data0; through gpio multiplexed with ata_data10 pad; pd12 fec_tx_clk: transmit clock signal; through gpio multiplexed with ata_data9 pad; pd11 fec_crs: carrier sense enable; through gpio multiplexed with ata_data8 pad; pd10 fec_mdc: management data clock; through gpio multiplexed with ata_data7 pad; p d9 fec_mdio: management data input/output, multiplexed with ata_data6 pad; pd8 fec_rxd3?1: receive data; through gpio multiplexed with ata_data5?3 pad; pd7?5 fec_rx_er: receive data error; through gpio multiplexed with ata_data2 pad; pd4 fec_txd3?2: transmit data; through gpio multiplexed with ata_data1?0; pad; pd3?2 fec_txd1: transmit data; through gpio multiplexed with sd3_clk pad; pd1 fec_txd0: transmit data; through gpio multiplexed with sd3_cmd pad; pd0 note: the rest ata signals are multiplexed with pcmcia pads. table 5-1. i.mx27 signal descriptions (continued) pad name function/notes signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-10 freescale semiconductor functional multiplexing information shown in table 5-2 enables the user to select the function of each pin by configuring the appropriate gpio registers when those pins are multiplexed to provide different functions. in some cases, the use of the func tion multiplexing control register (fmcr) in chapter 4, ?system control ? may be required to select multiplex functionality. 5.3.1 pull/pull strength/open drain descriptions for table 5-2 , the following notes describe the abbreviations used in the pull/pull strength/open drain section. ? kp?keeper circuit permanently on when in primary/alternate mode ? pu?pull up permanently on when in primary/alternate mode ? pd?pull down permanently on when in primary/alternate mode ? puen?pull up controllable from module when in primary/alternate mode ? pden?pull down controllable from module when in primary/alternate mode ? od?open drain permanently on when in primary/alternate mode ? oden?open drain enable controllable from module when in primary/alternate mode 5.3.2 gpio default and pull-up configuration ? the term primary name is the package contact name. ? the default column contains the gpio defau lt configuration as it a ppears after chip reset. ? pull-up configuration and pull strength?pin mux wi th gpio means that pull up is controlled by the gpio puen register (in primary, alternate or gpio mode), and the default pull strength is 100 k for all gpio use. 5.3.3 i/o mode and supply level the supply level shown in table 5-2 relates to the power bank segment. the same bank pad can be supplied same voltage. the voltage limitati on relates to the i/o mode selected. ? i/o type of ddr mode?voltage rating 1.65?1.95 v. supply level 1.8 v is recommended for 100% duty cycle. ? i/o type of slow mode?v oltage rating 1.65?3.3 v. supply level 3.05 v is recommended for 100% duty cycle; ? i/o type of fast mode?voltage rating 1.65?3 v. supply level 2.8 v is recommended for 100% duty cycle; ? for every analog pad a recommended supply voltage is shown. signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-11 table 5-2. i.mx27 pin mux table ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default t19 avdd supply avss static avss u18 avdd supply avdd static avdd u19 avdd slow/hyst boot2 i boot2 v23 avdd slow/hyst boot0 i boot0 y22 avdd slow/hyst boot3 i boot3 y23 avdd slow/hyst boot1 i boot1 m18 fpmvdd supply fpmvdd static fpmvdd p15 fpmvdd supply fpmvss static fpmvss r18 fusevdd supply fusevdd static fusevd d r19 fusevdd supply fusevss static fusevs s r15 mpllvdd supply mpllvss static mpllvss t18 mpllvdd supply mpllvdd static mpllvd d gnd nvdd1 supply nvss1 static nvss1 h1 nvdd1 fast nfrb i etmtrace pkt3 o pf0 puen nfrb j1 nvdd1 fast nfwp_b o etmtrace pkt1 o pf2 puen nfwp_b MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-12 freescale semiconductor signal descriptions and pin assignments k1 nvdd1 fast nfale o etmpipes tat 0 o pf4 puen nfale l1 nvdd1 fast nfwe_b o etmpipes tat 2 o pf6 pden nfwe_b l2 nvdd1 fast nfce_b o etmtrace pkt2 o pf3 puen nfcle l5 nvdd1 fast nfre_b o etmpipes tat 1 o pf5 puen nfre_b l6 nvdd1 fast nfcle o etmtrace pkt0 o pf1 puen nfce_b m1 nvdd1 ddr d14 b kp d14 m2 nvdd1 ddr d15 b kp d15 m3 nvdd1 ddr d11 b kp d11 m5 nvdd1 ddr d13 b kp d13 m6 nvdd1 ddr d9 b kp d9 n1 nvdd1 ddr d12 b kp d12 n2 nvdd1 ddr d7 b kp d7 n3 nvdd1 ddr d5 b kp d5 n5 nvdd1 ddr d3 b kp d3 n6 nvdd1 ddr d1 b kp d1 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-13 nvdd 1 nvdd1 supply nvdd1 static nvdd1 p1 nvdd1 ddr d10 b kp d10 p2 nvdd1 ddr d8 b kp d8 r1 nvdd1 ddr d6 b kp d6 r2 nvdd1 ddr d4 b kp d4 t1 nvdd1 ddr d2 b kp d2 t2 nvdd1 ddr d0 b kp d0 a10 nvdd10 slow/hyst ssi2_rxd at b gpt5_tin i pc25 puen pc25 a11 nvdd10 slow/hyst ssi3_rxd at b slcdc2_r s i pc29 puen pc_v s1 pc29 a12 nvdd10 slow_/hyst kp_row1 b pu/100k kp_row 1 a13 nvdd10 slow1/hyst kp_row5 b pu/100k kp_row 5 a8 nvdd10 slow/hyst ssi4_rxd at b pc17 puen iois16 pc17 a9 nvdd10 slow/hyst ssi1_rxd at b pc21 puen pc21 b10 nvdd10 slow/hyst ssi2_clk b gpt4_tin i pc27 puen pc27 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-14 freescale semiconductor signal descriptions and pin assignments b11 nvdd10 slow/hyst ssi3_clk b slcdc2_c lk i pc31 puen pc_w ait_b pc31 b12 nvdd10 slow/hyst kp_row3 b pu/100k kp_row 3 b7 nvdd10 slow/hyst tin i pc15 puen gpt6_ tout wkgd _b pc15 b8 nvdd10 slow/hyst ssi4_clk b pc19 puen pc_b vd1 pc19 b9 nvdd10 slow/hyst ssi1_clk b pc23 puen pc23 c12 nvdd10 slow/hyst kp_row2 b pu/100k kp_row 2 c9 nvdd10 slow/hyst ssi3_txd at b slcdc2_c s i pc30 puen pc_r eady pc30 e10 nvdd10 slow/hyst ssi3_fs b slcdc2_d 0 i pc28 puen pc_v s2 pc28 e11 nvdd10 slow/hyst kp_row4 b pu/100k kp_row 4 e8 nvdd10 slow/hyst tout o pc14 puen ssi_m clk1 ssi_m clk2 gpt6_ tin pc14 e9 nvdd10 slow/hyst ssi1_txd at b pc22 puen pc22 f10 nvdd10 slow/hyst ssi2_txd at b gpt4_tou t o pc26 puen pc26 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-15 f11 nvdd10 slow/hyst kp_row0 b pu/100k kp_row 0 f8 nvdd10 slow/hyst ssi4_fs b pc16 puen pc16 f9 nvdd10 slow/hyst ssi1_fs b pc20 puen pc20 g11 nvdd10 supply nvdd10 static nvdd10 g8 nvdd10 slow/hyst ssi4_txd at b pc18 puen pc_b vd2 pc18 g9 nvdd10 slow/hyst ssi2_fs b gpt5_tou t o pc24 puen pc24 gnd nvdd10 supply nvss10 static nvss10 a5 nvdd11 slow/hyst csi_d3 i uart6_rt s i pb13 puen lcdc _test 9 pb13 a6 nvdd11 slow/hyst csi_d5 i pb17 puen lcdc _test 11 pb17 a7 nvdd11 slow/hyst csi_hsyn c i uart5_rt s i pb21 puen lcdc _test 15 pb21 b4 nvdd11 slow/hyst csi_d1 i uart6_rx d i pb11 puen lcdc _test 7 pb11 b5 nvdd11 fast/hyst csi_mclk o pb15 puen pb15 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-16 freescale semiconductor signal descriptions and pin assignments b6 nvdd11 slow/hyst csi_d7 i uart5_rx d i pb19 puen lcdc _test 13 pb19 c4 nvdd11 slow/hyst csi_d0 i uart6_tx d o pb10 puen lcdc _test 6 pb10 e6 nvdd11 slow/hyst csi_d2 i uart6_ct s o pb12 puen lcdc _test 8 pb12 e7 nvdd11 fast/hyst csi_pixcl k i pb16 puen pb16 f6 nvdd11 slow/hyst csi_d4 i pb14 puen lcdc _test 10 pb14 f7 nvdd11 slow/hyst csi_d6 i uart5_tx d o pb18 puen lcdc _test 12 pb18 g10 nvdd11 supply nvdd11 static nvdd11 g7 nvdd11 slow/hyst csi_vsyn c i uart5_ct s o pb20 puen lcdc _test 14 pb20 gnd nvdd11 supply nvss11 static nvss11 b3 nvdd12 slow/hyst spl_spr o pa 2 7 pden slcd c1_cl k pa 2 7 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-17 c2 nvdd12 slow/hyst contras t o pa 3 0 puen pa 3 0 d1 nvdd12 slow/hyst hsync o pa 2 8 puen pa 2 8 d2 nvdd12 slow/hyst ps o pa 2 6 pden slcd c1_cs pa 2 6 d3 nvdd12 slow/hyst oe_acd o pa 3 1 puen pa 3 1 e1 nvdd12 slow/hyst rev o pa 2 4 pden sldc d1_d0 pa 2 4 e2 nvdd12 slow/hyst ld16 o pa 2 2 puen ext_d magra nt_b pa 2 2 f1 nvdd12 slow/hyst ld14 o pa 2 0 puen slcd c1_da t14 slcd c1_da t6 pa 2 0 f2 nvdd12 slow/hyst ld10 o pa 1 6 puen slcd c1_da t10 slcd c1_da t2 pa 1 6 f5 nvdd12 slow/hyst vsync o pa 2 9 puen pa 2 9 g1 nvdd12 slow/hyst ld8 o pa 1 4 puen slcd c1_da t8 slcd c1_da t0 pa 1 4 g2 nvdd12 slow/hyst ld6 o pa 1 2 puen slcd c1_da t6 pa 1 2 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-18 freescale semiconductor signal descriptions and pin assignments g5 nvdd12 slow/hyst ld17 o pa 2 3 puen pa 2 3 g6 nvdd12 slow/hyst cls o pa 2 5 pden slcd c1_rs pa 2 5 gnd nvdd12 supply nvss12 static nvss12 h2 nvdd12 slow/hyst ld4 o pa 1 0 puen slcd c1_da t4 pa 1 0 h3 nvdd12 slow/hyst ld12 o pa 1 8 puen slcd c1_da t12 slcd c1_da t4 pa 1 8 h5 nvdd12 slow/hyst ld13 o pa 1 9 puen slcd c1_da t13 slcd c1_da t5 pa 1 9 h6 nvdd12 slow/hyst ld15 o pa 2 1 puen slcd c1_da t15 slcd c1_da t7 pa 2 1 j2 nvdd12 slow/hyst ld0 o pa 6 puen slcd c1_da t0 pa 6 j3 nvdd12 slow/hyst ld2 o pa 8 puen slcd c1_da t2 pa 8 j5 nvdd12 slow/hyst ld7 o pa 1 3 puen slcd c1_da t7 pa 1 3 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-19 j6 nvdd12 slow/hyst ld5 o pa 1 1 puen slcd c1_da t5 pa 1 1 j7 nvdd12 slow/hyst ld11 o pa 1 7 puen slcd c1_da t11 slcd c1_da t3 pa 1 7 k2 nvdd12 fast/hyst lsclk o pa 5 puen pa 5 k5 nvdd12 slow/hyst ld3 o pa 9 puen slcd c1_da t3 pa 9 k6 nvdd12 slow/hyst ld1 o pa 7 puen slcd c1_da t1 pa 7 k7 nvdd12 slow/hyst ld9 o pa 1 5 puen slcd c1_da t9 slcd c1_da t1 pa 1 5 l7 nvdd12 supply nvdd12 static nvdd12 gnd nvdd13 supply nvss13 static nvss13 l24 nvdd13 slow/hyst osc32k_by pass i osc32k_b ypass m19 nvdd13 supply nvdd13 static nvdd13 n19 nvdd13 slow/hyst power_on_ reset i pu/100k power_on _reset table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-20 freescale semiconductor signal descriptions and pin assignments n22 nvdd13 slow/hyst power_cut i pd/100k power_cu t c23 nvdd14 fast/hyst cspi2_ss 1 b usbh2_da ta3/rxdp b pd20 puen pd20 c24 nvdd14 slow/hyst usbh1_o e_b b pb27 puen slcd c1_da t2 pb27 d22 nvdd14 fast/hyst cspi2_ss 2 b usbh2_da ta4/rxdm b pd19 puen pd19 d23 nvdd14 fast/hyst cspi2_sc lk b usbh2_da ta 0 / o e n b pd22 puen pd22 d24 nvdd14 slow/hyst usbh1_tx dp o uart4_ct s o pb29 pden slcd c1_da t4 uart4 _rxd_ alt pb29 e19 nvdd14 slow/hyst usbh1_fs b uart4_rt s i pb26 pden slcd c1_da t1 pb26 e22 nvdd14 fast/hyst cspi1_ss 2 b usbh2_da ta 5 / r c v b pd26 puen pd26 e23 nvdd14 fast/hyst cspi2_mo si b usbh2_da ta 1 / t x d p b pd24 puen pd24 e24 nvdd14 slow/hyst usbh1_r xdp b uart4_rx d i pb31 pden slcd c1_da t6 uart4 _rts_ alt pb31 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-21 f19 nvdd14 slow/hyst usbh1_tx dm o uart4_tx d o pb28 pden slcd c1_da t3 pb28 f20 nvdd14 fast/hyst cspi2_ss 0 b usbh2_da ta6/speed b pd21 puen pd21 f23 nvdd14 slow/hyst usb_pwr o pb23 puen pb23 f24 nvdd14 slow/hyst i2c2_scl b od pc6 puen slcd c1_da t8 pc6 g19 nvdd14 slow/hyst usbh1_s usp b pb22 puen usb_by p_b g20 nvdd14 fast/hyst cspi2_mis o b usbh2_da ta 2 / t x d m b pd23 puen pd23 gnd nvdd14 supply nvss14 static nvss14 h18 nvdd14 supply nvdd14 static nvdd14 h20 nvdd14 slow/hyst usb_oc_ b i pb24 puen pb24 h22 nvdd14 slow/hyst usbh1_r cv b pb25 puen slcd c1_da t0 pb25 j20 nvdd14 slow/hyst usbh1_r xdm b pb30 pden slcd c1_da t5 uart4 _cts pb30 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-22 freescale semiconductor signal descriptions and pin assignments j22 nvdd14 slow/hyst i2c2_sda b od pc5 puen slcd c1_da t7 pc5 a3 nvdd15 slow/hyst sd2_d3 b pu/pd/1 00k mshc_dat a3 bpu/pd/1 00k pb7 pden slcd c1_rs lcdc _test 3 pb7 a4 nvdd15 fast/hyst sd2_clk o mshc_scl k o pb9 pden lcdc _test 5 pb9 c1 nvdd15 slow/hyst sd2_d0 b pu/100k mshc_dat a0 b pd/100k pb4 pden lcdc _test 0 pb4 c5 nvdd15 slow/hyst sd2_cmd b pu/100k mshc_bs o pd/100k pb8 pden slcd c1_cs lcdc _test 4 pb8 c8 nvdd15 slow/hyst sd2_d2 b pu/100k mshc_dat a2 b pd/100k pb6 pden sldc d1_d0 lcdc _test 2 pb6 e3 nvdd15 slow/hyst sd2_d1 b pu/100k mshc_dat a1 b pd/100k pb5 pden slcd c1_cl k lcdc _test 1 pb5 gnd nvdd15 supply nvss15 static nvss15 h7 nvdd15 supply nvdd15 static nvdd15 aa1 nvdd2 ddr sd30 b kp sd30 aa2 nvdd2 ddr a24 o kp a24 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-23 aa3 nvdd2 ddr sd27 b kp sd27 ab1 nvdd2 ddr a23 o kp a23 ab2 nvdd2 ddr sd24 b kp sd24 ab4 nvdd2 ddr a21 o kp a21 ab5 nvdd2 ddr sd21 b kp sd21 ab8 nvdd2 ddr sd10 b kp sd10 ac3 nvdd2 ddr a22 o kp a22 ac4 nvdd2 ddr sd20 b kp sd20 ac5 nvdd2 ddr sd17 b kp sd17 ac6 nvdd2 ddr a18 o kp a18 ac7 nvdd2 ddr a17 o kp a17 ad3 nvdd2 ddr sd22 b kp sd22 ad4 nvdd2 ddr sd19 b kp sd19 ad5 nvdd2 ddr sd16 b kp sd16 ad6 nvdd2 ddr sd14 b kp sd14 ad7 nvdd2 ddr sd11 b kp sd11 gnd nvdd2 supply nvss2 static nvss2 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-24 freescale semiconductor signal descriptions and pin assignments nvdd 2 nvdd2 supply nvdd2 static nvdd2 p5 nvdd2 ddr a9 b kp a9 p6 nvdd2 ddr a12 b kp a12 r5 nvdd2 ddr a5 b kp a5 r6 nvdd2 ddr a7 b kp a7 t3 nvdd2 ddr ma10 o ma10 t5 nvdd2 ddr sdba1 o kp sdba1 t6 nvdd2 ddr a1 b kp a1 u1 nvdd2 ddr a13 b kp a13 u2 nvdd2 ddr a11 b kp a11 u3 nvdd2 ddr a3 b kp a3 u5 nvdd2 ddr sd31 b kp sd31 u6 nvdd2 ddr a25 o kp a25 v1 nvdd2 ddr a8 b kp a8 v2 nvdd2 ddr a6 b kp a6 v5 nvdd2 ddr sd26 b kp sd26 v6 nvdd2 ddr sd28 b kp sd28 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-25 v7 nvdd2 ddr sd29 b kp sd29 v8 nvdd2 ddr a19 o kp a19 w1 nvdd2 ddr a4 b kp a4 w2 nvdd2 ddr a2 b kp a2 w5 nvdd2 ddr sd23 b kp sd23 w6 nvdd2 ddr sdqs2 b kp sdqs2 w7 nvdd2 ddr sd25 b kp sd25 w8 nvdd2 ddr sdqs1 b kp sdqs1 w9 nvdd2 ddr sd13 b kp sd13 y1 nvdd2 ddr a0 b kp a0 y2 nvdd2 ddr sdba0 o kp sdba0 y3 nvdd2 ddr sdqs3 b kp sdqs3 y6 nvdd2 ddr a20 o kp a20 y7 nvdd2 ddr sd18 b kp sd18 y8 nvdd2 ddr sd15 b kp sd15 y9 nvdd2 ddr sd12 b kp sd12 ab12 nvdd3 ddr sd0 b kp sd0 ab9 nvdd3 ddr a14 b kp a14 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-26 freescale semiconductor signal descriptions and pin assignments ac10 nvdd3 ddr sd4 b kp sd4 ac11 nvdd3 ddr sd1 b kp sd1 ac8 nvdd3 ddr sd9 b kp sd9 ac9 nvdd3 ddr sd5 b kp sd5 ad10 nvdd3 ddr sd3 b kp sd3 ad11 nvdd3 ddr dqm3 o kp dqm3 ad8 nvdd3 ddr sd7 b kp sd7 ad9 nvdd3 ddr sdqs0 b kp sdqs0 gnd nvdd3 supply nvss3 static nvss3 nvdd 3 nvdd3 supply nvdd3 static nvdd3 w10 nvdd3 ddr sd6 b kp sd6 w11 nvdd3 ddr a16 o kp a16 y10 nvdd3 ddr sd8 b kp sd8 y11 nvdd3 ddr a15 b kp a15 y12 nvdd3 ddr sd2 b kp sd2 ab13 nvdd4 ddr ras_b o kp ras_b ab16 nvdd4 ddr cs1_b o cs1_b table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-27 ab17 nvdd4 ddr bclk o bclk ac12 nvdd4 ddr a10 b kp a10 ac13 nvdd4 ddr cas_b o kp cas_b ac14 nvdd4 ddr sdcke0 o kp sdcke0 ac15 nvdd4 ddr rw_b o rw_b ac16 nvdd4 fast ecb_b i pu/100k ecb_b ac17 nvdd4 ddr eb1_b o eb1_b ac18 nvdd4 fast jtag_ctr l i pu/100k jtag_ct rl ad12 nvdd4 ddr dqm0 o kp dqm0 ad13 nvdd4 ddr_clk sdclk b sdclk ad14 nvdd4 ddr_clk sdclk_b b sdclk_ b ad15 nvdd4 fast cs4_b o etmtrace sync o pf21 puen cs5_d ta c k cs4_b ad16 nvdd4 ddr cs0_b o cs0_b ad17 nvdd4 fast clko o pf15 puen clko ad18 nvdd4 fast ext_266m i ext_266 m gnd nvdd4 supply nvss4 static nvss4 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-28 freescale semiconductor signal descriptions and pin assignments v13 nvdd4 supply nvdd4 static nvdd4 w12 nvdd4 ddr dqm1 o kp dqm1 w13 nvdd4 ddr sdwe_b o kp sdwe_b w14 nvdd4 ddr cs3_b o kp cs3_b w15 nvdd4 fast cs5_b o etmtrace clk o pf22 puen cs5_b w16 nvdd4 ddr eb0_b o eb0_b w17 nvdd4 fast ext_60m i ext_60m y13 nvdd4 ddr dqm2 o kp dqm2 y14 nvdd4 ddr sdcke1 o kp sdcke1 y15 nvdd4 ddr cs2_b o kp cs2_b y16 nvdd4 ddr lba_b o lba_b y17 nvdd4 ddr oe_b o oe_b aa22 nvdd5 slow/hyst reset_o ut_b o pe17 puen pc_te st_ah bst0 reset_ out_b ab20 nvdd5 slow/hyst clkmode 0 i pu/100k clkmod e0 ab21 nvdd5 slow/hyst clkmode 1 i pu/100k clkmod e1 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-29 ac19 nvdd5 slow pc_cd2_b i ata _ d i ow o pf19 puen pc_cd2_ b ac20 nvdd5 slow pc_vs1 i ata _ da 1 o pf14 puen pc_vs1 ac21 nvdd5 slow pc_rst o ata _ r e s e t_b o pf10 puen pc_rst ac22 nvdd5 slow/hyst reset_in _b i pu/100k reset_i n_b ad19 nvdd5 slow pc_read y i ata _ c s 0 o pf17 puen pc_rea dy ad20 nvdd5 slow pc_bvd1 i ata_dmar q i pf12 puen pc_bvd 1 ad21 nvdd5 slow pc_rw_b o ata_iordy i pf8 puen pc_rw_ b ad22 nvdd5 slow/hyst por_b i por_b gnd nvdd5 supply nvss5 static nvss5 nvdd 5 nvdd5 supply nvdd5 static nvdd5 u20 nvdd5 slow iois16 i ata _ i n t r q i pf9 puen iois16 v20 nvdd5 slow pc_poe o ata_buff er_en o pf7 puen pc_poe w18 nvdd5 slow pc_cd1_b i ata _ d i o r o pf20 puen pc_cd1_ b table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-30 freescale semiconductor signal descriptions and pin assignments w19 nvdd5 slow pc_vs2 i ata _ da 0 o pf13 puen pc_vs2 w20 nvdd5 slow pc_bvd2 i ata _ d m a c k o pf11 puen pc_bvd 2 y18 nvdd5 slow pc_wait_ b i ata _ c s 1 o pf18 puen pc_wait _b y19 nvdd5 slow pc_pwro n i ata _ da 2 o pf16 pden pc_pwr on gnd nvdd6 supply nvss6 static nvss6 nvdd 6 nvdd6 supply nvdd6 static nvdd6 p19 nvdd6 slow/hyst ata_data6 b fec_mdio b pd8 puen slcd c1_da t6 ata _ dat a6 p20 nvdd6 slow/hyst ata_data2 b sd3_d2 b pd4 puen slcd c1_da t2 fec_ rx_e r ata _ dat a2 p23 nvdd6 slow/hyst sd3_cmd b pd0 puen fec_t xd0 sd3_cm d p24 nvdd6 slow/hyst sd3_clk o etmtrace pkt15 o pd1 puen fec_t xd1 sd3_clk r20 nvdd6 slow/hyst ata_data1 0 b etmtrace pkt9 o pd12 puen slcd c1_da t10 fec_ rxd0 ata _ dat a10 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-31 r23 nvdd6 slow/hyst ata_data0 b sd3_d0 b pd2 puen fec_t xd2 slcd c1_da t0 ata _ dat a0 r24 nvdd6 slow/hyst ata_data1 b sd3_d1 b pd3 puen fec_t xd3 slcd c1_da t1 ata _ dat a1 t20 nvdd6 slow/hyst ata_data1 4 b etmtrace pkt5 o pd16 pden fec_t x_er slcd c1_da t14 ata _ dat a14 t22 nvdd6 slow/hyst ata_data4 b etmtrace pkt14 o pd6 puen slcd c1_da t4 fec_ rxd2 ata _ dat a4 t23 nvdd6 slow/hyst ata_data5 b etmtrace pkt13 o pd7 puen slcd c1_da t5 fec_ rxd3 ata _ dat a5 t24 nvdd6 slow/hyst ata_data3 b sd3_d3 bpu/pd/1 00k pd5 pden slcd c1_da t3 fec_ rxd1 ata _ dat a3 u22 nvdd6 slow/hyst ata_data8 b etmtrace pkt11 o pd10 puen slcd c1_da t8 fec_ crs ata _ dat a8 u23 nvdd6 slow/hyst ata_data1 2 b etmtrace pkt7 o pd14 puen slcd c1_da t12 fec_ rx_cl k ata _ dat a12 u24 nvdd6 slow/hyst ata_data7 b etmtrace pkt12 o pd9 puen fec_ mdc slcd c1_da t7 ata _ dat a7 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-32 freescale semiconductor signal descriptions and pin assignments v24 nvdd6 slow/hyst ata_data9 b etmtrace pkt10 o pd11 puen slcd c1_da t9 fec_t x_clk ata _ dat a9 w23 nvdd6 slow/hyst ata_data1 1 b etmtrace pkt8 o pd13 puen slcd c1_da t11 fec_ rx_d v ata _ dat a11 w24 nvdd6 slow/hyst ata_data1 3 b etmtrace pkt6 o pd15 puen slcd c1_da t13 fec_ col ata _ dat a13 y24 nvdd6 slow/hyst ata_data1 5 b etmtrace pkt4 o pf23 pden fec_t x_en slcd c1_da t15 ata _ dat a15 g18 nvdd7 fast/hyst usbotg_ data1/txd p b pc11 puen slcd c1_da t13 pc11 g23 nvdd7 fast/hyst usbotg_ data2/txd m b pc10 puen slcd c1_da t12 pc10 g24 nvdd7 fast/hyst usbotg_ data6/spe ed b pc8 puen slcd c1_da t10 usbg _txr_ int_b pc8 gnd nvdd7 supply nvss7 static nvss7 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-33 h19 nvdd7 fast/hyst usbotg_ data5/rc v b pc7 puen slcd c1_da t9 pc7 h23 nvdd7 fast/hyst usbh2_cl k/txdm i pa 0 puen pa 0 h24 nvdd7 fast/hyst usbotg_ data4/rx dm b pc12 puen slcd c1_da t14 pc12 j19 nvdd7 fast/hyst usbotg_ data0/oen b pc9 puen slcd c1_da t11 pc9 j23 nvdd7 fast/hyst usbh2_st p/txdm o pa 4 puen pa 4 j24 nvdd7 fast/hyst usbh2_da ta 7 / s u s p end b pa 2 puen pa 2 k20 nvdd7 fast/hyst usbotg_ data3/rx dp b pc13 puen slcd c1_da t15 pc13 k23 nvdd7 fast/hyst usbh2_di r/txdm i pa 1 puen pa 1 k24 nvdd7 fast/hyst usbotg_ clk/txdm i pe24 puen pe24 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-34 freescale semiconductor signal descriptions and pin assignments l20 nvdd7 fast/hyst usbh2_n xt/txdm i pa 3 puen pa 3 l23 nvdd7 fast/hyst usbotg_ stp/txdm o kp_row6a b pe1 puen pe1 m20 nvdd7 fast/hyst usbotg_ nxt/txdm i kp_col6a boden pe0 puen pe0 m22 nvdd7 fast/hyst usbotg_ data7/su spend b pe25 puen pe25 n20 nvdd7 fast/hyst usbotg_ dir/txdm i kp_row7a b pe2 puen pe2 nvdd 7 nvdd7 supply nvdd7 static nvdd7 a19 nvdd8 slow/hyst rtck o owire bod pe16 puen rtck a20 nvdd8 slow/hyst sd1_d0 b cspi3_mis o i pe18 puen pc_te st_ah bst1 pe18 a21 nvdd8 slow/hyst sd1_cmd b cspi3_mo si o pe22 puen pc_te st_in t_er r pe22 a22 nvdd8 slow/hyst cspi1_mis o b pd30 puen pd30 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-35 b18 nvdd8 slow/hyst tdi i pu/100k tdi b19 nvdd8 slow/hyst tms i pu/100k tms b20 nvdd8 slow/hyst sd1_d2 b pe20 puen pc_te st_ca rdst 1 pe20 b21 nvdd8 slow/hyst cspi1_rd y/ext_dma req_b i pd25 puen pd25 b22 nvdd8 slow/hyst cspi1_ss 0 b pd28 puen pd28 c17 nvdd8 slow/hyst trst_b i pu/100k trst_b c20 nvdd8 slow/hyst cspi1_ss 1 b pd27 puen ext_d magra nt_b ext_d magra nt_b pd27 c21 nvdd8 slow/hyst cspi1_mo si b pd31 puen pd31 e16 nvdd8 slow/hyst tdo o tdo e17 nvdd8 slow/hyst sd1_d1 b pe19 puen pc_te st_ca rdst 0 pe19 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-36 freescale semiconductor signal descriptions and pin assignments e18 nvdd8 slow/hyst sd1_d3 b pu/pd/1 00k cspi3_ss opu/pd pe21 pden pc_te st_ca rdst 2 pe21 f17 nvdd8 slow/hyst tck i pu/100k tck f18 nvdd8 slow/hyst cspi1_sc lk b pd29 puen pd29 g15 nvdd8 supply nvdd8 static nvdd8 g17 nvdd8 slow/hyst sd1_clk o cspi3_scl k o pe23 puen pc_te st_in t_all pe23 gnd nvdd8 supply nvss8 static nvss8 a14 nvdd9 slow2/hyst uart2_rt s i kp_row7 b pe4 puen uart2_r ts a15 nvdd9 slow/hyst kp_col2 b pu/100k/ oden kp_col2 a16 nvdd9 slow/hyst uart2_tx d o kp_col6 boden pe6 puen uart2_t xd a17 nvdd9 slow/hyst uart3_ct s o pe10 puen pe10 a18 nvdd9 slow/hyst uart1_ct s o pe14 puen uart1_c ts b13 nvdd9 slow/hyst i2c_clk b od pd18 puen pd18 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-37 b14 nvdd9 slow/hyst kp_col0 b pu/100k/ oden kp_col0 b15 nvdd9 slow/hyst kp_col4 b pu/100k/ oden kp_col4 b16 nvdd9 slow/hyst uart3_tx d o pe8 puen pe8 b17 nvdd9 slow/hyst uart1_tx d o pe12 puen uart1_t xd c13 nvdd9 slow/hyst pwmo o pe5 puen pc_s pkou t tout 2 tout 3 pe5 c16 nvdd9 slow/hyst uart1_rt s i pe15 puen uart1_r ts e12 nvdd9 slow/hyst uart2_ct s o kp_col7 boden pe3 puen uart2_c ts e13 nvdd9 slow/hyst kp_col3 b pu/100k/ oden kp_col3 e14 nvdd9 slow/hyst uart2_rx d i kp_row6 b pe7 puen uart2_r xd e15 nvdd9 slow/hyst uart3_rt s i pe11 puen pe11 f12 nvdd9 slow/hyst i2c_data b od pd17 puen pd17 f13 nvdd9 slow/hyst kp_col1 b pu/100k/ oden kp_col1 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-38 freescale semiconductor signal descriptions and pin assignments f14 nvdd9 slow/hyst kp_col5 b pu/100k/ oden kp_col5 f15 nvdd9 slow/hyst uart3_rx d i pe9 puen pe9 f16 nvdd9 slow/hyst uart1_rx d i pe13 puen uart1_r xd g14 nvdd9 supply nvdd9 static nvdd9 gnd nvdd9 supply nvss9 static nvss9 aa23 osc26vdd supply osc26vd d static osc26v dd aa24 osc26vdd analog_by p xtal26m static xtal26m ab23 osc26vdd supply osc26vs s static osc26v ss ab24 osc26vdd analog_by p extal26m static extal26 m v19 osc26vdd analog osc26m_ test i osc26m _test m23 osc32vdd supply osc32vd d static osc32v dd m24 osc32vdd analog extal32k i extal32 k n23 osc32vdd supply osc32vs s static osc32v ss table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default i/o power supply and signal multiplexing scheme freescale semiconduter signal descriptions and pin assignments 5-39 n24 osc32vdd analog xtal32k i xtal32k gnd qvdd10 supply qvss10 static qvss10 qvdd qvdd10 supply qvdd10 static qvdd10 gnd qvdd12 supply qvss12 static qvss12 qvdd qvdd12 supply qvdd12 static qvdd12 gnd qvdd2 supply qvss2 static qvss2 qvdd qvdd2 supply qvdd2 static qvdd2 gnd qvdd3 supply qvss3 static qvss3 qvdd qvdd3 supply qvdd3 static qvdd3 gnd qvdd5 supply qvss5 static qvss5 qvdd qvdd5 supply qvdd5 static qvdd5 gnd qvdd6 supply qvss6 static qvss6 qvdd qvdd6 supply qvdd6 static qvdd6 gnd qvdd7 supply qvss7 static qvss7 qvdd qvdd7 supply qvdd7 static qvdd7 gnd qvdd8 supply qvss8 static qvss8 table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-40 freescale semiconductor signal descriptions and pin assignments qvdd qvdd8 supply qvdd8 static qvdd8 k18 rtcvdd supply rtcvss static rtcvss k19 rtcvdd supply rtcvdd static rtcvdd j18 upllvdd supply upllvdd static upllvdd m15 upllvdd supply upllvss static upllvss 1 indicates direction of primary signal. it may not indicate the direction of the pin as it may be dependent on other functions. 2 kp = keeper circuit permanently on when in primary/alternate mode; pu = pull up permanently on when in primary/alternate mode; puen = pull up controllable from module when in primary/alternate mode; od = open drain permanently on when in primary/alternate mode; oden = open drain controllable from module when in primary/alternate mode. 3 pin mux with gpio has its pull up controlled by the gpio puen register (in primary, alternate, or gpio mode) table 5-2. i.mx27 pin mux table (continued) ball map location power bank i/o type primary alternate gpio signal/pad name direction 1 pull-up/pull strength/open drain 2 signal direction 2 pull-up /pull strength /open drain mux 3 puen/pden ain bin cin aout bout default signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-41 5.4 package pin assignments table 5-3 through table 5-6 identifies the i.mx27 full package mapbga pin assignments. the connection of these pins depends solely upon the user application, however there are a few factory test signals that are not used in normal applications. follow ing is a list of these signals and how they are to be terminated for proper operati on of the i.mx27 processor: ? clkmode[1:0]: to ensure proper operation, leave these signals as no connects. ? osc26m_test: to ensure proper operation, leave this signal as no connect. ? ext_48m: to ensure proper operation, connect this signal to ground. ? ext_266m: to ensure proper operation, connect this signal to ground. signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-42 freescale semiconductor table 5-3. i.mx27 full package mapbga pin assignment (1 of 4) 12345678 agnd gnd sd2_d3_m shc _da ta 3_p b 7_ pad sd2_clk_m sh c_sclk_p b 9_ pad csi_d3_uart6 _rts_p b 13_p a d csi_d5_p b 17_ pad csi_hsync_u a rt5_rts_p b 21_p a d ssi4_rxda t_p c17_p a d bgnd gnd sp l_sp r_p a 2 7_p a d csi_d1_uart6 _rxd_p b 11_p a d csi_m clk_pb1 5_p a d csi_d7_uart5 _rxd_p b 19_p ad tin_pc15_pad ssi4_clk_p c19 _p a d c sd2_d0_m shc _da ta 0_p b 4_ pad contrast_p a 30_p a d csi_d0_uart6 _txd_p b 10_p a d sd2_cm d_m s hc_b s_p b 8_p ad sd2_d2_m shc _data2_pb6_ pad d hsync_p a 28_ pad ps_pa26_pad oe_a cd_p a 31 _p a d e rev_p a 24_p a d ld16_p a 22_p a d sd2_d1_m shc _da ta 1_p b 5_ pad csi_d2_uart6 _cts_p b 12_p a d csi_pixclk_p b16_pad tout_p c14_p ad f ld14_p a 20_p a d ld10_p a 16_p a d vsync_p a 29_ pad csi_d4_p b 14_ pad csi_d6_uart5 _txd_p b 18_p a d ssi4_fs_p c16_ pad g ld8_p a 14_p a d ld6_p a 12_p a d ld17_p a 23_p a d cls_p a 25_p a d csi_vsync_ua rt5_cts_p b 2 0_p a d ssi4_txda t_p c18_pad h nfrb_etm tr a cep kt3_p f0 ld4_p a 10_p a d ld12_p a 18_p a d ld13_p a 19_p a d ld15_p a 21_p a d nvdd15 j nfwp_b_etm tra cep kt1_p f2 ld0_p a 6_p a d ld2_p a 8_p a d ld7_p a 13_p a d ld5_p a 11_p a d ld11_p a 17_p a d k nfa le_etm p i pestat0_pf4 lsclk_p a 5_p ad ld3_p a 9_p a d ld1_p a 7_p a d ld9_p a 15_p a d l nfwe_b_etm pipestat2_pf 6 nfce_b_etm t racepkt2_pf 3 nfre_b _etm pipestat1_pf 5 nfcle_etm tr a cep kt0_p f1 nvdd12 m d14_pad d15_pad d11_pad d13_pad d9_pad nvdd1 signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-43 table 5-4. i.mx27 full package mapbga pin assignment (2 of 4) 13 14 15 16 17 18 19 20 21 22 23 24 kp_row 5_pad uart2_rts_kp _row 7_pe4_p a d kp_col2_pad uart2_txd_kp _col6_pe6_pa d uart3_cts_pe 10_pad uart1_cts_pe 14_pad rtck_ow ire_ p e16_pad sd1_d0_cspi3 _ m iso_pe18_pa d sd1_cm d_cspi 3 _m osi_pe22_p a d cspi1_m iso_p d 30_pad gnd gnd a i 2c_clk_pd18_ pad kp_col0_pad kp_col4_pad uart3_txd_pe 8_pad uart1_txd_pe 12_pad tdi_pad tm s_pad sd1_d2_pe20_ p ad cspi 1_rdy_pd 2 5_pad cspi1_ss0_pd2 8_pad gnd gnd b pw m o_pe5_pa d uart1_rts_pe 15_pad trst_b_pad cspi1_ss1_pd2 7_pad cspi1_m osi _p d 31_pad cspi2_ss1_us b h2_data3_pd2 0 usbh1_oe_b_ p b27_pad c cspi2_ss2_us b h2_data4_pd1 9 cspi 2_sclk_u s bh2_data0_pd 22 usbh1_txdp_ u art4_cts_pb2 9 d kp_col3_pad uart2_rxd_k p _row 6_pe7_p a d uart3_rts_pe 11_pad tdo_pad sd1_d1_pe19_ p ad sd1_d3_cspi3 _ ss_pe21_pad usbh1_fs_ua r t4_rts_pb26_ p ad cspi1_ss2_us b h2_data5_pd2 6 cspi2_m osi _u s bh2_data1_pd 24 usbh1_rxdp_ u art4_rxd_pb31 e kp_col1_pad kp_col5_pad uart3_rxd_p e 9_pad uart1_rxd_p e 13_pad tck_pad cspi1_sclk_p d 29_pad usbh1_txdm _ u art4_txd_pb2 8 cspi2_ss0_us b h2_data6_pd21 usb_pw r_pb2 3 _pad i2c2_scl_pc6_ pad f qvdd nvdd9 nvdd8 qvdd sd1_clk_cspi 3 _sclk_pe23_p a d usbotg_data1 _pc11_pad usbh1_susp_ p b22_pad cspi2_m iso_u s bh2_data2_pd 23 usbotg_data 2 _pc10_pad usbo tg_data 6 _pc8_pad g nvdd14 usbotg_data 5 _pc7_pad usb_oc_b_pb2 4_pad usbh1_rcv_p b 25_pad usbh2_clk_p a 0_pad usbo tg_data 4 _pc12_pad h upllvdd_pad usbotg_data 0 _pc9_pad usbh1_rxdm _ p b30_pad i2c2_sda_pc5 _ pad usbh2_stp_p a 4_pad usbh2_data7_ pa2_pad j gnd gnd gnd rtcvss_pad rtcvdd_pad usbotg_data 3 _pc13_pad usbh2_dir_pa1 _pad usbotg _clk_ p e24_pad k gnd gnd gnd nvdd7 nvdd7 usbh2_nxt_p a 3_pad usbotg_stp_ k p_row 6a_pe1 _ pad osc32k_bypa s s_pad l gnd gnd upllvss_pad fpm vdd_pad nvdd13 usbotg_nxt_ k p_col6a_pe0_ p ad usbotg_data 7 _pe25_pad osc32vdd_pad extal32k_pad m signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-44 freescale semiconductor table 5-5. i.mx27 full package mapbga pin assignment (3 of 4) n d12_pad d7_pad d5_pad d3_pad d1_pad nvdd1 gnd gnd gnd p d10_pad d8_pad a9_pad a12_pad qvdd gnd gnd gnd r d6_pad d4_pad a5_pad a7_pad nvdd2 gnd gnd gnd t d2_pad d0_pad m a10_pad sdba1_pad a1_pad nvdd2 u a13_pad a11_pad a3_pad sd31_pad a25_pad nvdd2 v a8_pad a6_pad sd26_pad sd28_pad sd29_pad a19_pad nvdd2 nvdd2 nvdd3 nvdd3 w a4_pad a2_pad sd23_pad sdqs2_pad sd25_pad sdqs1_pad sd13_pad sd6_pad a16_pad dqm 1_pad y a0_pad sdba0_pad sdqs3_pad a20_pad sd18_pad sd15_pad sd12_pad sd8_pad a15_pad sd2_pad aa sd30_pad a24_pad sd27_pad ab a23_pad sd24_pad a21_pad sd21_pad sd10_pad a14_pad sd0_pad ac gnd gnd a22_pad sd20_pad sd17_pad a18_pad a17_pad sd9_pad sd5_pad sd4_pad sd1_pad a10_pad ad gnd gnd sd22_pad sd19_pad sd16_pad sd14_pad sd11_pad sd7_pad sdqs0_pad sd3_pad dqm 3_pad dqm 0_pad 123456789101112 signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 5-45 table 5-6. i.mx27 full package mapbga pin assignment (4 of 4) gnd gnd gnd nvdd6 pow er_on_r e set_pad usbotg_di r_ k p_row 7a_pe2 _ pad pow er_cut_p ad osc32vss_pad xtal32k_pad n gnd gnd fpm vss_pad nvdd6 ata_data6_fe c_m dio_pd8_p ad ata_data2_sd 3_d2_pd4_pad sd3_cm d_pd0 _ pad sd3_clk_etm t racepkt15_p d 1 p gnd gnd m pllvss_pad fusevdd_pad fusevss_pad ata_data10_e t m tracepkt9_ p d12 ata_data0_sd 3_d0_pd2_pad ata_data1_sd 3_d1_pd3_pad r m pllvdd_pad avss_pad ata_data14_e t m tracepkt5_ p d16 ata_data4_et m tracepkt14 _ pd6 ata_data5_et m tracepkt13 _ pd7 ata_data3_sd 3_d3_pd5_pad t avdd_pad boot2_pad iois16_ata_int rq_pf9_pad ata_data8_et m tracepkt11 _ pd10 ata_data12_e t m tracepkt7_ p d14 ata_data7_et m tracepkt12 _ pd9 u nvdd4 qvdd qvdd qvdd nvdd5 nvdd5 osc26m _test_ pad pc_poe_ata_ b uffer_en_pf7 _ pad boot0_pad ata_data9_et m tracepkt10 _ pd11 v sdw e_b_pad cs3_b_pad cs5_b_etm tr a ceclk_pf22_p a d eb0_b_pad ext_60m _pad pc_cd1_b_at a _dior_pf20_p a d pc_vs2_ata_d a0_pf13_pad pc_bvd2_ata_ dm ack_pf11_p ad ata_data11_e t m tracepkt8_ p d13 ata_data13_e t m tracepkt6_ p d15 w dqm 2_pad sdcke1_pad cs2_b_pad lba_b_pad oe_b_pad pc_w ait_b_at a_cs1_pf18_p a d pc_pw ron_at a_da2_pf16_p a d boot3_pad boot1_pad ata_data15_e t m tracepkt4_ p f23 y reset_out_b _ pe17_pad osc26vdd_pad xtal26m _pad aa ras_b_pad cs1_b_pad bclk_pad clkm ode0_pad clkm ode1_pad osc26vss_pad extal26m _pad ab cas_b_pad sdcke0_pad rw _b_pad ecb_b_pad eb1_b_pad jtag_ctrl_pa d pc_cd2_b_at a _diow _pf19_p a d pc_vs1_ata_d a1_pf14_pad pc_rst_ata_ r eset_b_pf10_ p ad reset_i n_b_p a d gnd gnd ac sdclk_pad sdclk_pad_b cs4_b_etm tr a cesync_pf21_ pad cs0_b_pad clko_pf15_pa d ext_266m _pad pc_ready_at a _cs0_pf17_pa d pc_bvd1_ata_ dm arq_pf12_ p ad pc_rw _b_ata _ iordy_pf8_pa d por_b_pad gnd gnd ad 13 14 15 16 17 18 19 20 21 22 23 24 signal descriptions and pin assignments MCIMX27 multimedia applications processor reference manual, rev. 0.2 5-46 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-1 chapter 6 general-purpose i/o (gpio) 6.1 introduction the gpio module in i.mx27 processor provides six ge neral purpose i/o (gpio) ports (pa, pb, pc, pd, pe, and pf). each gpio port is a 32-bit port that may be multiplexed with one or more dedicated functions. this chapter contains the description of the top level i.mx27 i/o multiplexing strategy that consists of two parts: ? software controllable multiplexing done in the gpio module ? hardware multiplexing done by the iomux module the i/o multiplexing strategy is designed to configure the inputs and outputs of the bono device chip in different modes. it allows a user to use the same i/o pad for alternative purposes of the chip. the design of i/o multiplexer is targeted to be as flexible as possible. refer to chapter 5, ?signal descriptions and pin assignments ? for detailed i/o multiplexing information. figure 6-1 shows the block diagram of the gpio and io mux modules? partition at the top level of the bono processor. figure 6-2 shows a block diagram of an individual port of the gpio module. note a_in, b_in, c_in, a_out, and b_out are internal signals and do not represent individual port signals. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-2 freescale semiconductor figure 6-1. functional block diagram of gpio iomux (part of gpio) gpio i/o mux alternate function primary function pin gdir a_in b_in c_in a_out b_out gp 0 1 mux 0 1 mux 0 1 puen gin gout inuse general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-3 figure 6-2. gpio block diagram for an individual port 6.2 overview the gpio module provides general purpose i/o capa bility to the device. each i/o port can be programmed as either a general purpose input or gene ral purpose output. in addition to gpio functionality, pins can be changed from their default dedicated func tions to alternate functions . input and output signals of peripherals are connected to the iomux module at the dedicated (primary) or alternate inputs. in the output direction, one out of three alternate sources (o riginating from peripherals) can be selected. from the input direction, one out of two alternate destina tions (input to a peripheral) can be selected. 6.3 gpio features the following list contains the gpio features: ? six 32-bit ports, each with direction-configurable pins g_out [i] isr icr1 icr2 imr iconfa1 iconfa2 iconfb1 iconfb2 a_out[i] b_out[i] isr[i] 1?b0 1?b1 isr[i] 1?b0 1?b1 interrupt module ssr g_in[i] ocr1 ocr2 mux mux ddir[i] g_dir[31:0] gp gpr[31:0] g_dir[i] i gius in_use[31:0] puen a_in[i] b_in[i] c_in[i] mux puen[31:0] dr pa d in_use_reset_sel [31:0] general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-4 freescale semiconductor ? software control for input/output pin conf iguration through 32-bit direction register ? software control for multiplexing one out of four different sources for every output. three of them are functional pins from internal modules while the fourth is from the data register of the module. ? software control for routing of every input to two different destinations ? input data can be sampled to the data register. ? inputs can be internally tied to a logic 1 or 0 to ensure any transitions attempted to be processed are ignored. ? one 32-bit general purpose register is dedicated to each gpio port. these registers may be used for software control of iomux block of the gpio. ? every input is configurable as an interrupt and each interrupt can be defined as either: ? rising-edge triggered ? falling-edge triggered ? level sensitive ? the interrupts can be masked using a 32-bit mask register. ? two levels of interrupt masking are provided. interrupts can be indi vidually masked at the bit level or at the port level. ? software reset function: when the swr bit (swr regi ster, 0 bit) is written as a 1, the entire gpio module is reset immediately, and this reset signal is asserted for three system cycles. after this, the reset signal will be released automatically. 6.4 external signals description refer to chapter 5, ?signal descriptions and pin assignments ? for details on the i/o multiplexing scheme and external connection to the gpio module. 6.5 interrupts every external input passes through the interrupt modul e in the gpio module. inside this module, the interrupts may be defined as rising-e dge triggered, or falling-edge trigge red. each interrupt can be masked and also be designated as a high-level interrupt, or a low-level sensitive interrupt. the interrupt status register bits corresponding to the interrupts waiting for service are stored as a value of 1. the interrupt status register is write 1 to clear (w1c). the user is responsible for clearing the in terrupt status register bit after it has been serviced. 6.6 memory map and register definitions the gpio module has six ports and each port has 17 regi sters. in total, the gpio has 102 registers. the registers, other than the sample status register (s sr) and the interrupt status register (isr), have both read and write capability. the sample status register is a read only register, while the interrupt status register is a w1c register; the register can be read, but writing a 1 to any register bit clears the bit. writing a value of 0 to the bit has no effect. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-5 while there are six gpio ports, each capable of repr esenting 32 gpio configurable pins as inputs or outputs, not all bits are mapped to a pin and hence th ese bits do not have any effect and are marked as reserved. these reserved bits are indicated in section 6.6.10, ?gpio in use registers (gius) .? table 6-1 shows the gpio memory map. table 6-1. gpio memory map address register access reset value section/page general registers 0x1001_5000 (pta_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5100 (ptb_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5200 (ptc_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5300 (ptd_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5400 (pte_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5500 (ptf_ddir) data direction register r/w 0x0000_0000 6.6.2/6-11 0x1001_5004 (pta_ocr1) output configuration register 1) r/w 0x0000_0000 6.6.3/6-11 0x1001_5104 (ptb_ocr1) output configuration register 1 r/w 0x0000_0000 6.6.3/6-11 0x1001_5204 (ptc_ocr1) output configuration register 1) r/w 0x0000_0000 6.6.3/6-11 0x1001_5304 (ptd_ocr1) output configuration register 1 r/w 0x0000_0000 6.6.3/6-11 0x1001_5404 (pte_ocr1) output configuration register 1 r/w 0x0000_0000 6.6.3/6-11 0x1001_5504 (ptf_ocr1) output configuration register 1 r/w 0x0000_0000 6.6.3/6-11 0x1001_5008 (pta_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 0x1001_5108 (ptb_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 0x1001_5208 (ptc_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 0x1001_5308 (ptd_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 0x1001_5408 (pte_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-6 freescale semiconductor 0x1001_5508 (ptf_ocr2) output configuration register 2 r/w 0x0000_0000 6.6.4/6-12 0x1001_500c (pta_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_510c (ptb_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_520c (ptc_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_530c (ptd_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_540c (pte_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_550c (ptf_iconfa1) input configuration register a1 r/w 0xffff_ffff 6.6.5/6-13 0x1001_5010 (pta_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5110 (ptb_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5210 (ptc_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5310 (ptd_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5410 (pte_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5510 (ptf_iconfa2) input configuration register a2 r/w 0xffff_ffff 6.6.6/6-14 0x1001_5014 (pta_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5114 (ptb_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5214 (ptc_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5314 (ptd_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5414 (pte_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5514 (ptf_iconfb1) input configuration register b1 r/w 0xffff_ffff 6.6.7/6-15 0x1001_5018 (pta_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 table 6-1. gpio memory map (continued) address register access reset value section/page general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-7 0x1001_5118 (ptb_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 0x1001_5218 (ptc_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 0x1001_5318 (ptd_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 0x1001_5418 (pte_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 0x1001_5518 (ptf_iconfb2) input configuration register b2 r/w 0xffff_ffff 6.6.8/6-16 0x1001_501c (pta_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_511c (ptb_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_521c (ptc_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_531c (ptd_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_541c (pte_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_551c (ptf_dr) data register r/w 0x0000_0000 6.6.9/6-17 0x1001_5020 (pta_gius) gpio in use register a r/w 0xffff_ffff 6.6.11/6-19 0x1001_5120 (ptb_gius) gpio in use register b r/w 0xff3f_fff3 6.6.11/6-19 0x1001_5220 (ptc_gius) gpio in use register c r/w 0xffff_ffff 6.6.11/6-19 0x1001_5320 (ptd_gius) gpio in use register d r/w 0xfffe_0000 6.6.11/6-19 0x1001_5420 (pte_gius) gpio in use register e r/w 0xfffc_0f27 6.6.11/6-19 0x1001_5520 (ptf_gius) gpio in use register f r/w 0xff00_0000 6.6.11/6-19 0x1001_5024 (pta_ssr) sample status register r 0x0000_0000 6.6.12/6-22 0x1001_5124 (ptb_ssr) sample status register r 0x0000_0000 6.6.12/6-22 0x1001_5224 (ptc_ssr) sample status register r 0x0000_0000 6.6.12/6-22 table 6-1. gpio memory map (continued) address register access reset value section/page general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-8 freescale semiconductor 0x1001_5324 (ptd_ssr) sample status register r 0x0000_0000 6.6.12/6-22 0x1001_5424 (pte_ssr) sample status register r 0x0000_0000 6.6.12/6-22 0x1001_5524 (ptf_ssr) sample status register r 0x0000_0000 6.6.12/6-22 0x1001_5028 (pta_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_5128 (ptb_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_5228 (ptc_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_5328 (ptd_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_5428 (pte_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_5528 (ptf_icr1) interrupt configuration register 1 r/w 0x0000_0000 6.6.13/6-23 0x1001_502c (pta_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_512c (ptb_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_522c (ptc_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_532c (ptd_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_542c (pte_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_552c (ptf_icr2) interrupt configuration register 2 r/w 0x0000_0000 6.6.14/6-24 0x1001_5030 (pta_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 0x1001_5130 (ptb_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 0x1001_5230 (ptc_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 0x1001_5330 (ptd_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 0x1001_5430 (pte_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 table 6-1. gpio memory map (continued) address register access reset value section/page general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-9 0x1001_5530 (ptf_imr) interrupt mask register r/w 0x0000_0000 6.6.15/6-25 0x1001_5034 (pta_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5134 (ptb_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5234 (ptc_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5334 (ptd_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5434 (pte_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5534 (ptf_isr) interrupt status register r/w 0x0000_0000 6.6.16/6-26 0x1001_5038 (pta_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_5138 (ptb_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_5238 (ptc_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_5338 (ptd_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_5438 (pte_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_5538 (ptf_gpr) general purpose register r/w 0x0000_0000 6.6.17/6-27 0x1001_503c (pta_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_513c (ptb_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_513c (ptb_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_533c (ptd_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_543c (pte_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_553c (ptf_swr) software reset register r 0x0000_0000 6.6.18/6-28 0x1001_5040 (pta_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 table 6-1. gpio memory map (continued) address register access reset value section/page general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-10 freescale semiconductor 6.6.1 register summary the conventions in figure 6-3 and table 6-2 serve as a key for the register summary and individual register diagrams. table 6-2 provides a key for register figures and tables and the register summary. 0x1001_5140 (ptb_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 0x1001_5240 (ptc_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 0x1001_5340 (ptd_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 0x1001_5440 (pte_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 0x1001_5540 (ptf_puen) pull-up enable register r/w 0xffff_ffff 6.6.19/6-29 0x1001_5600 (pmask) port interrupt mask register r/w 0x0000_003f 6.6.20/6-30 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 6-3. key to register fields table 6-2. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. (previously designated slfclr) reset values 0 resets to zero. 1 resets to one. table 6-1. gpio memory map (continued) address register access reset value section/page general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-11 6.6.2 data direction register (ptn_ddir) the data direction registers determine whether eac h port pin operates as an input or an output pin. figure 6-4 shows the register and table 6-3 provides its field descriptions. figure 6-4. data direction register (ptn_ddir) 6.6.3 output configuration register 1 (ocr1) each port consists of 32-pins. because the output conf iguration for each pin is described using a two-bit combination the output configuration of the pins is c ontrolled by two identical 32-bit registers (ocr1 and ocr2). the output configuration register 1 (ocr1) configures the output signal for lower 16 pins (0?15) of the associated port. figure 6-5 shows the register and table 6-4 provides its field descriptions. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. 0x1001_5000 (pta_ddir) 0x1001_5100 (ptb_ddir) 0x1001_5200 (ptc_ddir) 0x1001_5300 (ptd_ddir) 0x1001_5400 (pte_ddir) 0x1001_5500 (ptf_ddir) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ddir w reset00000000000 0 0000 15141312111098765 4 3210 r ddir w reset00000000000 0 0000 table 6-3. data direction register field descriptions field description 31?0 ddir data direction. this is a read/write register that defines the current direction of the 32 pins of a port in the gpio module. 0 pin operates as an input. 1 pin operates as an output. table 6-2. register conventions (continued) convention description general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-12 freescale semiconductor figure 6-5. output configuration register 1 (ocr1) 6.6.4 output configuration register 2 (ocr2) the output configuration register 2 (ocr2) specif ies the output signal for upper 16 pins (16?31) of the associated port. the output configuration for each pin is described with a two-bit combination. figure 6-6 shows the register and table 6-5 provides its field descriptions. 0x1001_5004 (pta_ocr1) 0x1001_5104 (ptb_ocr1) 0x1001_5204 (ptc_ocr1) 0x1001_5304 (ptd_ocr1) 0x1001_5404 (pte_ocr1) 0x1001_5504 (ptf_ocr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ocr1 w pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 reset00000000000 0 0000 15141312111098765 4 3210 r ocr1 w pin 7 pin 6 pin 5 pin 4 p in 3 pin 2 pin 1 pin 0 reset00000000000 0 0000 table 6-4. output configuration register 1 field descriptions field description 31?0 ocr1 output configuration register 1. each field selects how each pin (0?15) is used as an output by the gpio. 00 input a_in output selected. 01 input b_in output selected. 10 input c_in output selected. 11 data register output selected. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-13 figure 6-6. output configuration register 2 (ocr2) 6.6.5 input configuration register a1 (iconfa1) the input configuration registers (iconfa1) specify th e signal or value driven to the a_out signals that is connected to internal modules of the bono device processor. each port pin is defined by two bits in the input configuration registers. figure 6-7 shows the register and table 6-6 provides its field descriptions. 0x1001_5008 (pta_ocr2) 0x1001_5108 (ptb_ocr2) 0x1001_5208 (ptc_ocr2) 0x1001_5308 (ptd_ocr2) 0x1001_5408 (pte_ocr2) 0x1001_5508 (ptf_ocr2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ocr2 w pin 31 pin 30 pin 29 pin 28 pin 27 pin 26 pin 25 pin 24 reset00000000000 0 0000 15141312111098765 4 3210 r ocr2 w pin 23 pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 reset00000000000 0 0000 table 6-5. output configuration register 2 field descriptions field description 31?0 ocr2 output configuration register 2. each field selects how each pin (16?31) is used as an output by the gpio. 00 input a_in output selected. 01 input b_in output selected. 10 input c_in output selected. 11 data register output selected. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-14 freescale semiconductor figure 6-7. input configuration register a1 (iconfa1) 6.6.6 input configuration register a2 (iconfa2) the input configuration registers (iconfa2) specify the signal or value driven to the a_out signals connected to internal modules. there are two bits in the input configuration registers for each port pin. figure 6-8 shows the register and table 6-7 provides its field descriptions. 0x1001_500c (pta_iconfa1) 0x1001_510c (ptb_iconfa1) 0x1001_520c (ptc_iconfa1) 0x1001_530c (ptd_iconfa1) 0x1001_540c (pte_iconfa1) 0x1001_550c (ptf_iconfa1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r iconfa1 w pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 reset11111111111 1 1111 15141312111098765 4 3210 r iconfa1 w pin 7 pin 6 pin 5 pin 4 p in 3 pin 2 pin 1 pin 0 reset11111111111 1 1111 table 6-6. input configuration register a1 field descriptions field description 31?0 iconfa1 input configuration. corresponds to port pins 0?15 and defines which one of the four options is driven to a_out. each port pin requires two iconfa1 bits to determine the input value. 00 gpio_in 01 interrupt status register 10 0 11 1 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-15 figure 6-8. input configuration register a2 (iconfa2) 6.6.7 input configuration register b1 (iconfb1) the input configuration registers iconfb1 specify the signal or value driven to the b_out signals connected to internal modules. there are two bits in the input configuration registers for each port pin. figure 6-9 shows the register and table 6-8 provides its field descriptions. 0x1001_5010 (pta_iconfa2) 0x1001_5110 (ptb_iconfa2) 0x1001_5210 (ptc_iconfa2) 0x1001_5310 (ptd_iconfa2) 0x1001_5410 (pte_iconfa2) 0x1001_5510 (ptf_iconfa2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r iconfa2 w pin 31 pin 30 pin 29 pin 28 pin 27 pin 26 pin 25 pin 24 reset11111111111 1 1111 15141312111098765 4 3210 r iconfa2 w pin 23 pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 reset11111111111 1 1111 table 6-7. input configuration register a2 field descriptions field description 31?0 iconfa2 input configuration. corresponds to port pins 16?31 and defines which one of the four options is driven to a_out. each port pin requires two iconfa2 bits to determine the input value. 00 gpio_in 01 interrupt status register 10 0 11 1 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-16 freescale semiconductor 6.6.8 input configuration register b2 (iconfb2) the input configuration registers iconfb2 specify the signal or value driven to the b_out signals connected to internal modules. there are two bits in the input configuration registers for each port pin. figure 6-10 shows the register and table 6-9 provides its field descriptions. 0x1001_5014 (pta_iconfb1) 0x1001_5114 (ptb_iconfb1) 0x1001_5214 (ptc_iconfb1) 0x1001_5314 (ptd_iconfb1) 0x1001_5414 (pte_iconfb1) 0x1001_5514 (ptf_iconfb1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r iconfb1 w pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 reset11111111111 1 1111 15141312111098765 4 3210 r iconfb1 w pin 7 pin 6 pin 5 pin 4 p in 3 pin 2 pin 1 pin 0 reset11111111111 1 1111 figure 6-9. input configuration register b1 (iconfb1) table 6-8. input configuration register b1 field descriptions name description 31?0 iconfb1 input configuration. corresponds to pins 0?15 of the port and defines which one of the four options is driven to b_out. each port pin requires two iconfb1 bits to determine the input value. 00 gpio_in 01 interrupt status register 10 0 11 1 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-17 figure 6-10. input configuration register b1 (iconfb2) 6.6.9 data register (dr) the data register holds data for out put from an associated port when a pin is configured as an output and the data register is chosen using output configura tion register 1 and output configuration register 2. figure 6-11 shows the register and table 6-10 provides its field descriptions. 0x1001_5018 (pta_iconfb2) 0x1001_5118 (ptb_iconfb2) 0x1001_5218 (ptc_iconfb2) 0x1001_5318 (ptd_iconfb2) 0x1001_5418 (pte_iconfb2) 0x1001_5518 (ptf_iconfb2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r iconfb2 w pin 31 pin 30 pin 29 pin 28 pin 27 pin 26 pin 25 pin 24 reset11111111111 1 1111 15141312111098765 4 3210 r iconfb2 w pin 23 pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 reset11111111111 1 1111 table 6-9. input configuration register b2 description name description 31?0 iconfb2 input configuration. corresponds to pins 16?31 of the port and defines which one of the four options is driven to b_out. each port pin requires two iconfb2 bits to determine the input value. 00 gpio_in 01 interrupt status register 10 0 11 1 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-18 freescale semiconductor figure 6-11. data register (dr) 6.6.10 gpio in use registers (gius) the gpio in use registers control a multiplexer in the iomux module. the settings in these registers choose whether a pin is utilized for a peripheral function or for its gpio function. if the register is set to a zero for a corresponding pin, then this register is used in conjunction with the gpr register to control the peripheral functionality. figure 6-12 shows a gius overview register and table 6-11 provides field descriptions of the gius registers. reset values for individual registers are shown in the following sections. 0x1001_501c (pta_dr) 0x1001_511c (ptb_dr) 0x1001_521c (ptc_dr) 0x1001_531c (ptd_dr) 0x1001_541c (pte_dr) 0x1001_551c (ptf_dr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dr w reset00000000000 0 0000 15141312111098765 4 3210 r dr w reset00000000000 0 0000 table 6-10. data register field descriptions field description 31?0 dr data register . contains the gpio output values when the output configuration registers select the data register as the output for the pin (selection 11). 0 drives the output signal is low. 1 drives the output signal is high. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-19 figure 6-12. gpio in use register (gius) 6.6.11 gpio in use register reset values the following sections describe the gpio in use (giu s) reset values for the various ports. additionally, the registers also indicate the reserved bits (unimplemented gpio bits) of the gpio ports. 6.6.11.1 gpio in use register a (pta_gius) the reset value of the pta_gius register is (0xffff_ffff). figure 6-13 shows the register. 0x1001_5020 (pta_gius) 0x1001_5120 (ptb_gius) 0x1001_5220 (ptc_gius) 0x1001_5320 (ptd_gius) 0x1001_5420 (pte_gius) 0x1001_5520 (ptf_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius w reset 1 ?????? ????? ? ???? 15141312111098765 4 3210 r gius w reset 1 ?????? ????? ? ???? 1 the reset value of this register is determined by the input value of the signal inuse_reset_sel [31:0]. table 6-11. gpio in use register field descriptions field description 31?0 gius gpio in use . informs the iomux module whether the port pin is utilized for its gpio function. when the pin is utilized for its gpio function, the multiplexed functions are not available. the reset value of this register is determined by the input value of the signal inuse_reset_sel [31:0]. 0 pin utilized for multiplexed function 1 pin utilized for gpio function general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-20 freescale semiconductor figure 6-13. gpio in use register a reset values (pta_gius) 6.6.11.2 gpio in use register b (ptb_gius) the reset value of the ptb_gius register is (0xff3f_fff3). figure 6-14 shows the register. figure 6-14. gpio in use register b reset values (ptb_gius) 6.6.11.3 gpio in use register c (ptc_gius) the reset value of the ptc_gius register is (0xffff_ffff). figure 6-15 shows the register. 0x1001_5020 (pta_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius w reset11111111111 1 1111 15141312111098765 4 3210 r gius w reset11111111111 1 1111 0x1001_5120 (ptb_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius w reset11111111001 1 1111 15141312111098765 4 3210 r gius 1 1 w reset11111111111 1 0011 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-21 figure 6-15. gpio in use register c reset values (ptc_gius) 6.6.11.4 gpio in use register d (ptd_gius) the reset value of the ptd_gius register is (0xfffe_0000). figure 6-16 shows the register. figure 6-16. gpio in use register d reset values (ptd_gius) 6.6.11.5 gpio in use register e (pte_gius) the reset value of the pte_gius register is (0xfffc_0f27). figure 6-17 shows the register. 0x1001_5220 (ptc_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius w reset11111111111 1 1111 15141312111098765 4 3210 rgius 1 1 1 1 1 w reset11111111111 1 1111 0x1001_5320 (ptd_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius w reset11111111111 1 1111 15141312111098765 4 3210 r gius w reset00000000000 0 0000 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-22 freescale semiconductor figure 6-17. gpio in use register e reset values (pte_gius) 6.6.11.6 gpio in use register f (ptf_gius) the reset value of the ptf_gius register is (0xff00_0000). figure 6-17 shows the register. figure 6-18. gpio in use register f reset values (ptf_gius) 6.6.12 sample status register (ssr) the read-only sample status registers contain the valu e of the gpio pins for each associated port. the register is updated on every clock tick. the contents ar e used as a status indicator when the pins are configured as inputs. figure 6-19 shows the register and table 6-12 provides its field descriptions. 0x1001_5420 (pte_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gius 1 1 gius w reset11111111111 1 1100 15141312111098765 4 3210 r gius w reset00000000000 0 0000 0x1001_5520 (ptf_gius) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 1 1 1 1 1 1 1 1 0 gius w reset11111111000 0 0000 15141312111098765 4 3210 r gius w reset00000000000 0 0000 general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-23 figure 6-19. sample status register (ssr) 6.6.13 interrupt configuration register 1 (icr1) this register specifies the external interrupt confi guration for each of the lower 16 interrupts of a port. there are two bits in the register for each port pin. figure 6-20 shows the register and table 6-13 provides its field descriptions. 0x1001_5024 (pta_ssr) 0x1001_5124 (ptb_ssr) 0x1001_5224 (ptc_ssr) 0x1001_5324 (ptd_ssr) 0x1001_5424 (pte_ssr) 0x1001_5524 (ptf_ssr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ssr w reset00000000000 0 0000 15141312111098765 4 3210 r ssr w reset00000000000 0 0000 table 6-12. sample status register field descriptions field description 31?0 ssr sample status. contains the value of the gpio pin [i]. it is sampled on every clock. 0 pin value is low. 1 pin value is high. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-24 freescale semiconductor figure 6-20. interrupt configuration register 1 (icr1) 6.6.14 interrupt configuration register 2 (icr2) this register specify the external interrupt configur ation for each of the upper 16 interrupts of the port. there are two bits in the register for each port pin. figure 6-21 shows the register and table 6-14 provides its field descriptions. 0x1001_5028 (pta_icr1) 0x1001_5128 (ptb_icr1) 0x1001_5228 (ptc_icr1) 0x1001_5328 (ptd_icr1) 0x1001_5428 (pte_icr1) 0x1001_5528 (ptf_icr1) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ricr1 w pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 reset00000000000 0 0000 15141312111098765 4 3210 ricr1 w pin 7 pin 6 pin 5 pin 4 p in 3 pin 2 pin 1 pin 0 reset00000000000 0 0000 table 6-13. interrupt configuration register 1 field descriptions field description 31?0 icr1 interrupt configuration. corresponds to interrupts 0?15 of the port and defines which one of the four options is the sensitivity of the interrupt. each interrupt [i] (i= 0 through 15) requires two icr1 bits to determine the sensitivity. 00 rising edge sensitive 01 falling edge sensitive 10 high level sensitive 11 low level sensitive general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-25 figure 6-21. interrupt configuration register 2 (icr2) 6.6.15 interrupt mask register (imr) the interrupt mask registers (imr) determine if an in terrupt will be asserted when an interrupt event occurs and when the pin and corresponding bit is configured in an interrupt mode. an interrupt is asserted when corresponding bits in the imr and isr are set. figure 6-22 shows the register and table 6-15 provides its field descriptions. 0x1001_502c (pta_icr2) 0x1001_512c (ptb_icr2) 0x1001_522c (ptc_icr2) 0x1001_532c (ptd_icr2) 0x1001_542c (pte_icr2) 0x1001_552c (ptf_icr2) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ricr2 w pin 31 pin 30 pin 29 pin 28 pin 27 pin 26 pin 25 pin 24 reset00000000000 0 0000 15141312111098765 4 3210 ricr2 w pin 23 pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 reset00000000000 0 0000 table 6-14. interrupt configuration register 2 field descriptions field description 31?0 icr2 interrupt configuration. corresponds to interrupts 16?31 of the port and defines which one of the four options is the sensitivity of the interrupt. each interrupt requires two icr2 bits to determine the sensitivity. 00 rising edge sensitive 01 falling edge sensitive 10 high level sensitive 11 low level sensitive general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-26 freescale semiconductor figure 6-22. interrupt mask register (imr) 6.6.16 interrupt status register (isr) the interrupt status registers (isr) indicate if an in terrupt has occurred. when an interrupt event occurs, the bit in this register is set. the condition nece ssary to set the bit is determined by the interrupt configuration registers (icr) and the inputs satisfying the interrupt condition. figure 6-23 shows the register and table 6-16 provides its field descriptions. 0x1001_5030 (pta_imr) 0x1001_5130 (ptb_imr) 0x1001_5230 (ptc_imr) 0x1001_5330 (ptd_imr) 0x1001_5430 (pte_imr) 0x1001_5530 (ptf_imr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r imr w reset00000000000 0 0000 15141312111098765 4 3210 r imr w reset00000000000 0 0000 table 6-15. interrupt mask register description name description 31?0 imr interrupt mask. masks the interrupts for this module. 0 interrupt is masked. 1 interrupt is not masked. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-27 figure 6-23. interrupt status register (isr) 6.6.17 general purpose register (gpr) the general purpose registers (gpr) control a multiplexer in the iomux module. when the corresponding bit in the associated gius register is se t to zero, the settings in these registers determine whether a pin is utilized for its primary peripheral f unction or for its alternate peripheral function. when the corresponding bit in the gius is set, the settings of this register have no effect. figure 6-24 shows the register and table 6-17 provides its field descriptions. 0x1001_5034 (pta_isr) 0x1001_5134 (ptb_isr) 0x1001_5234 (ptc_isr) 0x1001_5334 (ptd_isr) 0x1001_5434 (pte_isr) 0x1001_5534 (ptf_isr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 risr w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000000 0 0000 15141312111098765 4 3210 risr w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000000 0 0000 table 6-16. interrupt status register field descriptions field description 31?0 isr interrupt status. indicates whether the interrupt [i] has occurred for in the gpio module. the bits of this register are write 1 to clear. the w1c bit is cleared when a value of 1 is written to the associated bit. 0 interrupt has not occurred. 1 interrupt has occurred. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-28 freescale semiconductor 6.6.18 software reset register (swr) the software reset register (swr) controls the reset of the individual ports in the gpio module. when the swr bit of the software reset register is set, the gpio circuitry for the individual port resets immediately. the total time of the software reset sequence will take six clock cycles. the reset will be asserted from the third cycle and remains asserted for three clocks. figure 6-25 shows the register and table 6-18 provides its field descriptions. 0x1001_5038 (pta_gpr) 0x1001_5138 (ptb_gpr) 0x1001_5238 (ptc_gpr) 0x1001_5338 (ptd_gpr) 0x1001_5438 (pte_gpr) 0x1001_5538 (ptf_gpr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gpr w reset00000000000 0 0000 15141312111098765 4 3210 r gpr w reset00000000000 0 0000 figure 6-24. general purpose register table 6-17. general purpose register field descriptions field description 31?0 gpr general purpose register. selects between the primary and alternate functions of the pin. when the associated bit in the gius register is set, this bit has no meaning. note: ensure that this bit is cleared when there is not an alternate function for the associated pin. 0 select primary pin function 1 select alternate pin function general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-29 figure 6-25. software reset register (swr) 6.6.19 pull-up enable register (puen) the pull-up enable (puen) registers enable or disable a 69 k ? pull-up resistor on the associated pin. the pull-up can be applied to any gpio pin regardless of whether it is configured as primary, alternate or gpio function. the pin is tri-stated when the pul l-up is disabled and the pin is not driven. figure 6-26 shows the register and table 6-19 provides its field descriptions. note bits 27?24 on port a (pta_puen) enables or disables a 69 k ? pull-down resistor on the associated pin. bits 31?28, 26, and 9 on port b (ptb_puen) enables or disables a 69 k ? pull-down resistor on the associated pin. 0x1001_503c (pta_swr) 0x1001_513c (ptb_swr) 0x1001_523c (ptc_swr) 0x1001_533c (ptd_swr) 0x1001_543c (pte_swr) 0x1001_553c (ptf_swr) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000 0 0000 w reset00000000000 0 0000 15141312111098765 4 3210 r00000000000 0 000 0 w swr reset00000000000 0 0000 table 6-18. software reset register field descriptions field description 31?1 reserved . these bits are reserved and should read 0 0 swr software reset. controls software reset of the port. the reset signal is active for 3 system clock cycles and then it is released automatically. it is a self-clearing bit. 0no effect 1 gpio circuitry for port x reset general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-30 freescale semiconductor figure 6-26. pull-up enable register (puen) 6.6.20 port interrupt mask register (pmask) the gpio has six ports, each with interrupt generati on capability. the pmask register provides interrupt masking capability at the port level while the interr upt mask register provides control over individual interrupts. if a bit is zero, then all interrupts for that port are masked. a software reset on a port (swr is set) will clear the corresponding mask bit of the port in this register. figure 6-27 shows the register and table 6-20 provides its field descriptions. 0x1001_5040 (pta_puen) 0x1001_5140 (ptb_puen) 0x1001_5240 (ptc_puen) 0x1001_5340 (ptd_puen) 0x1001_5440 (pte_puen) 0x1001_5540 (ptf_puen) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r puen w reset11111111111 1 1111 15141312111098765 4 3210 r puen w reset11111111111 1 1111 table 6-19. pull-up enable register field descriptions field description 31?0 puen pull-up enable. determines whether the corresponding pad is pulled up to a logic-high or tri-stated. when the pin is configured as an input, clearing this bit causes the signal to be tri-stated when not driven by an external source. when the pin is configured as an output, clearing this bit causes the signal to be tri-stated when it is not enabled. 0 pin [i] is tri-stated when not driven internally or externally. 1 pin [i] is pulled high1 when not driven internally or externally. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 6-31 figure 6-27. port interrupt mask register (pmask) 0x1001_5600 (pmask) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000 0 0000 w reset00000000000 0 0000 15141312111098765 4 3210 r0000000000 ptf pte ptd ptc ptb pta w reset00000000001 1 1111 table 6-20. port interrupt mask register field descriptions field description 31?6 reserved. these bits are reserved and should read 0. 5 ptf port f. the bit helps in masking the port f interrupt. the bit clears during software reset of port f. 0 interrupt is masked. 1 interrupt is not masked. 4 pte port e. the bit helps in masking the port e interrupt. the bit clears during software reset of port e. 0 interrupt is masked. 1 interrupt is not masked. 3 ptd port d. the bit helps in masking the port d interrupt. the bit clears during software reset of port d. 0 interrupt is masked. 1 interrupt is not masked. 2 ptc port c. the bit helps in masking the port c interrupt. the bit clears during software reset of port c. 0 interrupt is masked. 1 interrupt is not masked. 1 ptb port b. the bit helps in masking the port b interrupt. the bit clears during software reset of port b. 0 interrupt is masked. 1 interrupt is not masked. 0 pta port a. the bit helps in masking the port a interrupt. the bit clears during software reset of port a. 0 interrupt is masked. 1 interrupt is not masked. general-purpose i/o (gpio) MCIMX27 multimedia applications processor reference manual, rev. 0.2 6-32 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 7-1 chapter 7 jtag controller (jtagc) 7.1 introduction the jtag controller (jtagc) module supports debug access to arm926 core and tri-state enabling of the i/o pads. the jtagc is compatible with 1eee1149.1 standard test access port and boundary scan architecture. 7.2 features the test and debug features of jtag provide the following capabilities: ? provide debug access to arm926 core and execute its specific jtag instructions independently ? controls tri-state enable of i/o pads 7.3 implementation the jtag controller consists of the jtag controller state machine, instruction register (ir), bypass register, boundary scan register, instruction decode, a nd various user specific data registers collectively reside inside the extradebug register. the tdo output from the jtag controller is the muxed output based on whether i.mx27 jtag controller or arm926 platform jtag mode is active . it changes on falling edge of tck. the tdo output enable is selected based on whether i.mx27 jtag controller or arm926 platform jtag mode is active. figure 7-1. jtag signals timing diagram the test mode select (tms) input from external pin by default connects to the arm926 platform after gating with the laser fuse output. at the rising edge of trst_b, the jtag_control input controls whether the tms pin should be connected to arm926 platform or to i.mx27 jtag controller. tck trst_n tms tap_state tdi tdo tdo_en rti reset capture dr ir shift ir eir update rti jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 7-2 freescale semiconductor when jtag_control input is high (by default), the tm s pin will be connected to arm926 platform after gating with the laser fuse output. the tms input of i.mx27 jtag controller will be held high in this case. when jtag_control input is low, the tms pin will be connected to i.mx27 jtag controller. the tms input of arm926 platform will be held high. ? the test reset (trst_b) input from external pi n will be connected to both arm926 platform and i.mx27 jtag controller. ? the test data input (tdi) input from external pin will be connected to both arm926 platform and i.mx27 jtag controller. ? the test clock (tck) input from external pin will be connected to both arm926 platform and i.mx27 jtag controller. 7.4 jtag controller pin list table 7-1 provides a list of the jtagc pins. 7.5 jtag overview figure 7-2 shows the i.mx27 jtag block diagram. table 7-1. jtagc pin list pin name direction description tdo output test data output tdo is asserted during rising edge of tck tck input test clock test clock input is used to synchronize the test logic. this includes an internal pull-up resistor. tdi input test data input tdi is captured during rising edge of tck. tdi includes an internal pull-up resistor. tms input test mode select tms is captured during rising edge of tck. tms includes an internal pull-up resistor. tms input for the arm926 platform and jtag controller is gated by the system logic. trst_b input test reset trst_b includes an internal pull-up resistor jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 7-3 figure 7-2. i.mx27 jtag block diagram 7.6 jtag modes two jtag modes are created based on the i/o pin jt ag_control. these modes are used to maintain compatibility to arm mcu multi-ice tm products as well as mainta in ieee jtag standards. 7.6.1 arm926 platform mode this mode connects the processed tms input to the arm926 platform. trst_b must be asserted to exit this mode. 7.6.2 i.mx27 jtag controller mode this mode will connect the processed tms input to the i.mx27 jtag controller. this will provide a dedicated user-accessible test access port that uses the same communication style as the ieee1149.1 standard. trst_b or por_b must be asserted to leave this mode. in this mode, i.mx27 jtag controller supports the following capabilities: ? query identification information (manufacturer, part number and version) of i.mx27 (idcode) ? tri-state i/o pads for iddq test (highz) ? bypass instruction 7.7 boundary scan register the boundary scan register (bsr) in the i.mx27 jtag im plementation contains bits for all device signals and clock pins and associated control signals. all i.mx 27 bidirectional pins have a single register bit in the boundary scan register for pin data, and are contro lled by an associated control bit in the boundary scan register. arm926ejs + ice arm jtag cntlr i.mx27 jtag controller jtag_tms jtag_tdo tms tdo tck trst_b tdi jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 7-4 freescale semiconductor 7.8 instruction register the jtag instruction register is 3 bits wi de. the settings of the ir is shown in table 7-2 . the instruction register is reset to 3?b000 whic h is equivalent to the idcode instruction. during the capture-ir state, the parallel inputs to the in struction register are loaded with the code 01 in the least significant bits as required by the ieee standard, the most significant bits are loaded with the values 0, leading to a capture value of 3?b001. 7.8.1 extest instruction the extest instruction selects the boundary scan regist er, and the 1149.1 test logic has control of the i/o pins. extest also asserts internal reset for the core to force a predictable internal state while performing external boundary scan operations. by using the tap controller, the register is capable of: ? scanning user-defined values into the output buffers ? capturing values presented to input pins c ontrolling the direction of bidirectional pins ? controlling the output drive of tri-statable output pins for more details on the function and use of extest, refer to the ieee 1149.1 document. 7.8.2 sample/preload instruction this selects the boundary scan register and th e system logic contro ls the i/o pins. the sample/preload instruction provides two separate functions. first, it provides a means to obtain a snapshot of system data and control signals. the snapshot occurs on the rising edge of tck in the capture-dr controller state. the data can be observed by shifting it transparently through the boundary scan register. table 7-2. jtag instruction register bit2 bit1 bit0 instruction 0 0 0 idcode 0 0 1 sample/preload 0 1 0 extest 0 1 1 enable_extradebug 100highz 1 0 1 access_generic_mbist 110clamp 1 1 1 bypass jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 7-5 note since there is no internal synchronization between the jtag clock (tck) and the system clock (clk), the user must provide some form of external synchronization to achieve meaningful results. the second function of sample/preload is to initialize the boundary scan register output cells prior to selection of extest. this initialization ensure s that known data will appear on the outputs when entering the extest instruction. 7.8.3 idcode instruction this selects the id register and the system logic controls the i/o pins. this instruction is a public instruction to allow the manufacturer, part number and the version of the ic to be available through tap. figure 7-3 shows the id register configuration. 7.8.4 enable_extradebug instruction the extradebug register consists of 44 bits comprisi ng a 40-bits register (maximum), a 3-bit address field and one read/write bit. the register data field does not need to be filled in during register read. the particular extradebug register connected between td i and tdo is selected by the extradebug controller based on the currently decoded addr ess during update_dr state. all communication with the extradebug controller is done through the select-dr-sc an path of the i.mx27 jtag controller. 7.8.5 highz instruction all output drivers, including the two-state drivers, are turned off (that is, high impedance). the instruction selects the bypass register. the highz instruction also asserts internal reset for the core to force a predictable internal state while performing external boundary scan operations. in this mode, all internal pull-up resistors on all the pins (except for the tms tdi tck trst cold_start muxctl pins) will be disabled. 0x0000_7000 (idcode) access: user r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r version information design center part number device number [21:12] w reset00001000010 0 0001 15141312111098765 4 3210 r device number [21:12] mfg 1 w reset00001011000 1 1101 figure 7-3. id register configuration jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 7-6 freescale semiconductor 7.8.6 clamp instruction selects the 1-bit bypass register as the serial path between tdi and tdo while allowing signals driven from the component pins to be determined from the boundary scan register. during testing of ics on pcb, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. the extest instruction could be used for this purpose, but since it selects the boundary-scan register the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. since the clamp instruction allows guarding values to be applied using the boundary-scan re gister of the appropriate ics while selecting their bypass registers, it allows much faster testing th an does the extest instruction. data in the boundary scan cell remains unchanged until a ne w instruction is shifted in or the jtag state machine is set to its reset state. the clamp instruction also asserts internal reset for the core to force a predictable internal state while performing external boundary scan operations. 7.8.7 bypass instruction selects the single bit bypass register and the system logi c controls the i/o pins. this creates a shift register path from tdi to the bypass register and finally to tdo. when the bypass register is selected by the current instruc tion, the shift-register stage is set to a logic zero on the rising edge of tck in the capture-dr controller st ate. the first bit to be shifted out after selecting the bypass register will always be a logic zero. 7.9 tms sequences 7.9.1 tms sequence to check id code the following table shows the tms sequence to check th e id code value, starting from any point in the state machine. table 7-1. tms sequence to check id code step tck tms state comment 0 x5 1 test logic reset sequence is : idcode read 1 x1 0 run-test/idle 2x11select dr 3 x1 1 select ir ir path : loading ?idcode? instr. 4 x1 0 capture ir 5 x1 0 shift ir shift ?idcode? inst.= 3'b010 thru tdi 6x20shift 7x11exit1 8 x1 1 update select idcode register 9 x1 0 run-test/idle jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 7-7 7.9.2 tms sequence to write to extradebug register table 7-2 shows the tms sequence to write to any of the extradebug registers, starting from any point in the state machine. 10 x1 1 select dr dr path: reading idcode reg. 11 x1 0 capture dr capture idcode value 12 x1 0 shift dr shift out idcode on 32bits 13 x31 0 shift 14 x1 1 exit1 15 x1 1 update 16 x1 0 run-test/idle table 7-2. tms sequence to write to extradebug register step tck tms state comment 0 x5 1 test logic reset sequence is : write extradebug register 1 x1 0 run-test/idle 2x11select dr 3 x1 1 select ir ir path : select extradebug register. 4 x1 0 capture ir 5 x1 0 shift ir shift ?enable extradebug? inst.= 3'b011 thru tdi 6x20shift 7x11exit1 8 x1 1 update select extradebug register 9 x1 0 run-test/idle 10 x1 1 select dr dr path: select extradebug register to write data 11 x1 0 capture dr 12 x1 0 shift dr shift in writ bit(1?b0) + register address + data 13 x43 0 shift 14 x1 1 exit1 15 x1 1 update write to the extradebug register 16 x1 0 run-test/idle table 7-1. tms sequence to check id code step tck tms state comment jtag controller (jtagc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 7-8 freescale semiconductor 7.9.3 tms sequence to read extradebug register the following table shows the tms sequence to read any of the extradebug registers, starting from any any point in the state machine. 7.10 i.mx27 jtag restrictions trst_b must be externally asserted to force the selection of arm926 platform tap or i.mx27 jtag controller. during por_b assertion, arm926 platform tap is selected. if tms either remains unconnected or connected to vdd, then the tap controller cannot leave the test-logic-reset state regardless of tck. table 7-3. tms sequence to read extradebug register step tck tms state comment 0 x5 1 test logic reset sequence is : read extradebug register 1 x1 0 run-test/idle 2x11select dr 3 x1 1 select ir ir path : select extradebug register. 4 x1 0 capture ir 5 x1 0 shift ir shift ?enable extradebug? inst.= 3'b011 thru tdi 6x20shift 7x11exit1 8 x1 1 update select extradebug register 9 x1 0 run-test/idle 10 x1 1 select dr dr path: select extradebug register to read 11 x1 0 capture dr 12 x1 0 shift dr shift in read bit(1?b1) + register address 13 x3 0 shift 14 x1 1 exit1 15 x1 1 update decode the 4 bits shifted in 16 x1 0 run-test/idle 17 x1 1 select dr 2nd dr path: extradebug read access 18 x1 0 capture dr read the extradebug register 19 x1 0 shift dr shift out the captured value 20 x39 0 shift 21 x1 1 exit1 22 x1 1 update 23 x1 0 run-test/idle MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 8-1 chapter 8 bootstrap mode operation 8.1 introduction the bootstrap program is a small program that resides in the internal rom of the i.mx27 processor. it is activated when the boot[3:0] selection pins are set to 4?b0000 or if there is any exception during the hab checking during boot-up. the bootstrap operation handles the commands from either usb or uart1 to establish a channel to interface the i.mx27 pr ocessor?s hardware and the external machine such as pc. it provides the following functions. 1. for hab enable-type silicon, it downloads authenticated binary image code to memory so as to execute in run time or perform flash update. 2. for hab disable-type silicon, it downloads binary image code to memory as to execute in run time or perform flash update. for hab enable-type silicon, a shell provides essentia l information such as the signatures, optimized commands, and the authenticated binary image to the irom to validate before the core to execute. 8.2 uart/usb configuration the configuration for rs 232 is using baud rate 115200, 8 data bits, no parity, 1 stop bits, and no flow control. the configuration for usb is for control e ndpoint 0 with max packet size equal 8 byte. bulk in at endpoint 2 with max packet size equal 64 bytes, bulk out at endpoint 1 with max packet size equal 64 bytes. note current rom code only supports full speed transmission over full speed transceiver(isp1301 and atlas) and high speed usb transceiver (isp 1504 or the like). the rom code does not support high-speed transmission over high-speed usb transceiver (isp 1504 or the like). 8.3 enter bootstrap mode configuration the i.mx27 processor enters bootstrap mode under the following conditions: 1. boot[3:0] is selected bootstrap mode or 2. for hab enabled type of silicon: hab authentication fails when booting from flash (for example nand flash, nor flash) refer to chapter 4, ?system control ? for the details of bootstrap m ode configuration and operation. bootstrap mode operation MCIMX27 multimedia applications processor reference manual, rev. 0.2 8-2 freescale semiconductor 8.4 bootstrap flow the overall flow of the bootstrap program is shown in figure 8-1 . figure 8-1. flow diagram for bootstrap mode hardware configuration address call usb/uart bootloader to download ram application. execute address csf address valid execute address? hab enabled? hardware configuration hardware configuration vector hab process csf csf data for downloaded code hab assert verification execute address return status return status = hab passed? hab su type = engg? jump to application code ye no ye ye no ye no hardware configuration address call usb/uart bootloader to download ram application. execute address csf address valid execute address? hab enabled? hardware configuration hardware configuration vector hab process csf csf data for downloaded code hab assert verification execute address return status return status = hab passed? hab su type = engg? jump to application code ye no ye ye no ye no yes yes yes yes bootstrap mode operation MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 8-3 8.4.1 bootstrap protocol and definition in this section, bootstrap protocol and the co mmand, response definition is defined. for the i.mx27 processor?s boot-up sequence, refer to system boot . for the csf, hw configuration, image definition, refer to the high assurance boot (hab). 8.4.1.1 synchronization operation when bootstrap is firstly entered, the status of th e irom can be obtained by issuing the command shown in figure 8-2 . figure 8-2. irom status command the sync command consists of 16 bytes using the format shown in table 8-1 . : response a is 4 bytes long using the format shown in table 8-2 . 8.4.1.2 write register operation to write to a register through bootstrap, requires a spec ific protocol. after the command is sent from pc to mx27 processor, two responses are returned from mx27. one is used to indicate the type of silicon (either hab enable or disable), the other is used to indicate whether the write operation is successful. figure 8-3. write register command write command is 16 bytes long using the format shown in table 8-3 . table 8-1. synch command response definition header (2 bytes) address (4 bytes) format (1 byte) bytecount (4 bytes) data (4 bytes) end (1 byte) 0505 00000000 00 00000000 00000000 00 table 8-2. response a definition byte 0byte 1byte 2byte 3 status code status code status code status code synch command response a pc to i.mx27: i.mx27 to pc: write command response b pc to i.mx27: i.mx27 to pc: response c bootstrap mode operation MCIMX27 multimedia applications processor reference manual, rev. 0.2 8-4 freescale semiconductor response b indicates type of silicon. it is composed of 8 bytes using the format shown in table 8-4 . response c indicates the success of a write operation as shown in table 8-5 . remarks: for hab enabled silicon, users can onl y write the following range of registers: 1. system control registers (address: 0x10027800-0x10027870) 2. phase-locked loop, clock and reset controller registers (address: 0x10027000?0x10027034) 3. nfc registers (address: 0xd8000000?0xd8000fff) 4. sdramc registers (address: 0xd8001000?0xd8001fff) 5. weim registers (address: 0xd8002000?0xd8002fff) 6. memory area of cs0, cs1, cs2, cs3, cs4, cs5, csd0, and csd1 (address: 0xa0000000?0xd7ffffff) 8.4.1.3 download operation memory is initialized before downloading a binary file to it. the following command can be used: figure 8-4. download command the download command is 16 bytes long using the formats shown in table 8-6 . table 8-3. write register command definition header (2 bytes) address (4 bytes) format (1 byte) bytecount (4 bytes) data (4 bytes) end (1 byte) 0202 address to be written format to be written (08: byte access 10: halfword access 20: word access) 00 data to be written to the register 00 table 8-4. response b definition byte 0 byte 1 byte 2 byte 3 hab disable/ development56787856 hab enable 12 34 34 12 table 8-5. response c definition byte 0byte 1byte 2byte 3 12 8a 8a 12 download command response b pc to i.mx27: i.mx27 to pc: binary data bootstrap mode operation MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 8-5 response b indicates the type of silicon. it is 8 bytes long using the format shown in table 8-7 . after the response b is received by the mx27 processor, the attached pc can start to download the binary data to mx27 until all the bytecount is downloaded. each time the image file is downloaded through header (0404), the maximum data to be downl oad is 0x1f0000. thus, if the image file size is greater then 0x1f0000, it will send the command repeat edly with end (0x00). after all the data is downloaded, pc must send a download command with end (aa) to the target execution address. 8.4.1.4 bootstrap end indication operation after all the bootstrap operations are completed, the i.mx27 processor will send response d to pc after the application pointer was sent to indicate bootstrap was completed. after response d, it will enter irom to perform the authentication check for hab enable silicon or to execute the image for hab disable/development silicon. figure 8-5. bootstrap end indication operation diagram response d is indicates the success of the write operation as shown in table 8-8 . table 8-6. download command definition header (2 bytes) address (4 bytes) format (1 byte) bytecount (4 bytes) data (4 bytes) end (1 byte) csf 0404 start address where the binary data is to be downloaded 00 number of byte to be written in hex start address in memory where data is to be written cc hwc 0404 start address where the binary data is to be downloaded 00 number of byte to be written in hex start address in memory where data is to be written ee image file 0404 start address where the binary data is to be downloaded 00 number of byte to be written in hex (max 0x1f0000) start address in memory where data is to be written 00 image file 0404 start address where the binary data is to be downloaded 00 number of byte to be written in hex start address in memory where data is to be written aa table 8-7. response b silicon type definition byte 0 byte 1 byte 2 byte 3 hab disable/ development 56 78 78 56 hab enable 12 34 34 12 table 8-8. bootstrap end indication operation diagram byte 0 byte 1 byte 2 byte 3 88 88 88 88 i.mx27 to pc: response d bootstrap mode operation MCIMX27 multimedia applications processor reference manual, rev. 0.2 8-6 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii: applications processors ? core and peripherals introduction book ii comprises detailed information on the appli cations processors? core and peripherals. book ii includes the following chapters. book ii, part 1: arm9 core and interrupts chapter 9, ?arm9 platform ,? on page 9-3 chapter 10, ?arm926ej-s interrupt controller (aitc) ,? on page 10-1 book ii, part 2: security chapter 11, ?security controller (scc) ,? on page 11-1 chapter 12, ?symmetric/asymmetric hashing and random accelerator (sahara2) ,? on page 12-1 chapter 13, ?run-time integrity checker (rtic) ,? on page 13-1 chapter 14, ?ic identification (iim) ,? on page 14-1 book ii, part 3: external interfaces chapter 15, ?external memory interface (emi) ,? on page 15-1 chapter 16, ?multi-master memory interface (m3if) , on page 16-1 chapter 17, ?wireless external interface module (weim) ,? on page 17-1 chapter 18, ?enhanced sdram controller (esdramc) ,? on page 18-1 chapter 19, ?nand flash controller (nfc) ,? on page 19-1 chapter 20, ?personal computer memory card international association (pcmcia) controller ,? on page 20-1 book ii, part 4: connectivity peripherals chapter 21, ?1-wire interface (1-wire) ,? on page 21-1 chapter 22, ?advanced technology attachment (ata) ?, on page 22-1 chapter 23, ?configurable serial peripheral interface (cspi) ,? on page 23-1 chapter 24, ?inter-integrated circuit (i2c) ,? on page 24-1 chapter 25, ?keypad port (kpp) ,? on page 25-1 chapter 26, ?memory stick host controller (mshc) ,? on page 26-1 MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor chapter 27, ?secured digital host controller (sdhc) ,? on page 27-1 chapter 28, ?universal asynchronous receiver/transmitters (uart) ,? on page 28-1 chapter 29, ?fast ethernet controller (fec) ,? on page 29-1 chapter 30, ?high-speed usb on-the-go (hs usb-otg) ,? on page 30-1 book ii, part 5: timer peripherals chapter 31, ?general purpose timer (gpt) ,? on page 31-1 chapter 32, ?pulse-width modulator (pwm) ,? on page 32-1 chapter 33, ?real time clock (rtc) ,? on page 33-1 chapter 34, ?watchdog timer (wdog) ,? on page 34-1 book ii, part 6: system control peripherals chapter 35, ?ahb-lite ip interface (aipi) module ,? on page 35-1 chapter 36, ?multi-layer ahb crossbar switch (max) ,? on page 36-1 chapter 37, ?direct memory access controller (dmac) ,? on page 37-1 book ii, part 7: multimedia peripherals chapter 38, ?digital audio mux (audmux) ,? on page 38-1 chapter 39, ?cmos sensor interface (csi) ,? on page 39-1 chapter 40, ?video codec (video_codec) ,? on page 40-1 chapter 41, ?enhanced multimedia accelerator light (emma_lt) ,? on page 41-1 chapter 42, ?synchronous serial interface (ssi) ,? on page 42-1 chapter 43, ?liquid crystal display controller (lcdc) ,? on page 43-1 chapter 44, ?smart liquid crystal display controller (slcdc) ,? on page 44-1 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 1: arm9 core and interrupts introduction this part provides an overview of the modules that make up the arm9 core and interrupts. chapter 9, ?arm9 platform ,? on page 9-3 chapter 10, ?arm926ej-s interrupt controller (aitc) ,? on page 10-1 arm9 platform the arm9 platform consists of the arm926ej- s processor, etm9, etb9, a 6 x 3 multi-layer ahb crossbar switch (max), and a ?primary ahb? complex. the instruction bus of the arm926ej-s processor (i-ahb) is connected directly to max master port 0. the data bus of the arm926ej-s processor (d-ahb) is connected directly to max mast er port 1. all four alternate bus master interfaces are connected to max master ports 2-5. the three sl ave ports of the max are ahb-lite compliant buses. slave port 0 is designated as the ?primary? ahb. the primary ahb is internal to the platform and has six slaves connected to it: the aitc interrupt module , the mctl memory controller, two aipi peripheral interface gaskets, and a rompatch module. slave ports 1 and 2 of the max are referred to as ?secondary? ahbs. each of the secondary ahb interfaces is only accessible off platform. arm936ej-s interrupt controller (aitc) the arm926ej-s interrupt controller (aitc) is a 32-bi t peripheral which collects interrupt requests from up to 64 sources and provides an interface to the arm926ej-s core. the aitc includes software controlled priority levels for normal interrupts. MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-3 chapter 9 arm9 platform 9.1 introduction the arm9 platform consists of the arm926ej- s processor, etm9, etb9, a 6 x 3 multi-layer ahb crossbar switch (max), and a ?primary ahb? complex. the instruction bus of the arm926ej-s processor (i-ahb) is connected directly to max master port 0. the data bus of the arm926ej-s processor (d-ahb) is connected directly to max mast er port 1. all four alternate bus master interfaces are connected to max master ports 2?5. the three sl ave ports of the max are ahb-lite compliant buses. slave port 0 is designated as the ?primary? ahb. the primary ahb is internal to the platform and has six slaves connected to it: the aitc interrupt module , the mctl memory controller, two aipi peripheral interface gaskets, and a rompatch module. slave ports 1 and 2 of the max are referred to as ?secondary? ahbs. each of the secondary ahb interfaces is only accessible off platform. the four alternate bus master ports on the arm9 plat form, which are connected directly to master ports of the multi-layer crossbar switch (max), are desi gned to support connections to multiple ahb masters external to the platform. an external arbitration a nd ahb control module is needed if multiple external masters are desired to share an arm9 platform alte rnate bus master port. however, the alternate bus master ports on the platform suppor t seamless connection to a single master with no external interface logic required. a pahbmux module (primary ahbmux) performs address decoding, read data muxing, bus watchdog, and other miscellaneous functions for the primary ahb within the platform. a clock control module (clkctl) is provided to support a power conscious design methodology as well as implementation of several clock synchronization circuits. the jam (just another module) impl ements the platform?s general pur pose registers and also contains miscellaneous platform logic. a block diagram of the arm9 platform can be seen in figure 9-1 . arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-4 freescale semiconductor figure 9-1. arm9 platform block diagram 9.1.1 design methodology summary other than the cpu and etb memories, this platform is a fully synthesizable, mux-d, rising edge clock based design. dft goals are for 95% fault coverage a nd the design includes bist engines for all memories implemented on the arm926ej-s, the etb module and ram or rom controlled by the mctl module. the platform will be designed with a dft friendly scan wrapper to allow for deeply embedded integrations. arm926ej-s r o m pat c h 6x3 max mctl aipi1 aipi2 pa h b m u x etm9 aitc m0 m1 m2 m3 m4 m5 s0 s1 s2 ccm i-ahb d-ahb etm i-ahb patch d-ahb patch etb arm926 platform primary ahb two ip-bus peripheral ports four ahb-lite alternate bus master ports (abm) two ahb-lite ?secondary? slave ports external ram/rom interrupts rt debug clkctl jtag sync jtag ip bus jam ip bus ip bus clock control ?bus request? arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-5 9.1.2 performance characteristics the arm9 platform will support two main clocks ?clk and hclk. clk will be connected to the arm926ej-s processor, etm9, etb and the clock cont rol module only. the remainder of the platform will be connected to hclk. the i-ahb and d-ahb fr om the arm926ej-s biu module will run at the hclk frequency and will be controlled by a single hclken input?that is, the two buses cannot be decoupled. refer to section 9.6, ?platform clocking ? for more information on arm926ej-s clock control. 9.1.2.1 performance target the arm9 platform team has committed to making an operating frequency of 266mhz characterized at the 1.1v, 105c wcs 3 sigma cmos90lp standard vt library and 400mhz characterized at the 1.45v, 105c wcs 3 sigma cmos90lp standard vt library. this is the level of performance re quired to meet functional requirements. due to the increased leakage of the cmos90lp library, well back-biasing will be employed along with other standard low power clocking methodologies. 9.2 arm9 platform sub-modules the sub-modules of the platform are listed below along with short functional descriptions. 9.2.1 arm926ej-s processor the arm926ej-s (arm926) is a member of the ar m9 family of general-purpose microprocessors targeted at multi-tasking applications. the arm926 supports the 32-bit arm and 16-bit thumb instructions sets. the arm926 includes features for ef ficient execution of java byte codes. a jtag port is provided to support the arm debug architecture, along with associated signals to support the etm9 real-time trace module. the arm926ej-s is a harv ard cached architecture including an arm9ej-s integer core, a memory management unit (mmu), separate instruction and data amba ahb interfaces, separate instruction and data cache s, and separate instruction and da ta tightly coupled memory (tcm) interfaces. the arm926 co-processor, instruction tcm, and data tcm interfaces will be tied off within the arm9 platform and will not be available for external connection. the arm926ej-s processor is a fully synthesizable macrocell with a c onfigurable memory system. both instruction and data caches will be 16 kbytes on the pl atform. the cache is virtually accessed and virtually tagged. the data cached has physical tags as well. the mmu provides virtual memory facilities which are required to support various platform operating syst ems such as symbian os, windows ce, and linux. the mmu contains eight fully associative tlb entries fo r lockdown and 64 set associ ative entries. refer to the arm926ej-s technical reference manual for more information. 9.2.1.1 arm926ej-s co-processor interface the co-processor interface will not exit the arm9 platform and will be tied off internally and synthesized away to improve routing congestion and timing. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-6 freescale semiconductor 9.2.1.2 tcm interfaces both instruction and data tightly-coupled memory (t cm) interfaces will not exit the arm9 platform and will be tied off internally and synthesized away to improve routing congestion and timing. 9.2.2 arm9 embedded trace macrocell and embedded trace buffer the arm9 platform will include an arm9 embe dded trace macrocell (etm9) and embedded trace buffer (etb) supporting real-time instruction and data tracing. the etm9/etb external interface may run at the arm926ej-s clock frequency or at half th e arm926ej-s clock frequency. the embedded trace buffer is sized at 2048x 32 and can be used as gene ral scratch pad memory when not being used for real-time tracing. this scratch pad memory is access ible via aipi2 slots 27 and 28. the etb registers can be accessed via aipi2 slot 29. refer to the etm 9 and etb technical reference manuals for more information. 9.2.3 the 6 x 3 multi-layer ahb crossbar switch (max) the arm926ej-s processor?s instruction and data buses and all alternate bus master interfaces arbitrate for resources via a 6 x 3 multi-layer ahb crossbar switch (max). there are six (m0?m5) fully functional master ports and three (s0?s2) fully func tional slave ports. the max is uni-directional. all master and slave ports are ahb-lite compliant. see section 9.9.1, ?definition of ahb-lite ? for an explanation of ahb-lite. the design of the crossbar switch allows for concurrent transactions to proceed from any master port to any slave port. that is, it is possible for all three slave ports to be active at the same time as a result of three independent master requests. if a particular slave port is simultaneously requested by more than one master port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the bus, while stalling the other requestor(s) until that transaction has completed. the slave port arbitration schemes supported are fixed, progra mmable fixed, programmable default input port parking, and a round robin arbitration scheme. the crossbar switch also monitors the ccm_br input (clock control module bus request) which request a bus grant from all four slave ports. the priority of ccm_br is programmable and defaults to the highest. upon receiving bus grants for all four output ports, th e ccm_bg output will assert. at this point, the clock control module can turn off hclk and be assured th ere are no outstanding ahb transactions in progress. once the ccm is granted a port, no other master will receive a grant on that port until the ccm bus request (ccm_br) negates. brief descriptions below provide more detail on the max. for complete functionality, refer to the arm9 platform ?multi-layer ahb crossbar switch? module (max) specification. 9.2.3.1 max configuration registers the crossbar switch has configuration and control regi sters accessible via the ip bus (slot 31 of aipi2). programmable registers exist to cont rol arbitration schemes, bus parki ng, as well as other crossbar bus switch functionality. altern ate master priority registers exists within the max module for each slave arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-7 output port. the alternate priority register can be sele cted for use by the internal arbitration logic by driving the sx_ampr_sel (x=0-2) input high. a write-block sticky bit is implemented for those applic ations where it is desirable to prevent changes to the max registers after boot. refer to the max module design specification for more details. 9.2.3.2 master ports master port 0 of the max is connected directly to the arm926ej-s i-ahb. master port 1 of the max is connected directly to the arm926ej-s d-ahb. the ot her four master ports exit the platform and will be connected to external alternate bus masters. mu ltiple external masters may be attached to a single alternate bus master port via use of an external arbiter. see section 9.9.3, ?single master seamless connection to abm port ? and section 9.9.4, ?multiple external masters connection to abm port ? for more information on how to connect either a single mast er or multiple masters to a single alternate master port. master port priorities are determined by the max prio rity register bit settings. refer to the max module design specification for more details. 9.2.3.3 slave ports slave port 0 through 2 are identical ahb-lite buses. slav e port 0 is designated as the ?primary ahb? bus, and is internal to the platform. slave port 1 and 2 are identical ?secondary ahb ? buses and are available external to the platform. see section 9.9.6, ?max ahb slave ports ? for more details. 9.2.3.4 debug support in addition to the jtag, etm9 and etb9 interfaces , several internal arm 926ej-s signals, several internal primary ahb signals as well as some inte rnal signals from master ports 0 and 1, have been brought out of the platform. these signals, along with alternate bus master a nd secondary ahb signals already available on the top-level of the platform, enable the user to gain insight into the operation of the processor and the max. specifically, it is possible to monitor these signals and determine which master currently owns each slave port. in addition, it is possible to determine which slave each master is targeting for its next request. 9.2.4 arm interrupt controller (aitc) the arm9 platform?s interrupt controller is called the aitc and is connected to the primary ahb as a slave device. it will generate the normal and fast interrupts to the ar m926ej-s processor. the aitc also supports hardware assisted vectoring. note if hardware assisted vectoring is use d, the vector space must be marked non-cacheable. since the vector is dynamically ?jammed? in by the aitc during a vector fetch, there would be no way to do this if cached. refer to the aitc specification for more details. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-8 freescale semiconductor 9.2.5 memory controller and bist engine (mctl) the mctl module interfaces the primary ahb to ra m and rom. bist engines are provided for both ram and rom. 9.2.5.1 ram the ram_connect input on the arm9 platform mu st be tied high if ram exists on the mctl ram interface. the mctl module supports a minimum of 1 kbyte of ram and a maximum of 1 mbyte. non power-of-two sizes between 1 kbyte and 1 mbyte ar e supported by strapping the ram_max_addr[9:0] inputs, which correspond to the primary ahb?s hadd r[19:10]. the ram_wait input should be tied high at integration time if a wait state is required to make read data timing on ram accesses (writes will still be zero wait state). the ram interface will support single clock edge non late -write style compiled memories, and will implement an internal write buffer to mimic the late-write capability for improved performance. a configurable bist engine is provided. refer to the arm9 platform mcu memory controller specification for more detail on the ram controller design. refer to table 9-4 for the ram?s location within the platform?s memory map. 9.2.5.2 rom the rom_connect input on the arm9 platform must be tied high if rom exists on the mctl rom interface. the mctl module supports a minimum of 1 kbyte of rom and a maximum of 4 mbyte. non power-of-two sizes between 1 kbyte and 4 mbyte ar e supported by strapping the rom_max_addr[11:0] inputs, which correspond to the primary ahb?s haddr[ 21:10]. the rom_wait input should be tied high at integration time if a wait state is required to make read data timing on rom accesses. a configurable bist engine is provided. 9.2.5.2.1 rom addressing the first 16 kbytes of rom will always be mapped starting at haddr [31:0]=32?h0000_0000. any rom larger than 16kbyte will have the remainder of its space mapped starting at haddr[31:0]=32?h0040_4000. any rom size smaller than 16 kbyte, will be al iased throughout the 16 kbyte region. accesses to the ?hole? between these two regions will be te rminated with an error response by the mctl. refer to the arm9 platform mcu memory controller specification for more detail on the rom controller design. 9.2.6 ahb ip bus interface (aipi) there are two ahb ip bus interface (aipi) modules that interface the primary ahb to two external ip bus interfaces. the ip bus interfaces and their peripherals will conform to the ip bus rev 2.0/3.0 specification. each aipi module supports up to 31 peri pherals (the aipi configuration registers consume the slot 0), however the arm9 platform will only support 48 external peripherals as shown in table 9-1 . arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-9 refer to the arm9 platform aipi specificati on for more details on the operation of the aipi. 9.2.7 pahbmux?primary ahb mux the pahbmux module is responsible for address d ecoding for the primary ahb module selects. in addition, the pahbmux module will perform the pr imary ahb read data muxing, the primary ahb watchdog, and other miscellaneous functions. refer to the arm9 platform ahbmux design specification for more detail. 9.2.8 rompatch the rompatch will sit on the arm926ej-s i-ahb and d-ahb interfaces which are connected to max master ports 0 and 1. this location will allow for patching of both internal and external memory addresses on both arm926ej-s processor buses. the re gisters of the rompatch will be programmed via the primary ahb. the rompatch can be used to patch source code or data tables. the rompatch supports 32 patches. 9.2.8.1 external boot an external boot feature exists in the rompatch module which allows patching of the reset vector fetch (address = 32?h0000_0000) if the boot_int signal is ne gated. this mechanism will cause the arm926ej-s to, in effect, fetch the reset vector from the address indicated by the ext_boot_addr[31:2] inputs. refer to the arm9 platform rompatch design specification for more details. table 9-1. aipi arm9 platform ip bus support aipi # module slot(s) use 1 0 aipi1 configuration registers 1 1?31 off platform ip bus module support 2 0 aipi2 configuration registers 2 1?17 off platform ip bus module support 2 18?26 reserved 2 27 on platform etb register interface 2 28 on platform etb ram interface 2 29 on platform etb ram interface 2 30 on platform jam interface 2 31 on platform max interface arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-10 freescale semiconductor 9.2.9 clock control module (clkctl) the clkctl module performs block level cl ock gating, arm926ej-s jtag synchronization requirements, as well as other miscellaneous clock c ontrol for the platform. refer to the arm9 platform clkctl design specification for more detail on design implementation. 9.2.10 jam the jam (?just another module?) implements misce llaneous logic with the platform. functionality within the jam includes ip bus #2 read data muxing, gating of the ahb debug signals in order to save power, and an ip bus interface for accessing arm9 platform general purpose registers. the ip bus interface on the jam populates aipi2, slot 30. the ip bus registers implemented in the jam are shown in table 9-2 . the registers may be aliased thr oughout the aipi2 slot 30 location; however, the registers should only be accessed at the above listed addresses. attempts to access the regi sters at aliased locations may result in an error response. additionally, attempts to access the registers in user mode or in non-word sizes will result in an error response. writes to the read only arm9p_gpr4 register are i gnored and will not cause an ahb transfer error. arm9p_gpr0 bit [1], etb_reg_clken, is reset to zero on power-up and disables the clocks to the etb for non debug purposes. when set to one, etb_reg_clken will en able clocks to the etb such that the memory in the etb can be used as general scratch-pad memory. arm9p_gpr0 bit [0], ahb_dbg_en, is reset to zero on power-up and disables the ahb debug related signals from toggling in order to save power. when set to a one, ahb_dbg_en enables the following top-level platform ahb related signa ls to toggle for platform debug: ? i-ahb: dbg_iahb_hready, dbg_iahb_htrans1, dbg_iahb_haddr[31:29] ? d-ahb: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_haddr[31:29] ? p-ahb: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_hmaster these signals, along with signals available on the alte rnate bus master and secondary ahb ports, can be used to gain insight into the functionality of the max. arm9p_gpr4 is provided for software to determine the version of the platform. these bits correspond to the static state of the tapid[31:0] signals wh ich include the tapid_ver[3:0] platform inputs. see section 9.4, ?jtag id register ? for more details. table 9-2. jam ip bus general purpose registers primary haddr register name type implementation 32?h1003_e000 arm9p_gpr0 write/read {30?h0, etb_reg_clken, ahb_dbg_en} 32?h1003_e010 arm9p_gpr4 read only tapid[31:0] arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-11 9.2.11 test wrapper the arm9 platform?s test architecture is composed primarily of two functions: scan and bist. the test module (arm926p_test) includes a test control unit wh ich decodes primary test mode input signals and places the platform into various test modes including sca n, ac path testing, bist, and safe state. these test modes support the ability to test a deeply embedded platform. refer to the arm9 platform dft specification for more information. 9.3 arm9 platform hierarchy the first two levels of the arm9 platform design hierarchy are shown in figure 9-2 . figure 9-2. arm9 platform hierarchy arm9p platform arm926p_core arm926p_test arm926ej-s clkctl pa h b m u x max (crossbar switch) mctl aipi1 aipi2 aitc r o m pat c h jam arm926p_wrapper arm926p_tcu arm926p_router arm926p_tsecure arm926p_tclocks jam arm926p_debug etb9 etm9 arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-12 freescale semiconductor 9.4 jtag id register the arm926ej-s processor has a 32-bit input bus which corresponds to the jtag id register. this 32-bit register is defined fields as shown in table 9-3 . arm requires bits [31:12] be set in accordance with their general rules such that multi-ice can auto-detect the device type. 9.5 system memory map haddr[31:29] on the max master ports are decoded dete rmine which slave port has been selected. only three bits are used in order to keep output port decode time to a minimum. table 9-4 shows a simplified breakdown of the eight 512 mbyte regions decoded within the 4 gbyte address space. 9.5.1 arm9 platform memory map table 9-5 shows the complete arm9 platform memory map. table 9-3. arm926ej-s jtag id register definition tapid[31:28] tapid[27:12] tapid[11:8] tapid[7:1] tapid[0] version part number manufacturing id 1?b1 4?b0 16?h7926 tapid_ver[3:0] 7?b001_0000 1?b1 table 9-4. upper address bit decode haddr[31:29] size use 3?b000 512 mbyte primary ahb?aipi1, aipi2, aitc, mctl (rom), rompatch 3?b001 512 mbyte reserved 3?b010 512 mbyte reserved 3?b011 512 mbyte reserved 3?b100 512 mbyte secondary ahb slave port 1 3?b101 1 gbyte secondary ahb slave port 2 3?b110 3?b111 512 mbyte primary ahb?mctl (ram) table 9-5. arm9 platform memory map address range size use 0000_0000?0000_3fff 16 kbyte rom: first 16kb (primary ahb) 0000_4000?0040_3fff 4 mbyte reserved 0040_4000?007f_ffff 4 mbyte?16 kbyte rom: exceeding 16kbyte (primary ahb) 0080_0000?0fff_ffff 256 mbyte?8 mbyte reserved 1000_0000?1000_0fff 4 kbyte aipi1 control registers (primary ahb) 1000_1000?1001_ffff 124 kbyte aipi1 peripheral space (primary ahb) arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-13 9.5.2 external peripheral space aipi1 supports 31 external peripherals starting at 32?h1000_1000. aipi2 has three slots used internal to the arm9 platform and supports 17 external peripherals from 1002_1000?1003_efff. note care should be taken when programmin g the psr of aipi2 since slot 31 (max), slot 30 (jam), slot 29 (etb registers), slot 28 (etb ram) and slot 27 (etb ram) will always be occ upied and slots 26:18 will always be unoccupied. 9.5.3 external boot when the boot_int input signal is asserted, the ar m926ej-s will boot internal from rom on the primary ahb. when boot_int is negated, the arm926ej-s reset ve ctor fetch will essentially be routed to an address indicated by the ext_boot_addr[31:2] input pins. this vectoring is done by the rompatch module, which monitors the i-ahb of the arm 926ej-s and over-rides th e reset vector fetch. refer to the rompatch design specification for more detail on the external boot mechanism. 1002_0000?1002_0fff 4 kbyte aipi2 control registers (primary ahb) 1002_1000?1003_1fff 68 kbyte aipi2 peripheral space (primary ahb) 1003_2000?1003_afff 36 kbyte reserved 1003_b000?1003_bfff 4 kbyte aipi2?etb registers (primary ahb) 1003_c000?1003_cfff 4 kbyte aipi2?etb ram (primary ahb) 1003_d000?1003_dfff 4 kbyte aipi2?etb ram (primary ahb) 1003_e000?1003_efff 4 kbyte aipi2?jam (primary ahb) 1003_f000?1003_ffff 4 kbyte aipi2?max (primary ahb) 1004_000?1004_0fff 4 kbyte aitc (primary ahb) 1004_1000?1004_1fff 4 kbyte rompatch (primary ahb) 1004_2000?1fff_ffff 256 mbyte?280 kbyte reserved 2000_0000?7fff_ffff 1.5gbyte reserved 8000_0000?9fff_ffff 512 mbyte secondary ahb slave port 1 a000_0000?dfff_ffff 1 gbyte secondary ahb slave port 2 e000_0000?ffef_ffff 511 mbyte reserved (aliased ram space) fff0_0000?ffff_ffff 1 mbyte ram (primary ahb) table 9-5. arm9 platform memory map (continued) address range size use arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-14 freescale semiconductor note when boot_int is negated and the arm926ej-s boots externally the arm9 platform is placed in an insecure state. 9.5.4 memory map considerations ? accesses to ?reserved? locations in table 9-5 other than aliased ram space will result in an ahb error response. ? accesses to unsupported address locations through the max will re sult in an ahb error response and the access will not pass through the max. ? accesses to address locations on the primary ahb bus which do not map to a specific module will time-out in accordance with the bmon_timeout[2:0] inputs. ? accesses to unimplemented locations within th e aitc and rompatch register space will be terminated without a bus-error. writes will have no effect and reads will return all zeros. 9.6 platform clocking this section will describe some of the clocking considerations within the arm9 platform. the circuits contained in the arm9 platform to address most of these issues will be implemented within the clock control module (clkctl). however, there are some exte rnal clock control issues that will be discussed. refer to the arm9 platform clkctl module design specification for more detail. 9.6.1 arm926ej-s clock considerations the arm926ej-s processor design uses a single clock, clk. in many systems, it will be desirable for the arm926ej-s processor to run at a higher frequency th an the ahb system bus (which runs on hclk). to support this, arm926ej-s requires a separate ahb clock enable for each of the two bus masters. dhclken is used to signify the rising edge of hclk for the system in which the data biu is the bus master. ihclken is used to signify the rising edge of hclk for the system in which the instruction biu is the bus master. figure 9-3 shows the relationship between clk, hclk and dhclken/ihclken. the arm9 platform will provide a single hclken input pin that will be fed to both the dhclken and ihclken inputs on the arm926ej-s. if hclk and clk are the same frequency, th e hclken input to the platform must be tied high. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-15 figure 9-3. ahb clock relationship clk and hclk must be synchronous and the skew betw een clk and hclk to the arm9 platform should be minimized. this will require some synchronization insi de the chip clock control module. an example of this is provided in figure 9-4 . in the example, clk and hclk are completely asynchronous and clk must be much faster to sample the slower clock, otherwise a different scheme will be needed. also, if clk and hclk are synchronous to each other by design, then a sync hronizer may not be needed, but care must still be taken in aligning the rising edges of both clocks to the arm9 platform. figure 9-4. example hclk to clk synchronization when clk is faster ( hclken ) d q clk d q clk d q clk ccm boundary arm9 platform boundary hclk clk_always hclken cpu clock (fast clock) bus clock (slow clock) insertion insertion delay + f/f clk->q clk gate_hclk clk insertion delay + f/f clk->q gate_clk delay >q arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-16 freescale semiconductor 9.6.2 arm926ej-s jtag port clocking considerations the arm926ej-s does not support direct connection to the jtag interface. the jtag interface must be synchronized to the clk domain. this synchronization will take place within the platform?s clkctl module. refer to the arm9 platform clkctl design specification for more detail. 9.6.2.1 jtag_tck the jtag_tck clock must be less than 1/8 the freque ncy of the clk input in order for the jtag port and synchronizer to function properly. note that the fr equency of clk can vary when executing low-power code. therefore, care must be taken such that jtag_tck is less than 1/8 the lowest possible frequency of clk. 9.6.3 external alternate bus master interfaces all four alternate bus master ports on the arm9 pl atform must have the ahb synchronized to hclk external to the platform. all alternate bus master ahb inputs and outputs to/from the arm9 platform will be synchronous to hclk. 9.6.4 external secondary ahb ports both secondary ahb ports inputs and outputs to and from the arm9 platform must be synchronous to the hclk and will run at the hclk frequency. 9.7 platform resets this section will describe the vari ous arm9 platform reset inputs. figure 9-5 shows the reset paths within the arm9 platform. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-17 figure 9-5. arm9 platform resets 9.7.1 hreset the hreset_b input is the asynchronous system reset for both the clk and hclk domains. it is gated with a test mode signal in the scan wrapper, and is then buffered for distribution throughout the platform. the hreset_b signal must satisfy the setup and hold time re quirements relative to both clk and hclk rising edges. 9.7.2 por and jtag_trst the power-on-reset (por) and the jtag reset (jtag_trs t_b) will be combined in the clkctl module to drive the dbg_clear_b signal to the arm926ej-s and etm9 modules. the dbg_clear_b output of the clkctl module can be considered as the jtag or debug reset of the platform. the dbg_clear_b signal will assert asynchronously when either por or jtag_t rst_b asserts, and will ne gate synchronously to clk (through a synchronizer). refer to the clkctl m odule design specification for more detailed information. arm9 platform hreset_b arm926p_test tcu_hreset_b ctbuf arm926p_core hreset_b clkctl por jtag_trst_b ctbuf dbg_clear_b arm926ej-s hresetn dbgntrst etm9 ntrst nreset (to all other platform modules) hreset_b sync or and clk_always ntrst nreset hresetn etb9 arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-18 freescale semiconductor 9.8 power management 9.8.1 register level clock gating a synopsys power compiler will be used to impleme nt clock-gating on all components of the arm9 platform. that is, under normal operating conditions, clocks internal to the platform will only be issued to registers or banks of flops that need a rising edge for proper functionality. otherwise, the clocks will be held low. 9.8.2 block level clock gating clocks to individual modules within the platform will be enabled only when necessary. on the primary ahb for example, the clkctl module will only enable hclk to a slave module when the current ahb access is addressed to that module. slaves can also drive a signal to the clkctl if it requires its hclk to run for any other reason. see the clkctl m odule design specification for more detail. 9.8.3 external clock gating the arm926ej-s processor may be put into a low-power state by the wait-for-interrupt instruction. this instruction switches the arm926ej-s into a low-power state until either an interrupt (nirq/nfiq) or a debug request occurs. the switch into the low-power state is indicated by the assertion of the arm_standbywfi output signal. if arm_standbywfi is asserted then it is guaranteed that all arm926ej-s external interfaces will be in an idle state. the ar m_standbywfi signal is intended to be used to shut down clocks to the other parts of the syst em, such as external coprocessors, which do not need to be clocked if the arm926ej-s is idle. note: the arm926ej-s clk must not be stopped during wait-for-interrupt mode if an external debugger is connected to the jtag port. an active clk is required to be able to write values into the arm9ej-s debug control register, which is required for a debugger to be able to force wait-for-interrupt mode to be exited. it should also be noted that the arm926ej-s needs clk to run in order for an interrupt to cause the negation of arm_standbywfi. the jtag synchronizer in the clkctl module needs to ha ve an ?always? clock running to it in order to, at any time, detect jtag activity a nd thereby determine that a debugger is connected to the jtag port. the presence of an active jtag debugger will be de tected by monitoring the jtag tms signal. after por (or trst_b) assertion, a low state on tms coincide nt with a rising-edge on tck will transition the jtag tap-controller from the test-logic-reset state to the run-test-idle state. the dbgen signal will be asserted, and held asserted, whenev er the tap-controller is not in th e test-logic-reset state. once dbgen asserts, an active trst_b or por is required to clear it (that is, once a debugger is detected to be connected, it is assumed to stay connected). when asserted, the a9p_clk_off output of the platform will indicate to an exte rnal clock control module that clk and hclken should be turned off at the earl iest opportunity. however, in order to assure that no alternate bus masters are in the middle of a transacti on, the external clock control module must assert the ccm_br input (bus request) of the crossbar switch. th is will request ownership of all ahb output ports. once the bus grant is asserted (ccm_bg), the external cl ock control module is then free to gate off hclk as all transactions on both the primary a nd secondary ahbs will have completed. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-19 figure 9-6 shows a block diagram of how the clocks to the platform might be handled in a typical implementation. figure 9-6. arm9 platform clocking strategy 9.8.4 well biasing a well bias clamp enable input, wt_en, will be driven by an external clock control module to the arm9 platform. when asserted, v bb+ will be shorted to vdd and v bb- will be shorted to gnd. 9.9 platform ahb interfaces this section will describe the major bus interface s of the arm9 platform and the crossbar switch. a simple block diagram of the bus connec tions to the platform is shown in table 9-1 . a definition of arm9 platform arm926ej-s aitc irq_b firq_b dbgen standbywfi hclken hclk external clock control module ccm_br ccm_bg a9p_clk_off irq[63:0] ip bus clk hclk jtag jtag sync clkctl ?arm? jtag clk gating module individual module enables clk hclken clk ihclken dhclken clk_always flop reset etm9 etm cg clk dbgtcken etb9 arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-20 freescale semiconductor ahb-lite, a functional description of the alternate bus master ports, and finally a description of the multi-layer crossbar switch slave ports follows. 9.9.1 definition of ahb-lite all master and slave ports of the multi-layer ahb crossbar switch are ahb-lite compliant. therefore, all ahbs connected externally to the arm9 platform must be ahb-lite compliant. the definition of ?ahb-lite? for the arm9 platform is as follows: ? ahb split and retry protocols are not supported within the arm9 platform. this means that all slaves connected to ahb-lite ports (input or out put) are prohibited from requesting a split or a retry. this also means there is only one response signal, hresp0. ? amba bus request and bus grant are not supported on the ahb-lite interfaces. ? bursts are supported. the default configuration of the crossbar switch (max) insures no early fixed length burst te rminations due to the switch arbiter. 9.9.2 alternate bus master ports there are four alternate bus master ports (abm) on th e arm9 platform which are connected directly to the multi-layer ahb crossbar switch. these four abm interfaces are ahb-lite compliant. table 9-6 lists the abm interface signals (?x? is equal to 2 through 5). all signals function as documented in the amba specification, rev 2.0, amba ahb chapter. it is assumed that the alternate bus masters are using the same hclk and hreset_b as the arm9 platform. table 9-6. alternate bus master interface signal list pin list direction 1 1 direction is relative to the arm9 platform. description mx_haddr[31:0] input ahb address bus mx_hmaster[3:0] input ahb master id mx_htrans[1:0] input ahb transfer type mx_hprot[3:0] input ahb access protection indicator mx_hlock input ahb master lock indicator mx_hmastlock input ahb-lite master lock indicator mx_hwrite input ahb access write indicator mx_hsize[1:0] input ahb transfer size mx_hburst[2:0] input ahb access burst type mx_hwdata[31:0] input ahb write data mx_hready_out output ahb termination/take indicator mx_hrdata[31:0] output ahb read data mx_hresp0 output ahb error indicator arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-21 9.9.3 single master seamless connection to abm port a single external master can connect seamlessly (no logic) to any of the four alternate bus master interfaces (all four abm interfaces are iden tical). in this configuration, table 9-7 lists the ahb signals which deserve special consideration. note the alternate bus master must drive htrans = idle when not requesting the bus as the arbiter may be parked on that input port. 9.9.4 multiple external masters connection to abm port the four alternate bus master interfaces of the arm9 platform have been desi gned to support connection of multiple external ahb-lite masters and slaves directly to the interface. figure 9-7 shows the connection of two external masters to a arm9 platfo rm alternate bus master interface. note the location of the arm9 platform in the figure below and that only one of four abm ports is shown. table 9-7. single external master connections to an alternate bus master interface ahb signal connection master?s hbusreq output if present leave unconnected master?s hgrant input if present tie asserted (high) master?s hready input connect to abm hready_out output master?s hlock output if present connect to abm hlock input 1 1 if the master does not have an hlock output, tie the abm hlock input negated (low). master?s hmastlock output if present connect to abm hmastlock input 2 2 if the master does not have an hmastlock output, tie the abm hmastlock input negated (low). arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-22 freescale semiconductor figure 9-7. example of two external masters connected to an abm port in the figure, two external masters, #1 and #2, arbi trate for control of the abm interface on the arm9 platform. an external arbiter is required. the arbiter accepts the bus master?s hbusreq signals, and responds to the masters with hgrants. the arbiter also controls the address/control and data muxing in the external ahbmux module. 9.9.5 alternate bus master design considerations this section will discuss various issues which shoul d be taken into account by engineers designing ahb masters to connect to the arm9 platform?s alternate bus master interfaces. 9.9.5.1 edge-based design all alternate bus masters should be edge-based desi gns in order to meet the stringent timing imposed. specifically, an ahb master?s addr ess and control information should be driven directly from the output of a flip-flop. similarly, an ahb master?s read data should go directly to a d-input of a flip-flop. arm9 bus master arbiter m1_hbusreq m1_hbgrant m2_hbusreq m2_hgrant external m1_haddr/ctrl m2_haddr/ctrl adr_select haddr/ctrl m2_haddr/ctrl m2_hwdata m2_hrdata m2_hready_out hwdata hrdata data_select hwdata hrdata a9p_hready hready hready hwdata a9p_hrdata (only one of four alternate bus master interfaces shown) # 1 bus master # 2 platform arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-23 9.9.5.2 htrans [1:0] some important issues to rememb er about the ahb htrans signals: ? it is important that alternate bus masters drive htrans = idle when not requesting the bus. this is critical because the arbiter can grant the bus to a master even when the master is not requesting it (for example, a ?parked? condition). ? although the amba ahb specification does not requi re it, it is suggested that alternate bus masters assert htrans = nseq with the initial assertion of hbusreq. in those systems where only a single master is connected to an input port, the hgrant signal will tied high, and improved performance may result. ? it is highly recommended that alternate bus master s insert an idle cycle after any locked sequence to provide an opportunity for the arbitration to change before commencing further transfers. 9.9.5.3 hlock/hmastlock the mx_hlock and mx_hmastlock abm interface signal connections are dependent on whether there is a single external master or connection to an external arbiter. the following notes specify the connections: ? for single masters only, the mx_hlock input should be connected directly to the master?s hlock output. in this case, the mx_hmastlock input should be tied low. if the single master produces an hmastlock instead the mx_hmastlock input should be connected directly to the master?s hmastlock output. in this case, the mx_hlock input should be tied low. ? for multiple master connections on an abm por t, the mx_hmastlock input signal should be connected to the external arbiter?s hmastlock out put. in this case, mx_hlock should be tied low. in either case above, logic within the crossbar swit ch will insure the locked cycles? functionality. 9.9.5.4 hmaster alternate bus masters external to the arm9 platform s hould be aware that four values of the hmaster field are used by bus masters internal to the platform. th e reserved and available hmaster encodings are shown in table 9-8 . table 9-8. hmaster encodings hmaster use 4?h0 reserved: max default 4?h1 reserved 4?h2 reserved: arm926ej-s i-ahb 4?h3 reserved: arm926ej-s d-ahb 4?h4?4?hf available to external bus masters arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-24 freescale semiconductor 9.9.5.5 hresp0?bus error a slave two cycle error response (hresp0 = high) al lows for a bus master to cancel the remaining transfers in a burst. however, this is not an ahb requirement, and it is acceptable for the master to continue the remaining transfers of the burst. ahb error responses generated on accesses to cacheab le or bufferable memory address on the i-ahb and d-ahb interfaces of the arm926ej-s are normally ignored by the processor. in the rompatch module, a feature can be enabled which will, on the a bove described accesses, ga te 0?s onto hrdata[31:0] on data reads, and swi opcodes onto hrdata[31:0] for instruction pref etches. at the same time, the rompatch module will generate an abort which w ill guarantee entry into the arm926ej-s platform?s abort exception handler. see the arm9 platform rompatch design specification for more detail. 9.9.5.6 unaligned transfers alternate bus masters should not request unaligned transfers. that is, a word access to a non-word aligned address; and, a halfword access to a non-halfword al igned address should not be requested as neither transactions are supported by this platform. the tran sfers will complete as normal, however the lower order address bits will be ignored according to figure 9-4 and figure 9-5 . 9.9.5.7 alternate bus master throttle control alternate bus masters should be designed with programmable maximum burst lengths as well as programmable bus request interval timers. this will allow software to effectively ?tune? the overall system for maximum throughput and efficiency. 9.9.5.8 halt request (ccm_br) care must be taken to ensure that the halt low prio rity bit is not changing as the clock control module?s halt request is asserted. this will result in unpredic table behavior. this can be avoided by not modifying this bit in the slave general purpose control register or in the alternate slave general purpose control register in software where halt could be requested. also, the halt low priority bit should be programmed the same in both the slave general purpose control register and the alternate slave general purpose control register, if it is likely the max can change between the general purpos e and alternate registers during the time halt could be requested. care should also be taken to ensure that the clock control module?s halt request is not asserted until at least two clock cycles after the last locked acc ess performed by any master connected to the max. 9.9.6 max ahb slave ports each slave port of the multi-layer crossbar swit ch is an ahb-lite compliant bus. brief functional descriptions and attributes of each output port are provided. arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-25 9.9.6.1 slave port 0?primary ahb (internal) slave port 0 of the max is connected to the ?pri mary? ahb of the arm9 platform. the primary ahb is completely contained within the arm9 platform . a simplified block diagram of the primary ahb components is shown in figure 9-8 . figure 9-8. the primary ahb the primary ahb will have the aitc, aipi (2), mctl and rompatch modules connected as slave devices. the pahbmux (primary ahb mux) module is the glue that pulls the primary ahb and its components together. it will decode the primary ahb haddr lines and issue module selects to the slaves, combine the slave hready and hresp0 signals from the slaves into the single bus hready and hresp0, and mux the read data from the currently selected slave onto the bus hrdata lines. a bus monitor module inside of pahbmux will terminate timed-out bus transac tions. in addition, the pahbmux will contain logic to terminate any idle cycles and issue the required assertion of hready following negation of the hreset_b. 9.9.6.1.1 primary ahb device latencies the latency of each slave device on the primary ahb can be found in table 9-1 . the clock latency number does not take into account the possible one clock arbitration delay of the max. multi-layer crossbar primary ahb aipi1 mctl aitc aipi2 haddr hcontrol hwdata hready hready hrdata[31:0] hresp0 hrdata hresp0 aitc_rdata mctl_rdata aipi1_rdata aipi2_rdata gnd addr decode haddr hsel_x hready_out, hresp0 from slaves combine bus monitor select pa h b m u x slave port 0 switch ahb (only signals are shown) (max) aitc_rdata_ovr rom rompatch_rdata pat c h regs arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-26 freescale semiconductor 9.9.6.2 secondary ahb slave ports 1 and 2 each of the secondary ahb slave ports are identical ahb-lite compliant bus es. it is envisioned that these ports will interface predominately to internal and external memory. however, it is possible to connect an external aipi interface along with associated periphe rals to these ports. the secondary port slave signals are list in table 9-2 where ?x? is equal to 1 or 2. 9.9.7 endian modes the arm9 platform will support both big and little endian modes. the relevant signals to/from the arm926ej-s processor are shown in table 9-3 below along with brief descriptions. table 9-1. primary ahb slave device latencies slave device transaction type latency aitc register access 1 clock aipi 1 1 the latency listed for the aipis are best case and based on a zero wait state response from the ip bus target device. each wait state the ip bus target device adds will add one extra clock to the listed latency value. writes reads 3 clocks 2 clocks mctl memory access 1 clock 2 2 assumes ram_wait and rom_wait are negated. rompatch register access 1 clock table 9-2. secondary ahb interface signal list pin list direction 1 1 direction is relative to the arm9 platform. description sx_haddr[31:0] output ahb address bus sx_hmaster[3:0] output ahb master id sx_htrans[1:0] output ahb transfer type sx_hprot[3:0] output ahb access protection indicator sx_hmastlock output ahb-lite master lock indicator sx_hwrite output ahb access write indicator sx_hsize[1:0] output ahb transfer size sx_hburst[2:0] output ahb access burst type sx_hwdata[31:0] output ahb write data sx_hready input ahb termination/take indicator sx_hrdata[31:0] input ahb read data sx_hresp0 input ahb error indicator arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-27 the bigendinit platform input is connected directly to the bigendinit input of the arm926ej-s and determines the processor and platform endian mode of operation upon exiting system reset. however, the endian mode of operation of the processor (and ther efore the platform and associated memory systems) may be changed according to the bigend bit in the cp15 control register. this output, cfg_bigend, reflects the bigend bit and is used to indicate the current endian mode of operation for the platform as well as all external bus masters and slaves. the relevant endian signals are shown in figure 9-9 . figure 9-9. endian configuration routing the dhbl signals of the arm926ej-s will not be used within the platform. instead, all modules affected by the endian mode will use the cfg_bigend signal in conjunction with hsize and haddr[1:0] in order to handle non-word transfers correctly. it is not envisioned that applications will need to dynamically change endianness. however, this is still under investigation, and should be possible since the platform will support both endian modes in hardware. it then becomes a software issue to insu re a graceful mode change. for example, the write buffers should be drained prior to changing endian modes. 9.9.7.1 affected modules only the aipi (2), mctl (ram and rom) and rompatch modules are affected by the cfg_bigend signal within the platform. etm9/etb is affected by the endian mode, and instead is connected to the etm_bigend signal internally. table 9-3. arm926ej-s endian related signals signal direction description bigendinit input determines the setting of the bigend bit held in the cp15 control register after system reset. when high, the reset state of the bigend bit will be 1 (big endian). when low, the reset state of the bigend bit will be 0 (little endian). cfgbigend output arm926ej-s bigend configuration indicator. this signal reflects the value of the bigend bit held in the cp15 control register, which is used to determine the behavior of the arm926ej-s wrt endianness. when high, the arm926ej-s treats bytes in memory as being in big endian format. when low, memory is treated as little endian. arm926ej-s arm9 platform bigendinit bigendinit cfgbigend cfg_bigend mctl aipi(2) ro m pat c h (to external ahb masters and slaves) etm/etb etm_bigend arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-28 freescale semiconductor 9.9.7.2 unaffected modules the aitc module is 32-bit write only. the registers within the max are also 32-bit access only, and the endian mode is transparent from the ahb switch perspective. the pahbmux module has no registers associated with it and the endian mode is transparent to its data muxing. 9.9.7.3 un-aligned transfers unaligned transfers are not supported by the arm9 pl atform and therefore should not be attempted by alternate bus masters connected to it. that is, altern ate bus masters should not attempt a 32-bit access to a non-word aligned address, nor a 16-bit access to a non half-word aligned addr ess. the transfers will complete as normal, however the lower orde r address bits will be ignored according to figure 9-4 and figure 9-5 . 9.9.7.4 endian mode and alternate bus masters alternate bus masters must be cognizant of the endi an mode if they are capable of performing non-word accesses. non-word register and memory transactions will be performed according to the state of the cfg_bigend output signal. the manner in which memory is accessed in the two endian modes is described in the following two sections. 9.9.7.5 little endian operation a little endian configured arm9 platform (cf g_bigend = 0) should have memory connected to its secondary ahb ports as follows: ? byte 0 of the memory connected to d[7:0] ? byte 1 of the memory connected to d[15:8] ? byte 2 of the memory connected to d[23:16] ? byte 3 of the memory connected to d[31:24] the byte write enables should be decoded by the ahb slaves as in table 9-4 . table 9-4. little endian byte write enable decoding hwrite hsize[1:0] haddr[1:0] we[31:24] we[23:16] we[15:8] we[7:0] 0xx0000 100000001 100010010 100100100 100111000 1010x0011 1011x1100 110xx1111 1 11 reserved arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-29 9.9.7.6 big endian operation a big endian configured arm9 platform (cfg_bigend= 1) should have memory connected to its secondary ahb ports as follows: ? byte 0 of the memory connected to d[31:24] ? byte 0 of the memory connected to d[23:16] ? byte 0 of the memory connected to d[15:8] ? byte 0 of the memory connected to d[7:0] the byte write enables should be decoded by the slaves as in table 9-5 . 9.10 preliminary size estimate table 9-6 show preliminary size estimates for the arm9 pl atform. note that the area estimates correspond to c90lp, wcs, 1.1 v, 105c. clk = 266 mhz, hclk = 133 mh z. gate equivalents are scaled to the area of the c90lp nand2_2 cell. table 9-5. big endian byte write enable decoding hwrite hsize[1:0] haddr[1:0] we[31:24] we[23:16] we[15:8] we[7:0] 0xx0000 100001000 100010100 100100010 100110001 1010x1100 1011x0011 110xx1111 1 11 reserved table 9-6. arm9 platform size estimates block number included in platform area in m 2 gate count total (nand2_2) i-cache data memory (1024x32) 4 259,512 i-cache tag memory (128x22) 4 74,990 i-cache valid memory (32x24) 1 16,122 * d-cache data memory (1024x32) 4 259,512 d-cache tag memory (256x22) 4 149,980 * d-cache valid memory (32x24) 1 16,122* d-cache dirty memory (128x8) 1 8,242 mmu ram (32x64) 2 73,286 arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-30 freescale semiconductor 9.11 power consumption table 9-7 summarizes preliminary power estimates for the various arm9 platform operating modes. power numbers will be measured off of the final freeze post-route netlist. there is no padding or margin included in these numbers. etb ram (1024x32) 2 129,756 memories total 23 987,522 350k arm926 core 1 tbd etm9 (medium +) 1 tbd etb11 1 tbd aitc 1 tbd mctl + rom bist 1 tbd aipi 2 tbd ahbmux 1 tbd max 1 tbd scan wrapper 1 tbd ro m pat c h 1 t b d bist for memories 4 tbd ip to ahb (for etb11) 1 tbd clock and sync control 1 tbd jam 1 tbd secure rom monitor 1 tbd clock tree 2 tbd logic total tbd tbd 55% routing efficiency (logic only) tbd tbd platform total tbd tbd table 9-7. arm9 platform power estimates mode of operation bcs corner (1.3 v ?20c) typ corner (1.2 v 25c) wcs corner (1.1 v, 105c) run mode tbd tbd tbd doze mode tbd tbd tbd table 9-6. arm9 platform size estimates (continued) block number included in platform area in m 2 gate count total (nand2_2) arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-31 the operating modes are described below: ? run mode clk, clk_always = 266mhz, hclk = 133mhz. code running out of cache, once instructions loaded into cache. exercising cache/mmu memories. core busy with arithmetic operations. activity on all alternate master ports and all slave ports c oncurrently. compiled memory models pessimistic when memories not being accessed. estimated loads on all plat form outputs ranging from 0.5pf to 1.5pf. ? doze mode clk, clk_always, and hclken stopped. hclk = 117mhz. no alternate bus master activity. estimated loads on all platform outputs ranging from 0.5pf to 1.5pf. ? sleep mode all clocks stopped. includes: clk, clk_always, hclke n, and hclk. basically represents platform leakage current. no dynamic or static power in sleep mode. well bias active power typ very crude estimate of 10x reduction + compiled memories. power due to charge pump not included since charge pump is external to the platform. wcs measured with well bias standard cell library. 9.12 arm9 platform i/o signal list the complete list of inputs and outputs for the arm9 platform are listed in table 9-8 . sleep mode without well bias active tbd tbd tbd sleep mode with well bias active tbd tbd tbd table 9-8. arm9 platform signal list signal type description clocks and resets clk input processor and nexus reference clock clk_always input clk that always runs hclk input ahb domain reference clock hclken input controls arm926ej-s sampling of hclk domain a9p_clk_off output to external clock control module: the arm9 platform clk may be turned off por input power-on reset hreset_b input system reset (arm926ej-s and ahb reset) platform configuration table 9-7. arm9 platform power estimates (continued) mode of operation bcs corner (1.3 v ?20c) typ corner (1.2 v 25c) wcs corner (1.1 v, 105c) arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-32 freescale semiconductor bigendinit input 1 = big endian, 0 = little endian determines initial endian mode out of reset cfg_bigend output 1 = big endian, 0 = little endian reflects the value of bigend bit in arm926ej-s cp15 register. determines endianness of platform slaves and external ahbs. boot_int input internal boot indicator ext_boot_adr[31:2] input external boot address bmon_timeout[2:0] input bus monitor timeout jtag interface and related i/o jtag_tck input jtag test clock jtag_trst_b input jtag test reset jtag_tms input jtag test mode select jtag_tdi input jtag test data input jtag_tdo output jtag test data output jtag_tdoen_b output jtag test data output tri-state control tapid_ver[3:0] input platform version number (jtag id register bits [11:8]) dbgrtck output tck ?return clock? from jtag synchronization arm926 debug related signals dbgrq input to arm926: debug request (connected to edbgrq) dbgack output from arm926: debug acknowledge dbgext[1:0] input to ice: external breakpoints/watchpoints dbgiebkpt input to arm926: instruction breakpoint dbgdewpt input to arm926: data watchpoint arm_dbgrng[1:0] output from arm926: embedded ice-rt range out arm_standbywfi output from arm926: processor is in wait for interrupt mode arm_java_mode output from arm926: processor is in java mode arm_thumb_mode output from arm926: processor is in thumb mode arm_fiq_b output from aitc: fast interrupt request to processor arm_irq_b output from aitc: interrupt request to processor arm_fiq_disable output from arm926: processor has disabled fiq interrupts arm_irq_disable output from arm926: processor has disabled irq interrupts arm_cpsr_mode[4:0] output from arm926: processor cpsr mode bits platform debug related signals table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-33 dbg_iahb_hready output arm926ej-s i-ahb hready dbg_iahb_htrans1 output arm926ej-s i-ahb htrans[1] dbg_iahb_haddr[31:29] output arm926ej-s i-ahb requested address (top 3 bits) dbg_dahb_hready output arm926ej-s d-ahb hready dbg_dahb_htrans1 output arm926ej-s d-ahb htrans[1] dbg_dahb_haddr[31:29] output arm926ej-s d-ahb requested address (top 3 bits) dbg_pahb_hready output primary ahb hready dbg_pahb_htrans1 output primary ahb htrans[1] dbg_pahb_hmaster[3:0] output primary ahb hmaster ownership dbg_a9p_ahb_en output enable output used for gpio muxing of these debug signals mctl rom memory interface rom_connect input indicates rom exists on the mctl interface. rom_max_addr[11:0] input indicates rom size. corresponds to haddr[21:10]. smallest size supported is 1kbyte, largest 4 mbyte. rom_wait input rom wait-state indicator 0 = no wait-state required 1 = one wait-state required mctl_ce_rom_b output mcu rom chip enable mctl_addr_rom[19:0] output mcu rom address. mem_q_rom[31:0] input rom read data mctl ram memory interface ram_connect input indicates ram exists on the mctl interface. ram_max_addr[9:0] input indicates ram size. corresponds to haddr[19:10]. smallest size supported is 1kbyte, largest 1 mbyte. ram_wait input ram read cycle wait-state indicator 0 = no wait-state required 1 = one wait-state required mctl_mbist_sddtm output mcu ram mbist sdd test mode output extram_oe output testmode control of external memories? output enable. this output should be connected to the oen ports of all memories external to the arm9 platform (sram and tcm). mctl_ce_ram_b output mcu ram chip enable mctl_wr_ram_b output mcu ram access type: read=0, write=1 mctl_addr_ram[17:0] output mcu ram address mctl_ben_ram_7_0 output mcu ram byte enables table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-34 freescale semiconductor mctl_ben_ram_15_8 output mcu ram byte enables mctl_ben_ram_23_16 output mcu ram byte enables mctl_ben_ram_31_24 output mcu ram byte enables mctl_d_ram[31:0] output ram write data mem_q_ram[31:0] input ram read data multi-layer ahb master port 2 m2_hlock input ahb locked cycle indicator (bus request timing) m2_hmastlock input ahb locked cycle indicator (address timing) m2_hmaster[3:0] input ahb master m2_htrans[1:0] input ahb transfer type m2_hprot[3:0] input ahb protection control m2_hwrite input ahb write/read indicator m2_hsize[1:0] input ahb transfer size m2_hburst[2:0] input ahb burst length m2_haddr[31:0] input ahb address m2_hwdata[31:0] input ahb write data m2_hready_out output ahb transfer done out m2_hrdata[31:0] output ahb read data m2_hresp0 output ahb transfer response multi-layer ahb?master port 3 m3_hlock input ahb locked cycle indicator (bus request timing) m3_hmastlock input ahb locked cycle indicator (address timing) m3_hmaster[3:0] input ahb master m3_htrans[1:0] input ahb transfer type m3_hprot[3:0] input ahb protection control m3_hwrite input ahb write/read indicator m3_hsize[1:0] input ahb transfer size m3_hburst[2:0] input ahb burst length m3_haddr[31:0] input ahb address m3_hwdata[31:0] input ahb write data m3_hready_out output ahb transfer done out m3_hrdata[31:0] output ahb read data table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-35 m3_hresp0 output ahb transfer response multi-layer ahb master port 4 m4_hlock input ahb locked cycle indicator (bus request timing) m4_hmastlock input ahb locked cycle indicator (address timing) m4_hmaster[3:0] input ahb master m4_htrans[1:0] input ahb transfer type m4_hprot[3:0] input ahb protection control m4_hwrite input ahb write/read indicator m4_hsize[1:0] input ahb transfer size m4_hburst[2:0] input ahb burst length m4_haddr[31:0] input ahb address m4_hwdata[31:0] input ahb write data m4_hready_out output ahb transfer done out m4_hrdata[31:0] output ahb read data m4_hresp0 output ahb transfer response multi-layer ahb master port 5 m5_hlock input ahb locked cycle indicator (bus request timing) m5_hmastlock input ahb locked cycle indicator (address timing) m5_hmaster[3:0] input ahb master m5_htrans[1:0] input ahb transfer type m5_hprot[3:0] input ahb protection control m5_hwrite input ahb write/read indicator m5_hsize[1:0] input ahb transfer size m5_hburst[2:0] input ahb burst length m5_haddr[31:0] input ahb address m5_hwdata[31:0] input ahb write data m5_hready_out output ahb transfer done out m5_hrdata[31:0] output ahb read data m5_hresp0 output ahb transfer response multi-layer ahb slave port 1 s1_hmastlock output ahb locked transfer s1_hmaster[3:0] output ahb master table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-36 freescale semiconductor s1_htrans[1:0] output ahb transfer type s1_hprot[3:0] output ahb protection control s1_hwrite output ahb write/read indicator s1_hsize[1:0] output ahb transfer size s1_hburst[2:0] output ahb burst length s1_haddr[31:0] output ahb address s1_hwdata[31:0] output ahb write data s1_hrdata[31:0] input ahb read data s1_hready input transfer done s1_hresp0 input transfer response multi-layer ahb slave port 2 s2_hmastlock output ahb locked transfer s2_hmaster[3:0] output ahb master s2_htrans[1:0] output ahb transfer type s2_hprot[3:0] output ahb protection control s2_hwrite output ahb write/read indicator s2_hsize[1:0] output ahb transfer size s2_hburst[2:0] output ahb burst length s2_haddr[31:0] output ahb address s2_hwdata[31:0] output ahb write data s2_hrdata[31:0] input ahb read data s2_hready input transfer done s2_hresp0 input transfer response max specific (crossbar switch) ccm_hbusreq input external clock control module low-power bus request ccm_hgrant output low-power mode bus grant s0_ampr_sel input slave port 0 alternate master priority register select. s1_ampr_sel input slave port 1 alternate master priority register select. s2_ampr_sel input slave port 2 alternate master priority register select. ip bus #1 (a) ipsa_module_en[31:1] output ip bus ?a? module select ipsa_addr[11:0] output ip bus ?a? address table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-37 ipsa_wdata[31:0] output ip bus ?a? write data ipsa_byte_31_24 output ip bus ?a? byte select ipsa_byte_23_16 output ip bus ?a? byte select ipsa_byte_15:8 output ip bus ?a? byte select ipsa_byte_7_0 output ip bus ?a? byte select ipsa_rwb output ip bus ?a? read/write indicator ipsa_supervisor_access output ip bus ?a? supervisor mode access control ipsa_rdata[31:0] input ip bus ?a? read data ipsa_xfr_wait input ip bus ?a? transfer wait state indicator ipsa_xfr_err input ip bus ?a? transfer error indicator ip bus #2 (b) ipsb_module_en[17:1] output ip bus ?b? module select ipsb_addr[11:0] output ip bus ?b? address ipsb_wdata[31:0] output ip bus ?b? write data ipsb_byte_31_24 output ip bus ?b? byte select ipsb_byte_23_16 output ip bus ?b? byte select ipsb_byte_15:8 output ip bus ?b? byte select ipsb_byte_7_0 output ip bus ?b? byte select ipsb_rwb output ip bus ?b? read/write indicator ipsb_supervisor_access output ip bus ?b? supervisor mode access control ipsb_rdata[31:0] input ip bus ?b? read data ipsb_xfr_wait input ip bus ?b? transfer wait state indicator ipsb_xfr_err input ip bus ?b? transfer error indicator etm/etb etm_traceclk output etm trace clock etm_clkdivtwoen output etm half rate clocking mode etm_dbgrq output debug request. etm_etmen output etm enabled etm_pipestat[2:0] output pipeline status etm_tracepkt[15:0] output etm trace packet etm_tracesync output trace synchronization. etm_portsize[2:0] output etm port size. table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-38 freescale semiconductor etm_portmode[1:0] output normal, multiplexed, or demultiplexed mode of operation etb_full output etb overflow indicator etb_acqcomp output etb trace acquisition complete etm_extout output external etm outputs ect_dbgrq input debug request. etm_extin[3:0] input external etm inputs. miscellaneous aitc_rise_arb output interrupt pending, raise arbitration priority if desired a9p_mem_on input used with a9p_mem_pwr_dn to power off arm926 icache, dcache, and mmu memories a9p_mem_pwr_dn input used with a9p_mem_on to power off arm926 icache, dcache, and mmu memories a9p_int_b[63:0] input external interrupts a9p_dsm_int_holdoff input deep sleep module interrupt disable wt_en input well tie input (physical connection only) wt_en_dnw input well tie input for deep n-wells (physical connection only) platform scan test interface ipt_mode[3:0] input test mode control ipt_clk_se input clock gating cell scan enable ipt_memory_read_inhibit_int input disables memory read operations from internal memories (caches, etb) during scan testing. read data is forced to zeros when asserted. when negated, memories function normally. ipt_scan_size[1:0] input scan chain length control ipt_scan_enable input scan shift enable ipt_scan_in[66:0] input platform test serial in ipt_scan_out[66:0] output platform test serial out scan wrapper test interface ipt_wrapper_clk_in[1:0] input platform wrapper clocks [0] = clk domain [1] = hclk domain ipt_wrapper_se input scan shift enable ipt_wrapper_scan_size[1:0] input scan wrapper chain length ipt_wrapper_scan_in[23:0] input scan wrapper test serial in [2:0] = clk [11:3] = hclk table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-39 ipt_wrapper_scan_out[23:0] output scan wrapper test serial out [2:0] = clk [11:3] = hclk memory bist interface ipt_bist_fail output aggregate memory bist fail status ipt_bist_done output aggregate memory bist execution status ipt_bist_bitmap[15:0] output memory bist bitmap data out ipt_bist_sdo output memory bist bitmap serial data out ipt_bist_addr_out[17:0] output memory bist address out ipt_bist_bmdata_avail output memory bist bitmap data strobe ipt_bist_done_dcache output data cache memory bist done ipt_bist_done_etb output etb memory bist done ipt_bist_done_icache output instruction cache memory bist done ipt_bist_done_mmu output mmu memory bist done ipt_bist_done_mram output mctl ram memory bist done ipt_bist_done_mrom output mctl rom memory bist done ipt_bist_fail_dcache output data cache memory bist fail ipt_bist_fail_etb output etb memory bist fail ipt_bist_fail_icache output instruction cache memory bist fail ipt_bist_fail_mmu output mmu memory bist fail ipt_bist_fail_mram output mctl ram memory bist fail ipt_bist_config_addr_mode[2:0] input memory bist address mode selection ipt_bist_config_alt_al_en input memory bist alternate algorithm enable ipt_bist_config_aftest_en input memory bist address fault test enable ipt_bist_config_dpat_en[7:0] input memory bist data pattern enable ipt_bist_config_dret_en input memory bist data retention test enable ipt_bist_config_dsof input memory bist disable ?stop on fail? ipt_bist_config_marchc_en input memory bist marching pattern test enable ipt_bist_config_sdd_en input memory bist sdd test enable ipt_bist_config_sel_dcache input memory bist data cache engine select ipt_bist_config_sel_etb input memory bist etb engine select ipt_bist_config_sel_icache input memory bist instruction cache engine select ipt_bist_config_sel_mmu input memory bist mmu engine select table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-40 freescale semiconductor 9.13 electrical specifications this section will present timing information for all major ahbs (both internal and external) to the platform. timing information on all other signals on the platform periphery will be grouped by functionality and presented after the ahb timings. 9.13.1 conditions the timing presented in this section were derived from an arm926ej-s synthesis run using the c90lp library, worst case process, 105 o c, 1.10 v with clk running at 266 mhz. in this case, the hclk domain (all ahbs) will run at half the clk speed or 133 mhz. 9.13.2 well bias mode the timing specifications in this section do not cover the well bias mode of operation. at the present time, well bias mode is planned to be used in sleep mode only. that is, clk and hclk will be stopped and the platform buses will be inactive. however, the negati on of the a9p_clock_off output when an interrupt is asserted is still required in order for the external clock control module to exit sleep mode and turn on the clocks. the delay for the a9p_int_b[61:0] to a9p_cloc k_off path will be affected by well bias mode, but not significantly so. 9.13.2.1 functional operation in well bias mode programmable options should be used to support laborator y testing of the platform in well bias mode. the platform?s ac performance will be impacted (slower) when well biasing is enabled and is tbd. care ipt_bist_config_sel_mram input memory bist mctl ram engine select ipt_bist_config_sel_mrom input memory bist mctl rom engine select ipt_bist_config_usrctrl_bm input memory bist user controlled parallel bitmap output rate ipt_bist_invoke input memory bist invoke ipt_bist_mode[2:0] input memory bist mode select ipt_bist_release input memory bist pause state release ipt_bist_repdata_out_en input memory bist repair data output enable ipt_bist_reset input memory bist reset ipt_bist_retention_en input memory bist retention enable ipt_bist_sdi input memory bist serial data in ipt_bist_serial_data_en input memory bist serial data enable ipt_bist_shift_clk input memory bist shift clock table 9-8. arm9 platform signal list (continued) signal type description arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-41 should be taken to identify external interfaces which may not be running in well bias mode as clock insertion and clock skew differ ences may prevent proper operation. 9.13.3 clk and jtag_tck relationship the jtag_tck clock input must always be less than 1/8 th e frequency of the clk clock input. this constraint is due to the jtag synchronization logic in the clkctl module. during the execution of low-power code, the frequency of clk is dynamic, and therefore care should be taken that jtag_tck is always less than 1/8 the frequency of clk at any given instant. to maximize throughput via the jtag port when uploa ding/downloading code or memory images, it is suggested the debugger enter debug mode directly out of reset with clk and jtag_tck running as fast as possible. however, once normal mode low-power code execution begins, the jtag_tck frequency should be set to be 1/8 the frequency of the lowest possible clk frequency. 9.13.4 clocks and reset timing table 9-9 and figure 9-10 are valid for all ahb interfaces on the arm9 platform. the same clock insertion delay and hreset_b negation timing will be used for all modules on the arm9 platform. table 9-9. arm9 platform ahb cloc k and reset timing constraints description delay clk_root period 3.75 ns (266 mhz) clk_root jitter (3% rounded up) 115.0 ps hclk_root period 7.5 ns (133 mhz) hclk_root jitter (3% rounded up) 230.0 ps clk_root to clk and hclk_root to hclk insertion delay (t insert ) 1.60 +/- 0.100 ns clk and hclk uncertainty 200 ps hreset_b hold time to hclk_leaf (t ihrst )1.80 ns hreset_b setup time to hclk_leaf (t isrst )1.60 ns hclken setup time to clk_leaf (t isclken )2.00 ns hclken hold time to clk_leaf (t ihclken )0.00 ns arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-42 freescale semiconductor figure 9-10. arm9 platform ahb cl ock and reset ti ming relationship 9.13.5 alternate bus master (abm) interface timing table 9-10 shows the loading constraints used on all arm9 platform alternate bus master bus interfaces. the timing parameters in figure 9-11 reflect these constraints. the alternate bus master signals are designated by the ?mx_? prefix attached to the normal ahb naming convention. table 9-10. alternate bus master constraints description value all output loading 0.50 pf input transition time (platform boundary) 0.750 ns (20/80) hclk_leaf hreset_b t ihrst t isrst hclk_root t insert clk_root clk_leaf hclken t isclken arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-43 figure 9-11. alternate bus master timing parameters hclk_leaf mx_htrans[1:0] t ihtr t istr mx_haddr[31:0] t iha t isa address transfer type t ihctl t isctl transfer control mx_hwrite t ihwd t iswd mx_hwdata[31:0] write data (a) read data (a) t ovrd t ohrd mx_hrdata[31:0] ok t ovrsp t ohrsp mx_hresp[1:0] mx_hprot[3:0] mx_hburst[3:0] mx_hlock hclk_root t insert mx_hmastlock mx_hmaster mx_hready_out t ovrdyo t ohrdyo mx_hsize[2:0] arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-44 freescale semiconductor 9.13.6 secondary ahb timing table 9-12 shows the loading constraints used on all arm9 platform secondary ahb interfaces. the timing parameters in figure 9-13 reflect these constraints. the constraints and ac parameters are valid for all 3 of the platform?s secondary ahbs. the seconda ry ahb signals are designated by the ?sx_? prefix attached to the norma l ahb naming convention. table 9-11. alternate bus master interface ac timing parameters description parameter timing (ns) hclk_leaf minimum clock period including jitter t clk 7.27 mx_hmaster/mx_htrans/mx_hprot/mx_hlock/mx_hmastlock/m x_hmaster transfer type setup time before hclk_leaf t istr 6.23 mx_hmaster/mx_htrans/mx_hprot/mx_hlock/mx_hmastlock/ mx_hmaster transfer type hold time after hclk_leaf t ihtr >0 mx_haddr[31:0] address setup time before hclk_leaf t isa 6.23 mx_haddr[31:0] address hold time after hclk_leaf t iha >0 mx_hwrite/mx_hsize/mx_hburst control signal setup time before hclk_leaf t isctl 6.23 mx_hwrite/mx_hsize/mx_hburst control signal hold time after hclk_leaf t ihctl >0 mx_hwdata write data setup time before hclk_leaf t iswd 6.00 mx_hwdata write data hold time after hclk_leaf t ihwd >0 mx_hready_out ready out valid time after hclk_leaf t ovrdyo 4.80 mx_hready_out ready out hold time after hclk_leaf t ohrdyo >0 mx_hrdata read data valid time after hclk_leaf t ovrd 6.00 mx_hrdata read data hold time after hclk_leaf t ohrd >0 mx_hresp0 valid time after hclk_leaf t ovrsp 6.00 mx_hresp0 hold time after hclk_leaf t ohrsp >0 table 9-12. secondary ahb constraints description value sx_haddr, sx_hwdata loading 0.50 pf all other output loading 0.50 pf input transition time (at platform boundary) 0.75 ns (20/80) arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-45 figure 9-12. secondary ahb ac timing parameters table 9-13. secondary ahb ac timing parameters description parameter timing (ns) hclk_leaf minimum clock period including jitter t clk 7.27 sx_htrans/sx_hprot/sx_hmastlock/sx_hmaster transfer type valid time after hclk_leaf t ovtr 5.00 hclk_leaf sx_htrans[1:0] t ohtr t ovtr sx_haddr[31:0] t oha t ova address transfer type sx_hsize[1:0] t ohctl t ovctl transfer control sx_hwrite t ohwd t ovwd sx_hwdata[31:0] write data (a) read data (a) t isrd t ihrd sx_hrdata[31:0] sx_hready t isrdy t ihrdy ok t isrsp t ihrsp sx_hresp0 sx_hprot[3:0] sx_hmastlock sx_hburst[3:0] hclk_root t insert sx_hmaster[3:0] arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-46 freescale semiconductor 9.13.7 ram and rom interface timing table 9-14 shows the loading constraints used when generating timing parameters on the arm9 platform?s ram and rom interfaces. external ram and rom interface signals not shown in the table below are either static or test related. sx_htrans/sx_hprot/sx_hmastlock/sx_hmaster transfer type hold time after hclk_leaf t ohtr >0 sx_haddr[31:0] address valid time after hclk_leaf t ova 4.30 sx_haddr[31:0] address hold time after hclk_leaf t oha >0 sx_hwrite/sx_hsize/sx_hburst control signal valid time after hclk_leaf t ovctl 5.70 sx_hwrite/sx_hsize/sx_hburst control signal hold time after hclk_leaf t ohctl >0 sx_hwdata write data valid time after hclk_leaf t ovwd 5.70 sx_hwdata write data hold time after hclk_leaf t ohwd >0 sx_hready setup time before hclk_leaf (input to slaves) t isrdy 5.60 sx_hready hold time after hclk_leaf t ihrdy >0 sx_hrdata setup time before hclk_leaf t isrd 4.10 sx_hrdata hold time after hclk_leaf t ihrd >0 sx_hresp0 setup time before hclk_leaf t isrsp 4.10 sx_hresp0 hold time after hclk_leaf t ihrsp >0 table 9-14. ram and rom interface loading constraints signal type constraint ram mctl_oen_ram output 0.50 pf mctl_ce_ram_b output 0.25 pf mctl_wr_ram_b output 0.50 pf mctl_addr_ram[17:0] output 0.50 pf mctl_ben_ram_*_* output 0.50 pf mctl_d_ram[31:0] output 0.50 pf mem_q_ram[31:0] input 0.75 ns (input transition time) rom mctl_ce_rom_b output 0.25 pf table 9-13. secondary ahb ac timing parameters (continued) description parameter timing (ns) arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 9-47 figure 9-13. ram and rom interface ac timing parameters mctl_addr_rom[19:0] output 0.50 pf mem_q_rom[31:0] input 0.75 ns (input transition time) table 9-15. ram and rom interface ac timing parameters description parameter timing (ns) hclk_leaf minimum clock period t clk 8.40 ram mctl_addr_ram valid time after hclk_leaf t ovaram 6.65 table 9-14. ram and rom interface loading constraints (continued) signal type constraint hclk_leaf t ovdram t ovcram mctl_d_ram[31:0] mctl_ce_ram_b mctl_addr_ram[17:0] mctl_wr_ram_b mctl_ben_ram mem_q_ram[31:0] mem_q_rom[31:0] t ovwram t ovbram t ovarom t isqram t isqrom t ovaram mctl_addr_rom[19:0] mctl_ce_rom_b t ovcrom hclk arm9 platform MCIMX27 multimedia applications processor reference manual, rev. 0.2 9-48 freescale semiconductor mctl_d_ram valid time after hclk_leaf t ovdram 6.60 mctl_ce_ram_b valid time after hclk_leaf t ovcram 6.70 mctl_wr_ram_b valid time after hclk_leaf t ovwram 6.55 mctl_ben_ram_*_* valid time after hclk_leaf t ovbram 6.6 mem_q_ram setup time before hclk_leaf t isqram 4.65 mem_q_ram hold time after hclk_leaf t ihqram >0 rom mctl_addr_rom valid time after hclk_leaf t ovarom 6.55 mctl_ce_rom_b valid time after hclk_leaf t ovcrom 6.80 mem_q_rom setup time before hclk_leaf t isqrom 3.85 mem_q_rom hold time after hclk_leaf t ihqrom >0 table 9-15. ram and rom interface ac timing parameters (continued) description parameter timing (ns) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-1 chapter 10 arm926ej-s interrupt controller (aitc) the arm926ej-s interrupt controller (aitc) is a 32-b it peripheral that collects interrupt requests from up to 64 sources, and provides an interface to the arm926ej-s core. the aitc includes software-controlled priority levels for normal interrupts. figure 10-1 shows the simplified block diagram of the aitc. figure 10-1. aitc block diagram 10.1 overview the aitc consists of a set of control registers a nd associated logic to perform interrupt masking, and priority support of normal interrupt s. interrupt source registers (intsrch/intsrcl) are a pair of 32-bit status registers with a single interrupt source associated with each of the 64 bits. an interrupt line or set of interrupt lines are routed from each interrupt source to the intsrch or intsrcl register. this allows up to 64 distinct interrupt sources in an implementation. priority encoder 6 64 32 haddr nivector nm equals to 0x0000_0018? opcode generator aitc_rdata 32 priority encoder 6 64 fivector fipend nipend force 64 64 64 64 64 aitc_rdata_ovr intin inttype intenable aitc_irq aitc_fiq equals to 0x0000_001c? fm software hready arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-2 freescale semiconductor 10.1.1 features 10.1.2 modes of operation interrupt requests may be forced to be asse rted by way of the interrupt force registers (intfrch/intfrcl). each bit in this register is logically ?or-ed? with the corresponding hardware request line prior to feeding the intsrch or intsrc l register inputs. there is a corresponding set of interrupt enable registers (intenableh/intenablel), also 32-bits wide which allow individual bit masking of the intsrch/intsrcl registers. there is also a corresponding set of interrupt type register (inttypeh/inttypel), which selects whether an interrupt source will generate a normal or fast interrupt to the arm926ej-s core. there is a corresponding set of normal interrupt pe nding registers (nipndh/nipndl) which indicate pending normal interrupt requests. these registers are e quivalent to the logical and of the interrupt source registers (intsrch/intsrcl), the interrupt en able registers (intenableh/intenablel), and the not of the interrupt type registers (inttypeh/inttypel). (refer to figure 10-1 ) the nipndh/nipndl register bits are bit-wise ?nor-ed? together to form the nirq signal routed to the arm926ej-s core. this core input signal is maskable by the normal interrupt disable bit (i bit) in the processor status register (cpsr). the normal interrupt vector register (nivecsr) indicates the vector index of highest priority pending normal interrupt. there is a corresponding set of fast interrupt pendi ng registers (fipndh/fipndl ) which indicate pending fast interrupt requests. these registers are equivale nt to logical and of interrupt source registers (intsrch/intsrcl), interrupt enable register s (intenableh/intenablel), and interrupt type registers (inttypeh/inttypel). (refer to figure 10-1 ) fipndh/fipndl register bits are bit-wise ?nor-ed? together to form the nfiq signal routed to the arm926ej-s core. this core input signal is maskable by the fast interrupt disable bit (f bit) in the cpsr. the fast interrupt vector register (fivecsr) indicates the vector index of highe st priority pending fast interrupt. aitc supports two vector table modes: high memory and low memory. if aitc is in high memory vector table mode, opcode is ?ldr pc, [pc,#-(288-4*(vector i ndex)]?. this causes arm926-es core to load the program counter (pc) with a vector from a table of 64 vectors located at 0xffff_ff00 to 0xffff_ffff; more specifically the pc is loaded with the vect or located at 0xffff_ff00 + 4*(vector index). if aitc is in low memory vector table m ode, this opcode is ?ldr pc, [pc, #((table pointer)+4*(vector index) ?32]?. this causes the arm926-ejs core to load the pc with a vector from a table of 64 vectors beginning at (table pointer) and ending at (table pointer)+0xff; mo re specifically the pc is loaded with the vector located at (table pointer) + 4*(vector index). this hardware mechanism al leviates the need for software to determine which interrupt source caused the interrupt to be asserted. all interrupt controller registers can be read and written during privileged mode only. writes attempted to read-only registers will be ignored. these registers can be only modified using 32-bit writes. intfrch/intfrcl registers are provided for software generation of interrupts. by enabling inte rrupts for these bit positions, software can force an interrupt request. this register can also be used to debug hardware interrupt service routines by providing an alternate method of interrupt a ssertion. the interrupt requests are prioritized in the following sequence: 1. fast interrupt requests, in order of highest number 2. normal interrupt requests, in order of highest priority level, then highest source number with the same priority arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-3 aitc provides 16 software controlled priority levels for normal interrupt s. every interrupt can be placed in any priority level. the aitc also provides a nor mal interrupt priority level mask (nimask) which disables any interrupt with a priority level lower th an or equal to the mask. if a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be selected assuming that nimask has not disabled level 1 norma l interrupts. if two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number will be selected, also assuming that nimask has not di sabled level 1 normal interrupts. 10.2 memory map and register definition aitc module has 26 registers. all of these registers are single cycle access as the aitc sits on the native bus of the arm926ej-s core. this section provides the detailed descriptions for a ll of the aitc registers. 10.2.1 memory map table 10-1 shows the aitc memory map. table 10-1. aitc memory map address register access reset value section/page general registers 0x1004_0000 (intcntl) interrupt control register r/w 0x0000_0000 10.2.3/10-8 0x1004_0004 (nimask) normal interrupt mask register r/w 0x0000_001f 10.2.4/10-10 0x1004_0008 (intennum) interrupt enable number register r/w 0x0000_0000 10.2.5/10-11 0x1004_000c (intdisnum) interrupt disable number register r/w 0x0000_0000 10.2.6/10-11 0x1004_0010 (intenableh) interrupt enable register high r/w 0x0000_0000 10.2.7/10-12 0x1004_0014 (intenablel) interrupt enable register low r/w 0x0000_0000 10.2.7/10-12 0x1004_0018 (inttypeh) interrupt type register high r/w 0x0000_0000 10.2.8/10-13 0x1004_001c (inttypel) interrupt type register low r/w 0x0000_0000 10.2.8/10-13 0x1004_0020 (nipriority7) normal interrupt priority level register 7 r/w 0x0000_0000 10.2.9/10-14 0x1004_0024 (nipriority6) normal interrupt priority level register 6 r/w 0x0000_0000 10.2.9/10-14 0x1004_0028 (nipriority5) normal interrupt priority level register 5 r/w 0x0000_0000 10.2.9/10-14 0x1004_002c (nipriority4) normal interrupt priority level register 4 r/w 0x0000_0000 10.2.9/10-14 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-4 freescale semiconductor 10.2.2 register summary figure 10-2 shows the key to the register fields and table 10-2 shows the register figure conventions. 0x1004_0030 (nipriority3) normal interrupt priority level register 3 r/w 0x0000_0000 10.2.9/10-14 0x1004_0034 (nipriority2) normal interrupt priority level register 2 r/w 0x0000_0000 10.2.9/10-14 0x1004_0038 (nipriority1) normal interrupt priority level register 1 r/w 0x0000_0000 10.2.9/10-14 0x1004_003c (nipriority0) normal interrupt priority level register 0 r/w 0x0000_0000 10.2.9/10-14 0x1004_0040 (nivecsr) normal interrupt vector and status register r 0xffff_ffff 10.2.10/10-22 0x1004_0044 (fivecsr) fast interrupt vector and status register r 0xffff_ffff 10.2.11/10-23 0x1004_0048 (intsrch) interrupt source register high r 0x0000_0000 10.2.12/10-24 0x1004_004c (intsrcl) interrupt source register low r 0x0000_0000 10.2.12/10-24 0x1004_0050 (intfrch) interrupt force register high r/w 0x0000_0000 10.2.13/10-27 0x1004_0054 (intfrcl) interrupt force register low r/w 0x0000_0000 10.2.13/10-27 0x1004_0058 (nipndh) normal interrupt pending register high r 0x0000_0000 10.2.14/10-28 0x1004_005c (nipndl) normal interrupt pending register high r 0x0000_0000 10.2.14/10-28 0x1004_0060 (fipndh) fast interrupt pending register high r 0x0000_0000 10.2.15/10-29 0x1004_0064 (fipndl) fast interrupt pending register low r 0x0000_0000 10.2.15/10-29 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write-only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 10-2. key to register fields table 10-1. aitc memory map (continued) address register access reset value section/page arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-5 table 10-3 shows the aitc register summary. table 10-2. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 10-3. aitc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1004_0000 (intcntl) r000000000 nidi s fidi s nia d fia d 0 0 md w r0000 pointer 00 w 0x1004_0004 (nimask) r00000000000000 00 w r00000000000 nimask w 0x1004_0008 (intennum) r00000000000000 00 w r00000000000000 00 w ennum arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-6 freescale semiconductor 0x1004_000c (intdisnum) r00000000000000 00 w r00000000000000 00 w disnum 0x1004_0010 (intenableh) r intenable[63:48] w r intenable[47:32] w 0x1004_0014 (intenablel) r intenable[31:16] w r intenable[15:0]] w 0x1004_0018 (inttypeh) r inttype[63:48] w r inttype[47:32] w 0x1004_001c (inttypel) r inttype[31:16] w r inttype[16:0] w 0x1004_0020 (nipriority7) r nipr63 nipr62 nipr61 nipr60 w r nipr59 nipr58 nipr57 nipr56 w 0x1004_0024 (nipriority6) r nipr55 nipr54 nipr53 nipr52 w r nipr51 nipr50 nipr49 nipr48 w 0x1004_0028 (nipriority5) r nipr47 nipr46 nipr45 nipr44 w r nipr43 nipr42 nipr41 nipr40 w table 10-3. aitc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-7 0x1004_002c (nipriority4) r nipr39 nipr38 nipr37 nipr36 w r nipr35 nipr34 nipr33 nipr32 w 0x1004_0030 (nipriority3) r nipr31 nipr30 nipr29 nipr28 w r nipr27 nipr26 nipr25 nipr24 w 0x1004_0034 (nipriority2) r nipr23 nipr22 nipr21 nipr20 w r nipr19 nipr18 nipr17 nipr16 w 0x1004_0038 (nipriority1) r nipr15 nipr14 nipr13 nipr12 w r nipr11 nipr10 nipr9 nipr8 w 0x1004_003c (nipriority0) r nipr7 nipr6 nipr5 nipr4 w r nipr3 nipr2 nipr1 nipr0 w 0x1004_0040 (nivecsr) r nivector w rniprilvl w 0x1004_0044 (fivecsr) r fivector w r fivector w 0x1004_0048 (intsrch) r intin[63:48] w r intin[48:32] w table 10-3. aitc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-8 freescale semiconductor 10.2.3 interrupt control register (intcntl) intcntl controls the interrupts in aitc. both normal a nd fast interrupts can be enabled to jump directly to the interrupt service routine. for fast interrupts, it may be faster to begin to fast interrupt routine at 0x1004_004c (intsrcl) r intin[31:16] w r intin[15:0] w 0x1004_0050 (intfrch) r force[63:48] w r force[47:32] w 0x1004_0054 (intfrcl) r force[31:16] w r force[15:0] w 0x1004_0058 (nipndh) r nipend[63:48] w r nipend[47:32] w 0x1004_005c (nipndl) r nipend[31:16] w r nipend[15:0] w 0x1004_0060 (fipndh) r fipend[63:48] w r fipend[47:32] w 0x1004_0064 (fipndl) r fipend[31:16] w r fipend[15:0] w table 10-3. aitc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-9 0x0000_001c instead of jumping to a service routine. the vector table can be sourced in high memory, 0xffff_ff00 to 0xffff_ffff, or in low memory. if th e vector table is located in low memory (md=1), a register has been provided to control where the vect or table is located. this register is located on the arm926ej-s native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. this register can be only modified using 32-bit writes. 0x1004_0000 (intcntl) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000 nidis fidis niad fiad 00 md w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000 pointer 00 w reset0000000000000000 figure 10-3. interrupt control register format table 10-4. interrupt control register field description field description 31?23 reserved. these bits are reserved and should read 0. 22 nidis normal interrupt disable. this bit, when set, disables the generation of the normal interrupt signal. this bit is similar to the i bit of the arm926ej-s core. this bit along with the fidis bit is used to enable secure operations. 0 does not affect the normal interrupt generation 1 disable all normal interrupts 21 fidis fast interrupt disable. this bit, when set, disables the generation of the fast interrupt signal. this bit is similar to the f bit of the arm926ej-s core. this bit along with the nidis bit is used to enable secure operations. 0 does not affect the fast interrupt generation 1 disable all fast interrupts 20 niad normal interrupt arbiter rise arm level. this bit, when asserted, increases bus arbitration priority of arm core when normal interrupt signal (nirq) is asserted. if an alternate master has ownership of the bus when a normal interrupt occurs, bus will be given back to the processor core after the dma device has completed its accesses. niad bit does not affect alternate master accesses that are in progress. to prevent an alternate master from accessing the bus during an interrupt service routine, the interrupt flag must not be cleared until the end of the service routine. another option is to use the abfen and abflag bits. 0 disregard the normal interrupt flag when evaluating bus requests 1 normal interrupt flag increases bus arbitration priority of the arm core to decrease the latency of interrupt service routine 19 fiad fast interrupt arbiter rise arm level. this bit functions same as niad bit except for the fast interrupts (nfiq). 0 disregard the fast interrupt flag when evaluating bus requests 1 fast interrupt flag increases bus arbitration priority of the arm core to decrease the latency of interrupt service routine. 18?17 reserved. these bits are reserved and should read 0. 16 md interrupt vector table mode. indicates whether the interrupt vector is located in high memory or low memory. 0 interrupt vector table located in high memory from 0xffff_ff00 to 0xffff_ffff 1 interrupt vector table located in low memory from pointer to pointer+0xff arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-10 freescale semiconductor 10.2.4 normal interrupt mask register (nimask) nimask controls the normal interrupt mask level. a ll normal interrupts with a priority level lower than or equal to nimask are disabled. the priority le vel of normal interrupts ar e determined by the normal interrupt priority level registers (nipriority7?0). reset state of th is register does not disable any normal interrupts. writing all 1?s, or ?1, to nimask sets normal interrupt mask to ?1 which does not disable any normal interrupt priority levels. this ha rdware mechanism can be used to create reentrant normal interrupt routines by disabling lower prior ity normal interrupts. refer section 10.3.6 for more details on use of nimask register. this register is located on the arm926ej-s native bus, accessible in 1 cycle, and can only be accessed to in privileged m ode. this register can be only modified using 32-bit writes. 15?12 reserved. these bits are reserved and should read 0. 11?2 pointer interrupt vector table pointer. indicates start of vector table when in low memory ( md =1). only word-aligned tables are allowed, and 2 zeros are added in the lsbs when this value is used by aitc. the value stored here is left shifted by 2 bits, so the actual table vector can be directly written into the appropriate bits. the value stored in 10 bits, times 4, must be set greater than or equal to 0x0000_0024 and less than or equal to 0x0000_0f00. 1?0 reserved. these bits are reserved and should read 0. address 0x1004_0004 (nimask) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000000 nimask w reset0000000000011111 figure 10-4. normal interrupt mask register format table 10-5. normal interrupt mask register field description field description 31?5 reserved. these bits are reserved and should read 0. 4?0 nimask normal interrupt mask. controls normal interrupt mask level. all normal interrupts of priority level lower than or equal to the nimask will be disabled. 0 disable priority level 0 normal interrupts 1 disable priority level 1 and lower normal interrupts ... 0xe (14)disable priority level 14 and lower normal interrupts 0xf (15)disable all normal interrupts 0x10?0x1fdo not disable any normal interrupts table 10-4. interrupt control register field description (continued) field description arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-11 10.2.5 interrupt enable nu mber register (intennum) the interrupt enable number register provides hardwa re accelerated enabling of interrupts. any write to this register enables an interrupt source. if 6 lsbs are 000000, then interrupt source 0 is enabled. if 6 lsbs are 000001, then interrupt source 1 is enabled. and so fort h. this register is decoded into a one hot mask that is logically or-ed with intenableh/intenablel register. this hardware mechanism alleviates the need for an atomic read/modify/write sequence to enable an interrupt source. to enable interrupts 10 and 20, software only preforms two writes to aitc : first write 10 to intennum register, then write 20 to intennum register (order of writes is irrelevant). this register is located on the arm926ej-s native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. this register can be only modified using 32-bit writes. this register always reads back all 0s. 10.2.6 interrupt disable numb er register (intdisnum) the interrupt disable number register provides hardwa re accelerated disabling of interrupts. any write to this register disables one interrupt source. if the 6 lsbs are equal 000000, then interrupt source 0 is disabled. if the 6 lsbs equal 000001, then interrupt sour ce 1 is disabled, and so on. this register is decoded into a one hot mask which is inverted and logically and-ed with the intenableh/intenablel register. the hardware mech anism alleviates the need for an atomic read/modify/write sequence to disable an interrupt source. to disable interrupts 10 and 20, the software need only preform two writes to the aitc: first write 10 to intdisnum register, then write 20 to intdisnum register (the order of the writes is irrele vant). this register is located on the arm926ej-s address 0x1004_0008 (intennum) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000000000 w ennum reset0000000000000000 figure 10-5. interrupt enable number register format table 10-6. interrupt enable number register description field description 31?6 reserved. these bits are reserved and should read 0. 5?0 ennum interrupt enable number. writing to this register will enable the interrupt source associated with this value. 0 enable interrupt source 0 1 enable interrupt source 1 ... 63 enable interrupt source 63 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-12 freescale semiconductor native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. this register can be only modified using 32-bit writes. this register always reads back all 0s. 10.2.7 interrupt enable regist er high (intenableh) and low (intenablel) the intenableh and intenablel registers are used to enable pending interrupt requests to the arm9 core. each bit in these registers corresponds to an interrupt source available in the system. the reset state of these registers are to have all interrupt s masked. these registers can be updated by various methods: writing directly to intenableh/intenab lel registers, setting bits in the intennum register, or clearing bits in the intdisnum regist er. these registers are located on the arm926ej-s native bus, accessible in 1 cycle, and can only be acce ssed to in privileged mode. these registers can be only modified using 32-bit writes. address 0x1004_000c (intdisnum) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000000000 w disnum reset0000000000000000 figure 10-6. interrupt enable number register format table 10-7. interrupt disable number register field description field description 31?6 reserved. these bits are reserved and should read 0. 5?0 disnum interrupt disable number. writing to this register will disable the interrupt source associated with this value. 0 disable interrupt source 0 1 disable interrupt source 1 ... 63 disable interrupt source 63 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-13 10.2.8 interrupt type register high (inttypeh) and low (inttypel) the inttypeh and inttypel registers are used to select whether a pending interrupt source, when enabled with the intenableh/intenablel, will create a normal interrupt or a fast interrupt to the arm9 core. each bit in these registers corresponds to an interrupt source available in the system. the reset state of these registers will cause all enabled interrupt sources to generate a normal interrupt. these registers are located on the arm926ej-s native bus, acce ssible in 1 cycle, and can only be accessed to in privileged mode. these registers can be only modified using 32-bit writes. address 0x1004_0010 (intenableh) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r intenable[63:48] w rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r intenable[47:32] w rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm reset0000000000000000 figure 10-7. interrupt enable register high format address 0x1004_0014 (intenablel) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r intenable[31:16] w rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r intenable[15:0] w rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm rwm reset0000000000000000 figure 10-8. interrupt enable register low format table 10-8. interrupt enable register low and high field descriptions field description 31?0 intenable interrupt enable. this bit enables the corresponding interrupt source to request a normal interrupt or a fast interrupt. a reset operation clears this bit. if an enable bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a normal or a fast interrupt request depending on associated inttypeh/inttypel setting. 0 interrupt disabled 1 interrupt enabled and will generate a normal or fast interrupt upon assertion arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-14 freescale semiconductor 10.2.9 normal interrupt priority level registers (nipriority n ) the normal interrupt priority level registers (nipriority7?0) provide a software controllable prioritization of normal interrupts. normal interrupts with a higher priority level will preempt normal interrupts with a lower priority. the reset state of thes e registers forces all normal interrupts to the lowest priority level. if a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be selected assuming that nimask has not disabled level 1 normal interrupts. if two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number will be selected, also assuming that nimask has not disabled level 1 normal interrupts. these registers can only be accessed to in privileged mode using 32-bit writes. address 0x1004_0018 (inttypeh) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r inttype[63:48] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r inttype[47:32] w reset0000000000000000 figure 10-9. interrupt type register high format address 0x1004_001c (inttypel) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r inttype[31:16] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r inttype[15:0] w reset0000000000000000 figure 10-10. interrupt type register low format table 10-9. interrupt type register high and low register description field description 31?0 inttype interrupt type. this bit indicates whether the corresponding interrupt source will request a normal interrupt or a fast interrupt. if inttype bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a fast interrupt request. 0 interrupt source will generate a normal interrupt (nirq). 1 interrupt source will generate a fast interrupt (nfiq). arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-15 address 0x1004_0020 (nipriority7) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr63 nipr62 nipr61 nipr60 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr59 nipr58 nipr57 nipr56 w reset0000000000000000 figure 10-11. normal interrupt priority level 7 register format table 10-10. normal interrupt priority level register 7 field description bits field description 31?28 nipr63 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr62 23?20 nipr61 19?16 nipr60 15?12 nipr59 11?8 nipr58 7?4 nipr57 3?0 nipr56 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-16 freescale semiconductor address 0x1004_0024 (nipriority6) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr55 nipr54 nipr53 nipr52 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr51 nipr50 nipr49 nipr48 w reset0000000000000000 figure 10-12. normal interrupt priority level 6 register format table 10-11. normal interrupt priority level register 6 field description field description 31?28 nipr55 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr54 23?20 nipr53 19?16 nipr52 15?12 nipr51 11?8 nipr50 7?4 nipr49 3?0 nipr48 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-17 address 0x1004_0028 (nipriority5) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr47 nipr46 nipr45 nipr44 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr43 nipr42 nipr41 nipr40 w reset0000000000000000 figure 10-13. normal interrupt priority level 5 register format table 10-12. normal interrupt priority level register 5 field description field description 31?28 nipr47 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr46 23?20 nipr45 19?16 nipr44 15?12 nipr43 11?8 nipr42 7?4 nipr41 3?0 nipr40 address 0x1004_002c (nipriority4) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr39 nipr38 nipr37 nipr36 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr35 nipr34 nipr33 nipr32 w reset0000000000000000 figure 10-14. normal interrupt priority level 4 register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-18 freescale semiconductor table 10-13. normal interrupt priority level register 4 field description field description 31?28 nipr39 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr38 23?20 nipr37 19?16 nipr36 15?12 nipr35 11?8 nipr34 7?4 nipr33 3?0 nipr32 address 0x1004_0030 (nipriority3) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr31 nipr30 nipr29 nipr28 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr27 nipr26 nipr25 nipr24 w reset0000000000000000 figure 10-15. normal interrupt priority level 3 register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-19 table 10-14. normal interrupt priority level register 3 field description field description 31?28 nipr31 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr30 23?20 nipr29 19?16 nipr28 15?12 nipr27 11?8 nipr26 7?4 nipr25 3?0 nipr24 address 0x1004_0034 (nipriority2) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr23 nipr22 nipr21 nipr20 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr19 nipr18 nipr17 nipr16 w reset0000000000000000 figure 10-16. normal interrupt priority level 2 register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-20 freescale semiconductor table 10-15. normal interrupt priority level register 2 field description bits field description 31?28 nipr23 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr22 23?20 nipr21 19?16 nipr20 15?12 nipr19 11?8 nipr18 7?4 nipr17 3?0 nipr16 address 0x1004_0038 (nipriority1) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr15 nipr14 nipr13 nipr12 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr11 nipr10 nipr9 nipr8 w reset0000000000000000 figure 10-17. normal interrupt priority level 1 register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-21 table 10-16. normal interrupt priority level register 1 field description field description 31?28 nipr15 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr14 23?20 nipr13 19?16 nipr12 15?12 nipr11 11?8 nipr10 7?4 nipr9 3?0 nipr8 address 0x1004_003c (nipriority0) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipr7 nipr6 nipr5 nipr4 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipr3 nipr2 nipr1 nipr0 w reset0000000000000000 figure 10-18. normal interrupt priority level 1 register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-22 freescale semiconductor 10.2.10 normal interrupt vector and status register (nivecsr) the nivecsr register displays the priority of th e highest pending normal interrupt and also provides vector index of the interrupt?s service routine. this num ber can be used directly as an index into a vector table to select the highest pending nor mal interrupt source. this read-onl y register can only be accessed to in privileged mode. table 10-17. normal interrupt priority level register 0 field description bits field description 31?28 nipr7 normal interrupt priority level. selects the software controlled priority level for the associated normal interrupt source. these registers do not affect the prioritization of fast interrupt priorities. 0 lowest priority normal interrupt ... 15 highest priority normal interrupt 27?24 nipr6 23?20 nipr5 19?16 nipr4 15?12 nipr3 11?8 nipr2 7?4 nipr1 3?0 nipr0 address 0x1004_0040 (nivecsr) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nivector w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rniprilvl w reset0000000000000000 figure 10-19. normal interrupt vector and status register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-23 10.2.11 fast interrupt vector and status register (fivecsr) fivecsr provides the vector index for highest priority active fast inte rrupt?s service routine (higher the source number of fast interrupt, higher will be the priority level). this hardware mechanism replaces the previous necessity for core support of the ff1 comma nd. this number can be directly used as an index into a vector table to select the highest pending fast interrupt source. this read-only register is located on the arm926ej-s native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. table 10-18. normal interrupt vector and status register field description field description 31?16 nivector normal interrupt vector. indicates vector index for the highest pending normal interrupt. ?1 no normal interrupt request pending 0 interrupt 0 highest priority pending normal interrupt 1 interrupt 1 highest priority pending normal interrupt ... 63 interrupt 63 highest priority pending normal interrupt 64+ (not ?1)unused, will not occur 15?0 niprilvl normal interrupt priority level. indicates priority level of highest priority normal interrupt. this number can be written to nimask to disable current priority normal interrupts to build a reentrant normal interrupt system. ?1 no normal interrupt request pending 0 highest priority normal interrupt is level 0 1 highest priority normal interrupt is level 1 ... 15 highest priority normal interrupt is level 15 16+ (not ?1)unused, will not occur address 0x1004_0044 (fivecsr) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fivector[31:16] w reset1111111111111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fivector[15:0] w reset1111111111111111 figure 10-20. fast interrupt vector and status register format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-24 freescale semiconductor 10.2.12 interrupt source register high (intsrch) and low (intsrcl) intsrch and intsrcl are both 32-bits wide. intsrch and intsrcl reflect the status of all interrupt request inputs into the interrupt controller. unused bit positions always read zero (no request pending). the state of this register out of rese t is determined by the peripheral circ uits generating the requests; normally, the requests would be inactive. these read-only registers can only be accessed in privileged mode and can only accessed with 32-bit reads. table 10-19. fast interrupt vector and status register description field description 31?0 fivector fast interrupt vector. indicates vector index for the highest pending fast interrupt. ?1 no fast interrupt request pending (?1 is defined as all bits in the field are set to 1.) 0 interrupt 0 highest pending fast interrupt 1 interrupt 1 highest pending fast interrupt ... 63 interrupt 63 highest pending fast interrupt 64+ (not ?1)unused, will not occur address 0x1004_0048 (intsrch) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r intin[63:48] w reset 1 1 the state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the request s would be inactive. 0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r intin[47:32] w reset 1 0000000000000000 figure 10-21. interrupt source register high format address 0x1004_004c (intsrcl) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r intin[31:16] w reset 1 0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r intin[15:0] w reset 1 0000000000000000 figure 10-22. interrupt source register high format arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-25 10.2.12.1 interrupt assignments high 1 the state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the request s would be inactive. table 10-20. interrupt source register high and low description field description 31?0 intin interrupt source. indicates the state of the corresponding hardware interrupt source. 0 interrupt source negated 1 interrupt source asserted table 10-21. interrupt source high (intsrch) assignment name bit interrupt source module notes int_dptc bit 31 dynamic process temperature compensate (dptc) int_iim bit 30 ic identify module (iim) int_lcdc bit 29 lcd controller (lcdc) int_slcdc bit 28 smart lcd controller (slcdc) int_sahara bit 27 symmetric/asymmetric hashing and random accelerator int_scm bit 26 scc scm int_smn bit 25 scc smn int_usbotg bit 24 usb otg int_usbhs2 bit 23 usb host2 int_usbhs1 bit 22 usb host1 int_h264 bit 21 h264 int_emmapp bit 20 emma post processor int_emmaprp bit 19 emma pre processor int_fec bit 18 fast ethernet controller int_uart5 bit 17 uart5 int_uart6 bit 16 uart6 int_dmach15 bit 15 dma channel 15 int_dmach14 bit 14 dma channel 14 int_dmach13 bit 13 dma channel 13 int_dmach12 bit 12 dma channel 12 int_dmach11 bit 11 dma channel 11 int_dmach10 bit 10 dma channel 10 int_dmach9 bit 9 dma channel 9 int_dmach8 bit 8 dma channel 8 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-26 freescale semiconductor 10.2.12.2 interrupt assignments low int_dmach7 bit 7 dma channel 7 int_dmach6 bit 6 dma channel 6 int_dmach5 bit 5 dma channel 5 int_dmach4 bit 4 dma channel 4 int_dmach3 bit 3 dma channel 3 int_dmach2 bit 2 dma channel 2 int_dmach1 bit 1 dma channel 1 int_dmach0 bit 0 dma channel 0 table 10-22. interrupt source low (intsrcl) assignment name bit interrupt source module notes int_csi bit 31 cmos sensor interface (csi) int_ata bit 30 advanced technology attachment (ata) hard disk int_nfc bit 29 nand flash controller (nfc) int_pcmcia bit 28 pcmcia/cf host controller (pcmcia) int_wdog bit 27 watchdog (wdog) int_gpt1 bit 26 general purpose timer (gpt1) int_gpt2 bit 25 general purpose timer (gpt2) int_gpt3 bit 24 general purpose timer (gpt3) int_pwm bit 23 pulse width modulator (pwm) int_rtc bit 22 real-time clock (rtc) int_kpp bit 21 key pad port (kpp) int_uart1 bit 20 uart1 int_uart2 bit 19 uart2 int_uart3 bit 18 uart3 int_uart4 bit 17 uart4 int_cspi1 bit 16 configurable spi (cspi1) int_cspi2 bit 15 configurable spi (cspi2) int_ssi1 bit 14 synchronous serial interface (ssi1) int_ssi2 bit 13 synchronous serial interface (ssi2) int_i2c1 bit 12 i 2 c bus controller (i 2 c1) table 10-21. interrupt source high (intsrch) assignment (continued) name bit interrupt source module notes arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-27 10.2.13 interrupt force register high (intfrch) and low (intfrcl) intfrch and intfrcl are both 32-bits wide. they allo w software generation of interrupts for each of the possible interrupt sources for functional or de bug purposes. system level design may reserve one or more sources for software purposes to allow software to self-schedule interrupts by forcing one or more of these ?sources? in appropriate interrupt force regi ster(s). these registers can only be accessed to in privileged mode. these registers can be only modified using 32-bit writes. int_sdhc1 bit 11 secure digital host controller (sdhc1) int_sdhc2 bit 10 secure digital host controller (sdhc2) int_sdhc3 bit 9 secure digital host controller (sdhc3) int_gpio bit 8 general purpose input/output (gpio) int_mshc bit 7 memory stick host controller (mshc) int_cspi3 bit 6 configurable spi (cspi3) int_rtic bit 5 real time integrity checker (rtic) int_gpt4 bit 4 general purpose timer (gpt4) int_gpt5 bit 3 general purpose timer (gpt5) int_gpt6 bit 2 general purpose timer (gpt6) int_i2c2 bit 1 i 2 c bus controller (i 2 c2) reserved bit 0 reserved address 0x1004_0050 (intfrch) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r force[63:48] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r force[47:32] w reset0000000000000000 table 10-22. interrupt source low (intsrcl) assignment (continued) name bit interrupt source module notes arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-28 freescale semiconductor 10.2.14 normal interrupt pending register high (nipndh) and low (nipndl) nipndh and nipndl are both 32-bits wide registers used to monitor the outputs of the enable and masking operations. these registers are actually a set of buffers; therefore, reset state of these registers are determined by normal interrupt enable registers, interrupt mask register and interrupt source registers. the value reflected in these registers is unaffected by the value of nimask register. these read-only registers are located on arm926ej-s native bus, accessible in 1 cy cle, and can only be accessed in privileged mode address 0x1004_0054 (intfrcl) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r force[31:16] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r force[15:0] w reset0000000000000000 figure 10-23. interrupt force register format table 10-23. interrupt force register high and low field description field description 31?0 force interrupt source force request. used to force a request for the corresponding interrupt source. 0 standard interrupt operation 1 interrupt forced asserted address 0x1004_0058 (nipndh) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipend[63:48] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipend [47:32] w reset0000000000000000 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-29 10.2.15 fast interrupt pending register high (fipndh) and low (fipndl) fipndh and fipndl are both 32-bits wide registers used to monitor the outputs of enable and masking operations. these registers are actually a set of buff ers; therefore, reset state of these registers are determined by fast interrupt enable registers, interrupt mask register and interrupt source registers. these read-only registers are located on the arm926ej-s na tive bus, accessible in 1 cycle, and can only be accessed to in privileged mode. address 0x1004_005c (nipndl) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r nipend[31:16] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nipend [15:0] w reset0000000000000000 table 10-24. normal interrupt pending register high and low description field description 31?0 nipend normal interrupt pending bit. if a normal interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a normal interrupt request. the normal interrupt pending bits reflect the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt. 0 no normal interrupt request 1 normal interrupt request pending address 0x1004_0060 (fipndh) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fipend[63:48] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fipend [47:32] w reset0000000000000000 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-30 freescale semiconductor figure 10-24. fast interrupt pending register high and low format 10.3 arm926ej-s interrupt controller operation 10.3.1 arm926ej-s prioritization of exception sources the arm926ej-s core imposes the followi ng priority among the various exceptions: ? reset (highest priority) ? data abort ? fast interrupt ? normal interrupt ? prefetch abort ? undefined instruction and swi (lowest priority) 10.3.2 aitc prioritization of interrupt sources aitc module prioritizes various interrupt sources by source number where higher source numbers have higher priority. fast interrupt always have higher priority over normal interrupt s. interrupt requests are prioritized in the following sequence: 1. fast interrupt requests, in order of highest source number 2. normal interrupt requests, in order of highest prio rity level, then in order of highest source number with the same priority level address 0x1004_0064 (fipndl) access: supervisor read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fipend[31:16] w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fipend [15:0] w reset0000000000000000 table 10-25. fast interrupt pending register high and low field description field description 31?0 fipend fast interrupt pending bit. if fast interrupt enable bit is set and the corresponding interrupt source is asserted, interrupt controller will assert fast interrupt request. fast interrupt pending bits reflect interrupt input lines which are asserted and are currently enabled to generate a fast interrupt. 0 no fast interrupt request 1 fast interrupt request pending arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-31 10.3.3 assigning and enabling interrupt sources interrupt controller provides for flexible assignment of any interrupt source to one of the two core interrupt request inputs. this is done by setting the appropria te bits in intenableh/intenablel registers and inttypeh/inttypel registers. usually, interrupt assignment is done once during system initialization and does not affect interrupt latency. interrupt assignment is the first of three steps required to enable an interrupt source, and this is done at chip integration. the second step is to program the source to generate interrupt requests. the final step is to enable the in terrupt inputs in the core by clearing the normal interrupt disable (i) and/or the fast inte rrupt disable (f) bits in the pr ogram status register (cpsr). 10.3.4 enabling interrupt sources there are two methods of enabling or disabling interrupt s in the aitc. the first method is directly reading intenableh/intenablel registers, logically or or bit clear these registers with a generated masks, then writing back to intenableh/intenablel registers. the second method is performing an atomic write to source number in intennum register . aitc will decode this 6-bit register and enable one of the 64 interrupt sources. aitc will automatically generate a ?one hot? enable mask and logically or this mask to the correct intenableh or inte nablel register. to disable interrupts is the same except the source number is written to the intdisnum register. 10.3.5 typical interrupt entry sequences table 10-26 shows a typical pipeline sequence for arm 926ej-s core when a normal interrupt occurs, assuming single cycle memories, it approximately ta kes 6 clocks from normal interrupt acknowledgment within arm926ej-s to fetch firs t opcode of interrupt routine. table 10-27 shows a typical pipeline sequence for arm926ej-s core when a fast interrupt oc curs, assuming that fiq service routine begins at 0x0000_001c and single cycle memories. table 10-26. typical hardware accelerated normal interrupt entry sequence addr time ?2 ?1 0 1 2 3 4 5 6 7 8 nirq assert nirq ack. last addr before nirq fetch dec exec link adjust +4 / +2 fetch dec +8 / +4 fetch 0x0000_0018 fetch dec exec data wrbk +4 fetch dec +8 fetch vector table vector n/a nirq routine fetch dec exec arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-32 freescale semiconductor 10.3.6 writing reentrant normal interrupt routines aitc can be used to create a reentrant normal interr upt system. this enables preempting of lower priority level interrupts by higher priority level interrupts. this requires a sm all amount of software support and overhead. 1. push the link register (lr_irq) on to the stack (sp_irq) 2. push the saved status register (spsr_irq) on to the stack 3. read the current value of nimask and push this value on to the stack 4. read current priority level via nivecsr 5. interrupts of the equal or lesser priority than the current priority level must be masked via the nimask register by writing value from nivecsr 6. clear i bit in arm926ej-s core by a msr or mrs command sequence (now a higher priority normal interrupt can preempt a lower priority one). also change operating mode of the core to system mode from irq mode 7. push system mode link register (lr) on to the stack (sp_user) 8. the traditional interrupt service routine is now included 9. pop system mode link register (lr) from the stack (sp_user) 10. set i bit in arm926ej-s core by msr or mrs command sequence (disable s all normal interrupts) 11. also change the operating mode of the core to irq mode from system mode 12. pop the original value of normal interrupt mask and write to the nimask register +4 fetch dec +8 fetch table 10-27. typical fast interrupt entry sequence addr time ?2?10123 nfiq assert nfiq ack. last addr before nfiq fetch dec exec link adjust +4 / +2 fetch dec +8 / +4 fetch 0x0000_001c fetch dec exec +4 fetch dec +8 fetch table 10-26. typical hardware accelerated normal interrupt entry sequence (continued) addr time ?2 ?1 0 1 2 3 4 5 6 7 8 arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 10-33 13. the saved status register must be popped from the stack (sp_irq) 14. the link register must be popped from the stack into the pc 15. return from nirq note steps 1, 2, 13, and 14 are automatically done by most c compilers and are included for completeness. 10.3.7 ahb interface of aitc aitc is ahb compliant. this means, idle or busy cy cles which are presented to aitc will receive an aitc_hready (as required by specification). arm926ej-s interrupt controller (aitc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 10-34 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 2: security introduction this part provides an overview of the modules that make up the i.mx27 security systems. chapter 11, ?security controller (scc) ,? on page 11-1 chapter 12, ?symmetric/asymmetric hashing and random accelerator (sahara2),? on page 12-1 chapter 13, ?run-time integrity checker (rtic),? on page 13-1 chapter 14, ?ic identification (iim) ,? on page 14-1 security controller (scc) the security controller (scc) is a hardware compon ent composed of two sub-blocks, the secure ram and the security monitor. the primary functionality of the scc is as sociated with establishing the following: ? a centralized security state controller and hardwa re security state with a hardware configured, unalterable security policy ? an uninterruptable hardware mechanism to de tect and respond to threat detection signals (specifically platform test access signals) ? a device-unique data protection/encryption resource to enable off chip storage of security sensitive data ? an internal storage resource that automatically and irrevocably destroys plain text security sensitive data upon threat detection symmetric/asymmetric hashing and random accelerator (sahara2) symmetric/asymmetr ic hashing and random accelerator (sahar a2) is a security co-processor that can be used on cell phone baseband processors or wireless pdas. it implements block encryption algorithms, (aes, des, and 3des), hashing algor ithms (md5, sha-1, sha-224, and sha-256), stream cipher algorithm (arc4), and a hardware random number generator. it has a slave ip bus interface for the host to write configuration and command information, and to read status information. it also has a dma controller, with an ahb bus interface, to reduce the burden on the host to move the required data to and from memory. MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor run time integrity checker (rtic) the run time integrity checker (rtic) ensures the integrity of the peripheral memory contents and assist with boot authentication. the rtic has the ability to verify the memory contents during system boot and during run time execution. if the memory contents at r untime fail to match the hash signature, an error in the security monitor is triggered. ic identification (iim) the ic identification module (iim) provides an inte rface for reading and in some cases programming and/or overriding identification and control informa tion stored in on-chip fuse elements. the module supports electrically-programmable poly fuses (e-fuses). the iim also provides a set of volatile software-accessible signals which can be used for software control of hardware elements, not requiring non-volatility. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 11-1 chapter 11 security controller (scc) the security controller (scc) is composed of two sub-blocks, the secure ram and the security monitor (see figure 11-1 ). the primary functionality of the scc is as sociated with establishing the following: ? a centralized security state controller and a hard ware security state with a hardware configured, unalterable security policy ? an uninterruptible hardware mechanism that de tects and responds to threat detection signals (specifically, platform test access signals) ? a device-unique data protection/encryption resource that enables off-chip storage of security-sensitive data an internal storage resource that automatically and irre vocably destroys plain text security-sensitive data upon threat detection. figure 11-1. security controller block diagram debug detector secure state controller algorithm sequence checker timer security policy security key (slid) red memory black memory key encryption memory controller state status debug ports (indicating jtag or test modes) ip bus security monitor secure ram security controller (scc) module bus interface security controller (scc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 11-2 freescale semiconductor 11.1 overview security and security services, in an embedded or data processing platform, refer to the platform?s ability to provide mandatory and optional information protection services. information in this context refers to all embedded data, both to program store and data load. therefore, a secure platform is intended to protect information and data from una uthorized access in the form of inspection (read), modification (write), or execution (use). 11.2 external signal description the scc has no external signals. note contact your freescale semiconductor sales office or distributor for additional information on scc. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 12-1 chapter 12 symmetric/asymmetric hashin g and random accelerator (sahara2) the symmetric/asymmetric hashing and random acce lerator (sahara2) is a security co-processor that can be used on cell phone baseband processors or wireless pdas. it implements block encryption algorithms, (aes, des, and 3des), hashing algor ithms (md5, sha-1, sha-224, and sha-256), stream cipher algorithm (arc4), and a hardware random number generator. it has a slave ip bus interface for the host to write configuration and command information, and to read status information. it also has a dma controller, with an ahb bus interface, to reduce the burden on the host to move the required data to and from memory. 12.1 features sahara2 accelerates the following security functions: ? aes encryption/decryption ? ecb, cbc, ctr, and ccm modes ? 128 bit key ?des/3des ? ebc, cbc and ctr modes ? 56-bit key with parity (des) ? 112-bit or 168-bit key with parity (3des) ? arc4 (rc4-compatible cipher) ? 5-16 byte key ? host accessible s-box ? md5, sha-1, sha-224 and sha-256 hashing algorithms. ? messages lengths which are multiples of bytes. ? autopadding supported. ? hmac (support for ipad and opad via descriptors). ? up to 2 32 byte message length. ? random number generator (based nist approved prng - fips 186-2). ? entropy is generated via an inde pendent free running ring oscillators sahara2 also provides the following enhanced features: ? descriptor based processing to reduce comm unication between host processor and sahara2 ? low power design symmetric/asymmetric hashing and random accelerator (sahara2) MCIMX27 multimedia applications processor reference manual, rev. 0.2 12-2 freescale semiconductor ? automatic power down of individual blocks when not in use ? clock gating on registers ? rng sleep mode ? restricted access to potentially sensitive information ? internal registers are cleared after descriptor chain has completed processing in batch mode ? security monitor can cause data to be cleared. ? scan reset and scan exit signals prevent data being scanned out. ? mixed endianness support. note contact your freescale semiconductor sales office or distributor for additional information on sahara2. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 13-1 chapter 13 run-time integrity checker (rtic) the run-time integrity checker (rtic) function is to ensure the integrity of the peripheral memory contents, and assist with boot authentication. the rt ic has the ability to verify the memory contents during system boot and during run-time execution. if th e memory contents at run-time fail to match the hash signature, an error in the security monitor is triggered. figure 13-1 is a block diagram of the rtic. figure 13-1. rtic block diagram 13.1 features the rtic offers the following features: ? sha-1 message authentication ? input dma interface ? segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) ? works with high assurance boot process ? support for up to four independent memory blocks ? programmable dma bus duty cycle timer and watchdog timer ? power-saving clock gating logic sam dmac controller hash register file ip-bus ahb t- s e c u r e ip-bus clock controller hclk ip-bus hash module en hclk_gated hclk_gated scc_rtic_err run-time timer once timer ckil (32 khz) run-time integrity checker (rtic) MCIMX27 multimedia applications processor reference manual, rev. 0.2 13-2 freescale semiconductor ? hardware configurable big/little-endian data format ? full word memory reads (word-aligned addresses, multiple of 32-bit lengths) 13.1.1 modes of operation the rtic operates in two primary modes: ? one-time hash mode ? is used during high assurance boot for code authentication or one time integrity checking ? stores hash result internally and signals interrupt to host ? continuous hash mode ? is used at run-time to continuously to verify integrity of memory contents ? checks re-generated hash against internally stored values and interrupts host only if error occurs 13.2 initialization/app lication information 13.2.1 system application the rtic is intended to serve as a single-use hash acce lerator to assist with code authentication and other services at boot time, and as an autonomous/passive memory integrity checker during run-time. it is programmed through the ip-slave interface, and sc ans the peripheral memory contents over the ahb interface using direct memory access. a typical sy stem configuration using the rtic is shown in figure 13-2 . figure 13-2. system diagram in this example, there are four independent memory blocks that can be checked by the rtic. memories a,b, and c have their contents partitioned over non-contiguous spaces. memory d does not contain any memory a memory b memory c memory d run-time integrity checker arm host processor scc ahb ip interface ipi_err_int run-time integrity checker (rtic) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 13-3 physical partitioning. the host would program the rtic with the starting address and length of each partition inside memory a, b, and c. for memory d, only one starting address and length would be specified, with the second start address/length fields for memory d being set to 0. after setting the a/b/c/d hash once memory enable bits in the rtic control register and hash once bit in the rtic command register, the rtic hashes each memory and stores the result in its hash register file to be read by the host. if the rtic is used to verify that the memories are not corrupted during run-time, the a/b/c/d run-time memory enable bits in the control register must be set, followed by the tun time check bit in the rtic command register. the rtic re-hashes each enabled memory in a continuous loop until either an error occurs or the rtic is reset. note contact your freescale semiconductor sales office or distributor for additional information on rtic. run-time integrity checker (rtic) MCIMX27 multimedia applications processor reference manual, rev. 0.2 13-4 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 14-1 chapter 14 ic identification (iim) the ic identification module (iim) provides an interf ace for reading and, in some cases, programming and/or overriding identification and control in formation stored in on-chip fuse elements. the iim also provides a set of volatile software-accessibl e signals that can be used for software control of hardware elements, not requiring non-volatility. 14.1 overview the iim provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. the iim also provides up to 28 volatile control signals. the iim consists of a master controller and a set of registers to hold the values of signals visible outside the module. up to eight arrays of fuse s (e-fuses) are associated with the iim. the iim is accessible using an 8-bit ip bus interface. an 8-bit interface is used because it matches the natural width of the fuse arrays. 14.1.1 features ? up to eight independent fuse banks (number of fuse banks and size of the bank are parameterized) ? maximum usable fuse bank size is 2048 bits ? laser- and e-fuse banks may be intermixed on a per bank basis ? support for driving secure jtag challenge and response values to the sjc (size of each field configurable using rtl pa rameter; challenge default size is 64 bits, response default size is 56 bits) ? up to 28 externally visible software-controlled vol atile signals (driving soc-level nets for feature enabling) lockable in groups of 7 ? ability to provide up to two distinct 168- bit 3des keys from a single set of fuses ? ability to override fuse values in software (doe s not affect the fuse element); override capability can be permanently disabled on a per-bank basis ? ability to write-protect e-fuses on a per-bank basis ? ability to scan-protect (read and program) on a per-bank basis ? fuses may be programmed by software, directly by jtag, or indirectly by jtag using a processor ? recommended signal assignments to maximize software re-use ic identification (iim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 14-2 freescale semiconductor note contact your freescale semiconductor sales office or distributor for additional information on iim. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 3: external interfaces introduction the i.mx27 processor contains th e following external interfaces: chapter 15, ?external memory interface (emi) ,? on page 15-1 chapter 16, ?multi-master memory interface (m3if) ,? on page 16-1 chapter 17, ?wireless external interface module (weim) ,? on page 17-1 chapter 18, ?enhanced sdram controller (esdramc) ,? on page 18-1 chapter 19, ?nand flash controller (nfc) ,? on page 19-1 chapter 20, ?personal computer memory card international association (pcmcia) controller ,? on page 20-1 external memory interface (emi) the external memory interface (m3if) controls all ic external memory accesses (read/write/erase/program) from all the masters in the system, through two master port gaskets (mpg)?(interface [ahb 32-bit] and mpg64 [ahb 64-bit])?to different external memories. all accesses are arbitrated by the multi master memory interface (m3if) module and controlled by the respective memory controller. the emi contains different external memory controllers to support se veral memory devices: ? m3if?multi master memory interface ? esdctl/mddrc?enhanced sdram/lpddr memory controller ? pcmcia?pcmcia memory controller ? nfc?nand flash memory controller ? weim?sram/psram/flash memory controller multi-master memory interface (m3if) the multi-master memory interface (m3if) controls memory accesses (read/write/erase/program) from one or more masters through different port interfac es to different external memory controllers esdctl/mddrc, pcmcia, nandflash, and weim. MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor wireless external interface module (weim) the wireless external interface module (weim) provi des the capability to the system for accessing external flash and ram memories connected to either of its six chip selects. it has the ability to provide a single-cycle burst access for extern al flashes and support for multiple burst devices when not using its smart burst feature. other features include big/e ndian mode support, cellular ram support, and support for multiplexed address/data bus. enhanced sdram controller (esdctl) the enhanced synchronous dynamic ram controller (esdctl) provides interface and control for synchronous dram memories for the system. sdra m memories use a synchronous interface with all signals registered on a clock edge. a command protocol is used for initialization, read, write, and refresh operations to the sdram and is generated on the signa ls by the controller when required due to external or internal requests. it has support for both singl e data rate rams and double data rate sdrams. it supports 64, 128, 256, and 512-mbit, 4 bank synchronous dram by two independent chip selects and with up to 64 mbytes addressa ble memory per chip select. nand flash controller (nfc) the nand flash controller (nfc) device is a type of flash memory that is optimized for data storage applications with its unique cell structure, providi ng significant cost advantages over conventional nor flash memory. the nand flash controller integrates the functionality necessary for access to these devices. nand flash has a smaller bit cell but has a fast sequential access as compared to a nor flash which has a large bit cell but a fast random access. this makes nand flash perfect as a data memory for storing audio/video files in nand flash because typically these files are stored in sequential manner while access to processor code is quite random. personal computer memory card international association (pcmcia) controller the pcmcia host adapter module provides the control logic for pcmcia socket interfaces, and requires some additional external analog power switching l ogic and buffering. the additional external buffers allow the pcmcia host adapter module to support one pcmcia socket. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-1 chapter 15 external memory interface (emi) the master memory interface (m3if) is an external memory interface that controls all ic external memory accesses (read/write/erase/program) from all the masters in the system, through two port interfaces (mpg (ahb 32 bit) and mpg64 (ahb 64-bit) to different external memories. all accesses are arbitrated by the m3if module and controlled by the resp ective memory controller. emi contains different external memory controllers in order to support several memory devices: ? m3if?multi master memory interface ? esdramc/mddrc?enhanced sdram/lpddr memory controller ? pcmcia?pcmcia memory controller ? nfc?nand flash memory controller ? weim?sram/psram/flash memory controller 15.1 overview the m3if-esdctl/mddrc interface is optimized and designed to reduce access latency by generating multiple accesses through dedicated esdctl/mddrc ar bitration (mab) module, which controls access to/from the enhanced sdram/mddr memory controller. for other memory interfaces, m3if only arbitrates and forwards the masters requests rece ived through the master port gasket (mpg/mpg64) interface (and m3if arbitration) to the respective memory controller. when a master request a memory access, the access will immediately be taken by the m3if if no other access is in progress. the m3if will forward the access to the respective memory controller (slave), and depending on the respective memory controller state a command to the memory will be generated. if the access can?t be started due to a previous active access, the master request pends (?hready? held negated) until it will be executed by the memory c ontroller. when the access execution is completed the hready will be asserted and a new request can be processed. emi provides the ability to connect to a wide variety of memory devices. this chapter contains technical information about the operation and configuration of th e emi modules in the chip to allow the designer to quickly integrate external memory devices into new and existing designs. several of the modules in the emi portion of the chip share pins with th e pcmcia, eim, sdramc, and nand controllers. the chip contains interfaces for the following types of memory devices: ? pcmcia ? flash memory devices ? sdram/low power ddr (lpddr) figure 15-1 shows the m3if block diagram. external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-2 freescale semiconductor figure 15-1. m3if system block diagram mpg64 #6 nand flash controller sdram/mddr pcmcia nand flash sram/psram flash mpg64 multi master memory interface (m3if) #5 external module interface (emi) mpg64 #4 mpg #3 mpg64 #1 mpg64 #2 m3if arbitration (amb + m3a) mpg #7 pcmcia controller weim controller esdctl/mddrc controller emi ahb mux emi i/o mux max application (arm) platform s2 m2 m3 m5 a/p rtic/ dma 64 64 32 64 32 sahara2 usbotg m4 h264-ahb h264-po h264-po h264-po lcdc slcdc tmax fec emma-it 64 64 64 mpg64 #0 external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-3 15.2 features m3if includes these distinctive features: ? multi master memory interface (m3if) ? supports multiple requests from 8 masters through two different input ports interfaces: master port gasket (mpg)?arm9 amba ahb-lite bus protocol. master port gasket (mpg64)?amba ahb access with 64 bits data bus width. ? supports memory ?snooping,? which monitors a region (from 2 kbytes up to 16 mbytes) in external memory for write accesses. ? enables ahb accesses to four different memory controllers (that share some of their i/o pads, through the emi ahb mux and emi i/o mux) ? enhanced sdram controller (esdctl) or mddr controller (mddrc) ? up to two chip selects (due to pads sharing a ll 2 chip selects are supported only in case that weim cs2 and cs3 are not is use). ? supports 32 bit sdr sdram (up to 2 gbytes @133 mhz) ? supports 32 bit mddr sdram (up to 2 gbytes @ 266 mhz) ? nand flash controller (nfc) ? 8/16 bit nand flash (up to 2 gbyte address space) ? 2-kbyte ram internal buffer ? personal computer memory card intern ational association controller (pcmcia) ? support pcmcia rel 2.1 ? compact flash ? pc card ? trueid mode ? wireless external interface memory controller (weim) ? up to 6 chip selects (due to pads sharing all 6 chip selects are supported only in case that both esdctl/mddrc chip selects are not is use). ? supports 16-bit sram memories ? supports 16-bit psram (up to 133 mhz) memories ? support s16-bit (nor) flash memories 15.3 pcmcia host adapter the personal computer memory card international association (pcmcia) interface provides a glueless interface to devices that comply with the pcmcia association standard pcmcia 2.1, which defines usage of memory and i/o devices as insertable and excha ngeable peripherals for personal computers or pdas. examples of these types of devices include compact flash and wlan adapters. figure 15-2 shows a simplified block diagram of the pcmcia controller. external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-4 freescale semiconductor figure 15-2. pcmcia host adapter simplified block diagram pcmcia host adapter module provides the all the nece ssary control logic for a single pcmcia socket and only requires some additional external analog power switching logic and buffering for pc card operations. pcmcia host adapter module can support one pcmcia socket. pcmcia controller shares its pins with other modules in the eim area of the chip. the modules that share pins with pcmcia are eim, sdramc and nand controllers. 15.3.1 interrupt generation there are 14 interrupt sources in pcmcia controller. in addition, pcmcia generates a signal which is a locator of all the possible interrupts. it is up to the sy stem?s integrator to decide which signal(s) to connect to the system?s interrupt controller module. pcmcia input pins register (pipr) reports any change of inputs from the pcmcia card to the host (bvd,cd,rdy,vs). pcmcia controller status changed static signals interface ahb bus int gen pcmcia controller pc card a[25:0] d[15:0] oe we iord iowr reg wait ce1 ce2 rdy/bsy iois16 /wp bvd1 bvd2 cd1 cd2 reset r/w poe vs1 vs2 interrupts endianness debug_signals pcmcia_access pwron card power circuit vcc/vpp ahb interface card interface access error external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-5 register (pscr) contents are l ogically anded with pcmcia controller enable register (per) to generate a pcmcia controller inte rrupt. the interrupt level is us er programmable and the pcmcia controller can generate an additiona l interrupt for rdy/ireq that can trigger upon a level (low or high) change or edge (fall or rise) of the input signal. 15.3.2 card extraction when a pc card is extracted the pcmcia controller?s registers are not reset. the registers settings remain the same as before the card?s extraction. this allows the host software to quickly activate the card once the cis indicates that it?s the same card on reinsertion. 15.3.3 trueide support the ata standard specifies an at attachment inte rface between the host systems and storage devices. pcmcia controller can be dynamically configured to support a pcmcia-compatible ata disk interface (commonly known as ide) instead of the standard pcmcia card interface. using the trueide interface on the pcmcia controller changes the function of some card socket signals to support the needs of ata disk interface. 15.4 nand flash controller (nfc) the nfc module interfaces standard nand flash devi ces to the ic and hides the complexities of accessing a nand flash memory device. it provides a glueless interface to both 8-bits and 16-bits nand flash parts with page sizes of 512 bytes or 2 kilobytes and densities up to 2 gbit. figure 15-3 shows a simplified block diagram of the nand flash controller. figure 15-3. nand flash controller simplified block diagram ahb bus read and write host control data output ram buffer register (command address/ status) ecc control address control nand flash control ahb bus interface bootloader cle ale ce re we wp rb din dout external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-6 freescale semiconductor 15.4.1 operation communicating with a flash memory device begins by the ahb host initiating a read from the nand flash controller (nfc). this is accomplished by conf iguring the nfc and then waiting for an interrupt from the flash memory device to be generated. when the nfc receives the interrupt, it inputs a page from the flash memory device, and upon completion, generates an interrupt to the ahb host. when ahb host receives the nfc interrupt, it reads the content from the internal ram buffer of the nfc. to complete the operation the ahb host checks the status of operation by reading the nfc status registers. data that is exchanged with the flash memory device is temporarily maintained in a 2 kilobyte ram buffer. this buffer is used as the boot ram during a cold reset (if the ic is configured for a boot to be carried out from the nand flash device). after the boot load completes, the ram is available as buffer ram for normal flash memory operations. 15.4.1.1 internal and external communications to ensure the greatest degree of flexibility, nfc provides an internal x16 bit and x32 bit interface to the ahb bus allowing, 16-bit or 32-bit bus transfers, and a pin selectable x8 or x16 interface to the external nand flash memory device. all communications between the nfc and the arm9 platform is accomplished through the ahb host. configuration and control of the nfc by the host is done using 14 16-bit registers. nfc generates all the control signals that controls the nand flash: ce (flash chip enable), re (read enable for read operations), we (flash write enable), cle (flash comma nd latch enable), ale (flash address latch enable). it also monitors the r/nb (flash ready/busy indication) signal to check if the nand flash memory device is currently in the middle of an ope ration. flash memory data?s integrity is monitored by automatic generation of ec c code of data during nfcs data loading from nand flash memory devices. 15.4.1.2 sharing of i/o pins the nfc provides necessary logic to share i/o pins with pins of anot her memory controller. nfc state machine halts when a request to free the pins is a sserted. nand flash signals when it finishes the existing transfer allowing other memory controller to c ontrol them. since nand flash memory accesses are typically long and relatively slow, priority is given to other memory controller sharing the pins. nfc must wait until other memory controller is finished with its operation and the pins are free before it can continue with its accesses. one example for this pin muxing is sharing the 16 i/o pins of the nand flash controller with the data pins of the wireless external interface module (weim) when interfacing to a psram. 15.5 enhanced sdram controller (esdramc) the esdramc module provides inte rface, configuration and control for many different types synchronous sdram and low power mobile ddr (lpddr) memories. figure 18-1 is the enhanced sdram controller top-level diagram that shows th e functional organization of the block. enhanced sdram controller consists of 9 major blocks, in cluding the sdram command state machine controller, bank register (page and bank address comparators), row/column address multiplexer, configuration registers, refresh request counter, command sequenc er, size logic (splitting access), data path (data aligner/multiplexer), lpddr interface and the power down timer. external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-7 15.6 m3if ahb mux the m3if ahb mux module controls traffic on the ahb bus (address and controls) between the memory controllers and the ic. m3if uses several muxes/glue logic to control the traffic on the ahb bus. only several ahb signals/busses are routed through the em i ahb mux toward the memory controllers. most of the ahb busses (data, address and controls) ar e directly routed from the m3if to the memory controllers. 15.6.1 overview of emi ahb mux operation figure 15-4 illustrates emi ahb mux block diagram. the interface is arm?s 11 amba-ahb-lite compliant (does not support retry and split transf ers). all ahb signals that are not shown in figure 15-4 are directly routed between the m3if and the re levant memory controllers. for the entire list of ahb signals refer to table 15-3 and to the relevant memory cont roller specification document. emi ahb mux generates hsel signals for all memory c ontrollers except esdctl (generated within the m3if due to latency hiding logic). 15.7 m3if i/o mux m3if i/o mux controls the traffic (data, address a nd controls) between the memory controllers and the external devices (via the ic i/o m ux/pads), and vice versa, for exampl e, from the external devices to the memory controllers. the m3if uses several m uxes/glue logic to control the traffic. refer figure 15-4 and figure 15-5 for a top level diagram of the emiahb and the emi i/o mux. only shared ic pads signals/busses are routed thro ugh the emi i/o mux toward the external devices. signals (mainly controls) that have dedicated pads are directly routed from the memory controllers to the external devices. 15.7.1 overview of emi i/o mux operation the signals not shown in figure 15-5 are directly routed between the memory controllers and the respective external device. for entire list of signals, refer table 15-3 and the relevant memory controller section. the select for muxes is choosen_slave[1:0] bus dr iven by m3if. choosen_slave encoding is listed in table 15-1 which summarizes emi outputs to ic pads (dedicated and shared among all memory controllers). table 15-1. choosen_slave encoding choosen_slave value selected memory controller 00 esdctl/mddrc 01 weim 10 pcmcia 11 nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-8 freescale semiconductor figure 15-4. emi ahb mux interface diagram nand flash controller m3if arbitration (amb + m3a) pcmcia controller weim controller emi ahb mux hready_pcmcia hresp_pcmcia hready_nfc hresp_nfc hready_eim hresp_eim pcmcia_hsel_card hsel_nfc hsel_weim_cs0 hsel_weim_cs1 hsel_weim_cs2 hsel_weim_cs3 hsel_weim_cs4 hsel_weim_cs5 pcmcia_hsel_reg hsel_weim_reg hready hready hready haddr[31:12] hresp0 external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-9 figure 15-5. emi i/o mux interface diagram nand flash device pcmcia device sram/psram flash emi i/o mux sdram/mddr sdctl_csd0_sel_b sdctl_csd1_sel_b weim_addr m3if_ma ipp_do_card_address_o choosen_slave(m3if) 2 26 14 26 nand flash controller pcmcia controller weim controller esdctl/mddrc controller device ipp_nfc_write_data_out 16 weim_data_out 16 ipp_do_card_wr_data_o 16 ipp_do_card_ce_b ipp_do_card_oe_b ipp_do_card_reg_b_o ipp_do_card_iord_b weim_eb_b ipp_do_card_iowr_b 2 ipp_do_weim_cs_b 2 2 m3if_cs_b ipp_do_card_we_b 2 weim_rw_b weim_wr_oe 4 weim_oe_b ipp_do_card_rw_b ic i o m u x - p a d s ipp_do_e m i_io_eb_b 2 ipp_do_e m i_io_oe_b ipp_do_nfc_write_data_o 16 ipp_obe_e m i_io_data_diir 2 ipp_do_weim_cs_b2_csd0 ipp_do_weim_cs_b3_csd1 ipp_do_e m i_addr 26 ipp_do_weim_rw_b ipp_ind_addr_in 16 ipp_ind_emi_data_in 31 ipp_ind_nfc_read_data_in 16 m3if_rd_data 32 m3if_wr_data 32 ipp_nfc_read_data_in 16 weim_addr_in 16 external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-10 freescale semiconductor table 15-2. external memory interface i/o mux description memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc weim/esdctl/pcmcia address muxing/weim muxed mode data[15:0] m3if_ma[0] ipp_do_card_add ress_o[0] weim_addr_data_o ut[0] ? ipp_do_e m i _addr [0] a0 ? ? weim_addr_data_i n[0] ipp_ind_addr_in [0] m3if_ma[1] ipp_do_card_add ress_o[1] weim_addr_data_o ut[1] ? ipp_do_e m i _addr [1] a1 ? ? weim_addr_data_i n[1] ipp_ind_addr_in [1] m3if_ma[2] ipp_do_card_add ress_o[2] weim_addr_data_o ut[2] ? ipp_do_e m i _addr [2] a2 ? ? weim_addr_data_i n[2] ipp_ind_addr_in [2] m3if_ma[3] ipp_do_card_add ress_o[3] weim_addr_data_o ut[3] ? ipp_do_e m i _addr [3] a3 ? ? weim_addr_data_i n[3] ipp_ind_addr_in [3] m3if_ma[4] ipp_do_card_add ress_o[4] weim_addr_data_o ut[4] ? ipp_do_e m i _addr [4] a4 ? ? weim_addr_data_i n[4] ipp_ind_addr_in [4] m3if_ma[5] ipp_do_card_add ress_o[5] weim_addr_data_o ut[5] ? ipp_do_e m i _addr [5] a5 ? ? weim_addr_data_i n[5] ipp_ind_addr_in [5] m3if_ma[6] ipp_do_card_add ress_o[6] weim_addr_data_o ut[6] ? ipp_do_e m i _addr [6] a6 ? ? weim_addr_data_i n[6] ipp_ind_addr_in [6] m3if_ma[7] ipp_do_card_add ress_o[7] weim_addr_data_o ut[7] ? ipp_do_e m i _addr [7] a7 ? ? weim_addr_data_i n[7] ipp_ind_addr_in [7] m3if_ma[8] ipp_do_card_add ress_o[8] weim_addr_data_o ut[8] ? ipp_do_e m i _addr [8] a8 ? ? weim_addr_data_i n[8] ipp_ind_addr_in [8] external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-11 m3if_ma[9] ipp_do_card_add ress_o[9] weim_addr_data_o ut[9] ? ipp_do_e m i _addr [9] a9 ? ? weim_addr_data_i n[9] ipp_ind_addr_in [9] ? ipp_do_card_add ress_o[10] weim_addr_data_o ut[10] ? ipp_do_e m i _addr [10] a10 ? ? weim_addr_data_i n[10] ipp_ind_addr_in [10] m3if_ma[11] ipp_do_card_add ress_o[11] weim_addr_data_o ut[11] ? ipp_do_e m i _addr [11] a11 ? ? weim_addr_data_i n[11] ipp_ind_addr_in [11] m3if_ma[12] ipp_do_card_add ress_o[12] weim_addr_data_o ut[12] ? ipp_do_e m i _addr [12] a12 ? ? weim_addr_data_i n[12] ipp_ind_addr_in [12] m3if_ma[13] ipp_do_card_add ress_o[13] weim_addr_data_o ut[13] ? ipp_do_e m i _addr [13] a13 ? ? weim_addr_data_i n[13] ipp_ind_addr_in [13] ? ipp_do_card_add ress_o[14] weim_addr_data_o ut[14] ? ipp_do_e m i _addr [14] a14 weim_addr_data_i n[14] ipp_ind_addr_in [14] ? ipp_do_card_add ress_o[15] weim_addr_data_o ut[15] ? ipp_do_e m i _addr [15] a15 weim_addr_data_i n[15] ipp_ind_addr_in [15] ? ipp_do_card_add ress_o[16] weim_addr_out[16] ? ipp_do_e m i _addr [16] a16 ? ipp_do_card_add ress_o[17] weim_addr_out[17] ? ipp_do_e m i _addr [17] a17 ? ipp_do_card_add ress_o[18] weim_addr_out[18] ? ipp_do_e m i _addr [18] a18 ? ipp_do_card_add ress_o[19] weim_addr_out[19] ? ipp_do_e m i _addr [19] a19 ? ipp_do_card_add ress_o[20] weim_addr_out[20] ? ipp_do_e m i _addr [20] a20 table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-12 freescale semiconductor ? ipp_do_card_add ress_o[21] weim_addr_out[21] ? ipp_do_e m i _addr [21] a21 ? ipp_do_card_add ress_o[22] weim_addr_out[22] ? ipp_do_e m i _addr [22] a22 ? ipp_do_card_add ress_o[23] weim_addr_out[23] ? ipp_do_e m i _addr [23] a23 ? ipp_do_card_add ress_o[24] weim_addr_out[24] ? ipp_do_e m i _addr [24] a24 ? ipp_do_card_add ress_o[25] weim_addr_out[25] ? ipp_do_e m i _addr [25] a25 esdctl address bit m3if_ma[10] has a dedicated pad ma10 (required due to precharge all during auto refresh commands). esdctl bank address bits have dedicated pads due to precharge bank during precharge timer time-out weim cre signal is driven on a23 in muxed mode operation. m3if_ma[10] ? ? ? ipp_do_e m i _ma10 ma10 m3if_ba[0] ipp_do_card_ce_ b[2] ? ? ipp_do_sdba[1:0] sdba0 m3if_ba[1] ipp_do_card_ce_ b[1] ? ? sdba1 since sdba pads are shared between sdr/ddr sdram bank address and pcmcia ce?, esdctl precharge timer cannot be used. during precharge timer, after selected inactivity period of time expires, esdctl issue a precharge command to a specific bank during off line period. it means that precharge command can be issued during the time when emi bus is not possessed by esdctl. sdram/mddr dedicated data pads m3if_wr_data[0] ? ? ? ipp_do_emii_data [0] sd0 m3if_rd_data[0] ipp_ind_emii_data _in [0] m3if_wr_data[1] ? ? ? ipp_do_emii_data [1] sd1 m3if_rd_data[1] ipp_ind_emii_data _in [1] m3if_wr_data[2] ? ? ? ipp_do_emii_data [2] sd2 m3if_rd_data[2] ipp_ind_emii_data _in [2] table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-13 m3if_wr_data[3] ? ? ? ipp_do_emii_data [3] sd3 m3if_rd_data[3] ipp_ind_emii_data _in [3] m3if_wr_data[4] ? ? ? ipp_do_emii_data [4] sd4 m3if_rd_data[4] ipp_ind_emii_data _in [4] m3if_wr_data[5] ? ? ? ipp_do_emii_data [5] sd5 m3if_rd_data[5] ipp_ind_emii_data _in [5] m3if_wr_data[6] ? ? ? ipp_do_emii_data [6] sd6 m3if_rd_data[6] ipp_ind_emii_data _in [6] m3if_wr_data[7] ? ? ? ipp_do_emii_data [7] sd7 m3if_rd_data[7] ipp_ind_emii_data _in [7] m3if_wr_data[8] ? ? ? ipp_do_emii_data [8] sd8 m3if_rd_data[8] ipp_ind_emii_data _in [8] m3if_wr_data[9] ? ? ? ipp_do_emii_data [9] sd9 m3if_rd_data[9] ipp_ind_emii_data _in [9] m3if_wr_data[10] ? ? ? ipp_do_emii_data [10] sd10 m3if_rd_data[10] ipp_ind_emii_data _in [10] m3if_wr_data[11] ? ? ? ipp_do_emii_data [11] sd11 m3if_rd_data[11] ipp_ind_emii_data _in [11] table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-14 freescale semiconductor m3if_wr_data[12] ? ? ? ipp_do_emii_data [12] sd12 m3if_rd_data[12] ipp_ind_emii_data _in [12] m3if_wr_data[13] ? ? ? ipp_do_emii_data [13] sd13 m3if_rd_data[13] ipp_ind_emii_data _in [13] m3if_wr_data[14] ? ? ? ipp_do_emii_data [14] sd14 m3if_rd_data[14] ipp_ind_emii_data _in [14] m3if_wr_data[15] ? ? ? ipp_do_emii_data [15] sd15 m3if_rd_data[15] ipp_ind_emii_data _in [15] m3if_wr_data[16] ? ? ? ipp_do_emii_data [16] sd16 m3if_rd_data[16] ipp_ind_emii_data _in [16] m3if_wr_data[17] ? ? ? ipp_do_emii_data [17] sd17 m3if_rd_data[17] ipp_ind_emii_data _in [17] m3if_wr_data[18] ? ? ? ipp_do_emii_data [18] sd18 m3if_rd_data[18] ipp_ind_emii_data _in [18] m3if_wr_data[19] ? ? ? ipp_do_emii_data [19] sd19 m3if_rd_data[19] ipp_ind_emii_data _in [19] m3if_wr_data[20] ? ? ? ipp_do_emii_data [20] sd20 m3if_rd_data[20] ipp_ind_emii_data _in [20] table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-15 m3if_wr_data[21] ? ? ? ipp_do_emii_data [21] sd21 m3if_rd_data[21] ipp_ind_emii_data _in [21] m3if_wr_data[22] ? ? ? ipp_do_emii_data [22] sd22 m3if_rd_data[22] ipp_ind_emii_data _in [22] m3if_wr_data[23] ? ? ? ipp_do_emii_data [23] sd23 m3if_rd_data[23] ipp_ind_emii_data _in [23] m3if_wr_data[24] ? ? ? ipp_do_emii_data [24] sd24 m3if_rd_data[24] ipp_ind_emii_data _in [24] m3if_wr_data[25] ? ? ? ipp_do_emii_data [25] sd25 m3if_rd_data[25] ipp_ind_emii_data _in [25] m3if_wr_data[26] ? ? ? ipp_do_emii_data [26] sd26 m3if_rd_data[26] ipp_ind_emii_data _in [26] m3if_wr_data[27] ? ? ? ipp_do_emii_data [27] sd27 m3if_rd_data[27] ipp_ind_emii_data _in [27] m3if_wr_data[28] ? ? ? ipp_do_emii_data [28] sd28 m3if_rd_data[28] ipp_ind_emii_data _in [28] m3if_wr_data[29] ? ? ? ipp_do_emii_data [29] sd29 m3if_rd_data[29] ipp_ind_emii_data _in [29] table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-16 freescale semiconductor m3if_wr_data[30] ? ? ? ipp_do_emii_data [30] sd30 m3if_rd_data[30] ipp_ind_emii_data _in [30] m3if_wr_data[31] ? ? ? ipp_do_emii_data [31] sd31 m3if_rd_data[31] ipp_ind_emii_data _in [31] weim/nfc/pcmcia data muxing ? ipp_do_card_wr _data_o[0] weim_data_out[0] ipp_nfc_write_d ata _ o u t [ 0 ] ipp_do_nfc_writ e_ data_out [0] d0 ipp_ind_card_rd _data_i[0] weim_data_in[0] ipp_nfc_read_da ta _ i n [ 0 ] ipp_ind_nfc_rea d_ data_in [0] ? ipp_do_card_wr _data_o[1] weim_data_out[1] ipp_nfc_write_d ata _ o u t [ 1 ] ipp_do_nfc_writ e_ data_out [1] d1 ipp_ind_card_rd _data_i[1] weim_data_in[1] ipp_nfc_read_da ta _ i n [ 1 ] ipp_ind_nfc_rea d_ data_in [1] ? ipp_do_card_wr _data_o[2] weim_data_out[2] ipp_nfc_write_d ata _ o u t [ 2 ] ipp_do_nfc_writ e_ data_out [2] d2 ipp_ind_card_rd _data_i[2] weim_data_in[2] ipp_nfc_read_da ta _ i n [ 2 ] ipp_ind_nfc_rea d_ data_in [2] ? ipp_do_card_wr _data_o[3] weim_data_out[3] ipp_nfc_write_d ata _ o u t [ 3 ] ipp_do_nfc_writ e_ data_out [3] d3 ipp_ind_card_rd _data_i[3] weim_data_in[3] ipp_nfc_read_da ta _ i n [ 3 ] ipp_ind_nfc_rea d_ data_in [3] ? ipp_do_card_wr _data_o[4] weim_data_out[4] ipp_nfc_write_d ata _ o u t [ 4 ] ipp_do_nfc_writ e_ data_out [4] d4 ipp_ind_card_rd _data_i[4] weim_data_in[4] ipp_nfc_read_da ta _ i n [ 4 ] ipp_ind_nfc_rea d_ data_in [4] ? ipp_do_card_wr _data_o[5] weim_data_out[5] ipp_nfc_write_d ata _ o u t [ 5 ] ipp_do_nfc_writ e_ data_out [5] d5 ipp_ind_card_rd _data_i[5] weim_data_in[5] ipp_nfc_read_da ta _ i n [ 5 ] ipp_ind_nfc_rea d_ data_in [5] ? ipp_do_card_wr _data_o[6] weim_data_out[6] ipp_nfc_write_d ata _ o u t [ 6 ] ipp_do_nfc_writ e_ data_out [6] d6 ipp_ind_card_rd _data_i[6] weim_data_in[6] ipp_nfc_read_da ta _ i n [ 6 ] ipp_ind_nfc_rea d_ data_in [6] table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-17 ? ipp_do_card_wr _data_o[7] weim_data_out[7] ipp_nfc_write_d ata _ o u t [ 7 ] ipp_do_nfc_writ e_ data_out [7] d7 ipp_ind_card_rd _data_i[7] weim_data_in[7] ipp_nfc_read_da ta _ i n [ 7 ] ipp_ind_nfc_rea d_ data_in [7] ? ipp_do_card_wr _data_o[8] weim_data_out[8] ipp_nfc_write_d ata _ o u t [ 8 ] ipp_do_nfc_writ e_ data_out [8] d8 ipp_ind_card_rd _data_i[8] weim_data_in[8] ipp_nfc_read_da ta _ i n [ 8 ] ipp_ind_nfc_rea d_ data_in [8] ? ipp_do_card_wr _data_o[9] weim_data_out[9] ipp_nfc_write_d ata _ o u t [ 9 ] ipp_do_nfc_writ e_ data_out [9] d9 ipp_ind_card_rd _data_i[9] weim_data_in[9] ipp_nfc_read_da ta _ i n [ 9 ] ipp_ind_nfc_rea d_ data_in [9] ? ipp_do_card_wr _data_o[10] weim_data_out[10] ipp_nfc_write_d ata _ o u t [ 1 0 ] ipp_do_nfc_writ e_ data_out [10] d10 ipp_ind_card_rd _data_i[10] weim_data_in[10] ipp_nfc_read_da ta _ i n [ 1 0 ] ipp_ind_nfc_rea d_ data_in [10] ? ipp_do_card_wr _data_o[11] weim_data_out[11] ipp_nfc_write_d ata _ o u t [ 1 1 ] ipp_do_nfc_writ e_ data_out [11] d11 ipp_ind_card_rd _data_i[11] weim_data_in[11] ipp_nfc_read_da ta _ i n [ 1 1 ] ipp_ind_nfc_rea d_ data_in [11] ? ipp_do_card_wr _data_o[12] weim_data_out[12] ipp_nfc_write_d ata _ o u t [ 1 2 ] ipp_do_nfc_writ e_ data_out [12] d12 ipp_ind_card_rd _data_i[12] weim_data_in[12] ipp_nfc_read_da ta _ i n [ 1 2 ] ipp_ind_nfc_rea d_ data_in [12] ? ipp_do_card_wr _data_o[13] weim_data_out[13] ipp_nfc_write_d ata _ o u t [ 1 3 ] ipp_do_nfc_writ e_ data_out [13] d13 ipp_ind_card_rd _data_i[13] weim_data_in[13] ipp_nfc_read_da ta _ i n [ 1 3 ] ipp_ind_nfc_rea d_ data_in [13] ? ipp_do_card_wr _data_o[14] weim_data_out[14] ipp_nfc_write_d ata _ o u t [ 1 4 ] ipp_do_nfc_writ e_ data_out [14] d14 ipp_ind_card_rd _data_i[14] weim_data_in[14] ipp_nfc_read_da ta _ i n [ 1 4 ] ipp_ind_nfc_rea d_ data_in [14] ? ipp_do_card_wr _data_o[15] weim_data_out[15] ipp_nfc_write_d ata _ o u t [ 1 5 ] ipp_do_nfc_writ e_ data_out [15] d15 ipp_ind_card_rd _data_i[15] weim_data_in[15] ipp_nfc_read_da ta _ i n [ 1 5 ] ipp_ind_nfc_rea d_ data_in [15] mask (byte enable) muxing table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-18 freescale semiconductor ? ? ipp_do_card_re g_b_o weim_eb_b[0] ? ipp_do_e m i _io_eb_b[1:0] eb0 ? ? ipp_do_card_ior d_b weim_eb_b[1] ? eb1 eb_b[2] and eb_b[3] will be driven on a24 and a25 respectivelly during muxed mode (in order to use 32 bit memory device. sdram/mddr mask (byte enable) m3if_dqm[0] ? ? ? ipp_do_dqm [3:0] dqm0 m3if_dqm[1] ? ? ? dqm1 m3if_dqm[2] ? ? ? dqm2 m3if_dqm[3] ? ? ? dqm3 output enable muxing ? ipp_do_card_iow r_b weim_wr_oe ? ipp_do_emi _oe_b oe chip select muxing ? ? ? ipp_do_weim_cs_b[ 0] ? ipp_do_weim_ cs_b0 cs0 ? ? ? ipp_do_weim_cs_b[ 1] ? ipp_do_weim_ cs_b1 cs1 m3if_cs_b[0] ? ipp_do_weim_cs_b[ 2] ? ipp_do_weim_ cs_b2_csd0 cs2 m3if_cs_b[1] ? ipp_do_weim_cs_b[ 3] ? ipp_do_weim_ cs_b3_csd1 cs3 ? ? ? ipp_do_weim_cs_b[ 4] ? ipp_do_weim_ cs_b4 cs4 ? ? ? ipp_do_weim_cs_b[ 5] ? ipp_do_weim_ cs_b5 cs5 chip select are system control register bits sdctl_ csd0_sel and sdctl_csd1_sel respectively. default select for both chip selects are for the esdctl/mddrc. write enable muxing ? ? ipp_do_card_we _b weim_rw_b ? ipp_do_weim_ rw_b rw sdram/mddr command dedicated pads ras_b ? ? ? ipp_do_m3if_ras_ b ras table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-19 cas_b ? ? ? ipp_do_m3if_cas_ b cas we_b ? ? ? ipp_do_sdrc_sd we sdwe cke[1] ? ? ? ipp_do_sdrc_sdc ke[1] sdck e [1] cke[0] ? ? ? ipp_do_sdrc_sdc ke[0] sdck e [0] sdclk_out ? ? ? ipp_do_sdrc_sdc lk sdclk ? mddr_ sdclk_ b ? ? ? ipp_do_mddr_sd clk_b sdclk _b ?dqs_o ut [3] ???ipp_do_dqs[3]dqs[3] dqs_in [3] ipp_din_dqs[3] ?dqs_o ut [2] ???ipp_do_dqs[2]dqs[2] ?dqs_in [2] ? ? ? ipp_din_dqs[2] ?dqs_o ut [1] ???ipp_do_dqs[1]dqs[1] ?dqs_in [1] ? ? ? ipp_din_dqs[1] ?dqs_o ut [0] ???ipp_do_dqs[0]dqs[0] ?dqs_in [0] ? ? ? ipp_din_dqs[0] ? ? ? ? ? m_request m_re ques t ?????m_grantm_gr ant nfc command dedicated pads ? ? ? ? ipp_nfc_we_out ipp_nfc_we_out nfwe _b ? ? ? ? ipp_nfc_wp_out ipp_nfc_wp_out nfwp _b table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-20 freescale semiconductor ? ? ? ? ipp_nfc_re_out ipp_nfc_re_out nfre_ b ? ? ? ? ipp_nfc_ale_out ipp_nfc_ale_out nfale ? ? ? ? ipp_nfc_cle_out ipp_nfc_cle_out nfcle ? ? ? ? ipp_nfc_ce_out ipp_nfc_ce_out nfce_ b ? ? ? ? ipp_nfc_rb_in ipp_nfc_rb_in nfrb weim command dedicated pads ? ? ipp_do_card_oe_ b ipp_do_weim_lba_ b ? ipp_do_weim_lba _b lba_b ? ? ? ipp_do_weim_bclk ? ipp_do_weim_bcl k bclk ? ? ? ipp_ind_weim_ecb_ b ? ipp_ind_weim_ec b_b ecb pcmcia command dedicated pads ? ? ipp_int_cd1_b ? ? ipp_int_cd1_b pc_c d1_b ? ? ipp_int_cd2_b ? ? ipp_int_cd2_b pc_c d2_b ? ? ipp_ind_wait_b_i ? ? ipp_ind_wait_b_i pc_w ait_b ? ? ipp_ind_pwr_on_i ? ? ipp_ind_pwr_on_i pc_p wron ? ? ipp_ind_rdy_irq_ b_i ? ? ipp_ind_rdy_irq_ b_i pc_re ady ? ? ipp_ind_vs1_b ? ? ipp_ind_vs1_b pc_vs 1 ? ? ipp_ind_vs2_b ? ? ipp_ind_vs2_b pc_vs 2 ? ? ipp_ind_bvd1_sts ch_b_i ? ? ipp_ind_bvd1_sts ch_b_i pc_bv d1 ? ? ipp_ind_bvd2_spk r_i ? ? ipp_ind_bvd2_spk r_i pc_bv d2 ? ? ipp_do_card_res et ? ? ipp_do_card_res et pc_rs t ? ? ipp_do_card_poe _o_b ? ? ipp_do_card_poe _o_b pc_p oe table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-21 15.7.2 emi input/output signals this section lists all input and output signals for the entire emi module. table 15-3 summarizes interface signals. for detailed descriptions of each signal func tion, refer to the relevant module chapters in this manual. ? ? ipp_do_card_rw _b ? ? ipp_do_card_rw _b pc_r w_b ? ? ipp_ind_wp_i ? ? ipp_ind_wp_i iois16 table 15-3. emi signal properties name port function reset state ahb interface outputs m3if_hready_m0 o ahb access completion strobe to master #0 ? lcdc 1 m3if_hready_m1 o ahb access completion strobe to master #1 ? fec 1 m3if_hready_m2 o ahb access completion strobe to master #2 emma 1 m3if_hready_m3 o ahb access completion strobe to master #3 max 1 m3if_hready_m4 o ahb access completion strobe to master #4 ? h264 1 m3if_hready_m5 o ahb access completion strobe to master #5 ? h264 1 m3if_hready_m6 o ahb access completion strobe to master #6 ? h264 1 m3if_hready_m7 o ahb access completion strobe to master #7 ? usbotg 1 m3if_hresp_m0 o ahb error response to master #0 ? lcdc 0 m3if_hresp_m1 o ahb error response to master #1 ? fec 0 m3if_hresp_m2 o ahb error response to master #2 emma 0 m3if_hresp_m3 o ahb error response to master #3 max 0 m3if_hresp_m4 o ahb error response to master #4 ? h264 0 m3if_hresp_m5 o ahb error response to master #5 ? h264 0 m3if_hresp_m6 o ahb error response to master #6 ? h264 0 m3if_hresp_m7 o ahb error response to master #7 ? usbotg 0 m3if_hrdata_m0[63:0] o ahb read data bus to master #0 ? lcdc 0 m3if_hrdata_m1[63:0] o ahb read data bus to master #1 ? fec 0 m3if_hrdata_m2[63:0] o ahb read data bus to master #2 emma 0 m3if_hrdata_m3[31:0] o ahb read data bus to master #3 max 0 m3if_hrdata_m4[63:0] o ahb read data bus to master #4 ? h264 0 table 15-2. external memory interface i/o mux description (continued) memory controller outputs emi output ic pin name sdramc mddrc pcmcia weim nfc external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-22 freescale semiconductor m3if_hrdata_m5[63:0] o ahb read data bus to master #5 ? h264 0 m3if_hrdata_m6[63:0] o ahb read data bus to master #6 ? h264 0 m3if_hrdata_m7[31:0] o ahb read data bus to master #7 ? usbotg 0 m3if and esdctl/mddrc outputs ipp_do_sdrc_sdcke[1:0] o sdram/mddr clock enable 0 m3if_dqm[3:0] o sdram data mask strobes. dqm0 corresponds to dq0?dq7, dqm1 corresponds to dq8?dq15, dqm2 corresponds to dq16?dq23 and dqm3 corresponds to dq24?dq31. 0 dqs_out[3:0] o mddr data sample strobes for write accesses. dqs0 corresponds to dq0?dq7, dqs1 corresponds to dq8?dq15, dqs2 corresponds to dq16?dq23 and dqs3 corresponds to dq24?dq31. 0 dqs_out_en_x o dqs output enable strobe 0 m3if_ma[13:0] o sdram/mddr address bits 0 m3if_ba[1:0] o sdram/mddr bank address bits 0 ipp_do_m3if_ma10 o sdram/mddr address bit a10 0 m3if_cs_b[1:0] o sdram/mddr chip select strobe 3 cas_b o sdram/mddr cas strobe 1 ras_b o sdram/mddr ras strobe 1 we_b o sdram/mddr we strobe 1 m3if_choosen_master[2:0] o m3if arbitration chosen master (for debug) 3 ipp_do_sdrc_sdclk o sdram/mddr clock (up to 133mhz) 0 ipp_do_mddr_sd_clk_b o mddr clock (up to 133mhz) 0 lpack o low power mode acknowledge ? toward ccm 1 sdrc_sf_wack o memory wakeup acknowledge indication to wdog 0 nfc outputs ipp_do_nfc_write_data_o ut[15:0] o nfc write data out toward i/o mux/pads. 0 ipi_int_nfc_b 0 nfc interrupt (indicating an access completion) 1 ipp_nfc_ale_out o nfc out nf_ale 0 ipp_nfc_ce_out o nfc out nf_ce 0 ipp_nfc_cle_out o nfc out nf_cle 0 ipp_nfc_re_out o nfc out nf_re 0 ipp_nfc_we_out o nfc out nf_we 0 ipp_nfc_wp_out o nfc out nf_wp 0 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-23 weim outputs ipp_do_weim_cs_b0 o weim cs0 chip select toward i/o mux/pads 1 ipp_do_weim_cs_b1 o weim cs1 chip select toward i/o mux/pads 1 ipp_do_weim_cs_b2_csd0 o weim cs2 or esdctl/mddrc csd0 chip select toward i/o mux/pads 1 ipp_do_weim_cs_b3_csd1 o weim cs2 or esdctl/mddrc csd1 chip select toward i/o mux/pads 1 ipp_do_weim_cs_b4 o weim cs4 chip select toward i/o mux/pads 1 ipp_do_weim_cs_b5 o weim cs5 chip select toward i/o mux/pads 1 ipp_do_weim_bclk o weim burst clock 0 ipp_do_lba_b o weim load burst address (lba) 1 ipp_do_weim_rw_b o weim read/write strobe 1 pcmcia outputs ipi_int_bvd1_b o bvd1 changed interrupt 1 ipi_int_bvd2_b o bvd2 changed interrupt 1 ipi_int_cd1_b o cd1 changed interrupt 1 ipi_int_cd2_b o cd2 changed interrupt 1 ipi_int_err_b o access error interrupt 1 ipi_int_irq_b o or of all the ready interrupts 1 ipi_int_nfc_b o nfc interrupt (indicating an action completed) 1 ipi_int_pcmcia_b o or of all the interrupts (status+access+ready) 1 ipi_int_poweron_b o power_on changed interrupt 1 ipi_int_rdy_f_b o rdy negedge interrupt 1 ipi_int_rdy_h_b o rdy is high interrupt 1 ipi_int_rdy_l_b o rdy is low level sensitive interrupt 1 ipi_int_rdy_r_b o rdy posedge sensitive interrupt 1 ipi_int_sts_b o or of all the status interrupts 1 ipi_int_vs1_b o vs1 changed interrupt 1 ipi_int_vs2_b o vs2 changed interrupt 1 ipi_int_wp_b o wp changed interrupt 1 ipp_do_card_poe_o o poe si gnal to transceivers 0 ipp_do_card_reset_o o reset signal to card 0 ipp_do_card_rw_b o rw_b signal to data transceiver 1 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-24 freescale semiconductor ipp_do_spkr_out_o o speaker out 0 global outputs m3if_dma_access o snooping detection indication toward ipu module 0 ipp_obe_ddr_en o mddr active indication to esdctl/mddrc data pads 0 ipp_do_emi_addr[25:0] o emi address out toward i/o mux/pads 0 ipp_do_nfc_write_data_o ut[15:0] o emi data (nfc, weim) out toward i/o mux/pads 0 ipp_do_emi_data[31:0] o emi sdram/ddr data out toward i/o mux/pads 0 ipp_obe_emi_data_dir o emi sdram/ddr data direction toward i/o mux/pads 0 ipp_obe_nfc_dir_high o emi (nfc, weim, pcmcia) data direction toward i/o mux/pads 0 ipp_obe_nfc_dir_low o emi (nfc, weim, pcmcia) data direction toward i/o mux/pads 0 ipp_do_sdba[1:0] o sdram/mddr bank address toward i/o mux/pads 0 ipp_do_m3if_ma10 o sdram/mddr address bit ma10 toward i/o mux/pads 0 ipp_do_emi_io_dqm[3:0] o sdram/mddr enable bytes toward i/o mux/pads 0 ipp_do_emi_oe_b o emi output enable toward i/o mux/pads 0 ipp_obe_io_addr_dir[1:0] o emi output enable (dir) toward i/o addr/weim muxed data mux/pads 0 ahb interface inputs m3if_haddr_m0[31:0] i ahb address bus from master #0 ? lcdc 0 m3if_haddr_m1[31:0] i ahb address bus from master #1 ? fec 0 m3if_haddr_m2[31:0] i ahb address bus from master #2 emma 0 m3if_haddr_m3[31:0] i ahb address bus from master #3 max 0 m3if_haddr_m4[31:0] i ahb address bus from master #4 ? h264 0 m3if_haddr_m5[31:0] i ahb address bus from master #5 ? h264 0 m3if_haddr_m6[31:0] i ahb address bus from master #6 ? h264 0 m3if_haddr_m7[31:0] i ahb address bus from master #7 ? usbotg 0 m3if_hwdata_m0[63:0] i ahb write data bus (bit) from master #0 ? lcdc 0 m3if_hwdata_m1[63:0] i ahb write data bus (bit) from master #1 ? fec 0 m3if_hwdata_m2[63:0] i ahb write data bus (32 bit) from master #2 emma 0 m3if_hwdata_m3[31:0] i ahb write data bus (32 bit) from master #3 max 0 m3if_hwdata_m4[63:0] i ahb write data bus (32 bit) from master #4 ? h264 0 m3if_hwdata_m5[63:0] i ahb write data bus (32 bit) from master #5 ? h264 0 m3if_hwdata_m6[63:0] i ahb write data bus (32 bit) from master #6 ? h264 0 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-25 m3if_hwdata_m7[31:0] i ahb write data bus (32 bit) from master #7 ? usbotg 0 m3if_hburst_m0[2:0] i ahb burst size bus from master #0 ? lcdc 0 m3if_hburst_m1[2:0] i ahb burst size bus from master #1 ? fec 0 m3if_hburst_m2[2:0] i ahb burst size bus from master #2 emma 0 m3if_hburst_m3[2:0] i ahb burst size bus from master #3 max 0 m3if_hburst_m4[2:0] i ahb burst size bus from master #4 ?h264 0 m3if_hburst_m5[2:0] i ahb burst size bus from master #5 ? h264 0 m3if_hburst_m6[2:0] i ahb burst size bus from master #6 ? h264 0 m3if_hburst_m7[2:0] i ahb burst size bus from master #7 ? usbotg 0 m3if_hsize_m0[1:0] i ahb data transfer width bus from master #0 ? lcdc 0 m3if_hsize_m1[1:0] i ahb data transfer width bus from master #1 ? fec 0 m3if_hsize_m2[1:0] i ahb data transfer width bus from master #2 emma 0 m3if_hsize_m3[1:0] i ahb data transfer width bus from master #3 max 0 m3if_hsize_m4[1:0] i ahb data transfer width bus from master #4 ? h264 0 m3if_hsize_m5[1:0] i ahb data transfer width bus from master #5 ? h264 0 m3if_hsize_m6[1:0] i ahb data transfer width bus from master #6 ?h264 0 m3if_hsize_m7[1:0] i ahb data transfer width bus from master #7 ?usbotg 0 m3if_hbstrb_m0[7:0] i byte lane (8) bus from master #0 ? lcdc 0 m3if_hbstrb_m1[7:0] i byte lane (8) bus from master #1 ? fec 0 m3if_hbstrb_m2[7:0] i byte lane (4) bus from master #2 emma 0 m3if_hbstrb_m3[3:0] i byte lane (4) bus from master #3 max 0 m3if_hbstrb_m4[7:0] i byte lane (4) bus from master #4 ? h264 0 m3if_hbstrb_m5[7:0] i byte lane (4) bus from master #5 ? h264 0 m3if_hbstrb_m6[7:0] i byte lane (4) bus from master #6 ? h264 0 m3if_hbstrb_m7[3:0] i byte lane (4) bus from master #7 ? usbotg 0 m3if_htrans_m0[1:0] i ahb transfer state bus from master #0 ? lcdc 0 m3if_htrans_m1[1:0] i ahb transfer state bus from master #1 ? fec 0 m3if_htrans_m2[1:0] i ahb transfer state bus from master #2 emma 0 m3if_htrans_m3[1:0] i ahb transfer state bus from master #3 max 0 m3if_htrans_m4[1:0] i ahb transfer state bus from master #4 ? h264 0 m3if_htrans_m5[1:0] i ahb transfer state bus from master #5 ? h264 0 m3if_htrans_m6[1:0] i ahb transfer state bus from master #6 ? h264 0 m3if_htrans_m7[1:0] i ahb transfer state bus from master #7 ? usbotg 0 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-26 freescale semiconductor m3if_hwrite_m0 i ahb read/write signal from master #0 ? lcdc 0 m3if_hwrite_m1 i ahb read/write signal from master #1 ? fec 0 m3if_hwrite_m2 i ahb read/write signal from master #2 emma 0 m3if_hwrite_m3 i ahb read/write signal from master #3 max 0 m3if_hwrite_m4 i ahb read/write signal from master #4 ? h264 0 m3if_hwrite_m5 i ahb read/write signal from master #5 ? h264 0 m3if_hwrite_m6 i ahb read/write signal from master #6 ? h264 0 m3if_hwrite_m7 i ahb read/write signal from master #7 ? usbotg 0 m3if_hprot_m0 i ahb protection mode signal from master #0 ? lcdc 0 m3if_hprot_m1 i ahb protection mode signal from master #1 ? fec 0 m3if_hprot_m2 i ahb protection mode signal from master #2 emma 0 m3if_hprot_m3 i ahb protection mode signal from master #3 max 0 m3if_hprot_m4 i ahb protection mode signal from master #4 ? h264 0 m3if_hprot_m5 i ahb protection mode signal from master #5 ? h264 0 m3if_hprot_m6 i ahb protection mode signal from master #6 ?h264 0 m3if_hprot_m7 i ahb protection mode signal from master #7 ?usbotg 0 m3if_hunalign_m0 i unalign access signal from master #0 ? lcdc 0 m3if_hunalign_m1 i unalign access signal from master #1 ? fec 0 m3if_hunalign_m2 i unalign access signal from master #2 emma 0 m3if_hunalign_m3 i unalign access signal from master #3 max 0 m3if_hunalign_m4 i unalign access signal from master #4 ? h264 0 m3if_hunalign_m5 i unalign access signal from master #5 ? h264 0 m3if_hunalign_m6 i unalign access signal from master #6 ? h264 0 m3if_hunalign_m7 i unalign access signal from master #7 ? usbotg 0 m3if and esdctl/mddrc inputs m3if_hclk i m3if ahb system clock?up to 133 mhz 0 hclk32 i 32 khz clock for esdctl refresh counter 0 ipp_ind_sdrc_sdclk_fb i sdram/mddr feedback clock (up to 133mhz) 0 lpmd i low power mode indication signal, ?0?=stop, ?1?=run. 1 dqs_in[3:0] i mddr data sample strobes for read accesses. dqs0 corresponds to dq0?dq7, dqs1 corresponds to dq8?dq15, dqs2 corresponds to dq16?dq23 and dqs3 corresponds to dq24?dq31. 0 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-27 sdctl_csd0_sel_b i sdram/mddr csd0 select multiplexed with cs2 (configurable via the system control register, fmcr) 0 sdctl_csd1_sel_b i sdram/mddr csd1 select multiplexed with cs3 (configurable via the system control register, fmcr) 0 nfc inputs nf16_boot_b i boot mode source is 16 bit nand flash memory. application dependent nf8_boot_b i boot mode source is 8 bit nand flash memory. application dependent nf_16bit_sel i 16 bit nand flash memory is use indication. 0 nfc_hclk i nfc ahb input clock 0 nfc_rd_oe i nfc read output enable ? controls the direction of data bus 0 nfc_wr_oe i nfc write output enable ? controls the direction of data bus 0 ipp_ind_flash_clk i nand flash side clock with period of 40ns 0 ipp_ind_nfc_rb_in i nfc in nf_rb 0 weim inputs weim_boot_cfg[3:0] i weim bootmode select (from ccm) ?101? - 16 bit cs0 at d[15:0] application dependent ipp_ind_weim_ecb_b i weim end current burst 1 weim_hclk i weim ahb input clock 0 ipp_ind_weim_dtack_b i external dtack acknowledge 1 pcmcia inputs ipp_ind_cd_b_i[1:0] i cd[1:0] signals from card 3 ipp_ind_vs_i[1:0] i vs[1:0] signals from card 0 ipp_ind_bvd1_stsch_b_i i bvd1/stschg signals from card 0 ipp_ind_bvd2_spkr_i i bvd2/spkr signals from card 0 ipp_ind_pwr_on_i i power_on signals from card/board 0 ipp_ind_rdy_irq_b_i i ready/irq_b signals from card 1 ipp_ind_wp_i i wp signals from card 1 global inputs ipp_ind_resetb i reset signal 1 hreset_hclk_b i reset signal 1 ipp_ind_nfc_read_data_in[ 15:0] i external memories (non sdram) read data in from i/o mux/pads 0 ipp_ind_emi_data_in[31:0] i emi sdram/ddr data in from i/o mux/pads 0 table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-28 freescale semiconductor 15.8 memory map and register definitions the emi supports four memory controllers. table 15-4 and table 15-5 illustrates the emi registers and memory map (mapped by all memory controllers). for de tailed descriptions regarding registers definitions and memory map, refer to the releva nt module chapters in this manual. ipp_ind_addr_in[15:0] i emi weim muxed data in from i/o mux/pads. weim/nfc/pcmcia address out to i/o mux/pads. 0 ipp_ind_emi_data_in[31:0] i sdram/mddr read data in from i/o mux/pads 0 m3if_bigend_m0 i endian mode signal from master #0 ? lcdc master dependent m3if_bigend_m1 i endian mode signal from master #1 ? fec master dependent m3if_bigend_m2 i endian mode signal from master #2 emma master dependent m3if_bigend_m3 i endian mode signal from master #3 max master dependent m3if_bigend_m4 i endian mode signal from master #4 ? h264 master dependent m3if_bigend_m5 i endian mode signal from master #5 ? h264 master dependent m3if_bigend_m6 i endian mode signal from master #6 ? h264 master dependent m3if_bigend_m7 i endian mode signal from master #7 ? usbotg master dependent table 15-4. emi registers definition address use access m3if registers space 0xd800_3000?0xd800_3fff m3if registers space (4k) read/write esdctl/mddrc registers space 0xd800_1000?0xd800_1fff esdctl/mddrc registers space (4k) read/write pcmcia registers space 0xd800_4000?0xd800_4fff pcmcia registers space (4k) read/write weim registers space 0xd800_2000?0xd800_2fff weim registers space (4k) read/write nfc memory space 0xd800_0e00?0xd800_0fff nfc registers space read/write table 15-3. emi signal properties (continued) name port function reset state external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 15-29 1. can be used as a boot memory region. table 15-5. emi memory map address use access esdctl/mddrc memory space 0xa000_0000?0xafff_ffff csd0 sdram/mddr memory region (256 mbytes) read/write 0xb000_0000?0xbfff_ffff csd1 sdram/mddr memory region (256 mbytes) read/write pcmcia memory space 0xdc00_0000?0xdcff_ffff pcmcia/cf memory region (64 mbytes) read/write weim memory space 0xc000_0000?0xc7ff_ffff weim cs0 memory region 1 (128 mbytes) read/write 0xc800_0000?0xcfff_ffff weim cs1 memory region (128 mbytes) read/write 0xd000_0000?0xd1ff_ffff weim cs2 memory region (32 mbytes) read/write 0xd200_0000?0xd3ff_ffff weim cs3 memory region (32 mbytes) read/write 0xd400_0000?0xd5ff_ffff weim cs4 memory region (32 mbytes) read/write 0xd600_0000?0xd7ff_ffff weim cs5 memory region (32 mbytes) read/write nfc memory space 0xd800_0000?0xd800_0fff nfc memory region 1 (4k, nand flash) read/write external memory interface (emi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 15-30 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-1 chapter 16 multi-master memory interface (m3if) the m3if controls memory accesses (read/write/e rase/program) from one or more masters through different port interfaces to different external memory controllers esdctl/mddrc, pcmcia, nand flash, and weim. figure 16-1 provides top-level diagram that shows the functional organization of the block. 16.1 overview the m3if-esdctl/mddrc interface is optimized and designed to reduce access latency by generating multiple accesses through the dedicated esdctl/mdd rc arbitration (mab) module, which controls the access to/from the enhanced sdram/mddr memory controller. for the other port interfaces, the m3if only arbitrates and forwards the master requests rece ived through the master port gasket (mpg) interface and m3if arbitration (m3a) module toward the respec tive memory controller. the masters that interface with the m3if include the arm platform, sdma, mpeg-4 encoder, and the ipu. the controllers are the esdctl/mddrc, pcmcia, nand flash, and weim. when a master requests a memory access, the access is immediately taken by the m3if if no other access is in progress. the m3if forwards the access to th e respective memory controller (slave), and depending on the state of the respective memory controller, a command to the memory is generated. if the access cannot be started due to a previous active access, the master request remains pending (hready held negated) until it is executed by the memory contro ller. when the access execution is complete, the hready is asserted and a new request can be processed. accesses to sdram or mddr external devices are optimized through command anticipation (mif2 strategy). for example, the next access control phase (memory address and command) is driven during the previous access data phase (data flow to/from the me mory), thus an overlap between accesses is created and latency is partially or fully hidden. 16.1.1 m3if interfaces the interface between m3if and the controllers can be divided into two different types: m3if-esdctl, and m3if-all others. the m3if-esdctl/mddrc in terface reduces access latency by generating multiple accesses using the dedicated esdctl/md drc arbitration (mab) module. for other port interfaces, m3if arbitrates and forwards the masters? requests received through the master port gasket (mpg) interfaces and the m3if arbitration (m3a) m odule toward the respective memory controller. to support multiple accesses to the esdctl/mddrc, the mab includes a fifo which controls the access traffic from/to the esdctl/mddrc. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-2 freescale semiconductor figure 16-1. m3if block diagram?system overview arbitration and master multi master memory interface (m3if) module m3if arbitration (sdctl) (m3a) (mab) nfc ctrl weim sdram/lp ddr pcmcia nand flash sram flash m3if registers max application (arm) platform s2 m2 m3 m5 a/p rtic/ dma 64 64 32 64 32 mpg64 #5 mpg64 #4 mpg64 #6 mpg #3 mpg64 #0 mpg64 #1 mpg #7 ctrl pcmcia ctrl esdctl mddrc via emi and io muxes sahara2 usbotg m4 h264-ahb h264-po h264-po h264-po mpg64 #2 lcdc slcdc tmax fec emma-it 64 64 64 buffering multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-3 m3if can be viewed as a device that has multiple sdram/mddr controllers and one controller per other memory type, therefore, the m3a arbitrates the requests as follows: ? a round robin chooses the next master that is going to grant the bus: ? if this master is requesting access to non-sdram/mddr memory controller, m3a waits until the previous access finishes and only then passes the request. ? if the master is requesting access to esdctl/m ddrc, m3if arbitration passes the access to mab in two cases: ? after previous non-esdctl access is accomplished. ? if previous access was to esdctl, m3if ar bitration will pass the request immediately without waiting for the previous access to accomplished. m3if arbitration (m3a) and the esdctl/mddrc mast er arbitration and buffering (mab) supports a round-robin arbitration scheme (which can be programed to non-equal probability). if two masters request access to the memory port on the same cycle the master with the token (see section 16.4.3.2, ?m3a?find first 1 (ff1) algorithm? for more details) gains control on the bus to the slave. to support multiple accesses to the esdctl/mddrc, the mab includes a fifo which controls the access traffic from/to the esdctl/mddrc. once a master grants the bus, the memory controller gaining the access converts the access to a command to the specified memory. 16.1.2 features m3if master port gasket (mpg) converts the master re quest (data write, data rea d, address, and controls) to a set of bus/signals that the m3if arbitra tion, the sdctl/mddrc arbitration, and other memory controllers need. the mpg is also responsible to gi ve the right response to the master after getting the response from the relevant memory controller. m3if support 2 port interfaces (the number and types of gasket ports used depends on the system requirements): mpg?master port gasket for arm9 amba-ahb lit e with 32 bit data bus.mpg64?master port gasket for amba-ahb lite with 64 bit data bus.the m3if includes these distinctive features: ? supports multiple requests from masters through 2 different input port interfaces: ? master port gasket (mpg)?arm9 amba ahb lite bus protocol. ? master port gasket (mpg64)?amba ahb acce ss with 64 bits data bus width.arbitrates requests to four different memory controllers (that share some of their i/o pads) ? enhanced sdram controller (esdctl) or mddr controller (mddrc) ? nand flash controller?(nfc) ? pcmcia controller?wireless external interface memory (weim) controller ? multiple requests capabilities to esdctl th rough a dedicated arbitration mechanism. ? flexible round robin access arbitration, with equal priority or 50% priority to selective masters. ? programmable master that cont rols (lock) accesses to sdra m/ddr and programmable master that controls (lock) accesses to other memories (= general: nfc, weim, pcmcia). ? multi-endianness support to all memory controllers. ? supports memory snooping, an example of which would be monitoring a region in external memory for write accesses: multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-4 freescale semiconductor ? the region?s location is specified by a base a ddress (from 2 kb up to 16 mb), which is divided into 64 equal segments. ? each segment has an access status and enable bit in the m3if register definition. ? m3if generates a one cycle dma_access for each snooping detection. 16.2 external signal description 16.2.1 overview this section discusses input and output signals betwee n the m3if, masters, and the memory controllers. table 16-1 summarizes the interface signals, and is followe d by a detailed descripti on of signal functions. interconnect and timing diagrams are included as part of the detailed discussion on controller operation in section 16.4, ?functional description.? detailed m3if sub-block diagrams are shown in figure 16-11 and figure 16-19 . table 16-1. m3if signal properties name port function reset state m3if_hrdata_m#[63:0] o read data to master 0 m3if_hready_m# o access completion strobe to master 1 m3if_hresp_m# o error response to master 0 htrans[1:0] o transfer state bus to memory controllers 0 hprot o protection mode signal to memory controllers 0 hwdata[31:0] o write data bus to memory controllers 0 haddr[31:0] o address bus to memory controllers 0 hburst[2:0] o burst size bus to memory controllers 0 hsize[1:0] o data transfer width bus to memory controllers 0 hwrite o read/write signal to memory controllers 0 hbstrb[3:0] o byte lane bus to memory controllers 0 hunalign o unalign signal to memory controllers 0 bigendian o big/little endian signal (internal) to memory controllers system dependent dvfs_grant o m3if acknowledge to ccm, indicating that m3if is ready for frequency changes (dvfs activation) 0 ma10_share o ma10 share indication toward emi 0 m3if_guard_2_pcmcia o assert high during active esdctl/mddrc/nfc/weim request execution 0 m3if_guard_2_eim o assert high during active esdctl/mddrc/nfc/pcmcia request execution 0 eim_pcmcia_active o assert high during request/active weim/pcmcia access execution 0 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-5 chosen_slave[1:0] o num of slave to be activated 0 dma_access o snooping detected strobe 0 m3if_chosen_master[2:0] o reflects the current master number that has ownership on the external data bus (to/from memories). 0 hclk i ahb system clock (up to 133 mhz) 0 hclk32 i 32 khz clock (use for sdram/mddr refresh) 0 m3if_haddr_m# 1 [31:0] i address bus from master 0 m3if_hwdata_m#[63:0] i write data bus from master 0 m3if_hburst_m#[2:0] i burst size bus from master 0 m3if_hsize_m#[1:0] i data transfer width bus from master 0 m3if_hbstrb_m#[7:0] i byte lane bus from master 0 m3if_htrans_m#[1:0] i transfer state bus from master 0 m3if_hwrite_m# i read/write signal from master 0 m3if_hprot_m# i protection mode signal from master 0 m3if_hunalign_m# i unalign access signal from master 0 m3if_hmastlock_m# i hmasterlock access indication from master 0 m3if_bigend_m# i big/little endian signal specific/dedicated from each master connected to m3if mpg system dependent hready_eim i eim controller ready signal 1 hready_pcmcia i pcmcia controller ready signal 1 hready_nf i nf controller ready signal 1 hresp_eim i eim controller error response signal 0 hresp_pcmcia i pcmcia controller error response signal 0 hresp_nf i nf controller error response signal 0 hrdata_eim i read data bus from eim controller 0 hrdata_pcmcia i read data bus from pcmcia controller 0 hrdata_nf i read data bus from nf controller 0 reset i reset signal 1 eim_guard i assert high during weim write burst access to psram external memory 0 nf_active i assert high during nfc page fetch 0 dvfs_req i ccm request signal to m3if, indicating ccm frequency change is pending for acknowledge (dvfs algorithm) 0 1 signals names with suffix ?_m#?, states for master number. the number of masters in use is system architecture de- pendent. table 16-1. m3if signal properties (continued) name port function reset state multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-6 freescale semiconductor 16.3 memory map and register definition m3if programming model consists of two classes of registers, m3if control and lock registers and snooping configuration and status registers as shown in table 16-2 . the control and master lock general register defines the m3if configurable logic functi onality. the configuration and status registers set and monitor snooping activity. all m3if registers are 32-bits in length with bit fields defined in figure 16-3 to figure 16-10 . all implemented bits are fully readable and writable in supervisor mode only (an error response will be generated in case of user mode access to m3if registers). all m3if (and esdctl) registers can be accessed only by a single word (32- bit) access, through the ahb bus protocol. accesses of any other size or type will cause an undetermined behavior. all registers can be accessed by only one master at a time. multi access to m3if register causes undetermined behavior. the only exception is m3if master lock general register can be accessed by more than one master at a time. the reset state of each bit is shown underneath the bit field name. an asterisk indicates that the value is dependent on th e operating mode selected during reset. details are provided in the following bit field descriptions. 16.3.1 memory map m3if supports four different memory controllers. e ach memory controller defines a specific memory address mapped as shown in table 16-2 . table 16-3 shows the m3if memory space summary. table 16-2. m3if memory map address register access reset value section/page 0xd800_3000 (m3ifctl) m3if control register r/w 0x0000_0000 16.3.3.1/16-10 0xd800_3028 (m3ifscfg0) m3if snooping configuration register 0 r/w 0x0000_0000 16.3.3.2/16-12 0xd800_302c (m3ifscfg1) m3if snooping configuration register 1 r/w 0x0000_0000 16.3.3.3/16-13 0xd800_3030 (m3ifscfg2) m3if snooping configuration register 2 r/w 0x0000_0000 16.3.3.3/16-13 0xd800_3034 (m3ifssr0) m3if snooping status register 0 r/w 0x0000_0000 16.3.3.4/16-14 0xd800_3038 (m3ifssr1) m3if snooping status register 1 r/w 0x0000_0000 16.3.3.4/16-14 0xd800_3040 (m3ifmlwe0) m3if master lock weim cs0 register r/w 0x0000_0000 16.3.3.5/16-16 0xd800_3044 (m3ifmlwe1) m3if master lock weim cs1 register r/w 0x0000_0000 16.3.3.5/16-16 0xd800_3048 (m3ifmlwe2) m3if master lock weim cs2 register r/w 0x0000_0000 16.3.3.5/16-16 0xd800_304c (m3ifmlwe3) m3if master lock weim cs3 register r/w 0x0000_0000 16.3.3.5/16-16 0xd800_3050 (m3ifmlwe4) m3if master lock weim cs4 register r/w 0x0000_0000 16.3.3.5/16-16 0xd800_3054 (m3ifmlwe5) m3if master lock weim cs5 register r/w 0x0000_0000 16.3.3.5/16-16 table 16-3. m3if memory space summary address use access esdctl/mddrc memory space 0xa000_0000?0xafff_ffff csd0 sdram or mddr memory region (256 mbyte) read/write multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-7 1 can be used as a boot memory region. 16.3.2 register summary figure 16-2 shows the key to the register fields and table 16-4 shows the register figure conventions. figure 16-2. key to register fields 0xb000_0000?0xbfff_ffff csd1 sdram or mddr memory region (256 mbyte) read/write weim memory space 0xc000_0000?0xc7ff_ffff weim cs0 memory region (128 mbyte) read/write 0xc800_0000?0xcfff_ffff weim cs1 memory region (128 mbyte) read/write 0xd000_0000?0xd1ff_ffff weim cs2 memory region (32 mbyte) read/write 0xd200_0000?0xd3ff_ffff weim cs3 memory region (32 mbyte) read/write 0xd400_0000?0xd5ff_ffff weim cs4 memory region (32 mbyte) read/write 0xd600_0000?0xd7ff_ffff weim cs5 memory region (32 mbyte) read/write nfc memory space 0xd800_0000?0xd800_0fff nand flash memory region 1 (4 kbyte) read/write pcmcia memory space 0xdc00_0000?0xdfff_ffff pcmcia memory region (64 mbyte) read/write always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 16-4. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. table 16-3. m3if memory space summary (continued) address use access multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-8 freescale semiconductor table 16-5 shows the m3if register summary. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 16-5. m3if register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141312 1110987654 3 210 0xd800_3000 (m3ifctl) rsda 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 000 mlsd _en mlsd mrrp w 0xd800_3028 (m3ifscfg0) r swba w r swba 0 00 00 0 swsz se w 0xd800_302c (m3ifscfg1) r sse0 w r sse0 w 0xd800_3030 (m3ifscfg2) r sse1 w r sse1 w 0xd800_3034 (m3ifssr0) r sss0 w r sss0 w table 16-4. register figure conventions (continued) convention description multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-9 0xd800_3038 (m3ifssr1) r sss1 w r sss1 w 0xd800_3040 (m3ifmlwe0) rwem a0 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e0_e n mlwe0 w 0xd800_3048 (m3ifmlwe2) rwem a2 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e2_e n mlwe2 w 0xd800_3048 (m3ifmlwe2) rwem a2 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e2_e n mlwe2 w 0xd800_304c (m3ifmlwe3) rwem a3 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e3_e n mlwe3 w 0xd800_3050 (m3ifmlwe4) rwem a4 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e4_e n mlwe4 w table 16-5. m3if register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141312 1110987654 3 210 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-10 freescale semiconductor 16.3.3 register descriptions this section contains detailed regist er descriptions for m3if registers. 16.3.3.1 m3if control register (m3ifctl) m3ifctl contains access status, provides access control to sdram/mddr memory devices and arbitration priority for m3if port masters. the field assignments for this register are shown in figure 16-3 and the field descriptions are listed in table 16-6 . 0xd800_3054 (m3ifmlwe5) rwem a5 0 0 0 0 0 0 0 00 0 00 0 0 0 w r0 0 0 0 0 0 0 0 00 0 0mlw e5_e n mlwe5 w 0xd800_3000 (m3ifctl) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sda 0 0 0 0 0 0 0 00 0 00 0 0 0 w reset0000000000000000 1514131211109876543210 r 0 0 0 0 mlsd _en mlsd mrrp w reset0000000000000000 figure 16-3. m3if control register table 16-5. m3if register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141312 1110987654 3 210 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-11 table 16-6. m3if control register field descriptions field description 31 sda sdram/mddr memory active. this is a read-only status bit, that if set, indicates that an active/pending access to sdram/mddr memory exists. the sda bit will be set on one of the following conditions: mlsd_en cleared?any active/pending access to sdram/mddr memory space will set the bit (until the access is completed). mlsd_en is set?any accesses to sdram/mddr memory space initiated previously to mlsd_en assertion, will keep the sda status bit set. the bit will clear after all pending/active accesses execution is completed. access from master number equal to mlsd field will not assert the status bit. note: when mlsd_en is set, any new accesses (initiated after mlsd_en assertion) to sdram/mddr not from mlsd master will be pending without setting sda to 1. only the sdram/mddr memory space region will be lock to the mlsd port. accesses to m3if/esdctl registers are available to all masters in the system and its system/software responsibility not to access those registers during lock period. 0 no active/pending access to sdram/mddr memory exists. 1 indicates an active/pending access to sdram/mddr memory exists. 30?12 reserved 11 mlsd_en master lock sdram/mddr access. this bit enables the master control sdram/mddr access (mlsd). the reset value of this bit is ?0?. 0 master control sdram/mddr access (mlsd) disabled. 1 master control sdram/mddr access (mlsd) enabled. 10?8 mlsd master lock sdram/mddr access. this 3-bit field defines the master port number (mpg) that will be the only master in the system that will be served by the sdram/mddr controller. all accesses toward the sdram/mddr from the other masters will be postponed, until the mlsd master will clear mlsd_en bit. the reset value of the mlsd is ?0?. note: accesses to esdctl registers are not effected by the mlsd field. for example, they can be accessed by any master even if mlsd_en is set. 10?8 mlsd prior to lock accesses, the mlsd master should perform the following steps: 1. set mlsd_en bit and mlsd field (with the desired value) in the m3ifctl register. 2. read m3ifctl register and check: 3. sda status bit is cleared (no pending/active access to sdram/mddr memory space exists). 4. mlsd_en bit is set. 5. mlsd (value) points to the required port number (master port number that requires lock access). 000 master port gasket 0 001 master port gasket 1 010 master port gasket 2 011 master port gasket 3 100 master port gasket 4 101 master port gasket 5 110 master port gasket 6 111 master port gasket 7 7?0 mrrp master round robin priority. mrrp field is an 8-bit field with one bit per master (bit #i to master #i). masters with their mrrp bit set are added to a priority arbitration ?list? so that together they will have 50% probability to gain access through both m3a and mab arbitration processes (50% probability for each one of the arbitration separately). assertion of mrrp bit for an unused master is forbidden. if all mrrp bits are cleared the masters will have equal probability to pass the arbitration processes. for more details about the m3if arbitration see section 16.4.3.2, ?m3a?find first 1 (ff1) algorithm.? 0 the respective master is not on the priority arbitration ?list?. 1 add respective master to priority arbitration ?list? with a 50% probability to pass the arbitration processes. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-12 freescale semiconductor 16.3.3.2 m3if snooping configuration register 0 (m3ifscfg0) m3ifscfg0 register contains the snooping window ba se address, the size of snooping window and the snooping control bit fields which are used by the m3if to monitor the write access. the snooping feature is described in detail in section 16.4.5, ?snooping logic.? the field assignments for this register are shown in figure 16-5 and the field descriptions are listed in table 16-7 . 0xd800_3028 (m3ifscfg0) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r swba w reset0000000000000000 1514131211109876543210 r swba 0 00 00 0 swsz se w reset0000000000000000 figure 16-5. m3if snooping configuration register 0 (m3ifscfg0) table 16-7. m3if snooping configuration register 0 field descriptions field description 31?11 swba snooping window base address. this field defines the snooping window base address to be monitored by the m3if. m3if monitors write accesses to the memory region above the base address window. 10?5 reserved 4?1 swsz snooping window size. this field define the snooping window size as described in table 16-8 . 0 se snooping enable. this bit enables snooping detection. the m3if monitors and detects write accesses to the snooping window. 0 snooping feature is disabled. 1 snooping feature is enabled. table 16-8. swsz field descriptions swsz snooping window size window base address bits window address bits in use 0000 2 kbyte [31:11] [10:0] 0001 4 kbyte [31:12] [11:0] 0010 8 kbyte [31:13] [12:0] 0011 16 kbyte [31:14] [13:0] 0100 32 kbyte [31:15] [14:0] multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-13 16.3.3.3 m3if snooping configuration register 1?2 (m3ifscfg1?2) m3ifscfg1 register contains enable bits for lower 32 segments [31:0] in m3ifscfg0 register. m3ifscfg2 register contains enable bits for upper 32 segments [63:32] in m3ifscfg0 register. snooping feature is described in detail in section 16.4.5, ?snooping logic.? the field assignments for these register are shown in figure 16-6 and figure 16-7 and the field descriptions are listed in table 16-9 . 0101 64 kbyte [31:16] [15:0] 0110 128 kbyte [31:17] [16:0] 0111 256 kbyte [31:18] [17:0] 1000 512 kbyte [31:19] [18:0] 1001 1 mbyte [31:20] [19:0] 1010 2 mbyte [31:21] [20:0] 1011 4 mbyte [31:22] [21:0] 1100 8 mbyte [31:23] [22:0] 1101 16 mbyte [31:24] [23:0] 1110 reserved ? ? 1111 reserved ? ? 0xd800_302c (m3ifscfg1) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sse0 w reset0000000000000000 1514131211109876543210 r sse0 w reset0000000000000000 figure 16-6. m3if snooping configuration register 1 (m3ifscfg1) table 16-8. swsz field descriptions (continued) swsz snooping window size window base address bits window address bits in use multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-14 freescale semiconductor 16.3.3.4 m3if snooping status register 0?1 (m3ifssr0?1) m3ifssr0 register contains the snooping status bits for the lower 32 segments. m3ifssr1 register contains the snooping status bits for the higher 32 segm ents.the snooping feature is described in detail in section 16.4.5, ?snooping logic.? the field assignments for these registers are shown in figure 16-8 and figure 16-9 and the field descriptions are listed in table 16-10 and table 16-11 . 0xd800_3030 (m3ifscfg2) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sse1 w reset0000000000000000 1514131211109876543210 r sse1 w reset0000000000000000 figure 16-7. m3if snooping configuration register 2 (m3ifscfg2) table 16-9. m3if snooping configuration register 1?2 field descriptions field description 31?0 sse0 snooping segment enable 0. this register contains the enable bits for the lower 32 segments [31:0] in the snooping window (defined by the m3ifscfg0 register). if snooping is enabled for segment #x (respective sse0 bit is high), than any write access detected to that segment will set the dma_access for one cycle and the respective snooping status bit will be set. if the sse0 bit is low, and a write access to the respective segment is detected by the m3if, only the relevant status bit in the snooping status register will be set but the dma_access will not be generated. 0 snooping segment #x is disabled. 1 snooping segment #x is enabled. 31?0 sse1 snooping segment enable 1. this register contains the enable bits for the higher 32 segments [63:32] in the snooping window (defined by the m3ifscfg1 register). if snooping is enabled for segment #x (respective sse1 bit is high), than any write access detected to that segment will set the dma_access for one cycle and the respective snooping status bit will be set. if the sse1 bit is low, and a write access to the respective segment is detected by the m3if, only the relevant status bit in the snooping status register will be set but the dma_access will not be generated. 0 snooping segment #x is disabled. 1 snooping segment #x is enabled. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-15 0xd800_3034 (m3ifssr0) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sss0 w reset0000000000000000 1514131211109876543210 r sss0 w reset0000000000000000 figure 16-8. m3if snooping status register 0 (m3ifssr0) table 16-10. m3if snooping status register 0 field descriptions field description 31?0 sss0 snooping segment status 0. this register contains the snooping status bits for the lower 32 segments [31:0] in the snooping window (defined by the m3ifscfg0 register). a bit in the sss0 register is asserted if snooping to the respective segment occurred. note: if snooping occurred the status bit will be updated regardless of the respective snooping segment enable bit sse0[x]. the dma_access will be asserted only if the respective snooping segment enable bit sse0[x] is enabled. 0 snooping for segment #x did not occur. 1 snooping for segment #x occurred. 0xd800_3038 (m3ifssr1) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sss1 w reset0000000000000000 1514131211109876543210 r sss1 w reset0000000000000000 figure 16-9. m3if snooping status register 1 (m3ifssr1) multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-16 freescale semiconductor 16.3.3.5 m3if master lock weim csx register (m3ifmlwex) the field assignments for this register are shown in figure 16-10 and the field descriptions are listed in table 16-12 . table 16-11. m3if snooping status register 1 field descriptions field description 31?0 sss1 snooping segment status 1. this register contains the snooping status bits for the higher 32 segments [63:32] in the snooping window (defined by the m3ifscfg1 register). a bit in the sss1 register is asserted if snooping to the respective segment occurred. note: if snooping occurred the status bit will be updated regardless of the respective snooping segment enable bit sse0[x]. the dma_access will be asserted only if the respective snooping segment enable bit sse1[x] is enabled. 0 snooping for segment #x did not occur. 1 snooping for segment #x has occurred. 0xd800_3040 (m3ifmlwe0) 0xd800_3044 (m3ifmlwe1) 0xd800_3048 (m3ifmlwe2) 0xd800_304c (m3ifmlwe3) 0xd800_3050 (m3ifmlwe4) 0xd800_3054 (m3ifmlwe5) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r wem ax 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 1514131211109876543210 r 0 0 0 0 0 0 0 0 mlg e_en mlge w reset0000000000000000 figure 16-10. m3if lock general register (m3ifmlge) multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-17 16.4 functional description this section provides the functional description for the m3if module. 16.4.1 master port gasket (mpg) mpg is a flexible port gasket. up to 8 masters can be connected to the m3if with any combination of mpg type, which support the following different port types: ? mpg?master port gasket for arm9 amba-ahb lite 32 bits data bus. ? mpg64?master port gasket amba-ahb lite 64 bits data bus table 16-12. m3if lock general register field descriptions field description 31 wemax weim csx (0-) memory active. this is a read-only status bit, that if set indicates that an active/pending access to a weim csx memory exists. the weimx bit is set on one of the following conditions: mlwex_en cleared?any active/pending access to weim csx memory space will set the bit (until the access is completed). mlwex_en is set?any accesses to weim csx memory space initiated previously to mlwex_en assertion, will keep the wemax status bit set. the bit clears after all pending/active accesses execution is completed. access from master number equal to mlwex field does not assert the status bit. note: when mlwex_en is set, any new accesses (initiated after mlwex_en assertion) to weim csx memories (or to m3ifmlwex register) not from mlwex master will be pending without setting wemax to 1. both the m3ifmlwex register and the weim csx space region will be lock to the mlwex port. 0 no active/pending access to weim csx memory exists. 1 indicates an active/pending access to weim csx memory exists. 30?4 reserved 3 mlwex_en master lock weim csx access enable. this bit enables the master lock weim csx access (mlwex). the reset value of this bit is 0. note: after mlwex master does not need the lock any more, the master should clear mlwex_en bit, so weim csx memory region is open to all masters. 0 master lock weim csx access (mlwex) is disabled. 1 master lock weim csx access (mlwex) is enabled. 2?0 mlwex master lock weim csxl access. this 3 bits field defines the master port number (mpg) that will be the only one in the system served by the weim controller. all accesses to the weim csx memory space from the other masters will be postponed. the reset value of the mlwex is 0. 1. prior to lock accesses, the mlge master should perform the following steps: 2. set the mlwex_en bit and the mlwex field (with the desired value) in the m3ifmlwex register. 3. read m3ifmlwex register and check: wemax status bit is cleared (no pending/active accesses to weim csx memory space exists). mlwex_en bit is set. mlwex (value) points to the required port number (master port number that requires lock accesses). 000 master port gasket 0 001 master port gasket 1 010 master port gasket 2 011 master port gasket 3 100 master port gasket 4 101 master port gasket 5 110 master port gasket 6 111 master port gasket 7 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-18 freescale semiconductor the number and type of ports in use is system depe ndent, and the unused ports will be unconnected at the system level. each one of the mpg gaskets communi cates with a single master, through one of the (two) defined port interfaces/protocols. 16.4.1.1 overview of mpg operation mpg port gasket is used for those system masters that are 32-bit arm9 ahb lite bus compliant. mpg port gasket appears as another sl ave to any master it connects to. table 16-13 lists the access types supported by the mpg. note unsupported access types will produce undefined behavior but an error response will not be generated. figure 16-11 shows mpg port interface diagram. the interface is arm 11 amba-ahb lite compliant (does not support retry and split transfers). mpg works with both m3a and mab, and output ahb_bus and control signals to/from m3a (i ncluding request to esdctl/mddrc signal and request to non-esdctl/mddrc = general signal). mp g decodes ahb bus inputs and convert them to mab_control bus, which includes addr, data an d control signals (like suspend and abort commands). once an accesses is initiated by one of the m3if masters, the access reaches the respective mpg. the mpg asserts the request signal toward the m3a which starts the arbitration process. once the arbitration is completed and the request can gain access to the bus, the request is accepted by the mpg and the handshake between the mpg and the m3a is completed for that access. if the access was not targeted toward the esdctl, the master can start the access (by passing the master ahb bus) toward the respective slave (nfc, eim). if initiated access is targeted to the esdctl after m3a arbitration process is completed, the request is transferred toward the mab, which arbitrates and sc hedules the access toward the esdctl as a function of esdctl state. an internal handshake betwee n the mab and esdctl is used to schedule the new table 16-13. mpg supported burst accesses hburst type m3if slaves esdctl 32-bit eim 32-bit nfc 16/32-bit pcmcia 8/16-bit 000 single yes yes yes yes 001 incr yes yes yes yes 010 wrap 4 yes yes no yes 011 incr 4 yes yes yes yes 100 wrap 8 yes yes no yes 101 incr 8 yes yes yes yes 110 wrap 16 no yes no yes 111 incr 16 no yes yes yes multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-19 access, and once the handshake is completed, the mab asserts the request accept signal toward the mpg. all esdctl related ahb signals are transferred from the master to the mpg which convert them to an internal protocol between the mpg and the mab. figure 16-11. master port gasket (mpg) interface diagram mpg also converts mab or m3a outputs to the ahb standard interface. table 16-14 presents the signals name in both modules. table 16-14. mpg max signals ahb master?signal name mpg?signal name description s#_hwrite (o) m3if_hwrite_m# (i) hwrite is high?indicates a write transfer. hwrite is low?indicates a read transfer. s#_hprot[3:0] (o) m3if_hprot_m#[3:0] (i) the protection control signals provide additional information about a bus access. for more information on this signal see protection discussion in the ahb document. m3if is using only hprot[1] signal?user/supervisor access. this signal is used to protect both registers and restricted memory regions. an error response will be generated in case of protection violation, for example, access supervisor registers/memory regions in user mode. s#_hsize[1:0] (o) m3if_hsize_m#[1:0] (i) indicates the size of the transfer. 00 8-bits (byte) 01 16-bits (half-word) 10 32-bits (word) 11 not define for mpg s#_hmaster[3:0] (o) not defined not used by m3if. s#_hprot s#_hwrite s#_hsize master gasket port 2 s#_hburst 3 s#_haddr 32 s#_hwdata 32 s#_hmaster 4 4 s#_htrans 2 m3if_hrdata m3if_hresp0_m# m3if_hready_m# ahb_bus(m3a) mab_control(mab) mab?master arbitrator and buffering s#?slave port number m#?m3if master port number (from 0 to 8) s#_hunalign s#_hbstrb 4 32 m3a_control(m3a) multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-20 freescale semiconductor s#_hburst[2:0] (o) m3if_hburst_m#[2:0] (i) burst information is provided using hburst signal, and the 8 possible types are: 000 single (single transfer) 001 incr (incrementing burst of unspecified length) 010 wrap4 (4-beat wrapping burst) 011 incr4 (4-beat incrementing burst) 100 wrap8 (8-beat wrapping burst) 101 incr8 (8-beat incrementing burst) 110 wrap16 (16-beat wrapping burst) 1 111 incr16 (16-beat incrementing burst) 1 s#_haddr[31:0] (o) m3if_haddr_m#[31:0] (i) indicates the 32 bits memory address bus. s#_hwdata[31:0] (o) m3if_hwdata_m#[31:0] (i) the write data bus is driven by the master during write transfers (on data phase). if the transfer is extended then the bus master hold the data valid until the transfer completes, as indicated by hready high. s#_htrans[1:0] (o) m3if_htrans_m#[1:0] (i) each transfer can be classified into one of four different types, as indicated by the htrans[1:0] signals: 00 idle. indicates that no data transfer is required. the idle transfer type is used when a bus master is granted the bus, but does not wish to perform a data transfer. m3if will provide a zero wait state okay response to idle transfers. 01 busy. busy transfer type allows bus masters to insert idle cycles in the middle of bursts of transfers. this transfer type indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately. m3if will provide a zero wait state okay response to idle transfers. when a master uses the busy transfer type the address and control signals reflects the next transfer in the burst. 10 nonseq. indicates the first transfer of a burst or a single transfer. single transfers on the bus are treated as bursts of one and therefore transfer type is nonsequential. 11 seq. the remaining transfers in a burst are sequential and the address and control are related to the previous transfer. in the case of a wrapping burst the address of the transfer wraps at the boundary equal to the size (in bytes) multiplied by the number of beats in the transfer (4,8 or 16). s#_hbstrb[3:0] (o) m3if_hbstrb_m#[3:0] (i) indicates which byte lanes are valid for each word transfer. 2 s#_hunalign (o) m3if_hunalign (i) signal to indicate an unalign access requiring hbstrb information. 2 s#_hmastlock (o) m3if_hmastlock (i) indicates that the current master is performing a locked sequence of transfers. s#_hready (i) m3if_hready_m# (o) m3if uses hready signal to insert the appropriate number of wait states in to the transfer (the m3if adds wait states as long as the hready in signal is deasserted). the transfer completes with hready high (and an okay response, which indicates the successful completion of the transfer). one wait state will be added for every cycle that has hready diasserted. table 16-14. mpg max signals (continued) ahb master?signal name mpg?signal name description multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-21 a granted bus master starts an amba ahb transfer by driving the address and control signals. these signals provides information on the address, direction and width of the transfer, as well as indication if the transfer forms parts of a burst. two differ ent forms of burst transfers are allowed: ? incrementing bursts, which do not wrap at address boundaries. ? wrapping bursts, which wrap at particular address boundaries. a write data bus is used to move data from the master to m3if, while read data bus is used to move data from m3if to the master. every transfer consists of: ? an address and contro l cycle (address phase) ? one or more cycles for the data (data phase) since the first address phase cannot be extended (since it will always get hready asserted high) m3if samples all control bus during first address phase, so if the master doe s not gain access immediately, the address phase information will be saved. the data, however, can be extended by using m3if_hready_mx signal. when low this signal causes wa it states to be inserted into the transfer and allows extra time for m3if (esdctl/mddrc or memories ) to provide or sample data. in this way, back to back access between different/same slave can be performed and mpg will store all needed bus/signals so that when the master gains access, all the needed bus/signals will be available. during a transfer, m3if shows the status using only one response signal hresp0 (since m3if is only ahb lite compliant). ? 0-okay?the okay response is used to indicate that the transfer is progressing normally and when m3if_hready_mx goes high this shows th e transfer has completed successfully. ? 1-error?the error response indicates that a tr ansfer error has occurred and the transfer has been unsuccessful. s#_hresp0 (i) m3if_hresp0_m# (o) hresp0 response is used by m3if to indicate some form of error condition with the associated transfer. since m3if is ahb lite compliant (ahb split and retry protocols are not supported) means that only one response signal is needed. hreps0 encoding is: 0 okay. when hready is high this shows the transfer has completed successfully. okay response is also used for any additional cycles that are inserted, with hready low. 1 error. this (two cycle) response shows an error has occurred. the error condition is signalled to the bus master so it is aware the transfer has been unsuccessful. m3if response with error on cases as specified in section 16.4.1.4, ?mpg transfer response.? s#_hrdata[31:0] (i) m3if_hrdata[31:0] (o) the read data bus is driven by the m3if during read transfers. if m3if extends the read transfer by holding hready low then m3if will provide valid data at the end of the final cycle of the transfer, as indicated by hready high. 1 incr16/wrap16 are supported only for accesses addressed to the eim or pcmcia. 2 huanlign and hbstrb are supported only by esdctl and weim. table 16-14. mpg max signals (continued) ahb master?signal name mpg?signal name description multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-22 freescale semiconductor 16.4.1.2 mpg basic transfer an amba ahb transfer consists of two distinct sections: ? address phase. ? data phase that may require several cycles. this is achieved using m3if_hready_mx signal. figure 16-12 shows the simplest transfer, one data with no wait states. ? the ahb lite bus compliant master drives the a ddress and control signals onto the bus after the rising edge of the clock. ? m3if then samples the address and control informa tion in the next rising edge of the clock and access starts (memory is not busy). ? after m3if has sampled the address and contro l (and derived the appropriate command to the memory) it can start to drive the appropriate res ponse and this is sampled by the bus master on the third rising edge of the clock. figure 16-12. mpg simple transfer the address phase of any transfer occurs during the da ta phase of the previous transfer. this overlapping of address and data is at the pipelined nature of the ahb bus and allows for high performance operation. m3if may insert wait states into any transfer, as shown in figure 16-13 , which extends the transfer allowing additional time for completion. ? for write operations the bus master will hold the data stable throughout the extended cycles. ? for read transfer, m3if does not have to provide va lid data until the transfer is about to complete. when a transfer is extended in this way, it will have side effect to extend address phase for the next transfer. this is shown in figure 16-14 , which shows three transfers to unr elated addresses, a, b, and c. ? the transfers to addresses a and c are both zero state. ? the transfer to address b is one wait state. clock sx_haddr[31:0] addr a control bus control a sx_hwdata[31:0] data a m3if_hready_mx m3if_hrdata[31:0] data a data phase address phase multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-23 extending the data phase of the transf er to address b has the effect of extending the address phase of the transfer to address c. figure 16-13. mpg with wait states figure 16-14. mpg multiple transfers 16.4.1.3 mpg transfer type every transfer can be classified into one of four di fferent types, as indicated by sx_htrans[1:0] signals as described in table 16-14 . figure 16-15 shows a number of different transfer types being used. ? the first transfer is the start of a burst and therefore is non-sequential. ? the master is unable to perform the second tran sfer of the burst immediately and therefore the master uses busy transfer to de lay the start of the next transfer (after m3if sees busy with hready high it continues to give hready high until htrans bus changes from busy and clock sx_haddr[31:0] addr a control bus control a sx_hwdata[31:0] data a m3if_hready_mx m3if_hrdata[31:0] data a data phase addr phase clock sx_haddr[31:0] addr a addr b addr c control bus control a control b control c sx_hwdata[31:0] data a data b data c m3if_hready_mx m3if_hrdata[31:0] data a data b data c multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-24 freescale semiconductor then hready will act as usual). in this example the master requires only one cycle before it is ready to start the next transfer in the burst, which completes with no wait states. ? the master performs the third transfer of the burst immediately, but this time the m3if is unable to complete and uses m3if_hready_mx to insert a single wait state. ? the final transfer of the burst completes with zero wait states. figure 16-15. mpg?transfer type examples 16.4.1.4 mpg transfer response whenever m3if is accessed it provides a response wh ich indicates the status of the transfer. the m3if_hready_mx signal is used to extend the transfer and this works in combination with the response signals, m3if_hresp_mx, which provide the status of the transfer. m3if can complete the transfer in a number of ways: ? complete the transfer immediately. ? insert one or more wait states to allow time to complete the transfer. ? signal error to indicate that the transfer has failed. the m3if_hready_mx signal is used to extend the data portion/phase of a transfer. when low the m3if_hready_mx indicates the transfer is to be ex tended and when high indicates that data transfer had completed. both m3if_hready_mx and m3if_hresp0 encoding is described in figure 16-12 . it should be noted that m3if does not support amba ahb, split and retry transfer response. a transfer will complete successfully (as defined by the ahb bus protocol) with m3if_hready_mx high and an okay response (m3if_hresp[1] lo w). a transfer will co mplete unsuccessfully (error response) with two consecutive cycles of m3if_hresp[1] high, while during the first cycle m3if_hready_mx is low and during the second cycle m3if_hready_mx is high (as defined by the ahb bus protocol). the error response is used by the m3if to indicate one of the following error types (which can be associated with the transfer): clock sx_htrans[1:0] nonseq busy seq seq seq sx_haddr[31:0] 0x20 0x24 0x24 0x28 0x2c sx_hburst[2:0] inc sx_hwdata[31:0] d 20 d 24 d 28 d 2c m3if_hready_mx m3if_hrdata[31:0] d 20 d 24 d 28 d 2c multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-25 ? master is trying to access a disabled cs d in the esdctl/mddrc system register. ? master in user mode is trying to access a csd that is configured to supervisor access only. ? system gave software reset command to esdc tl/mddrc while access to esdctl/mddrc is in progress. ? error response coming from all other memo ry controllers (except esdctl/mddrc). ? access to esdctl registers during an active access to sdram memory. note m3if controls/handles esdctl error re sponse logic, and only transfer the error response signal from all other memory controllers (pcmcia, nfc, and weim). for more details regarding the error response generation from other memory controllers, consult the respective memory controller chapter available in the respective system architecture. if an error response is generated by the mpg on the begi nning of an access, the access will not be executed and none of the data that is supposed to be read/wr ite will get transferred; however, if the error response has been given after few data transfers (in a burst acce ss), the status of the first data transfer before the error response, for write access, is unknown (data ma ybe written or not) and the master should treat the data of the whole access as unknown data. in the case th at this access was a read access the data that has been transferred until the error response is valid data and master can use it. if an error occurs during a burst access, the m3if will generate an (ahb) error response for all remaining beats from the burst. 16.4.1.5 mpg burst operation four, eight and sixteen-beat bursts are defined in the amba ahb protocol, as well as incremental undefined length bursts and single transfers. both in crementing and wrapping bursts are supported in the protocol. a detailed description of the suppor ted access type by the mpg is shown at table 16-13 . burst information is provided usi ng sx_hburst[2:0] signal and the eight possible types are defined in figure 16-12 . it is acceptable to perform single transfers using an unspecified length incrementing burst which only has a burst length of one. the burst size indicates the number of beats in the burst, not the number of bytes transferred. the total amount of data transferred in a burst is calculated by multiplying the number of beats by the amount of data in each beat, as indicated by sx_hsi ze[1:0]. sx_hsize[1:0] encoding is shown in figure 16-12 . the size is used in conjunction with the sx_hburst[2:0] signals to determine the address boundary for wrapping bursts. all transfers within a burst must be aligned to the ad dress boundary equal to the size of the transfer (that must be a word as mentioned). for example, word transfers must be aligned to word address boundaries (that is a[1:0]=00). if an unalign access is being perform hunalign signal must be asserted high and the respective hbstrb bus must be given by the master. note unaligned burst crossing bus width boundary is supported only if eventual number of transfers on the bus is not higher than the value implied by hburst. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-26 freescale semiconductor four beat wrapping and incrementing burst are shown in figure 16-16 and figure 16-17 , respectively. figure 16-16. mpg four beat wrapping burst figure 16-17. mpg four beat incrementing burst 16.4.1.6 mpg early burst termination m3if can determine when a burst has terminated ea rly by monitoring the sx_htrans[1:0] signals and ensuring that after the start of the burst every transfer is labelled as sequential or busy. if a non-sequential transfer occurs in middle of a bur st it indicates that a new burst has started and therefore the previous one must be terminated immediately. if an idle transfer occurs in middle of a burst, it indicates the burst should be terminated immediately. clock sx_htrans[1:0] nonseq seq seq seq sx_haddr[31:0] 0x38 0x3c 0x30 0x34 sx_hburst[2:0] wrap 4 control control for burst, size = word sx_hwdata[31:0] d 38 d 3c d 30 d 34 m3if_hready_mx m3if_hrdata[31:0] d 38 d 3c d 30 d 34 clock sx_htrans[1:0] nonseq seq seq seq sx_haddr[31:0] 0x38 0x3c 0x40 0x44 sx_hburst[2:0] incr 4 control control for burst, size = word sx_hwdata[31:0] d 38 d 3c d 40 d 44 m3if_hready_mx m3if_hrdata[31:0] d 38 d 3c d 40 d 44 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-27 if a master cannot complete a burst because it loses ownership of the bus (for example, max slave port sx_htrans[1:0] is idle during a burst access due to max internal arbitration logic, means that the served max master port loses ownership of the bus) th en it must rebuild the burst appropriately when it re-gains access to the bus. for example, if a master has only completed one beat of a four-beat burst then it must use an undefined-length burst to perform the remaining three transfers. figure 16-18 shows incrementing bursts of undefined length that starts after aborting previous incr 4 burst access. figure 16-18. mpg undefined length bursts note to perform burst access length not equal to 4 or 8 words, it is possible to start incr access of undefined length a nd to abort it after the desired words, or to start 4/8 burst length access and to abort it after the desired word., both ways are supported by the m3if and it is the master?s decision which way to choose. 16.4.1.7 multi-endianness m3if supports multi-endianness, an example of this is there is an endian signal input to each one of the mpgs. the endianness signal from each master should be static after reset, means that all accesses from each master will have the same endianness type. if in a given system, there are masters connected to the m3if that does not drive endian signal (means th ey support only one endian type, big or little) the respective mpgs big end signal should be static, mean ing connected to 0 or 1 (depends on the endianness supported by the master connected to it). m3if does not support shared external memory area for masters with different endianness mode. this feature should be handled by software or other additional hardware in the system. clock sx_htrans[1:0] nonseq seq nonseq seq seq sx_haddr[31:0] 0x20 0x22 0x5c 0x60 0x64 sx_hburst[2:0] incr 4 incr control size = word size = word sx_hwdata[31:0] d 20 d 22 d 5c d 60 d 64 m3if_hready_mx m3if_hrdata[31:0] d 20 d 22 d 5c d 60 d 64 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-28 freescale semiconductor 16.4.2 master port gasket 64 (mpg64) 16.4.2.1 overview mpg64 port gasket is used for those system masters that have 64 bits data bus. table 16-15 presents the access types supported by the mpg. figure 16-19 shows the mpg64 port interface diagram. mpg64 does not support retry and split transfers. table 16-15. mpg64 supported burst accesses 1. nfc does not support accesses of 8 bit data width. 2. pcmcia does not support accesses of 32 or 64 bit data width. 3. m3if mpg64 supports only double word (64 bits) or word (32 bits) size bursts. since single access is not a burst type access, byte (8 bits) or half word (16 bits) is supported as well. for mpg64 brief overview description, see section 16.4.1.1, ?overview of mpg operation .? table 16-17 only shows the buses that have different widths, all other signals are the same as described in table 16-15 . hburst type m3if slaves esdctl eim nfc pcmcia 32 bit 64 bit 32 bit 64 bit 16/32 bit 64 bit 8/16 bit 64 bit 000 single yes yes yes 3 yes yes yes yes no 001 incr yes yes yes yes yes yes yes no 010 wrap 4 yes yes yes yes no no yes no 011 incr 4 yes yes yes yes yes yes yes no 100 wrap 8 yes no yes no no no yes no 101 incr 8 yes yes yes yes yes yes yes no 110 wrap 16 no no yes no no no yes no 111 incr 16 no no yes no yes no yes no multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-29 figure 16-19. mpg64 port interface diagram table 16-17. mpg64 additional signals 64-bit master?signal name mpg64?signal name description s#_hbstrb[7:0] (o) m3if_hbstrb_m#[7:0] (i) indicates which byte lanes are valid (each bit for each byte)?extended to 8 bits. s#_hwdata[63:0] (o) m3if_hwdata_m#[63:0] (i) the write data bus extended to 64 bit width s#_hsize[1:0] (o) m3if_hsize_m#[1:0] (i) indicates the size of the transfer 00 8 bits (byte) 01 16 bits (halfword) 10 32 bits (word) 11 64 bits (double-word) (defined only for mpg64) s#_hburst[2:0] (o) m3if_hburst_m#[2:0] (i) burst information is provided using hburst signal, and the 8 possible types are; 000 single (single transfer) 001 incr (incrementing burst of unspecified length) 010 wrap4 (4-beat wrapping burst) 011 incr4 (4-beat incrementing burst) 100 wrap8 (8-beat wrapping burst) 101 incr8 (8-beat incrementing burst) 110 wrap16 (16-beat wrapping burst) 111 incr16 (16-beat incrementing burst) s#_hrdata[63:0] (i) m3if_hrdata_m#[63:0] (o) the read data bus extended to 64 bit width s#_hprot(l2c) s#_hwrite(l2c) s#_hsize(l2c) master port gasket 64 2 s#_hburst(l2c) 3 s#_haddr(l2c) 32 s#_hwdata(l2c) 64 s#_hmaster(l2c) 4 4 s#_htrans(l2c) 2 m3if_hrdata(max) m3if_hresp0_m#(max) m3if_hready_m#(max) mab?master arbitrator and buffering s#?l2c port number m#?m3if master port number (from 0 to 8) s#_hunalign(l2c) s#_hbstrb(l2c) 8 64 l2c?layer 2 cache ahb_bus(m3a) mab_control(mab) m3a_control(m3a) multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-30 freescale semiconductor 16.4.2.2 mpg64 basic transfer all basic transfer for 32 bits access are perfor m as amba-ahb usual access as described in 16.4.1.2, ?mpg basic transfer .? all 64 bits access are performed differently. since the output data port is 32 bits wide, each 64 bit (double word) access is translated into 2 separated access, so a single read/write access of 64 bits is translated by the mpg64 into two singl e read/write 32 bits access. burst length of 4 double words is being translated into 8 words (32 bits) burst length and 8 double words burst length is translated into 2 bursts of 8 words (32 bits) length. for 32 bit mddr there is no need for the mpg64 gasket to translate the access since 64 bits can be transferred by the mddr each cycle. figure 16-20 shows the simplest transfer of a single double wo rd, one data with two wait states (one cycle translation and one cycle per two single acc ess of 32 bits access should be perform). ? the master drives the address and control signals onto the bus af ter the rising edge of the clock. ? m3if then samples the address and control inform ation and translate it to 2 separated single access of 32 bits. ? first and then second access is performed on the sdram. ? each single access is treated as described in section 16.4.1.2, ?mpg basic transfer .? ? the response that the 64 bit master s ees is similar to amba-ahb response. figure 16-20. mpg64 simple double word transfer 16.4.2.3 mpg64 transfer type see section 16.4.1.3, ?mpg transfer type .? clock sx_haddrs[31:0] addr a internal_haddrs addr a addr a+4 control bus control a internal control control a1 control a2 sx_hwdata[63:0] data a internal_hwdata[31:0] d a[31:0] d a[63:32] m3if_hready_mx internal_hready m3if_hrdata[63:0] data a internal_hrdata[31:0] d a[31:0] d a[63:32] multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-31 16.4.2.4 mpg64 transfer response see section 16.4.1.4, ?mpg transfer response .? 16.4.2.5 mpg64 burst operation there are few things different than what is described in section 16.4.1.5, ?mpg burst operation .? the size of each beat can be either 8, 16, 32 or 64-bits (byte/half word/word/double word), as shown in table 16-15 . if a burst access of double word is issued, wrap8, incr16 and wrap16 are not supported by the m3if. eight beat incremental burst of double word beat size is translated into 2 burst of 8 words length each, as shown in figure 16-21 (for 32 bit mddr there is no need for the mpg64 gasket to translate the access). figure 16-21. mpg64?8 beat incremental burst of double words to 32-bit sdram 16.4.2.6 mpg64 early burst termination see section 16.4.1.6, ?mpg early burst termination .? 16.4.2.7 multi endianness see section 16.4.1.7, ?multi-endianness .? clock sx_htrans[1:0] nonseq seq seq seq seq seq internal htrans[1:0] idle non seq seq seq seq seq seq seq non seq seq sx_haddr[31:0] 0x38 0x40 0x48 0x50 0x58 0x60 sx_hburst[2:0] incr 8 control control for burst, size = double word sx_hwdata[63:0] d 38 d 40 d 48 d 50 d 58 m3if_hready_mx internal hready m3if_hrdata[63:0] d 38 d 40 d 48 d 50 d 58 internal_haddr[31:0] 0x38 0x40 0x48 0x50 0x58 0x3c 0x44 0x4c 0x54 0x60 0x5c multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-32 freescale semiconductor 16.4.3 m3if arbitration (m3a) 16.4.3.1 overview m3a is a programmable arbiter. all incoming requests from the different masters are on hold until access is granted by the arbiter. the arbitration is perf ormed by a round robin algorith m which grants the access to the master that holds the token. in the case that a master holds the token but does not request access (to one of the m3if slaves), the bus is granted to th e nearest requesting master with a higher round robin number. the internal signal bus free indicates the ff1 algor ithm to choose a new master. the bus_free signal is asserted high by the m3a by monitoring htrans bus of th e active master (the master that grants access). as soon as the m3a notices that the access has be en accomplished (htrans equal to nonseq or idle with hready asserted high) it allows to a new mast er to gain access according to the round robin value. when a new master gain an access the m3a will tr ansfer the ahb bus coming from this master to all memory controllers with an hsel signal to the specific memory controller, (all other will get low hsel). because mab can get multiple access to the esdctl and pass accesses to the esdctl according to internal handshake between the esdctl and the mab, the m3a will allow multiple access to pass to the mab without waiting for previous accesses to be completed. the m3a will pass the request to the mab if the access is to the esdctl, and will pass a new access to the mab (before the previous/active master access is completed) if the master with the token is accessing the esdctl if the request is for a different memory controller the m3a will hold the access until all pending transfers in the mab (esdctl accesses) are finished. in this case (multiple access to mab are in progress) the bus_free signal will assert hi gh when the mab completes all incoming requests. there two different access paths: 1. access request to sdram/mddr?involves es dctl/mddrc memory controller. the access path is as follows: a) master #x initiates access to sdram/mddr memory ?> m#_esdctl_req signal is high. b) m3a arbitrates master request. c) after successful arbitration m3a passes th e request to mab (by master_req_en signal set to 1). d) mab and the respective mpg (the one that initi ated the access) are handling the access directly from/to the esdctl/mddrc (m3a is not involved). e) all data transfer is accomplished by the esdctl/mddrc and the sdram/mddr external memory. 2. access request not to sdram/mddr memory?invol ves the respective memory controller. the access path is as follows: a) master #x initiates access not to sdram/ mddr memory ?> m#_general_req signal is high. b) m3a arbitrates master request. c) after successful arbitration m3a passes the ah b bus (address, data, control signals) of the respective master to the relevant memory controller. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-33 d) m3a and the respective mpg (the one that initiated the access) are handling the access from/to the relevant memory controller (mab is not involved). e) all data transfer is accomplished by the relevant memory controller and the external memory. figure 16-22. m3a block diagram note although ahb bus indicates only one direction, the round robin scheme demux the ahb response signals (hready, hresp, and hrdata) from all slaves (except from esdctl that goes directly to the mpg). figure 16-23 illustrates a simple transfer (all previous accesses are completed, and there are no other pending requests) between one of the m3if masters and the eim module. there is one cycle penalty at the beginning of the access. the mpg samples the acce ss relevant signals and de-asserts hready signal toward the master, until the target slave conf irms the access (eim_hready high with eim_nonseq cycle). after the target slave (eim in this example) confirms the request (hready high with eim_nonseq cycle) the access traffic (control and data) is direct between the master and the target slave (eim). ... m1_ahb_bus m1_esdctl_req m1_general_req m#_esdctl_req m#_general_req master gasket port round scheme robin 0 1 n ahb mux (ff1) ahb_bus(slaves) choosen_slave master_req_en(mab) m3if registers #1 master gasket port #n bus free logic m#_ahb_bus request logic multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-34 freescale semiconductor figure 16-23. m3a simple transfer timing diagram 16.4.3.2 m3a?find first 1 (ff1) algorithm arbitration between the various re quests is done by find first 1 algorit hm based on round robin algorithm (see figure 16-24 ). if two or more masters request access to the m3if the master with the token, or the master that will be the first to receive the token (in case the master with the token does not request access) will gain control over the ahb bus or will enable his request signal to the mab. for example, if masters 0, 1, and 6 requesting access at the same time and the toke n is at master 2, then master 6 will gain control over the ahb bus or his request signal to the mab will be enabled, since it will be the first to receive the token (this is done to reduce arbitration time, in th is example 4 clock cycles are saved). the round robin pointer increase its value in two cases, if the master with the token does not request access or if the master with the token requests access and gains the ahb bus /enable request?on the cycle that the master gains the ahb bus/enable request the round robin pointer will increase its value. if a master requests an access and has the token but does not gain access because no new access can pass on, the round robin will not increase until the master ga ins the ahb bus/enable request. clock sx_htrans[1:0] nonseq seq seq seq sx_haddr[31:0] 0x38 0x3c 0x30 0x34 sx_control control for burst, size = word sx_hwdata[31:0] d 38 d 3c d 40 d 44 m3if_hready_mx m3if_hrdata[31:0] d 38 d 3c d 30 d 34 eim_htrans[1:0] nonseq seq seq eim_haddr[31:0] 0x3c 0x30 0x34 eim_control control for burst, size = word eim_hwdata[31:0] d 38 d 3c d 40 d 44 eim_hready eim_hrdata[31:0] d 38 d 3c d 40 d 44 seq 0x38 idle multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-35 figure 16-24. m3a?round robin token chain?equal priority there is an option to program the round robin to work with different priority using mrrp field of the m3if control register. when the mrrp equal to 0 no prio rity is given to any master so the probability to gain access is equal for each one of the masters. if one or more bits of the mrrp are set to 1, the priority changes, and all master with their bit set to 1, will ge t together 50% priority of gaining access. for example, if both master 1 and master 4 bits set to 1 in the mrrp field, the priority to gain access of master 1 and 4 together will be 50%. if only one bit is set the respective master (that his bit is set) will alone have 50% priority to gain access. note by default (after reset) all mrrp bits are cleared, means that all m3if masters have the same priority. the 50% priority refers only to round robin mechanism. if a non priority master (mrrp respective bit is not set) with the token is already waiting to gain the bus the new coming request from the priority master (mrrp respective bit is set) will not gain access be fore the previous master request is completed. additionally, priority master cannot and will not terminate an on going access of any other masters. figure 16-25 shows round robin chain in case that mrrp configured to 8?b000 1 00 1 0?master 1 and 4 set to 1. figure 16-25. m3a?round robin token chain?masters 1 and 4 has 50% priority master 0 master 1 master 2 master n-1 master n master 0 after previous access execution completes, bus_free signal is high, so master #0 will gain access to the bus and the round robin will change its value. with each clock cycle the ?token? can shift between the masters if one of the conditions come true. since bus_free signal is low no new master can gain access. and round robin does not change its value since master #0 is requesting access. round robin parks on master #0 until he gains access to the bus. bus_free is low, means an access is in progress. master 0 master 1 and 4 together has the probability of 50% to gain access. master 1/4 master 1 master 2 master 4 master 3 master 1 master 5 master 4 master n multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-36 freescale semiconductor 16.4.3.3 bus_free signal algorithm when the bus_free signal asserts high, it indicates th e new master can gain access. the bus_free asserts high in the following cases: ? when the previous access was a non esdctl access and the htrans bus of the previous master that gained the access was equal to non sequential or idle and hready asserted high. ? when the previous access was an esdctl access and the new master that gained access was also an esdctl access. ? when the previous access or accesses were esdc tl accesses and all previous accesses finished. note to avoid contention between the memory controllers/memories, there is a special signal coming from the mpg and from the mab to the m3a and going to the bus_free algorithm indicating which kind of slave is still using shared i/o pins so no new access to a different memory begins. 16.4.4 master arbitration and buffering (mab) 16.4.4.1 overview of mab operation mab arbiter uses the same programmable arbiter as the m3a ( section 16.4.3.2, ?m3a?find first 1 (ff1) algorithm ?). all incoming requests from the different masters are put on hold until access is granted by the arbiter. the mab communicates with the esdctl and grants access at the earliest possible time, for example when the esdctl is ready to handle a new memory request. each time esdctl can get a new access, the new access is sampled into the contro l and data buffers so esdctl receives stable inputs during the time the access is in progress. the data buffer is sampled according to esdctl write acknowledge response. figure 16-26 shows mab operation block diagram. 16.4.4.2 m3b?find first 1 (ff1) algorithm this operation of the arbiter algorithm is identi cal to the m3a arbiter algorithm described in section 16.4.3.2, ?m3a?find first 1 (ff1) algorithm .? each time new_access goes high it indicates that the esdctl is ready to handle a new memory request, meaning that the previous request is eith er completed or controlled by the sdram memory. during the same cycle the memory port is granted to the master with the token. figure 16-27 shows the arbitration process for 4 master requests. at the fi rst clock cycle masters m0, m1, and m2 simultaneously request the memory port. at the rising edge of th e clock (while new_access is high) master m0 has the token, so the memory port is controlled by m0 (see master_control signals). during that time all m3if_hready_m# signals are low, besides m3 if_hready_m3 which was the previous served master. the same arbitration process occurs for the following requests. master m1 has the token and grant access to the esdctl (see master_control). hready of master m0 asserted high and accomplished the previous access. after several cycles m0 asse rt the request signal again due to a new access. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-37 figure 16-26. mab overview block diagram once a master has control over the port, the ot her requests remain on hold, meaning that their m3if_hready_m# is low. the current master has control over the memory port until it completes the requested transfer. the new master gaining access to the memory port is the master with the new token. the mab addr/ctrl mux and wdata mux connect (using the round robin algorithm) the selected master and when new_access arrives the mux output is sampled by the mab so that a stable bus is provided to esdctl. after a new access is detected by the esdctl, data transfer between the memory and the masters can start. in order for the mab to serve more than one master at a time, a cyclic 4 entry fifo with two pointers (read/write) is used. the fifo read pointer is used (by the decode block) as the selector for the memory response signals and for the wdata mux, while the fifo write pointer is used to add a new master to the fifo entries. (sin ce esdctl hides latency a new access can start before previous access ended. this why this mux control s hould work separately for information to the esdctl and esdctl response. figure 16-27 shows the mab arbitration process timing diagram. master gasket port m1_wdata m1_addr and control ... m1_request m1_response(mpg) master gasket port m2_wdata m2_addr and control m#_request m2_response(mpg) master gasket port m#_wdata m#_addr and control m2_request m#_response(mpg) round scheme robin decode esdctl rdata (shared bus to all mpgs) 0 1 n 0 1 n 0 1 n master arbitration and buffering addr/ctrl mux wdata mux sdram bus wbuffer rbuffer fifo resp select wdata rdata control buffer (ff1) m3if registers #1 #2 #n m3a multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-38 freescale semiconductor figure 16-27. mab arbitration process timing diagram figure 16-28 shows a detailed multi master memory request time diagram. the diagram shows two masters presenting memory request (amba ahb) signa ls and their conversion by the mpg and mab to the esdctl. the hrdata timing is also shown with the respective m3if_hready_m# signal. the hrdata bus from the memory (during read transfers) is shared with all present masters (except 64-bit masters that become a 64-bit bus after decoding by mp g64) while the arbitration is completed by the use of the m3if_hready_m# signals at the master level. 16.4.4.3 m3if operation during hmastlock accesses if a hmastlock access to any memory controller (mem ory space) is initiated by one of the m3if masters, the request need to pass the arbitration like a regular access. after the access passes the arbitration it ?locks? the arbitration and all other accesses (re gardless to memory space destination) will remain pending until the hamstlock signal (from the master that initiated the hmastlock access) de-asserts. while the hmastlock is high all accesses initiated by the locking master will be executed without arbitration, while all other masters accesses will remain pending. note during hmastlock high, the locking master is not allowed to change the memory space destination, from sdr/ddr sdram space to non sdr/ddr sdram, or vice versa. clock round_robin 0 0 1 1 1 2 2 3 3 3 request_m0 request_m1 request_m2 request_m3 new_access master_control m3 m0 m1 m2 m3if_hready_m0 m3if_hready_m1 m3if_hready_m2 m3if_hready_m3 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-39 figure 16-28. mab multi-master request time diagram 16.4.5 snooping logic m3if snooping feature (used by the image processor unit, ipu), monitors and detects write accesses to a configurable window (snooping window ) in one of the memory regions mapped by the m3if. the snooping window base address, memory region, and window size are configurable parameters through the m3ifscfg0 register (register details at section 16.3.3.2, ?m3if snooping c onfiguration register 0 clock round_robin 1 2 3 0 1 1 1 2 3 0 0 request_m0 request_m1 new_access s0_haddr[31:0] a20 a24 a28 a2c a40 s0_hburst burst size = 4 burst size = 8 s0_hwrite s1_haddr[31:0] a10 s1_hburst burst size = 0, single access s1_hwrite master_control m0 m1 mab_addr[31:0] a20 a10 mab_burst burst size = 4 burst size = 0 mab_rw m3if_hready_m0 m3if_hready_m1 m3if_hrdata[31:0] d20 d24 d28 d2c d10 multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-40 freescale semiconductor (m3ifscfg0) ?). snooping window is further divided into 64 equally sized segments. a detected write access to the snooping window results in: ? the respective segment status bit in m3if ssr0 and/or m3ifssr1 registers is set. ? dma_access strobe is asserted for 1 clock cycl e if the snooping segment enable bit is set for the snooped segment. the snooping segment enable b it is configured via 2 snooping configuration registers, m3ifscfg1 and m3ifscfg2. it is the software?s responsibility to clear the snoope d segment status bits, but the snooped segment status bit will be set for each snooping de tection regardless of its value. 16.5 initialization/app lication information 16.5.1 m3if in a system this section provides an example of m3if initializat ion, integration and configur ation in a given system. the system requirements are listed below: ? several masters with external memories access capabilities. ? several masters access the m3if via ap max crossbar switch. ? arm i-cache?32-bit data bus ? arm d-cache?32-bit data bus ? the system uses 2 sdram memory devices (32 bits), a 32-bit flash (via weim cs0) and one sram (via weim cs1). figure 16-29 presents m3if integration in the system. al l the above masters are connected to the m3if through ports. multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 16-41 figure 16-29. m3if system example esdctl dma a/p max arm platform mpg64 multi master memory interface (m3if) rtic h264 weim controller m3if registers snooping logic mpg fce mpg64 #0 #3 #4 flash sram sdram sdram csd0 csd1 cs0 cs1 via emi and io muxes mpg64 lcdc multi-master memory interface (m3if) MCIMX27 multimedia applications processor reference manual, rev. 0.2 16-42 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-1 chapter 17 wireless external in terface module (weim) the wireless external interface module (weim) handl es interface to devices external to the chip, including generation of chip selects, clock and control for external peripherals and memory. it provides asynchronous and synchronous access to devices with sram-like interface. figure 17-1 shows a top-level weim block diagram. all block signals are shown in table 17-1 and described in table 17-2 . 17.1 features ? six chip selects for external devices, with cs0 and cs1 each covering a range of 128 mbytes, and cs2 ?cs5 , each covering a range of 32 mbytes ?cs0 range can be increased to 256 mbytes when collapsed with cs1 ? selectable protection for each chip select ? programmable data port size for each chip select ? asynchronous accesses with programmable setup and hold times for control signals ? synchronous memory burst read mode support fo r amd, intel, and micron burst flash memory ? synchronous memory burst write m ode support for psram (cellularram tm from micron, infineon, and cypress) ? support for multiplexed a ddress/data bus operation ? external cycle termination/postpone with dtack signal ? programmable wait-state generator for each chip select ? support for big endian and little endian modes of operation per access ? arm ahb slave interface 17.2 overview weim has six modes of operation. weim does not requi re a dedicated low-power mode because most of clocks are gated anytime when there are no accesses to weim providing maximum energy conservation. ? asynchronous mode. this is a non-burst mode is used for sram access. in this mode a single data is read/written with each access (asserted addres s). all controls timings are controlled by preset values in chip sele ct control registers. ? synchronous read mode. this is a burst mode is used for reading flash memory devices. in this mode after address assertion, a burst of sequential data can be rea d. data exchange is carried out according to bclk clock that is generated by we im. an access may be delayed by external ecb signal assertion after first word of data. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-2 freescale semiconductor ? page mode. this mode is used for memory burst read, but address is asserted for each data in the burst as lba and bclk operate asynchronously. in this m ode, setup time is greater for first data burst than for the remaining da ta burst (in the same page). figure 17-1. weim block diagram capture ahb eim config eim clock output control addr path read data path write data path input capture ahb controls ecb dtack hwdata[31:0] hrdata[31:0] haddr[31:0] enables state gated clocks configuration oe eb [3:0] rw cs [5:0] io_dir lba ahb ahb ahb addr data mux m_data_in[15:0] ahb clock (hclk 133 mhz) guard data_in[15:0]/ bclk addr[25:16] addr[15:0]/ m_data_out[15:0] data_out[15:0]/ m_data_out[31:16] m_data_in[31:16] [3:0] boot_cfg [5:0] bigend bclk_fb strobe bus controller wr_guard wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-3 ? synchronous read/write mode (psr am synchronous mode). in this mode, read and write are synchronous. access may be additi onally delayed according to ecb state before first piece of data arrives (refresh wait enable). ? dtack mode. this is a non-burst mode used fo r pcmcia access. in this mode, weim waits for dtack acknowledge until 1024 counts of ahb cloc k have passed. in this mode, dtack can be used as posedge or level sensitive according to wsc field and ew bit settings. ? multiplexed address/data mode. in this mode, multiplexing addr esses and data bits on same pins is supported for synchronous/asynchronous accesses to the 32-bit data width memory devices. 17.3 external signal description this section discusses input and output signals (see table 17-1 ) between weim and external devices. table 17-1. signal properties name port function direction reset state addr[25:16] ? address bus msb/eb [3:2], cre out low addr[15:0]/ m_data_out[15:0] ? address bus lsb/output data multiplexed bus lsb out low bclk ? burst clock out low bclk_fb ? feedback burst clock in ? bigend ? data endian in ? boot_cfg[5:0] ? boot configuration in ? cs [5:0] ? chip selects out high data_in[15:0]/ m_data_in[31:16] ? input data bus lsb/input data multiplexed bus msb in ? data_out[15:0]/ m_data_out[31:16] ? output data bus lsb/output data multiplexed bus msb out low dtack ? data transfer acknowledge/wait in ? eb [3:0] ? enable byte out high ecb ? end current burst/wait in ? guard ? input guard in ? io_dir[3:0] ? io direction out low lba ? load burst address out high m_data_in[15:0] ? input data multiplexed bus lsb in ? oe ? output enable out high rw ? read/write out high wr_guard ? write guard out high wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-4 freescale semiconductor 17.4 detailed signal descriptions table 17-2. weim detailed signal descriptions signal i/o description addr [25:16] io address bus msb. these pins are used as address bits [25:16]. in the multiplexed mode these pins do not change their state. if corresponding ausx bit is set, those pins reflect [25:16] ahb address bits. if ausx bit is not set, these pins represent [27:18] ahb address bits for word-width memory, [26:17] bits for halfword width memory and [25:16] bits for byte-width memory. addr[25:24] also are used as eb [3:2] in the multiplexed mode (mum=1). addr[23] also is used as cre in psram mode (psr=1). addr[15:0]/ m_data_out[15:0] io multiplexed address bus lsb/output data bus lsb. in non-multiplexed mode those pins are used as address bits [15:0]. if corresponding ausx bit is set those pins reflect [15:0] ahb address bits. if ausx bit is not set, those pins reflect [17:2] ahb address bits for word width memory, [16:1] bits for halfword width memory and [15:0] bits for byte width memory. in multiplexed address/data mode those bits are multiplexed between address and output data [15:0] bits. in the multiplexed address/data mode its behavior is affected by the lba, lbn and lah fields in the chip select control registers. in synchronous multiplexed mode its behavior is affected by the bcs, bcd and lah fields. bidirectional lsb address/data bus are made in io pad from m_data_in[15:0] and addr[15:0]/m_data_out[15:0]. bclk o burst clock. this active-high output signal bclk is used to clock external, burst-capable devices to synchronize the loading and incrementing of addresses and delivery of burst read and write data to/from the weim. its behavior is affected by the bcm bit in the weim configuration register and the sync bit and bcd and bcs fields in the chip select control registers. bclk can start on both rising and falling edge of hclk. bclk_fb i burst clock feedback. this input is used to provide input data sampling clock in high data speed. it is a feedback from the io pad of the bclk output pin that intend to align the clock used by the memory, and the one that is used to sample the read data. bigend i big/little endian. this input is used to provide big/little endian support in the weim. weim supports big and little endian accesses according table 17-4 . weim supports mixing big and little endian accesses. boot_cfg[5:0] o boot configuration. these input pins determine the state of some weim configuration bits after hardware reset. see ta bl e 1 7 - 3 for settings. cs [5:0] o chip selects. the cs [5:0] signals are chip selects active-low output pins. its behavior is affected by the csa and csn fields in the chip select control registers. cs [0] address space range can be increased to 256 mbytes by merging the cs [0] and cs [1] ranges. in this case the merged address space (mas) bit is set in the weim configuration register, and the cs [1] pin is used as address line a26. as shown in ta bl e 1 7 - 6 , the chip select signals are asserted based on a decode of address lines [31:24] (when enabled). data_in[15:0]/m_dat a_in[31:16] io input data bus lsb/input data multiplexed bus msb. these signals are the input data bus used to transfer data from external devices. in a non multiplexed mode it is lsb, in a multiplexed mode it is msb. bidirectional lsb data bus are made in io pad from data_in[15:0]/m_data_in[31:16] and data_out[15:0]/m_data_out[31:16]. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-5 data_out[15:0]/ m_data_out[31:16] 0 output data bus lsb/output data multiplexed bus msb. these signals are the output data bus used to transfer data to an external devices. in a non-multiplexed mode, it is lsb and in a multiplexed mode, it is msb. bidirectional lsb data bus are made in io pad from data_in[15:0]/m_data_in[31:16] and data_out[15:0]/m_data_out[31:16]. dtack i data transfer acknowledge. this input signal is used to externally terminate a data transfer when enabled. for dtack enabled cycles, the bus time-out monitor generates a bus error if dtack after has been asserted is not deasserted before 1024 clocks have elapsed. this signal is used in two modes: with rising edge detection or with level detection with an insensitiveness time. edge detection mode is used for devices like pcmci card. level detection mode is used for asynchronous devices like ati graphic controller. dtack control keeps backward compatibility with previous architectures that used it in the application processors. eb [3:0] o enable byte. those active-low output pins indicate active data bytes for the current access. they may be configured to assert for read and write cycles or for write cycles only as programmed in the chip select control registers. eb [0] corresponds to data_out[7:0] and m_data_out[7:0]. eb [1] corresponds to data_out[15:8] and m_data_out[15:8]. eb [2] corresponds to m_data_out[23:16]. eb [3] corresponds to m_data_out[31:24]. eb [3:2] also are multiplexed to the addr[25:24] bits in the multiplexed mode (mum = 1). in the write accesses its behavior is affected by the ebwa and ebwn fields and ebc bit in the chip select control registers. in the read accesses its behavior is affected by the ebra and ebrn fields in the chip select control registers. ecb i end current burst (wait). this active-low input signal ecb is asserted by external burst capable devices. it is serviced in synchronous mode only (sync=1). this signal can be used in two different modes depending on the ew bit in the chip select control register. in the ecb mode (ew=0) ecb indicates the end of the current (continuous) burst sequence. following assertion, the weim terminates the current burst sequence and initiate a new one. in the wait mode (ew=1) the memory device asserts this signal to insert wait states during refresh collisions or during a row boundary crossing. following assertion, the weim does not terminate the current burst sequence and continues it once wait is negated. ecb will have a pull up resistor in io. for burst devices ecb /wait output should be configured to change one cycle before data is ready (before delay). guard i guard. this active-high input signal indicates that io is locked by another module and current access should be postponed till io unlocked. guard and wr_guard together are used in back to back accesses between memory controllers to avoid contention on the shared pins. io_dir[3:0] o io direction. these active-high output signal indicates io direction (0 for input and ?1? for output). bidirectional buses are made in io module from addr[15:0]/m_data_out[15:0] and m_data_in[15:0] from data_out[15:0]/m_data_out[31:16] and data_in[15:0]/m_data_in[31:16]. bit io_dir[0] corresponds to addr[7:0]/m_data_out[7:0]/m_data_in[7:0], bit io_dir[1] corresponds to addr[15:8]/m_data_out[15:8]/m_data_in[15:8], bit io_dir[2] corresponds to data_out[7:0]/m_data_out[23:16]/data_in[7:0]/m_data_in[23:16], and bit io_dir[3] corresponds to data_out[15:8]/m_data_out[31:24]/data_in[15:8]/m_data_in[31:24] lba o load burst address. this active-low output signal is asserted during burst mode accesses to cause the external burst capable device to load a new starting burst address. assertion of lba indicates that a valid address is present on the address bus. its behavior is affected by the sync bit, bcd, bcs, lba and lbn fields in the chip select control registers. in asynchronous mode (sync=0) lba length decreased by lba and lbn fields. in the synchronous mode (sync=1) lba length is equal bcd + bcs + lbn + 1 half ahb clock cycles. table 17-2. weim detailed signal descriptions (continued) signal i/o description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-6 freescale semiconductor m_data_in[15:0] i mux data input bus. these signals are lsb input data bus used to transfer data from an external devices in multiplexed mode. bidirectional lsb address/data bus are made in io pad from m_data_in[15:0] and addr[15:0]/m_data_out[15:0]. oe o output enable. this active-low output signal oe indicates the bus access is a read and enables slave devices to drive the data bus with read data. its behavior is affected by the oea and oen fields in the chip select control registers. rw o read/write. rw output signal indicates if the current bus access is a read or write cycle. a high (logic one) level indicates a read cycle and a low (logic zero) level indicates a write cycle. its behavior is affected by the rwa and rwn fields in the chip select control registers. strobe o strobe. this signal allows capture current access controls, address and data on logic analyzer. sync. and async. accesses are supported. wr_guard o wr_guard. this active-high output signal indicates that io is locked by weim. (it is asserted also in extra dead cycles time). wr_guard and guard together are used in back to back accesses between memory controllers to avoid contention on the shared pins. table 17-3. boot configuration settings boot_cfg bits configured bits place 5 aus0 wcr 4 mum cscr0a 3maswcr 2:0 dsz[2:0] cscr0u table 17-2. weim detailed signal descriptions (continued) signal i/o description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-7 17.5 memory map and register definition the weim module includes 19 user-accessible 32-bit re gisters. there is a common register called weim configuration register (wcr) that contains control bits to configure weim for certain operation modes. the other 18 registers: chip select control regi ster 0?5 upper, lower, and additional (cscr0u, table 17-4. weim out/in data in case ahb out/in data is 0xb3b2b1b0 endian mode ahb access ahb address [1:0] port size and used bits word port halfword port byte port [31:24] [23:16] [15:8] [7:0] external address [0] [31:24] ([15:8]) [23:16] ([7:0]) external address [1:0] [31:24] ([15:8], [23:16], [7:0]) big word 0 0xb3 0xb2 0xb1 0xb0 0 0xb3 0xb2 0 0xb3 10xb2 1 0xb1 0xb0 2 0xb1 30xb0 half word 0 0xb3 0xb2 0 0xb3 0xb2 0 0xb3 10xb2 2 0xb1 0xb0 1 0xb1 0xb0 2 0xb1 30xb0 byte 0 0xb3 0 0xb3 0 0xb3 1 0xb2 0xb2 1 0xb2 20xb110xb120xb1 30xb00xb030xb0 little word 0 0xb3 0xb2 0xb1 0xb0 0 0xb1 0xb0 0 0xb0 10xb1 1 0xb3 0xb2 2 0xb2 30xb3 half word 0 0xb1 0xb0 0 0xb1 0xb0 0 0xb0 10xb1 2 0xb3 0xb2 1 0xb3 0xb2 2 0xb2 30xb3 byte 0 0xb0 0 0xb0 0 0xb0 1 0xb1 0xb1 1 0xb1 20xb2 1 0xb220xb2 3 0xb3 0xb3 3 0xb3 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-8 freescale semiconductor crcr0l, crcr0a,..., cscr5u, cscr5l, cscr5a) and six chip select control registers 0?5 (cscr0?cscr5) for each chip select. the layout of control register is slightly different for the cscr0 register because the cscr0 reset state depends on boot_cfg input. these registers are accessible only in supervisor mode with word (32-bit) reads a nd writes. complete decoding is not performed, so shadowing can occur with these registers. the user should not attempt to address these registers at any other address location other than those listed in table 17-5 and table 17-6 . 17.5.1 memory map memory map for weim is shown in table 17-5 and memory map for chip select is shown in table 17-6 . table 17-5. weim memory map address definition access reset section/page 0xd800_2000 (cscr0u) chip select 0 upper control register r/w 0x0000_1e00 17.5.3.1/17-12 0xd800_2004 (cscr0l) chip select 0 lower control register r/w 0x000_081 1 1 some bits are set according boot_cfg input. 17.5.3.2/17-16 0xd800_2008 (cscr0a) chip select 0 addition control register r/w 0x0000_000 17.5.3.3/17-20 0xd800_2010 (cscr1u) chip select 1 upper control register r/w 0x0000_0000 17.5.3.1/17-12 0xd800_2014 (cscr1l) chip select 1 lower control register r/w 0x0000_0000 17.5.3.2/17-16 0xd800_2018 (cscr1a) chip select 1 addition control register r/w 0x0000_0000 17.5.3.3/17-20 0xd800_2020 (cscr2u) chip select 2 upper control register r/w 0x0000_0000 17.5.3.1/17-12 0xd800_2024 (cscr2l) chip select 2 lower control register r/w 0x0000_0000 17.5.3.2/17-16 0xd800_2028 (cscr2a) chip select 2 addition control register r/w 0x0000_0000 17.5.3.3/17-20 0xd800_2030 (cscr3u) chip select 3 upper control register r/w 0x0000_0000 17.5.3.1/17-12 0xd800_2034 (cscr3l) chip select 3 lower control register r/w 0x0000_0000 17.5.3.2/17-16 0xd800_2038 (cscr3a) chip select 3 addition control register r/w 0x0000_0000 17.5.3.3/17-20 0xd800_2040 (cscr4u) chip select 4 upper control register r/w 0x0000_0000 17.5.3.1/17-12 0xd800_2044 (cscr4l) chip select 4 lower control register r/w 0x0000_0000 17.5.3.2/17-16 0xd800_2048 (cscr4a) chip select 4 addition control register r/w 0x0000_0000 17.5.3.3/17-20 0xd800_2050 (cscr5u) chip select 5 upper control register r/w 0x0000_0000 17.5.3.1/17-12 0xd800_2054 (cscr5l) chip select 5 lower control register r/w 0x0000_0000 17.5.3.2/17-16 0xd800_2058 (cscr5a) chip select 5 addition control register r/w 0x0000_0000 17.5.3.3/17-20 0xd800_2060 (wcr) weim configuration register (wcr) r/w 0x0000_0100 17.5.3.4/17-23 table 17-6. weim chip selection memory map address use access 0xc000_0000 0xc7ff_ffff cs0 memory region r/w 0xc800_0000 0xcfff_ffff cs1 memory region r/w wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-9 17.5.2 register summary figure 17-2 shows the key to the register fields and table 17-7 shows the register figure conventions. figure 17-2. key to register fields 17.5.3 register descriptions this section consists of register descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bits and field function follow the register diagrams, in bit order. table 17-8 provides a summary of the registers in the weim module. the 96 bits 0xd000_0000 0xd1ff_ffff cs2 memory region r/w 0xd200_0000 0xd3ff_ffff cs3 memory region r/w 0xd400_0000 0xd5ff_ffff cs4 memory region r/w 0xd600_0000 0xd7ff_ffff cs5 memory region r/w always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 17-7. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read-only. writing this bit has no effect. wwrite-only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. slfclr self-clearing bit. writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 17-6. weim chip selection memory map (continued) address use access wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-10 freescale semiconductor used to control chip select are divided into thre e registers: chip select x upper control register (cscrxu), chip select x lower control register (cscrxl) and chip select x additional control register (cscrxa). ? bits [95:64] are located in chip select x upper control register (see figure 17-3 ). ? bits [63:32] are located in chip se lect x lower control register (see figure 17-4 ). ? bits [31:0] are located in chip sel ect x additional control register (see figure 17-5 ). table 17-8. weim register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xd800_2000 (cscr0u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2004 (cscr0l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w 0xd800_2008 (cscr0a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w 0xd800_2010 (cscr1u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2014 (cscr1l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w 0xd800_2018 (cscr1a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-11 0xd800_2020 (cscr2u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2024 (cscr2l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w 0xd800_2028 (cscr2a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w 0xd800_2030 (cscr3u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2034 (cscr3l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w 0xd800_2038 (cscr3a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w 0xd800_2040 (cscr4u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2044 (cscr4l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w table 17-8. weim register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-12 freescale semiconductor 17.5.3.1 chip select x upper control register (cscrxu) figure 17-3 shows the register and table 17-9 provides its field descriptions. 0xd800_2048 (cscr4a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w 0xd800_2050 (cscr5u) r sp wp bcd bcs psz pme syn c dol w r cnc wsc ew wws edc w 0xd800_2054 (cscr5l) r oea oen ebwa ebwn w r csa ebc dsz csn psr cre wra p cse n w 0xd800_2058 (cscr5a) r ebra ebrn rwa rwn w r mu m lah lbn lba dww dct ww u age cnc 2 fce w 0xd800_2060 (wcr) r ecp 5 ecp 4 ecp 3 ecp 2 w r ecp 1 ec p0 aus 5 aus 4 aus 3 aus 2 aus 1 aus 0 bc m mas w table 17-8. weim register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-13 0xd800_2000 (cscr0u) 0xd800_2010 (cscr1u) 0xd800_2020 (cscr2u) 0xd800_2030 (cscr3u) 0xd800_2040 (cscr4u) 0xd800_2050 (cscr5u) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sp wp bcd bcs psz pme sync dol w reset0000000000000000 1514131211109876543210 r cnc wsc 1 1 wsc field (bits 8?13) reset value is 011110 for cs0u register and is 0 for all others. ew wws edc w reset0000000000000000 figure 17-3. chip select x upper control register table 17-9. chip select x upper control register field descriptions field description 31 sp supervisor protect. this bit prevents accesses to the address range defined by the corresponding chip select when the access is attempted in the user mode. sp is cleared by a hardware reset. 0 user mode accesses are allowed in the memory range defined by chip select. 1 user mode accesses are prohibited. all attempts to access an address mapped by this chip select in user mode results in a error response on the ahb and no assertion of the chip select output. 30 wp write protect. this bit prevents writes to the address range defined by the corresponding chip select. wp is cleared by a hardware reset. 0 writes are allowed in the memory range defined by chip. 1 writes are prohibited. all attempts to write to an address mapped by this chip select result in a error response on the ahb and no assertion of the chip select output. 29?28 bcd burst clock divisor. this bit field contains the value used to program the burst clock divisor for bclk generation. it is used to divide the internal ahb bus frequency (hclk 133 mhz). see 17.6.4/17-26 for more information on the burst clock divisors. an example is shown in figure 17-41 . when the bcm bit is set in the weim configuration register, bcd is ignored. bcd is cleared by a hardware reset. 00 divide ahb clock by 1 01 divide ahb clock by 2 10 divide ahb clock by 3 11 divide ahb clock by 4 27?24 bcs burst clock start. if sync 1 this bit field determines the number of half cycles after address assertion before the first rising edge of bclk is seen. see example on the figure 17-41 . a value of 0 results in a half clock delay, not an immediate assertion. when the bcm bit is set in the weim configuration register, this overrides the bcs bits. bcs is cleared by a hardware reset. 0000 1 half ahb clock cycle. 0001 2 half ahb clock cycles. 1111 16 half ahb clock cycles. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-14 freescale semiconductor 23?22 psz page size. if pme is clear the psz bit field indicates memory burst length in words (where word is defined by the dsz field) and should be properly initialized for mixed wrap/increment ahb accesses support. continuous psz value corresponds to continuous burst length setting of the external memory device. if pme is set (set to 1) the psz bit field indicates number of words (where ?word? is defined by the port size in dsz field) in a page in memory. this ensures that the weim does not burst past a page boundary at increment access when the pme bit is set. psz is cleared by a hardware reset. see table 17-10 for psz bit field combinations. 21 pme page mode emulation. this bit enables page mode emulation in burst mode. when pme is set (and sync equals 1), the external address is asserted for each piece of data requested. additionally, the lba and bclk signals behave in the same way when an asynchronous access is performed (see figure 17-25 ). pme is cleared by a hardware reset. 0 disables page mode emulation 1 enables page mode emulation 20 sync synchronous burst mode enable. this bit enables synchronous burst mode if pme is clear (see also pme and psr description). when enabled, the weim is capable of interfacing to burst flash devices through additional burst control signals: bclk, lba , and ecb (see example on the figure 17-29 ). the sequencing of these additional i/os is controlled by other weim configuration register bit settings as described in section 17.6.3, ?burst mode memory operation .? sync is cleared by a hardware reset. 0 disables synchronous burst mode 1 enables synchronous burst mode 19?16 dol data output length. if sync is set (equals 1) the dol bit field specifies number of wait states during the burst access after the delay of the first data according to the settings shown below (see examples on the figure 17-25 and figure 17-40 ). the reset value 0 specifies that burst data is held for a single ahb clock period. as ahb clock frequencies increase, it may become necessary to delay sampling the data for multiple ahb clock periods in order to meet burst memory setup and/or frequency specifications and/or weim data setup time requirements. dol has no effect on burst data length when sync = 0. dol is cleared by a hardware reset. 0000 1 ahb clock cycle data length. 0001 2 ahb clock cycles data length. ? 1111 16 ahb clock cycles data length. 15?14 cnc chip select negation clock cycles. this bit field specifies the minimum number of clock cycles a chip select must remain negated after it is negated (but doesn?t guarantee negation for back-to-back accesses, it requires edc using) according to the settings shown below. see examples on the figure 17-12 , and figure 17-13 . cnc has no effect on write accesses when any csa bit is set. cnc is cleared by a hardware reset. the number of clock cycles of this field can be increased using the cnc2 bit in the appropriate chip select addition control register. 00 0 minimum number of ahb clock cycles cs must remain negated. 01 1 minimum number of ahb clock cycles cs must remain negated. 10 2 minimum number of ahb clock cycles cs must remain negated. 11 3 minimum number of ahb clock cycles cs must remain negated. table 17-9. chip select x upper control register field descriptions (continued) field description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-15 13?8 wsc wait state control. this bit field programs the number of wait-states for an access to the external device connected to the chip select (see figure 17-7 ). for sync = 1 wsc programs the number of ahb clock cycles required for the initial access (see figure 17-25 , and figure 17-32 ) of a memory burst sequence initiated by the weim to an external burst device. for ew = 1 after the wait cycle count expires ecb is sampled and the cycle terminates when the ecb is negated. on other case weim special watch dog counter check that ecb will not be asserted for more than 1024 ahb clocks. additionally in this case weim suppresses lba generation after next ecb assertion (during increment burst at page boundary crossing). for write accesses the number of wait-states is increased according wws value or decreased by dww (see ta bl e 1 7 - 1 1 ). wsc = 11_1111 indicates operation in a positive edge-sensitive dtack mode. it selects dtack input as access length control sign (instead of default wsc counter). it means that access length is determined by dtack length. wsc is set to 01_1110 by a hardware reset for cscr0. wsc is cleared by a hardware reset for cscr1 ? cscr5. note: for sync=1 and dol=0, wsc value should be at least 4. for sync=1, mum =0, wsc 2(bcd + 1) + (bcs + lbn + 2)/2. for sync=1, mum =1, wsc? 2(bcd + 1) + (bcs + lbn + 2 + lbh) + 2/2. for psr=1, the number of wait-states is increased by one for read access. 7 ew ecb /wait. this bit determines how weim supports the ecb input in the synchronous mode. in asynchronous mode this bit determines the operation of level-sensitive dtack mode. (see ta bl e 1 7 - 1 8 for ew effect on weim operation modes) 0 for sync = 1, if ecb goes to low state in the middle of memory burst access then the weim starts a new access by asserting the current ahb address to the addr pins and lba assertion (ecb mode). if sync = 0 and wsc=111111, the weim waits for dtack posedge for access termination. 1 if ecb goes to low state in the middle of a memory burst access then the weim waits until ecb goes high (wait mode) to continue current access; at the end of first access in burst it allows to wait ecb negation till 1024 clock. for sync = 0 weim begins access and after (2+dct) clocks tests dtack input. if dtack is low weim waits dtack high state then loads wsc value (see figure 17-27 and figure 17-28 ). 6?4 wws write wait state. this bit field determines whether additional wait-states are required for write cycles (see table 17-11 ). this is useful for writing to memories that require additional data setup time (see example on figure 17-9 ). the dww field should be zero when this field is in use. wws is cleared by a hardware reset. note: to decrease write wait states use the dww bit field. 3?0 edc extra dead cycles. this bit field determines whether idle cycles are inserted before a new access (see example in figure 17-10 ). if the currently accessed cs edc field is not empty then idle cycles are inserted before next access except for two conditions: current access is an asynchronous write (its sync = 0) or the next access is an asynchronous read from the same chip select. this field is used in two cases: slow memory or peripherals that use long cs or oe to output data hold times to prevent data bus contention on back-to-back external transfers. synchronous accesses (sync = 1) to provide cs high minimum pulse width (even for back-to-back accesses). the edc field is cleared by a hardware reset. note: on some occasions, setting edc field to 0000 may result in memory read/write mistakes. therefore, the recommended configuration for edc field is 2 or higher. 0000 no idle ahb clock cycles inserted. 0001 1 idle ahb clock cycle inserted. ? 1111 15 ahb clock cycles inserted. table 17-9. chip select x upper control register field descriptions (continued) field description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-16 freescale semiconductor 17.5.3.2 chip select x lower control register (cscrxl) figure 17-4 shows the register and table 17-12 provides its field descriptions. table 17-10. psz bit field values psz pme=0 memory burst length pme=1 number of words in page 00 4 4 01 8 8 10 16 16 11 continuous 32 table 17-11. wsc bit field values wsc number of wait-states read access write access wws = 0, dww = 0 wws = 1, dww = 0 wws = 7, dww = 0 wws = 0, dww = 1 wws = 0, dww = 2 000000111711 000001112811 000010223911 000011 3 3 4 10 2 1 000100 4 4 5 11 3 2 ?????? 110111 119 119 120 126 118 117 111000 120 120 121 127 119 118 111001 121 121 122 127 120 119 111010 122 122 123 127 121 120 111011 123 123 124 127 122 121 111100 124 124 125 127 123 122 111101 125 125 126 127 124 123 111110 126 126 127 127 125 124 111111 posedge sensitive dtack mode wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-17 0xd800_2004 (cscr0l) 0xd800_2014 (cscr1l) 0xd800_2024 (cscr2l) 0xd800_2034 (cscr3l) 0xd800_2044 (cscr4l) 0xd800_2054 (cscr5l) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r oea 1 1 oea (bits 28?31) reset value is 1010 for cscr0l register and 0 for other registers oen ebwa ebwn w reset0000000000000000 1514131211109876543210 r csa ebc 2 2 ebc (bit 11) reset value is 1 for cscr0l register and 0 for other registers dsz 3 3 dsz (bits 8?10) reset value is configurable for the cscr0l register and 0 for other registers csn 4 4 csn (bits 4?7) reset value is 0100 for cscr0l register and 0 for other registers psr cre wra p csen w reset0000000000000000 5 5 bit 0 reset value is 1 for cscr0l register and 0 for other registers figure 17-4. chip select x lower control register wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-18 freescale semiconductor table 17-12. chip select x lower control register field descriptions field description 31?28 oea oe assert. this bit field determines when oe is asserted during a read cycle. for sync = 0, oea determines number of half clocks before oe asserts during a read cycle. for sync = 1, after initial memory burst access, oe is asserted continuously for subsequent memory burst accesses, and is not affected by oea (see memory burst read timing diagram for more detail); the behavior of oe on initial memory burst access is same as when sync = 0 (see example on figure 17-25 ). oea field do not affect the cycle length. oea is set to 1010 by a hardware reset for cscr0l register and is cleared for other registers. note: minimum time oe is asserted is one clock cycle. 0000 0 half ahb clock cycles between oe assertion and end of access 0001 1 half ahb clock cycle between oe assertion and end of access ? 1111 15 half ahb clock cycles between oe assertion and end of access 27?24 oen oe negate. this bit field determines when oe is negated during a read cycle (see example on figure 17-20 ). setting the sync bit (sync = 1) overrides oen and oe negates at the end of a read access and no sooner. oen does not affect the cycle length, except in posedge sensitive dtack mode. oen is cleared by a hardware reset. note: the term ?end of a read access? is the nearest possible address, data or control signal change by another access (an own next access or an access from others pin shared controller). minimum time oe is asserted is one clock cycle. 0000 0 half ahb clock cycles between oe negation and end of access 0001 1 half ahb clock cycle between oe negation and end of access ? 1111 15 half ahb clock cycles between oe negation and end of access 23?20 ebwa eb write assert. this bit field determines when eb [3:0] is asserted during write cycles (see example on figure 17-8 ). this is useful to meet data setup time requirements for slow memories. ebwa does not affect the cycle length. ebwa is cleared by a hardware reset. 0000 0 half ahb clock cycles before eb is asserted. 0001 1 half ahb clock cycle before eb is asserted. ? 1111 15 half ahb clock cycles before eb is asserted. 19?16 ebwn eb write negate. this bit field determines when eb [3:0] outputs are negated during a write cycle (see example on figure 17-8 ). this is useful to meet data hold time requirements for slow memories. ebwn does not affect the cycle length, except in posedge sensitive dtack mode. setting the sync bit (sync = 1) overrides ebwn and eb negates at the end of a write access and according ahb hbstrb[3:0]. ebwn is cleared by a hardware reset. 0000 0 half ahb clock cycles between eb negation and end of access. 0001 1 half ahb clock cycle between eb negation and end of access. ? 1111 15 half ahb clock cycles between eb negation and end of access. 15?12 csa cs assert. this bit field determines when chip select is asserted for devices that require additional address setup time (see example on figure 17-11 ). it does not affect the cycle length. csa is cleared by a hardware reset. note: csa bit setting affects both reads and writes for all weim modes. 0000 0 half ahb clock cycles before cs is asserted. 0001 1 half ahb clock cycle before cs is asserted. ? 1111 15 half ahb clock cycles before cs is asserted. 11 ebc enable byte control. this bit indicates the types of access that assert enable byte outputs eb [3:0] (see example on figure 17-7 ). the eb [3:0] outputs can be configured as byte write enables. ebc is set by a hardware reset for cscr0l register and is cleared for other registers. 0 both read and write accesses assert the eb [3:0]. 1 only write accesses assert the eb [3:0], thus configuring as byte write enables. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-19 10?8 dsz data port size. this bit field defines the width of an external device?s data port as shown in the table 17-13 . dsz is mapped by a hardware reset for cscr0l by the value of the boot_cfg [2:0] bits. boot_cfg [2] maps to dsz [2], boot_cfg [1] maps to dsz [1] and boot_cfg [0] maps to dsz [0]. dsz and mum (multiplexed mode) affected on data port location as shown in ta b l e 1 7 - 1 3 . dsz is cleared by a hardware reset of cscr1l?cscr5l. 7?4 csn cs negate. this bit field determines when chip select is negated for devices that require additional address/data hold times (see example on figure 17-11 ). csn affects only asynchronous (read and write) access (sync=0), and is ignored on synchronous (sync=1). csn does not affect cycle length, except in positive edge sensitive dtack mode. csn is set to 0100 by a hardware reset for cscr0l register and is cleared by a hardware reset for other registers. 0000 0 half ahb clock cycles between cs negation and end of access. 0001 1 half ahb clock cycle between cs negation and end of access. ? 1111 15 half ahb clock cycles between cs negation and end of access. 3 psr pseudo sram enable (burst write enable). this bit enables four function for pseudo sram (for example,. cellularram tm ) or any other device that support these modes: burst write, write wrap disable, read wait state increase and memory control register accessibility. if psr=1, then memory burst write is enable (with sync = 1). in this mode, wrap bit is masked on write time, unless wwu bit is set in cscrxa register, and wait state on read is automatically increased to wsc +1 (see figure 17-40 and figure 17-41 ). an asynchronous access (sync=0) should be used with psr=1 and cre=1 to write to the memory control register. psr is cleared by a hardware reset. 0 psram mode is disabled. 1 psram mode is enabled. 2 cre control register enable. this bit indicates cre memory pin state while writing to cs address space, for psram control register write. for psr=1 the cre bit will be driven on pin addr[23] in a write access time. cre is cleared by a hardware reset. note: sync = 0 should be used to access to psram control register. 0 cre pin 0 1 cre pin 1 1 wrap wrap memory mode. this bit indicates that memory is in wrap mode. wrap size is set using the psz field. in case not matching wrap boundaries in both memory (psz field) and ahb access on current address, weim puts address on address bus and generates lba signal (see example on figure 17-37 ). wrap is cleared by a hardware reset. 0 memory is in not in wrap mode. 1 memory is in wrap mode. 0 csen cs enable. this bit controls the operation of the chip select pin. csen is set by a hardware reset for cscr0l to allow cscr0l to select from an external boot rom. csen is cleared by a hardware reset to cscr1l?cscr5l. 0 chip select function is disabled; attempts to access an address mapped by this chip select results in a error respond on the ahb and no assertion of the chip select output. 1 chip select is enabled, and is asserted when presented with a valid ahb access. table 17-13. dsz bit field values dsz data port size mum=0 mum=1 000 reserved reserved 001 reserved reserved 010 8-bit port, resides on data_in/out [15:8] pins reserved 011 8-bit port, resides on data_in/out [7:0] pins reserved table 17-12. chip select x lower control register field descriptions (continued) field description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-20 freescale semiconductor 17.5.3.3 chip select x additional control register (cscrxa) figure 17-5 shows the register and table 17-14 provides its field descriptions. 100 reserved 16-bit port, resides on addr/m_data_in/out [15:0] pins 101 reserved reserved 110 reserved 32-bit port, resides on addr/m_data_in/out [15:0] and m_data_in/out [31:16] pins 111 reserved the same 0xd800_2008 (cscr0a) 0xd800_2018 (cscr1a) 0xd800_2028 (cscr2a) 0xd800_2038 (cscr3a) 0xd800_2048 (cscr4a) 0xd800_2058 (cscr5a) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ebra ebrn rwa rwn w reset0000000000000000 1514131211109876543210 r mum lah 1 1 lah (bits 13, 14) reset value is 10 for cscr0a and 0 for other registers lbn 2 2 lbn (bits 10 -12) reset value is 100 for cscr0a and 0 for other registers lba dww dct wwu age cnc2 fce w reset 1 3 0 3 mum (bit 15) reset value is determined by settings of boot_cfg inputs (see ta bl e 1 7 - 3 ) for cscr0a and 0 for other registers 000000000000000 figure 17-5. chip select x addition control register table 17-13. dsz bit field values (continued) dsz data port size mum=0 mum=1 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-21 table 17-14. chip select x addition control register field descriptions field description 31?28 ebra eb read assert. this bit field determines when eb [3:0] is asserted during read cycles (see example on figure 17-25 ). ebra does not affect the cycle length. ebra is cleared by a hardware reset. note: minimum time eb is asserted is one clock cycle. 0000 0 half ahb clock cycles before eb asserted. 0001 1 half ahb clock cycle before eb asserted. ? 1111 15 half ahb clock cycles before eb asserted. 27?24 ebrn eb read negate. this bit field determines when eb [3:0] outputs are negated during a read cycle (see example on figure 17-20 ). ebrn does not affect the cycle length, except when in positive edge sensitive dtack mode. setting the sync bit (sync = 1) overrides ebrn and eb negates at the end of a read access but not sooner. ebrn is cleared by a hardware reset. note: minimum time eb is asserted is one clock cycle. 0000 0 half ahb clock cycles between eb negation and end of access. 0001 1 half ahb clock cycle between eb negation and end of access. ? 1111 15 half ahb clock cycles between eb negation and end of access. 23?20 rwa rw assertion. this bit field determines when rw is asserted during write cycles. (see example on figure 17-28 ). rwa is cleared by a hardware reset. note: minimum time rw is asserted is one clock cycle. 0000 0 half ahb clock cycles rw delay 0001 1 half ahb clock cycle rw delay. ? 1111 15 half ahb clock cycles rw delay. 19?16 rwn rw negation. this bit field determines when rw is negated during a write cycle (see example on figure 17-28 ). rwn does not affect the cycle length, except in posedge sensitive dtack mode. setting the sync bit (sync = 1) overrides rwn and rw negates at the end of a write access and no sooner. rwn is cleared by a hardware reset. note: minimum time rw is asserted is one clock cycle. 0000 0 half ahb clock cycles between rw negation and end of access. 0001 1 half ahb clock cycle between rw negation and end of access. ? 1111 15 half ahb clock cycles between rw negation and end of access. 15 mum multiplexed mode. this bit determines the address/data multiplexed mode for asynchronous and synchronous accesses (see examples in figure 17-43 ? figure 17-46 ). port mapping is defined in the table 17-13 . mum is cleared by a hardware reset for cscr1a?cscr5a. for cscr0a mum is configured at reset time with the boot_cfg[4] (see ta bl e 1 7 - 3 ). 0 non-multiplexed mode 1 multiplexed mode 14?13 lah lba to address hold. this bit field determines address hold time after lba de-assertion for mum = 1 only. see example on the figure 17-43 and figure 17-44 . lah is cleared by a hardware reset for cscr1a?cscr5a. for cscr0a lah is set to 10 by hardware reset. 00 0 ahb half clock cycles between lba negation and address invalid. 01 1 ahb half clock cycle between lba negation and address invalid. 10 2 ahb half clock cycles between lba negation and address invalid. 11 3 ahb half clock cycles between lba negation and address invalid. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-22 freescale semiconductor 12?10 lbn lba negation. this bit field determines when lba is negated. for sync=0 and mum =0 lbn determines how many half ahb clock cycle will be between lba negation and end of access (see example on the figure 17-8 ). for sync=0 and mum =1 this field determines lba length (see example on the figure 17-44 ). negation time and lba lengths are listed in table 17-15 . for sync=1 (mum=0 and mum=1) lba negation occurs (lbn+bcd+1) half ahb clock cycles after first bclk posedge detection. lbn does not affect the cycle length, except in positive edge sensitive dtack mode. lbn is cleared by a hardware reset for cscr1a?cscr5a. for cscr0a lbn is set to 100 by hardware reset. note: minimum of time lba to be asserted is a one clock for mum = 0 and two clocks for mum = 1. 9?8 lba lba assertion. this bit field determines when lba is asserted according the settings shown below (see example on the figure 17-11 ). lba is cleared by a hardware reset. note: lba field affects all modes. minimum of time lba to be asserted is a one clock for mum = 0 and two clocks for mum = 1. 00 0 ahb half clock cycles between beginning of access and lba assertion. 01 1 ahb half clock cycle between beginning of access and lba assertion. 10 2 ahb half clock cycles between beginning of access and lba assertion. 11 3 ahb half clock cycles between beginning of access and lba assertion. 7?6 dww decrease write wait state. this bit field in combination with wws determines whether write cycles are shorter than the read cycles (see ta bl e 1 7 - 1 1 ). wws field should be zero when this field is in use. dww is cleared by a hardware reset. 5?4 dct dtack check time. this bit field determines time of insensitivity at the beginning of access for sync=0 and ew=1 according to the settings shown below (see example on the figure 17-27 ). dct is a number of clock cycles between cs assertion and first dtack check. dct is cleared by a hardware reset. 00 2 ahb clock cycles between cs assertion and first dtack check. 01 6 ahb clock cycles between cs assertion and first dtack check. 10 8 ahb clock cycles between cs assertion and first dtack check 11 12 ahb clock cycles between cs assertion and first dtack check. 3 wwu write wrap unmask. this bit allow unmask wrap bit in case psr = 1 and write access. wwu is cleared by a hardware reset. 0 prevents wrap during write access 1 allow wrap on write 2 age acknowledge glue enable. this bit is used to enable/disable glue logic between external dtack and internal control logic. the glue logic is a flip-flop that is reset by cs assertion, it?s data input is a constant 1 and dtack goes to it?s clock input. this glue logic is used to synchronize the posedge of the external dtack in a worst noise or a slowly edge grown conditions. age is cleared by a hardware reset. 0 disable glue logic 1 enable glue logic 1 cnc2 chip select negation clock cycles, bit [2]. this bit is used to increase the cnc field to a 3-bit field. see cnc field description in the chip select x upper control register. cnc2 is cleared by a hardware reset. the number of ahb clock cycles produced by both bit fields is shown in ta bl e 1 7 - 1 6 . 0 fce feedback clock enable. this bit is used to enable/disable data capture by bclk_fb. if fce=1, weim used addition one clock to synchronize feedback clock captured data to ahb clock, so read access is slow then fce=0. fce is cleared by a hardware reset. 0 data captured using ahb clock 1 data captured using bclk_fb table 17-14. chip select x addition control register field descriptions (continued) field description wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-23 17.5.3.4 weim configuration register (wcr) wcr contains control bits for the configuration and operation of weim. figure 17-6 shows the register and table 17-17 provides its field descriptions. table 17-15. lbn bit field values lbn half ahb clock cycle between lba negation and end of access lba length, half ahb clock cycle mum = 0 mum = 1 000 0 2 001 1 3 ? ? 111 7 9 table 17-16. cnc/cnc2 bit values cnc2 cnc minimum cs negation, in ahb clock cycle 000 0 001 2 010 3 011 4 100 5 101 6 110 7 111 8 0xd800_2060 (wcr) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 ecp5 ecp4 ecp3 ecp2 w reset0000000000000000 1514131211109876543210 r ecp1 ecp0 aus5 aus4 aus3 aus2 aus1 aus0 00000 bcm mas w reset 0 000000 0 00000001/0 1 figure 17-6. wcr register wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-24 freescale semiconductor 17.6 functional description 17.6.1 configurable bus sizing weim supports byte, halfword, and word operands allo wing access to 8-bit, 16-bit, and multiplexed 32-bit ports. port size is programmable via the dsz field in the corresponding chip select control register. in addition, portion of the data bus used for transfer to or from an 8-bit ports is programmable via the same dsz field. an 8-bit port can reside on data_in/out bus bits [15:8] or [7:0]. a 16-bit port reside on data_in/out bus bits [15:0]. a 32-bit multiplexe d port resides on m_data_in/out bus bits [31:0]. note misaligned transfers are not supported. a word access to or from an 8-bit port requires four ex ternal bus cycles to complete the transfer. a word access to or from a 16-bit port requires two external bus cycles to complete the transfer. a halfword access to or from an 8-bit port requires two external bus cycles to complete the transfer. in case of a multi-cycle table 17-17. weim control register field descriptions field description 31?20 reserved 19-14 ecp5 ecp4 ecp3 ecp2 ecp1 ecp0 ecb capture phase. this bit indicates in which phase of hclk, bclk is generated to the memory for synchronous (cs5, cs4, cs3, cs2, cs1 or cs0) write accesses. this bit is xored with bcs[0] bit in write accesses to determine the bclk starting phase to memory and it also influence on capturing of ecb in weim design. 0 bclk starting phase is as bcs[0] bit indicates. 1 bclk starting phase is the opposite of bcs[0] bit indicates for write accesses only. 13 aus5 aus4 aus3 aus2 aus1 aus0 address unshifted for (cs5, cs4, cs3, cs2, cs1 or cs0). this bit indicates an unshifted mode for address assertion for (cs5, cs4, cs3, cs2, cs1 or cs0) accesses. this bit is cleared by a hardware reset. 0 address shifted according (cs5, cs4, cs3, cs2, cs1 or cs0) port size. 1 address unshifted 7?3 reserved 2 bcm burst clock mode. this bit selects the burst clock mode of operation. it is mainly used for system debug mode. bcm is cleared by a hardware reset. 0 burst clock runs only when accessing a chip select range with sync bit set; when burst clock is not running, it remains in a logic 0 state; when burst clock is running, it is configured by bcd and bcs fields in chip select control register. 1 burst clock runs on every memory access (independent of chip select configuration) 1 reserved 0 mas merged address space. this bit indicates merged address space mode. if mas is set the cs1 address space is merged with cs0 for a total of 256 (for halfword width port and 512 for word width port) mbytes. cs1 output is used as a26. this bit is configured at reset time with the boot_cfg[] pin. 0 standard address space 1 merged address space wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-25 transfer, the lower two address bits (addr[1:0]) ar e incremented appropriately. weim address bus is configured according to dsz field a nd ausx bits, too. there is either one or two bits right shift of ahb address bits for halfword or word width port accor dingly. weim has a data multiplexer which takes the four bytes of the ahb interface data bus and routes them to their required positions to properly interface to memory and peripherals. 17.6.2 weim operational modes weim has 9 main operational modes selected by control fields settings as described in the table 17-18 . for details see corresponding bit fields descriptions. 17.6.3 burst mode memory operation with memory burst mode enabled (sync = 1), weim attempts to translate ahb burst accesses to memory burst accesses, being limited by the memory bur st length, predefined psz value, or memory and ahb wrap/incr boundary crossing non-matching. weim onl y displays the first address accessed in a memory burst sequence unless the page mode emulation (pme) bit is set. weim may translate from some ahb sequential accesses to one or few memory burst s, but not from two ahb nonsequential accesses to one memory burst. for the first access in a memory burst sequence, weim asserts lba ?causing the external burst device to latch the starting burst address?and then toggle th e burst clock (bclk) a predefined number of cycles in order to latch the first unit of data. subsequent accessed data units can then be burst in fewer clock cycles, realizing an overall increase in bus bandwidth. memory burst accesses are terminated by weim whenever it detects that: ? the next ahb access is not sequential, ? the next sequential access crosses boundary with unequal condition (wrap/increment, burst length) on the ahb and memory, table 17-18. weim operation modes field settings control fields brief mode description sync pme mum ew wsc 0 0 0 0 < 11_1111 asynchronous 1 0 asynchronous multiplexed 0 1 asynchronous level sensitive dtack mode 0 0 11_1111 asynchronous posedge sensitive dtack mode 1 1 0 0 < 11_1111 page mode emulation 0 0 0 synchronous burst with restart on ecb negation 1 0 synchronous multiplexed burst with restart on ecb negation 0 1 synchronous burst with wait on ecb negation 1 1 synchronous multiplexed burst with wait on ecb negation wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-26 freescale semiconductor ? current memory burst length reached, ? by external burst device request it needs additiona l cycles to retrieve the next requested memory location. in last case, burst memory device provides an ecb (or wait) feedback signal to weim whenever it is necessary to terminate/postponed the on-going burst se quence. if ew = 0, weim initiate a new (with long first access) memory burst sequence, if ew = 1, weim only waits for ecb negation to continue current memory burst sequence. additionally ew = 1 allows wait states insertion after wait state counter expires, but ecb still asserted. over this a new memory burst sequence should be generated. synchronous mode is also used for burst cellular ram, which supports memory burst writes, which is enabled by psr = 1. 17.6.4 burst clock divisor in some cases it may be necessary to slow the external bus in relation to the internal bus to allow accesses to burst devices that have a maximum operating freque ncy which is less than the operating frequency of internal bus. internal ahb bus frequency (hclk 133 mh z) can be divided by two, three, or four for presentation on the external bus in burst mode opera tion. by programming the bcd field to various values, two signals on the external bus are affected; lba and bclk. lba signal is asserted according to lba field programming and remain asserted until the first falling edge of bclk signal. bclk signal runs with 50% duty cycle until a non-sequential internal re quest is received or an external ecb signal is recognized. caution should be exercised when programming thes e fields to ensure wsc and dol fields are coordinated to provide the desired external bus wa veforms. bcd and dol fields should always get the same value when configured. for example, if bcd field is programmed to 01, dol field should be programmed to 0001 and if bcd field is programme d to 10, dol field should be programmed to 0010. bcm bit in weim configuration register has priority over the bcd field. if bcm = 1, bclk runs at full frequency on every memory access (both with sync=1 and with sync=0). bcm bit is used mainly for system debug mode. it has no functional use of weim. 17.6.5 burst clock start in an effort to allow greater flexibility in achiev ing minimum number of wait states on bursted accesses, user can determine when they want the bclk to start toggling. this allows bclk to be skewed from point of data capture on the ahb clock by any number of ahb clock phases. care must be exercised when setting bcs field in conjunction with the bcd, wsc, and dol fields. see external timing diagrams from section 17.8.4, ?burst memory accesses timing diagrams ? for some examples of how to use the bcs, bcd, wsc, and dol fields together. 17.6.6 page mode emulation setting pme and sync bits causes weim to perform memory bursted accesses by emulating page mode operation. lba signal remains asserted for entire access, burst clock does not send a signal, and the external address asserts when each access are made. the initial access timing is dictated by the wsc field, and the page mode access timing is dictated by the dol field. see external timing diagrams from the section 17.8.2, ?page mode timing diagrams ? for some examples. weim can take advantage of improved page timing for sequential accesses only. acce sses that are on the page but are not sequential in wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-27 nature have their timing dictated by the wsc field. the page size can be set via the psz field to 4, 8, 16, or 32 words (word size is determined by data width of the external memory, such as the dsz field). 17.6.7 psram mode operation a control bit psr is provided to enable psram opera tion. for sync = 1, this bit enables a memory burst write. in this mode, wrap bit on write time is automatically masked (cellularram tm spec wrap supports only for read accesses) unless wwu bit is set. initial wait state value is automatically incremented on read access (see figure 17-40 and figure 17-41 ). bit ew determines how weim supports ecb input. for sync = 1, if ecb goes to low state in middle of memory burst access then weim only waits; it?ll go high (wait mode) to continue current acce ss; at the end of first access in memory burst it allows to wait ecb negation during psram refresh insertion. bi t cre and an unused address line can be used to drive the control register enable (cre) memo ry input to load the psram configuration registers. for psr = 1, cre bit will be driven on pin addr[23] in a write access time. note sync = 0 should be used to access the psram control register. 17.6.8 multiplexed address/data mode a control bit mum allows memory support with mult iplexed address/data bus both in asynchronous and synchronous modes. lbn and lbh bit fields shoul d be used for proper bus timing setup (see figure 17-43 ? figure 17-46 ). 17.6.9 mixed ahb/memory burst modes support to provide mixed sequential/wrap accesses with di fferent length, weim interprets burst signal and generate additional lba signals whenever unequal address or burst boundary crossing condition appears (see section 17.6.3/17-25 ). psz field and wrap bit should be used to notify weim about the current memory burst and wrap condition for proper exte rnal address generation. in case of non matching boundaries in both the memory and ahb access, we im starts a new memory burst access by putting address from ahb on address bus and generating lba signal. for example, table 17-20 shows how weim interprets with various types of ahb access in th e case when memory is configured as 8 beat burst with wrap. 17.6.10 ahb bus cycles support weim uses an arm ahb slave interface. it has a 32-b it bus and supports four tr ansfer types defined in the ahb specification (idle, busy, nonseq, and seq). note only 32-bit accesses are supported for seq mode. it also supports ahb transfers shown in table 17-19 . these ahb cycles will be translated into necessary cycles on the memory side. for optimal operation, arm c ache is configured to 8 beat burst with wrap, a synchronous flash and cellular ram me mory should be configured in 16 word wrap burst mode when wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-28 freescale semiconductor using a 16-bit data port, and in 8 word wrap burst m ode when using a 32-bit data port. weim uses wrap bit and psz field for support different memory configur ations. the controller splits the transaction when needed in some cases (see section section 17.6.3, ?burst mode memory operation ? on page 17-25 ). for example, table 17-20 shows ahb bus sequential accesses breaking in to external memory bursts for memory configured to 8 beat burst with wrap and fo r some different ahb burst types and start addresses. lba (x) means start memory burst access (lba generation) from address x (all addresses in hex form). some examples are shown in figure 17-32 to figure 17-39 . table 17-19. ahb burst cycles supported hburst type supported description 000 single yes single transfer 001 incr yes incrementing burst 010 wrap4 yes 4-beat wrapping burst 011 incr4 yes 4-beat incrementing burst 100 wrap8 yes 8-beat wrapping burst 101 incr8 yes 8-beat incrementing burst 110 wrap16 yes 16-beat wrapping burst 111 incr16 yes 16-beat incrementing burst table 17-20. external memory bursts start addresses for some ahb burst accesses ahb burst type memory data port width ahb burst start address 0 4 8 c 10 14 18 1c wrap8 16-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (10) lba (10) lba (10) lba (10) lba (0) lba (0) lba (0) lba (0) lba (0) lba (0) lba (0) lba (10) lba (10) lba (10) 32-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) incr8 16-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (10) lba (10) lba (10) lba (10) lba (20) lba (20) lba (20) lba (20) lba (20) lba (20) lba (20) lba (30) lba (30) lba (30) 32-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (20) lba (20) lba (20) lba (20) lba (20) lba (20) lba (20) wrap4 16-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) 32-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (0) lba (0) lba (0) lba (10) lba (10) lba (10) incr4 16-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (10) lba (10) lba (10) lba (20) lba (20) lba (20) 32-bit lba (0) lba (4) lba (8) lba (c) lba (10) lba (14) lba (18) lba (1c) lba (20) lba (20) lba (20) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-29 17.6.11 dtack mode it is a mode where weim timing depends on dtack input signal. this signal may be used in two ways: by posedge sensitive or by level sensitive (with an in itial insensitiveness time). posedge sensitive mode is set by wsc=111111 (ew=0) and selects dtack input as access length control sign (instead of default wsc counter). it means that access length is determined by dtack length. weim begins deasserting control signals after a pproximately 1.5 clock (synchronization de lay) in the sequence according to negation control fields. note it may be required to program csa a nd/or csn fields for a correct word access to 16 or 8-bit port in this mode if corresponding module is cs sensitive. csn maximum value is 6 for this case. level sensitive mode is set by ew=1 (wsc < 111111). the access length is controlled by wsc. in this case, weim begins access (by cs assertion) and after some clocks (according to dct field) checks dtack input. if dtack is low, weim waits for dtack high state and reload wait state counter (see figure 17-27 and figure 17-28 ). for sequential ahb accesses, wher e cs doesn?t negates during burst, dtack is being checked on the first access only. glue logic enabled by age bit of the cscrxa register can be used for noisy or slowly rising dtack . refer age bit description for more details. 17.6.12 internal input data capture in typical case, input data is not sampled by weim but it is sampled by ahb master on the rising edge of hclk when hready is high. weim assert hready si gnal to ahb master (according to wsc or dol count). this allows better performance on the data path. there are 2 cases by which input data gets sampled inside the weim. first one is when an access size is larger then a port size. in this case, weim samples all data coming from the memory device except the last one. for example, if there is a word access to the byte wide memory, weim captures first three input bytes internally and dr ive them together with the last byte to ahb master (last byte is not sampled in weim). weim captures data by rising edge of hclk when wsc (or dol if it is a part of burst) time expi res and (if it depends) suitable ecb or dtack input condition. second case is when a feedback clock is used (fce =1) for synchronous burst. da ta will be sampled on the rising edge of the feedback clock (when wsc or dol time expires and input condition kept) and then those captured data is again sampled by hclk before it will be driven to the ahb master. 17.6.13 error conditions the following conditions cause an error signal: ? access to a disabled chip select (access to a mapped chip select address space where csen bit in the corresponding chip select control register is clear) ? write access to a write-protected chip select a ddress space (wp bit in the corresponding chip select control register is set) ? user access to a supervisor-protected chip sel ect address space (the sp bit in the corresponding chip select control register is set) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-30 freescale semiconductor ? user read or write access to a chip select control register or the weim configuration register ? byte or halfword access to a chip select cont rol register or the weim configuration register ?dtack acknowledge is absent more then 1024 clock ? wait deassertion more then 1024 clock. 17.7 initialization/app lication information weim is ready to work with cs0 after hardware reset, but it has been configured for very slowly access (for boot purpose) without additional setup and hold time. other cs are disabled by hardware reset. so any cs has to be properly initialized be fore using it by writing values to high and low configuration register. example 17-1 shows how to prepare weim and 16-bit flash memory to work in the synchronous mode. example 17-1. weim and flash memory initialization for work in synchronous mode 17.8 external bus timing diagrams the following timing diagrams shows access timing to memory or a peripheral with different timing parameters. all examples are for cs0 , but they are same for any others chip select. eb means one from current used eb [3:0] for asynchronous mode: ? figure 17-7 to figure 17-13 shows halfword read and write accesses to halfword-width memory. ? figure 17-14 to figure 17-24 shows word read and write accesses to halfword-width memory. ? figure 17-25 shows page mode timing diagram, figure 17-26 to figure 17-28 shows two kinds of dtack accesses. ? figure 17-43 and figure 17-44 shows asynchronous data exchange in multiplexed address/data mode with word-width memory. for synchronous (burst) mode: ? figure 17-29 shows synchronous word read accesses to halfword-width memory. ? figure 17-30 shows recommended parameter setting using for synchronous accesses: bclk clock has a short pulse at the end of access. @; config weim to async access with edc, oea, rwa, rwn, ebc, 16 bit port and psr write weim_cscr2u, 0x12020802 write weim_cscr2l, 0x80330d03 @ ; config flash to wrap 8 mode (by half word accesses) write_h (cs2_base_addr+0x2384), 0x60 @ ; offset = 0x11c2 << 1 for 16 bit port write_h (cs2_base_addr+0x2384), 0x03 write_h (cs2_base_addr+0x0), 0xff @ ; flash to read mode @ ; config to weim sync access with wrap8, 16 bit port write weim_cscr2u, 0x13510802 write weim_cscr2l, 0x80330d03 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-31 ? different cases of wrap/increment states on ahb and memory are shown in the figure 17-32 through figure 17-39 for burs size 4. ahb increment/wrap ac cesses with another length are made like this. ? psram read and write accesses are shown in the figure 17-40 and figure 17-41 . ? figure 17-45 and figure 17-46 show synchronous data exchange in multiplexed address/data mode with word-width memory. wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-32 freescale semiconductor 17.8.1 asynchronous memory accesses timing diagrams 17.8.1.1 ahb halfword access to halfword width memory figure 17-7. read access, wsc=1 nonseq read v1 last valid data v1 last valid address v1 read v1 hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 wsc wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-33 figure 17-8. write access, wsc=1, ebwa=1, ebwn=1, lbn=1 nonseq write v1 last valid data write data (v1) unknown last valid data last valid address v1 write last valid data write data (v1) hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_out cs0 rw lba oe eb ebwa ebwn lbn wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-34 freescale semiconductor figure 17-9. read and write accesses, wsc=2, wws=2, ebwa=1, ebwn=2 nonseq nonseq read write v1 v2 last valid data write data last valid data read data last valid addr address v1 address v2 read write read data last valid data write data hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_in data_out rw lba oe eb (ebc=0) eb (ebc=1) cs0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-35 figure 17-10. read and write accesses, wsc=2, wws=1, ebwa=1, ebwn=2, edc=1 nonseq nonseq read write v1 v2 last valid data write data last valid data read data last valid addr address v1 address v2 read write read data last valid data write data write idle read hclk htrans hwrite haddr hready hwdata hrdata bclk addr rw lba oe eb (ebc=0) eb (ebc=1) data_in data_out cs0 cs1 edc wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-36 freescale semiconductor figure 17-11. read and write accesses, wsc=3, csa=1, csn=1, lba=1, lbn=1 nonseq nonseq read write v1 v2 last valid data write data last valid data read data last valid addr address v1 address v2 read write read data last valid data write data hclk htrans hwrite haddr hready hwdata hrdata bclk addr cs0 rw lba oe eb (ebc=0) eb (ebc=1) data_in data_out csa csn csa csn lba lbn lba lbn wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-37 figure 17-12. read accesses, wsc=2, oea=2, cnc=2, bcm=1, ebra=2 nonseq idle seq read read v1 v2 last valid data read data (v1) read data (v2) last valid addr address v1 address v2 read read data read data cnc hclk htrans hwrite haddr hready hrdata bclk addr cs0 rw lba oe eb (ebc=0) eb (ebc=1) data_in (v1) (v2) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-38 freescale semiconductor figure 17-13. read and write accesses, wsc=2, oea=2, ebwa=1, ebwn=2, cnc=2, ebra=2 nonseq idle nonseq read write v1 v2 last valid data write data last valid data read data last valid addr address v1 address v2 read read data last valid data write data cnc cnc hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_in data_out write cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-39 17.8.1.2 ahb word access to halfword width memory figure 17-14. read access, wsc=1, oea=1, ebra=1 nonseq read v1 last valid data v1 word last valid addr address v1 address v1 + 2 read 1st halfword 2nd half word hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-40 freescale semiconductor figure 17-15. write access, wsc=1, ebwa=1, ebwn=1 nonseq write v1 last valid data write data (v1 word) last valid data last valid addr address v1 address v1 + 2 write 1st halfword 2nd halfword hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_out cs0 rw lba oe eb wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-41 figure 17-16. read access, wsc=3, oea=2, ebra=2 nonseq read v1 last valid data v1 word last valid addr address v1 address v1 + 2 read 1st halfword 2nd halfword hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-42 freescale semiconductor figure 17-17. write access, wsc=3, ebwa=1, ebwn=3 nonseq write v1 last valid write data (v1 word) last valid data last valid addr address v1 address v1 + 2 write last valid data 1st halfword 2nd halfword hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_out data cs0 rw lba oe eb wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-43 figure 17-18. read access, wsc=3, oea=4, ebra=4 nonseq read v1 last valid data v1 word last valid addr address v1 address v1 + 2 read 1st halfword 2nd halfword hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-44 freescale semiconductor figure 17-19. write access, wsc=3, ebwa2, ebwn=3 nonseq write v1 last valid write data (v1 word) last valid data last valid addr address v1 address v1 + 2 write last valid data 1st halfword 2nd halfword hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_out data cs0 rw lba oe eb wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-45 figure 17-20. read access, wsc=3, oen=2, ebrn=2 nonseq read v1 last valid data v1 word last valid addr address v1 address v1 + 2 read 1st halfword 2nd halfword hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 ebrn oen wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-46 freescale semiconductor figure 17-21. read access, wsc=3, oea=2, oen=2, ebra=2, ebrn=2 nonseq read v1 last valid data v1 word last valid addr address v1 address v1 + 2 read 1st 2nd hclk htrans hwrite haddr hready hrdata bclk addr data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 halfword halfword wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-47 figure 17-22. write access, wsc=2, wws=1, ebwa=1, ebwn=2 nonseq write v1 last valid write data (v1 word) unknown last valid data last valid addr address v1 address v1 + 2 write last valid data 1st halfword 2nd halfword hclk htrans hwrite haddr hready hwdata hrdata bclk addr data_out data cs0 rw lba oe eb wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-48 freescale semiconductor figure 17-23. write access, wsc=1, wws=2, ebwa=1, ebwn=2 nonseq write v1 last valid write data (v1 word) unknown last valid data last valid addr address v1 address v1 + 2 write last valid data 1st halfword 2nd halfword hclk htrans hwrite haddr hready hwdata hrdata bclk addr cs0 rw lba oe eb data_out data wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-49 figure 17-24. write access, wsc=2, csa=1, wws=1, csn=1 nonseq write v1 last valid write data (word) last valid data last valid addr address v1 address v1 + 2 write last valid data write data (1st halfword) write data (2nd half word) hclk htrans hwrite haddr hready hwdata hrdata bclk addr cs0 rw lba oe eb data_out data wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-50 freescale semiconductor 17.8.2 page mode timing diagrams 17.8.2.1 ahb word accesses to halfword width memory figure 17-25. sequential read access, wsc=7, oea=8, pme=1, sync=1, dol=1, ebra=8 non seq idle read read v1 v1+4 last valid data v1 word v1+4 word last valid v1 read v1 1st v1 2nd v1+4 1st v1+4 2nd hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in addr seq halfword halfword halfword halfword cs0 rw lba oe eb (ebc=0) eb (ebc=1) v1+4 v1+6 v1+2 wsc dol ebra oea wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-51 17.8.3 dtack mode memory accesses timing diagrams 17.8.3.1 ahb word accesses to word-width memory figure 17-26. read access, wsc=3f, oea=8, oen=5, ebra=8, ebrn=5 non read v1 last valid data v1 data last valid read hclk htrans hwrite haddr hready hrdata bclk addr dtack data_in addr seq cs0 rw lba oe eb (ebc=0) eb (ebc=1) v1 v1 data wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-52 freescale semiconductor figure 17-27. sequential read accesses, wsc=1, ew=1, dct=1 nonseq seq idle read read read read v1 last valid data v1 word last valid addr read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr dtack data_in hburst single seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word cs0 rw lba oe eb (ebc=0) eb (ebc=1) inc4 inc4 inc4 inc4 address v1 v1+4 v1+8 v1+12 dct wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-53 figure 17-28. sequential write accesses, wsc=1, ew=1, rwa=1, rwn=1 nonseq seq write v1 last valid addr write hclk htrans hwrite haddr hready hwdata bclk addr dtack data_out hburst seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word cs0 rw lba oe eb inc4 inc4 inc4 inc4 write write write last valid data v1 word v1+4 word v1+8 word v1 word address v1 v1+4 v1+8 rwa rwn wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-54 freescale semiconductor 17.8.4 burst memory accesses timing diagrams 17.8.4.1 ahb word accesses to halfword width memory figure 17-29. non-sequential read accesses, wsc=2, sync=1, dol=0 nonseq nonseq idle read read v1 v2 last valid data v1 word v2 word last valid addr address v1 address v2 read v1 v1+2 v2 v2+2 hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in halfword halfword cs0 rw lba oe eb (ebc=0) eb (ebc=1) halfword halfword wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-55 figure 17-30. sequential read access, wsc=7, oea=8, sync=1, dol=1, bcd=1, bcs=1, ebra=8 non seq idle read read v1 v1+4 last valid data v1 word v1+4 word last valid address v1 read v1 1st v1 2nd v1+4 1st v1+4 2nd hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in addr seq halfword halfword halfword halfword cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-56 freescale semiconductor figure 17-31. non-sequential read accesses, wsc=3, sync=1, dol=1 nonseq nonseq idle read read v1 v2 last valid data v1 word v2 word last valid addr address v1 address v2 read v1 1st v1 2nd v2 1st v2 2nd hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in halfword halfword halfword halfword cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-57 17.8.4.2 ahb accesses to word-width burst memory figure 17-32. increment 4 ahb read access, wsc=2, sync=1, dol=1, wrap=0 in figure 17-32 , any address may be a four word boundary a ddress, but not a memory boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr address v1 read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word cs0 rw lba oe eb (ebc=0) eb (ebc=1) wsc wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-58 freescale semiconductor figure 17-33. increment 4 ahb read access, wsc=2, sync=1, dol=1, wrap=0 in figure 17-33 , (v1+8) is a memory boundary address and may be a four word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word cs0 rw lba oe eb (ebc=0) eb (ebc=1) address v1 address v1+8 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-59 figure 17-34. increment 4 ahb read access, wsc=3, sync=1, dol=1, wrap=0, ew=0 in figure 17-34 , (v1+8) is a memory boundary address and may be a four word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word cs0 rw lba oe eb eb address v1 address v1+8 (ebc=0) (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-60 freescale semiconductor figure 17-35. increment 4 ahb read access, wsc=3, sync=1, dol=1, wrap=0, ew=1 in figure 17-35 and figure 17-36 , (v1+8) is a memory boundary a ddress and may be a four word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word cs0 rw lba oe eb eb address v1 (ebc=0) (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-61 figure 17-36. increment 4 ahb read access, wsc=3, sync=1, wrap=0, ew=1 nonseq seq idle read read read v1 last valid data last valid addr read v1 hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 v1+12 cs0 rw lba oe eb eb address v1 (ebc=0) (ebc=1) v1+4 v1+8 v1+12 v1 v1+8 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-62 freescale semiconductor figure 17-37. increment 4 ahb read access, wsc=2, sync=1, dol=1, wrap=1, psz=0 in figure 17-37 , (v1+12) is a four-word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr address v1 read v1 word v1+4 word v1+8 word v1+12 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst incr4 single incr4 incr4 incr4 seq seq v1+4 v1+8 v1+12 v1+4 word v1+8 word v1+12 word address v1+12 cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-63 figure 17-38. wrap 4 ahb read access, wsc=2, sync=1, dol=1, wrap=0 in figure 17-38 , (v1-4) is a four-word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr address v1 read v1 word v1+4 word v1+8 word v1?4 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst wrap4 single wrap4 wrap4 wrap4 seq seq v1+4 v1+8 v1-4 v1+4 word v1+8 word v1?4 word address v1- 4 cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-64 freescale semiconductor figure 17-39. wrap 4 ahb read access, wsc=2, sync=1, dol=1, wrap=1, psz=0 in figure 17-39 , (v1-4) is a four-word boundary address. nonseq seq idle read read read read v1 last valid data v1 word last valid addr address v1 read v1 word v1+4 word v1+8 word v1-4 word hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in hburst wrap4 single seq seq v1+4 v1+8 v1-4 v1+4 word v1+8 word v1-4 word wrap4 wrap4 wrap4 cs0 rw lba oe eb (ebc=0) eb (ebc=1) wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-65 17.8.5 synchronous accesses timing diagrams with psram 17.8.5.1 ahb sequential accesses to halfword width psram memory figure 17-40. write access, bcd=1, bcs=1, wsc=5, sync=1, dol=1, ew=1, psr=1 v1+4 2nd nonseq seq write v1 v1+4 last valid addr write v1 1-st v1 2nd hclk htrans hwrite haddr hready hwdata bclk addr data_out refresh time v1+4 1st wr_guarg write tail cs0 rw lba oe eb (ebc=0) eb (ebc=1) ecb v1 word v1+4 word idle address v1 halfword halfword halfword v1 1st halfword dol wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-66 freescale semiconductor figure 17-41. read access, bcd=1, bcs=1, wsc=5, sync=1, dol=1, ew=1, psr=1 nonseq seq idle read v1 v1+4 v1 word v1+4 word last valid addr read hclk htrans hwrite haddr hready hrdata bclk addr ecb data_in refresh time cs0 rw lba oe eb (ebc=0) eb (ebc=1) address v1 v1 1st v1 2nd v1+4 2nd v1+4 1st halfword halfword halfword halfword bcs wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-67 17.8.5.2 ahb sequential accesses to word-width psram memory figure 17-42. write access, bcs=1, wsc=4, sync=1, psr=1 nonseq write v1 last valid addr write v1 1-st hclk htrans hwrite haddr hready hwdata bclk addr data_out refresh time wr_guarg write tail cs0 rw lba oe eb ecb idle address v1 v1 v1+8 v1+4 v1+12 v1+8 seq seq v1 v1+4 v1+12 v1+4 v1+8 v1+12 wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-68 freescale semiconductor 17.8.6 multiplexed a/d mode 17.8.6.1 asynchronous word accesses to word-width memory figure 17-43. read access, wsc=7, lba=1, lbn=1, lah=1, oea=7 nonseq read v1 read data read read data hclk htrans hwrite haddr hready hrdata bclk addr/ m_data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 io_dir address v1 last valid data idle last valid addr lah lbn m_data_out external io pins addr/data address v1 read data wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-69 figure 17-44. write access, wsc=7, lba=1, lbn=1, lah=1 nonseq write v1 write hclk htrans hwrite haddr hready hwdata bclk addr/ rw lba oe eb cs0 io_dir address v1 write data last valid data write data idle last valid addr lah m_data_out wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-70 freescale semiconductor 17.8.6.2 synchronous accesses with word-width memory figure 17-45. read access, bcd=1, sync=1, wcs=4, dol=1, lbn=2, lah=1, psr=1 nonseq read v1 read hclk htrans hwrite haddr hready hrdata bclk addr/ data_in rw lba oe eb (ebc=0) eb (ebc=1) cs0 io_dir address v1 last valid data last valid addr v1 data v1+4 data v1 data v1+4 data v1+4 seq idle ecb m_data_out external io pins addr/data address v1 v1 data v1+4 data wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 17-71 figure 17-46. write access, bcd=1, sync=1, wcs=5, dol=1, lbn=2, lah=1, psr=1 nonseq write v1 read hclk htrans hwrite haddr hready hwdata bclk addr/ rw lba oe eb cs0 io_dir last valid addr v1+4 data v1+4 seq idle ecb last valid data v1 data address v1 data v1 v1+4 data lbn m_data_out wireless external interface module (weim) MCIMX27 multimedia applications processor reference manual, rev. 0.2 17-72 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-1 chapter 18 enhanced sdram controller (esdramc) the enhanced synchronous dynamic ram controller (esdramc) provides inte rface and control for synchronous dram memories for the system. sdra m memories use a synchronous interface with all signals registered on a clock edge. a command protocol is used for initialization, read, write, and refresh operations to the sdram and is generated on the signa ls by the controller when required due to external or internal requests. it has support for both singl e data rate rams and double data rate sdrams. it supports 64-mbyte, 128-mbyte, 256-mbyte, and 512- mbyte, 1-gbyte, 2-gbyte, 4-bank synchronous dram by two independent chip selects and with up to 64-mbyte addressable memory per chip select. figure 18-1 shows the enhanced sdram controller top- level diagram that shows the functional organization of the block. 18.1 overview enhanced sdram controller consists of nine major blocks, including the sdram command state machine controller, bank register (page and ba nk address comparators), row/column address multiplexer, configuration registers, refresh reque st counter, command sequencer, size logic (splitting access), data path (data aligner/multiplexer), lpddr interface, and the power down timer. 18.1.1 sdram command controller this functional block controls th e majority of the actions within the enhanced sdram controller, including 12 ff indicating if the bus to the memory is busy for the next 12 cycles, and all the command to the memory are executing through this block. 18.1.2 bank model there are a total of 8 address comparators, one compar ator for each of the 4 banks within a chip select region. the comparators are used to determine if a re quested access falls within the address range of a currently active sdram page. the bank model incl udes also all timing parameters comparators. 18.1.3 decoder and address mux all synchronous sdrams incorporate a multiplexed address bus, although the address folding points vary according to memory density, number of data i/o, and the processor data bus width. the enhanced sdram controller takes these variables into a ccount and provides the proper alignment of the multiplexed address through the comb ination of the row/column addr ess multiplexer, non-multiplexed address pins, and the connect ions between the controller and the memory devices. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-2 freescale semiconductor figure 18-1. enhanced sdr/lpddr sdram controller block diagram decoder ahb bus n and address mux cs config_reg n ba(sdram) 2 ma(sdram) 14 csd (sdram) 2 command control ras (sdram) cas (sdram) we (sdram) command sequencer command get_new_command next_command n addr 32 control n master arbitration data path wdata(sdram) 32 rdata(sdram) 32/16 dqm(sdram) 4 fb_clk(i/o) wr_data wr_ack rd_data rd_ack 64/32 64 size logic n control access_ctrl n config_reg addr(mab) (mab) get_new_access lpack(crm) wack(wdog) bank model #1 #2 #3 #4 #5 #6 #7 #8 refresh sequencer ipg_clk_32k(crm) #1 #2 bigendian p_lpmd(ccm) 4 sd_clk(sdram) #2 config and control register #1 hclk(crm) 9 timing and status cke(sdram) 2 powerdown timer #1 #2 rst 32 8 3 15 5 wdata(sdram) 32 rdata(sdram) 32/16 fb_clk(i/o) lpddr interface dqs_in dqs_out mddr_sd_clk_b(mddr) 4 4 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-3 18.1.4 esdramc control and configuration registers control and configuration registers determine the operating mode of the m3if. memory device density and bus width, number of memory devi ces, cas latency, row to column delay, and burst length, and others are all configurable. enable bits are provided for refresh and the power down timer. mode bits provide a mechanism for software initiated sdram initialization, setting the device mode register, precharge, and auto-refresh cycles. 18.1.5 refresh sequencer sdram memories require periodic refresh to retain data. the refresh request counter generates requests to the sdram command controller to perform those re fresh cycles. requests are scheduled according to a 32-khz clock input. one, 2, 4, 8, or 16 refres h cycles are generated per a 32-khz clock. 18.1.6 command sequencer the command sequencer block send the commands be exec uted (precharge (all/bank), active, read, write, and burst terminate) to the command controller, after taking in account the bank?s state of the access, the command controller execute signal and the command busy situation. 18.1.7 size logic the size logic block gets as inputs from one side the address, access size, and wrap/incr access, and from the other side the configuration va lues?burst length and dsiz. in case of a misaligned access, the size logic splits the access into multiple access as a functions of all inputs. 18.1.8 mobile/low power ddr (lpddr) interface the lpddr interface adds ability to interface with low power double data rate sdramit converts the double data rate which is synchronized to both positive and negative edges of the dqs signals to a double width of data bus synchronized to the positive edge of the controller internal clock (which is derived from hclk). the interface uses a read fifo which samples the data with delayed dqs (data strobe) in read cycles. two read fifos are used: one for positive clock edge and the other is for negative clock edge. delay lines are used to generate a delayed version of dqs input signals in order to sa mple the data at the middle of the data valid window. in write cycles dqs are output signals that are generated using a delay lines. the data at the input to the interface has a double width from the memory so it is divided into the memory width but with double frequency. for this purpose a mux is used to pass the upper half and lower half of the data. this way in read cycles we receive double rate data with a dqs signal wh ich is edge-aligned with read data and create double data rate and centered dqs in write cycles. dqs delay lines are based on three units: 1. measurement unit which measures one cycle time fr om positive edge to the next positive edge. the output of this unit is the number of small delay unit needed to delay a specific positive edge of the clock to overlap the following positive edge. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-4 freescale semiconductor 2. dividing the result of the measurement by 4. 3. delay unit take the result and selects the correct delay tap. the delay unit is duplicated 5 times: 4 units for read (each byte has dqs signal) and one unit for write (to delay the data sampling). 18.1.8.1 power down timer a power down timer detects periods of inactivity to the sdram and disables the clock when the inactive period surpasses the selected time-out. data is retain ed during the power down state. subsequent requests to the sdram incur only a minimal added start-up de lay (beyond the normal access time, as specified in table 18-26 ). the power down timer may be programmed to expire anytime the controller is not actively reading/writing the memory, after 64 or 128 cl ocks of inactivity, or disabled entirely. 18.1.9 features the esdramc includes the following features: ? optimization of consecutive memory accesse s through memory command anticipation (latency hiding) ? hiding latency by optimization the commands to both cs connected-command anticipation ? keeping track of open memory pages ? bank-wise memory address mapping ? sdram burst length configuration of 4 or 8 (for 16-bit memory burst length 4 is not supported) or full page mode ? lpddr burst length configuration of 8 ? support of different internal burst length (1/4/8 words) by using burst truncate commands ? arm amba ahb light compliant ? shared address and command bus to sdram/lpddr ? supports 64-mbyte, 128-mbyte, 256-mbyte, 512-m byte, 1-gbyte, 2-gbyte, 4-bank, single data rate, synchronous sdram, and lpddr ? two independent chip selects ? up to 256-mbyte per chip select ? up to four banks active simultaneously per chip select ? jedec standard pinout/operation ? support for 16-bit and 32-bit mobile/low power ddr266 devices ? pc133-compliant interface ? 133 mhz system clock achievable with ?-7? option pc133 compliant memories ? single fixed-length (4/8-word) burst or full page access ? access time of 9-1-1-1-1-1-1-1 at 133 mhz (for read access when memory bus is available, row is open and cas latency configured to 3 cycles). the access time includes the m3if delay (assuming no arbitration penalty). enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-5 ? software configurable for different system and memory devices requirements ? 16- or 32-bit memory data bus width ? number of row and column addresses ? row cycle delay (t rc ) ? row precharge delay (t rp ) ? row to column delay (t rcd ) ? column to data delay (cas latency) ? load mode register to active command (t mrd ) ? write to precharge (t wr ) ? write to read (t wtr ) for lpddr memories only ? lpddr exit power down to next valid command delay (t xs ) ? active to precharge (t ras ) ? active to active (t rrd ) ? built in auto-refresh timer and state machine ? hardware and software supported self-refresh entry and exit ? keeps data valid during syst em reset and low power modes ? auto power down timer (one per chip select) ? auto precharge timer (one per bank in each chip select) 18.1.10 modes of operation each of the enhanced sdram controller (esdramc ) operating modes are briefly described in this section. the esdramc?s different operati ng modes for each chip select (csd 0 and csd 1) are defined by the smode field (3 bits) in the esdctl0 and es dctl1 registers respectively. in addition to the normal operating mode, the c ontroller is capable of operating in th e alternate operating modes primarily used for sdram/lpddr initialization. any access to the sdram/lpddr memory space, while in one of the alternate modes, results in the corresponding special cycle being run. moving from norm al to any other mode does not close (precharge) any banks that may be open (activated). under most circumstances, software should run a precharge-all cycle when transitional out of normal read/write mode. reset initializes the operating mode to ?normal read/write?. this is a high level description only, detailed descriptions of ope rating modes are contained in section 18.4, ?functional description .? ? normal read/write mode: this is the normal operating mode used to read/write (single or burst accesses) from/to external sdram/lpddr devices. esdramc automatically drives the precharge/active/burst terminate commands during the normal operating mode. ? precharge mode: the manual precharge command is used to manually deactivate the open row (active) in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (trp) after the precharge command is issued. external memory device input a10 determines whet her one or all banks are to be precharged, and in the case that only one bank is to be precharged, inputs ba0 and ba1 select the bank. the manual enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-6 freescale semiconductor precharge command is used during sdram initialization, load mode register command and manual refresh cycles ? auto refresh mode: the auto refresh command is used to retain data in the sdram memory devices. this command is non persistent, so it must be issued each time a refresh is required. the esdramc has a refresh counter fo r each csd_b (external memory region) and it automatically handles the refresh co mmands toward the memory. the manual auto refresh command is used during sdram initializ ation or in case that the refrsh counters are not enabled. ? load mode register mode: the mode register is us ed to define the specific mode of operation of the sdram device. this definition includes the se lection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode. the mode re gister is programmed via the load mode register command and will retain the stored information until it is programmed again or the external memory device loses power . the mode register must be loaded when all banks are idle (after precharge all). the e nhanced sdram controller will wait a specified (t mrd) period of time as configured in esdcfg0 or esdcfg1 registers. violating either of these requirements by an incorrect cont roller register configuration re sults in unspecified operation. 18.2 external signal description this section discusses input and out put signals between the enhanced sdram controller and the external memory devices. other than the chip select outputs (csd 0 and csd 1) and clock enables (cke0 and cke1), all signals are shared between the two chip select regions. table 18-1 summarizes the interface signals, and is followed by a detaile d description of signal functions. interconnect and timing diagrams are included as part of the detailed discussion on controller operation in section 18.4, ?functional description .? table 18-1. esdramc signal properties name port function reset state direction sd_clk ? clock to sdram (up to 133mhz) 1 output fb_clk_in ? feedback clock 0 input cke0 ? clock enable to sdram 0 0 output cke1 ? clock enable to sdram 1 0 output csd [0] ? chip select to sdram array 0 1 output csd [1] ? chip select to sdram array 1 1 output rdata[31:0] ? read data from memories 0 input wdata[31:0] ? write data to memories 0 output ma[13:0] ? multiplexed address 0 output ba[1:0] ? bank address 0 output dqm3 ? data qualifier mask byte 3 (d[31:24]) 0 output dqm2 ? data qualifier mask byte 2 (d[23:16]) 0 output dqm1 ? data qualifier mask byte 1(d[15:8]) 0 output enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-7 18.2.1 detailed signal descriptions table 18-2 lists the signals and descriptions of all of the i/o signals that interface with the esdramc. dqm0 ? data qualifier mask byte 0 (d[7:0]) 0 output we ? write enable 1 output ras ? row address strobe 1 output cas ? column address strobe 1 output lpack ? low power mode acknowledge 1 output wack ? memory wake up 0 output bigend ? big endian signal system dependent input p_lpmd ? low power mode entry request 0 input mobile lpddr signals mddr_sd_clk_b ? inverted clock to lpddr sdram 0 output dqs_out3 ? data strobe byte 3 (d[31:24]) 0 output dqs_out2 ? data strobe byte 2 (d[23:16]) 0 output dqs_out1 ? data strobe byte 1 (d[15:8]) 0 output dqs_out0 ? data strobe byte 0 (d[7:0]) 0 output dqs_in3 ? data strobe byte 3 (d[31:24]) 0 input dqs_in2 ? data strobe byte 2 (d[23:16]) 0 input dqs_in1 ? data strobe byte 1 (d[15:8]) 0 input dqs_in0 ? data strobe byte 0 (d[7:0]) 0 input table 18-2. esdramc detailed signal description signal i/o description sd_clk o sdram clock. sd_clk output provides the timing reference for the memory devices. all other sdram interface signals are referenced to this clock. sd_clk is synchronous to the system clock, but is gated off during low power operating modes when both cke0 and cke1 are negated. fb_clk_in i feedback clock. the fb_clk_in signal is us ed by the enhanced sdram controller to sample the data during read cycles. the fb_clk_in is a delayed sd_clk, and at a good proximity is identical to the external memory device clock. a delay between sd_clk and fb_clk_in compensates the pad input/output buffers, chip route. ckeo cke1 o sdram/mmdr clock enables. clock enable outputs to the sdram memory devices. cke0 corresponds to sdram/lpddr array 0 and cke1 to sdram/lpddr array 1. activates the memory?s clock input when high, indicating a stable clock is being supplied. deactivates the memory?s clock input when low. ckex low initiates power down and self refresh modes to the sdram. table 18-1. esdramc signal properties (continued) name port function reset state direction enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-8 freescale semiconductor csd0 csd1 o sdram/lpddr chip select. csd0 and csd1 are used to select sdram/lpddr array 0 and sdram/lpddr array 1, respectively. the chip select signals are used to indicate when a valid command is present on the other control signals and to which device the command is directed. rdata[31:0] wdata[31:0] i/o read/write data bus. the 32 data pins are used to transfer data between the enhanced sdram controller and memory. data bit 31 is the most significant bit. bit 0 is the least significant. 16-bit memory alignment is selectable according to the programming of the dsiz field in the esdctl register (see section 18.3.3, ?register descriptions ?). ma[13:0] o multiplexed address bus specifies the sdram page and location within the page targeted by the current access. connections between enhanced sdram controller and memory will vary depending on sdram device density, consult section 18.4.2, ?address multiplexing ? and specifically table 18-23 and ta bl e 1 8 - 2 4 for details on supported sdram configurations. ba[1:0] o bank address bus. the bank address pins specify to which bank the current command is targeted. table 18-23 and ta b l e 1 8 - 2 4 document which address pins are used as the bank address bus for given device configuration. dqm3, dqm2, dqm1, dqm0 o data qualifier mask. during read cycles, dqmx controls the sdram data output buffers. dqmx asserted high disables the output buffers leaving them in a high-impedance state. dqmx low allows the data buffers to drive normally. during write cycles, dqmx controls which bytes are written in the sdram. dqmx driven low enables a write to the corresponding byte, while dqmx asserted high leaves the byte unchanged. dqm0 corresponds to d[7:0] and dqm3 to d[31:24]. sixteen bit memories require only two dqm connections. memories aligned to the upper data bus (d[31:16]) connect to dqm2 and dqm3, while memories aligned to the lower data bus (d[15:0]) connect to dqm0 and dqm1. the esdramc takes care of the endian operating mode, and drives the respective dqm strobe required. note: when the controller is used to interface mobile/low power ddr, dqm will change twice each cycle (like the data) and will be aligned to dqs edges. we o write enable is part of the three bit command field (ras and cas make up the other two bits) used by the sdram. generally, sdwe is asserted low if a command transfers data to the memory. a detailed summary of the supported sdram commands is provided in ta bl e 1 8 - 2 7 . ras o row address strobe is also part of sdram command field. it is generally used to indicate an operation affecting an entire bank or row. ras is an active low signal. table 18-27 provides details on sdram command encoding. cas o column address strobe is the third signal comprised in the command field. it generally signifies a column oriented command. cas is an active low signal. ta bl e 1 8 - 2 7 provides details on sdram command encoding. lpack o low power mode acknowledge. this signal indicates that the external memory devices operates in one of the low power mode. this signal is used by the system clock and reset module to enable the deactivation of the system clock during system low power operating mode. the default value of lpack is high, not to affect in case that the memory devices are not used/disabled. l_lpmd i low power mode entry indication. this input signal (from the crm) is used as a low power mode entry indication. during run mode p_lpmd value is 0. while there is a system request to enter low power mode (stop) the p_lpmd value changes to 1. during sleep mode the esdctl clock is shut off, so the external memory devices need to enter self refresh. this change will cause the esdctl to complete all active/pending requests afterwards, the external memory devices will be placed in self refresh mode. table 18-2. esdramc detailed signal description (continued) signal i/o description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-9 18.3 memory map and register definition the enhanced sdram controller programming model c onsists of control and configuration registers (32-bit length) for each chip select a nd a miscellaneous register, as shown in table 18-3 . the control register maintain system dependent informati on, while the configuration register maintain sdram/lpddr memory device dependent informati on. esdcfg0 defines the operating characteristics for the region selected by csd0 , while esdcfg1 does the same for the csd1 region. bit field assignments within the registers are identical, so a single description will apply to both registers. both the control and configuration registers are 32 bits in length with bit fields defined in figure 18-4 to figure 18-7 , respectively. all implemented bits are fully readable and writable. reserved bit locations are unaffected by writes and always read back as zero. all register accesses must be single word (32-bit) operations through the ahb bus protoc ol. accesses of any other size wi ll have indeterminate results. all enhanced sdram controller registers can be access only by one master at a time. multi access to the enhanced sdram controller register causes undetermined behavior. reset state of each bit is shown underneath the bit field name. an asterisk indicates that the value is dependent on the operating mode selected during rese t. details are provided in the following bit field descriptions. 18.3.1 memory map the esdramc supports 64-mbyte, 128-mbyte, 256-mbyt e, 512-mbyte, 1-gbyte and 2-gbyte, 4 bank, single data rate, synchronous drams on two independent chip selects. each chip selects defines a specific wack o external memory device wakeup. this signal indicates that the external memory device power up period is over, so the initialization commands can be issued. this signals goes down during reset or low power operating mode. this signal can be used by the system watchdog module to disable/mask watchdog reset/interrupt during the time wack is low. sd_clk/mddr_sd_c lk o lpddr sdram inverted clock. sd_clk and mddr_sd_clk are mobile/low power ddr differential clocks. all lpddrs address and control input signals are sampled on the crossing of the positive edge of sd_clk and negative edge of mddr_sd_clk . internal clock signals are derived from sd_clk/mddr_sd_clk . dqs_out3, dqs_out2, dqs_out1, dqs_out0 o data strobes outputs. data strobes are used for data capture for lpddr memory. during write cycles, they are generated by the sdramc controller and are centered with write data. dqs3 corresponds to the most significant byte and dqs0 to the least significant byte. dqs_in3, dqs_in2, dqs_in1, dqs_in0 i data strobes inputs. during read cycles, dqs_inx are generated by the memory devices and are edge aligned with read data. for read data, the controller receives a dqs signal that is edge aligned with the read data. the dqs delay module is used to delay the dqs signal and center it in the data valid window. bigend i big endian. defines the byte ordering. for example, it controls how multi-byte objects are represented by the underlying architecture. this signal is driven by the arm platform, and defines two endianess modes, little and big as illustrated in figure 18-3 . table 18-2. esdramc detailed signal description (continued) signal i/o description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-10 freescale semiconductor memory address mapped as shown in table 18-4 . table 18-3 shows the esdramc memory map and table 18-4 shows the esdramc register definition. 18.3.2 register summary figure 18-2 shows the key to the register fields and table 18-5 shows the register figure conventions. figure 18-2. key to register fields table 18-3. esdramc memory map address register access reset section/page 0xd800_1000 (esdctl0) enhanced sdram control register 0 r/w 0x0111_0080 18.3.3.1/18-13 0xd800_1004 (esdcfg0) enhanced sdram configuration register 0 r/w 0x0076_eb3a 18.3.3.2/18-18 0xd800_1008 (esdctl1) enhanced sdram control register 1 r/w 0x8112_0080 18.3.3.1/18-13 0xd800_100c (esdcfg1) enhanced sdram configuration register 1 r/w 0x007a_c727 18.3.3.2/18-18 0xd800_1010 (esdmisc) enhanced sdram miscellaneous register r/w 0x0000_0000 18.3.3.3/18-31 0xd800_1020 (esdcdly1) enhanced mddr delay line 1 configuration debug register r/w 0x001c_0000 18.3.3.4/18-33 0xd800_1024 (esdcdly2) enhanced mddr delay line 2 configuration debug register r/w 0x001c_0000 18.3.3.4/18-33 0xd800_1028 (esdcdly3) enhanced mddr delay line 3 configuration debug register r/w 0x001c_0000 18.3.3.4/18-33 0xd800_102c (esdcdly4) enhanced mddr delay line 4 configuration debug register r/w 0x001c_0000 18.3.3.4/18-33 0xd800_1030 (esdcdly5) enhanced mddr delay line 5 configuration debug register r/w 0x001c_0000 18.3.3.4/18-33 0xd800_1034 (esdcdlyl) enhanced mddr delay line cycle length debug register r n/a 18.3.3.5/18-35 table 18-4. esdramc memory map address use access 0xa000_0000?0xafff_ffff csd0 sdram or lpddr memory region (256 mbyte) read/write 0xb000_0000?0xbfff_ffff csd1 sdram or lpddr memory region (256 mbyte) read/write always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-11 table 18-6 shows the esdramc register summary. table 18-5. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read-only. writing this bit has no effect. wwrite-only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 18-6. esdramc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xd800_1000 (esdctl0) r sde smode sp row 0 0 col 00 dsiz w r srefr 0 pwdt 0 fp bl 0 prct w 0xd800_1004 (esdcfg0) r 0 0 0 0 0 0 0 0 0 txp twtr trp tmrd w r twr tras trrd tcas 0 trcd trc w 0xd800_1008 (esdctl1) r sde smode sp row 0 0 col 00 dsiz w r srefr 0 pwdt 0 fp bl 0 prct w enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-12 freescale semiconductor 0xd800_100c (esdcfg1) r 0 0 0 0 0 0 0 0 0 txp twtr trp tmrd w r twr tras trrd tcas 0 trcd trc w 0xd800_1010 (esdmisc) r sdram_ rdy 00000000 0 0 0 0 0 0 0 w r 0 00000000 ma1 0_s har e lhd mddr _mdis 0 md dr en 00 w mdd r_dl _rst rst 0xd800_1020 (esdcdly1) r sel_dly _reg_1 0 0 0 0 dly_corr_1 w r 0 0 0 0 0 dly_reg_1 w 0xd800_1024 (esdcdly2) r sel_dly _reg_2 0 0 0 0 dly_corr_2 w r 0 0 0 0 0 dly_reg_2 w 0xd800_1028 (esdcdly3) r sel_dly _reg_3 0 0 0 0 dly_corr_3 w r 0 0 0 0 0 dly_reg_3 w 0xd800_102c (esdcdly4) r sel_dly _reg_4 0 0 0 0 dly_corr_4 w r 0 0 0 0 0 dly_reg_4 w 0xd800_1030 (esdcdly5) r sel_dly _reg_5 0 0 0 0 dly_corr_5 w r 0 0 0 0 0 dly_reg_5 w table 18-6. esdramc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-13 18.3.3 register descriptions this section consists of register descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. note memory may be viewed from either a big endian or little endian byte ordering perspective depending on th e processor configuration (see figure 18-3 ). in big endian mode (the typical default operating mode), the most significant byte (byte 0) of word 0 is located at address 0. for little endian mode, the most significant byte of word 0 is located at address 3. within registers, bits are numbered with in a word starting with bit 31 as the most significant bit. by convention, byte 0 of a register is the most significant byte regardless of endian mode. figure 18-3. data organization in memory 18.3.3.1 esdctl0 and esdctl1 control registers this register contains the controlling various memory and control settings for the esdramc. the bit assignments for the register are shown in figure 18-4 and figure 18-5 . the field descriptions for the bit assignments are listed in table 18-7 . 0xd800_1034 (esdcdlyl) r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 0 0 0 0 dly_cycle_length w table 18-6. esdramc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte 0 byte 4 byte 8 byte 9 byte 5 byte 1 byte 2 byte 6 byte a byte b byte 7 byte 3 big endian mode byte 3 byte 7 byte b byte a byte 6 byte 2 byte 1 byte 5 byte 9 byte 8 byte 4 byte 0 little endian mode word at 0 word at 4 word at 8 word at 0 word at 4 word at 8 31 0 31 0 : : enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-14 freescale semiconductor 0xd800_1000 (esdctl0) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sde smode sp row 0 0 col 00 dsiz w reset0000000100010001 1514131211109876543210 r srefr 0 pwdt 0 fp bl prct w reset0000000010000000 figure 18-4. enhanced sdram control register (esdctl0) 0xd800_1008 (esdctl1) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sde smode sp row 0 0 col 00 dsiz w reset1000000100010010 1514131211109876543210 r srefr 0 pwdt 0 fp bl prct w reset0000000010000000 figure 18-5. enhanced sdram control register (esdctl1) enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-15 table 18-7. enhanced sdram control register (esdctl0/1) field descriptions field description 31 sde enhanced sdram controller enable. this control bit enables/disables the enhanced sdram controller. the reset value of the sde0 bit is ?0?, means the module is disabled for csd0. writing a one to those control bits enables the module, for both chip selects. clearing those bits disables the module. by disabling both bits (sde0 and sde1) all clocks within the module shuts off (with the exception of register accesses). 0 disabled 1 enabled 30?28 smode sdram controller operating mode. this bit field determines the operating mode of the enhanced sdram controller. in addition to the normal operating mode, the controller is capable of operating in the alternate operating modes listed below. these modes are primarily used for sdram initialization. any access to the sdram memory space, while in one of the alternate modes, will result in the corresponding special cycle being run. moving from normal to any other mode does not close (precharge) any banks that may be open (activated). under most circumstances, software should run a precharge-all cycle when transitional out of normal read/write mode. operating mode details are provided in section 18.4, ?functional description .? reset initializes the operating mode to ?normal read/write?. 000 normal read/write 001 precharge command 010 auto-refresh command 011 load mode register command 100 manual self refresh 101 ? 111 reserved 27 sp supervisor protect. this control bit is used to restrict user accesses within the chip select region. the default at reset are that both user and supervisor accesses are allowed. 0 user mode accesses are allowed to this chip select region. 1 user mode accesses are prohibited. an attempted access to this chip select region while in user mode will result in a high hresp[1] being returned back to the cpu. the chip select will not be asserted. esdramc error response is generated by the m3if arbitrator. 26?24 row row address width. this control field specifies the number of row addresses used by the memory array. this number does not include the bank, column, or data qualifier addresses. parameters affected by the programming of this field include the page-hit address comparators and the bank address bit locations. 000 11 row addresses 001 12 row addresses 010 13 row addresses 011 14 row addresses 100 15 row addresses 101?111 reserved 23?22 reserved 21?20 col column address width. this control field is used to specify the number of column addresses in the memory array and will determine the break point in the address multiplexer. column width is the number of multiplexed column addresses and does not include bank, and row addresses, or addresses used to generate the dqm signals. the settings for the col bit field encoding are shown in table 18-8 . 19?18 reserved 17?16 dsiz sdram memory data width. this field defines the width of the sdram memory and its alignment on the external data bus. 16-bit ports may be aligned to either the high or low half word to equalize capacitive loading on the bus. data qualifier mask control outputs must be matched to the selected data bus alignment. memories aligned to d[31:16] use dqm2 and dqm3. memories aligned to d[15:0] use dqm0 and dqm1. 00 16-bit memory width aligned to d[31:16] 01 16-bit memory width aligned to d[15:0] (reset value for csd0) 10 32-bit memory width (reset value for csd1) 11 reserved enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-16 freescale semiconductor 15?13 srefr sdram refresh rate. this control bit field enables/disables sdram refresh cycles and controls the refresh rate. refresh cycles are referenced to a 32 khz clock. at each rising edge 1, 2, 4, 8 or 16 rows are refreshed as determined by this bit field. multiple refresh cycles will be separated by the row cycle delay specified in the src control field. refresh is disabled by hardware reset. srefr bit field encoding settings are listed in table 18-9 . usage example see ta bl e 1 8 - 2 0 . 12 reserved 11?10 pwdt power down timer. this field determines whether the sdram will be placed in a power down condition after a selectable delay from the last access. the power down time-out can be triggered on either the absence of an active bank (pwdt=01) or a clock (hclk) count from the last access (pwdt=10 or 11). count based time-outs do not force the sdram into an idle condition (for example., any active banks remain open). the power down timers feature is disabled by hardware reset. see section 18.4.5.3, ?precharge power down mode ? and section 18.4.5.4, ?active power down mode ? for a comprehensive description of this operating mode. a listing of the pwdt bit field encoding is shown in table 18-10 . 9 reserved 8 fp full page. this bit should be set to 1 if the burst length of the sdram connected to the csd has been configured to full-page mode. this bit is needed since esdramc needs to induce a burst terminate (bt) command to terminate early all accesses that are less than full page. 0 burst length of the external memory device is not set to full page. 1 burst length of the external memory device is set to full page. note: full page mode is not supported when lpddr external devices are used. 7 bl burst length. this bit configures the access burst length. for proper operation the esdramc burst length configuration must match the external sdram/lpddr memory device (configured via special operating mode load mode register). if this bit is set to 1 means that the external memory device connected to the csd have been configured to burst length of 8. if this bit is cleared to 0, means that the external memory device connected to the csd have been configured to burst length of 4. the settings for the burst length bit field encoding is listed in table 18-11 . 6 reserved 5?0 prct precharge timer. precharges a bank after 2xprct clocks (hclk, up to 133 mhz) of no activity. table 18-12 illustrates the prct bit field encoding. ?closing? (due to precharge command) the last used/open row in any non active bank within a chip select reduces the power consumption of the external memory device. the power saving is device dependent, and one should consult/examine the external memory device specification for more details on power consumption reduction. if prct is enabled, a precharge command is issued after approximately number of cycles (as shown in table 18-12 ) of non activity to one of the sdram/lpddr banks. the number of cycles before the precharge command is issued depends on command bus (we, ras, cas and csd) availability (means there is no active access to other bank) and the memory timing parameters. table 18-8. col bit field encoding col[1:0] number of column addresses 00 8 01 9 10 10 11 reserved table 18-7. enhanced sdram control register (esdctl0/1) field descriptions (continued) field description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-17 table 18-9. srefr bit field encoding srefr[2:0] rows each refresh clock # rows/64 ms @ 32 khz row rate @ 32 khz 000 refresh disabled (bit field reset value) 001 1 2048 31.25 s 010 2 4096 15.62 s 011 4 8192 7.81 s 100 8 16384 3.91 s 101 16 32768 1.95 s 110 reserved 111 reserved table 18-10. pwdt bit field encoding pwdt[1:0] power down time-out memory device operating mode 00 disabled (bit field reset value) run mode 01 any time no banks are active precharge power down 10 64 clocks (hclk) after completion of last access 1 1 this setting can?t be used if the prct (precharge timer) is enabled. active power down 11 128 clocks (hclk) after completion of last access 2 active power down table 18-11. burst length bit field encoding bl sdr sdram lpddr sdram 04 1 1 for 16-bit sdram memory devices a bl setting of 4 is not supported. reserved 1 2 2 bit field reset value 88 table 18-12. prct bit field encoding prct[5:0] 1 precharge timer 2 000000 disabled (bit field reset value) 000001 2 clocks to precharge 000010 4 clocks to precharge 000011 6 clocks to precharge 000100 8 clocks to precharge 000101 10 clocks to precharge 000110 12 clocks to precharge enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-18 freescale semiconductor 18.3.3.2 esdramc configuration registers (esdcfg0 /esdcfg1) the bit assignments for the confi guration registers are shown in figure 18-6 and figure 18-7 . the field descriptions for the registers is listed in table 18-13 . 000111 14 clocks to precharge 001000 16 clocks to precharge .... ? 010000 32 clocks to precharge .... ..... 100000 64 clocks to precharge .... ..... 111111 126 clocks to precharge 1 prct can be used only if pwdt is disabled (?00?) or set to ?any time no banks are active (?01?).? prct can?t be used with any other pwdt settings. 2 number of clocks is approximate and it depends on external bus availability. 0xd800_1004 (esdcfg0) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 txp twtr trp tmrd w reset0000000001110110 1514131211109876543210 r twr tras trrd tcas 0 trcd trc w reset1110101100111010 figure 18-6. enhanced sdram configuration register 0 (esdcfg0) table 18-12. prct bit field encoding (continued) prct[5:0] 1 precharge timer 2 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-19 0xd800_100c (esdcfg1) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 txp twtr trp tmrd w reset0000000001111010 1514131211109876543210 r twr tras trrd tcas 0 trcd trc w reset1100011100100111 figure 18-7. enhanced sdram configuration register 1 (esdcfg1) table 18-13. esdcfg0/esdcfg1 field descriptions field description 31?23 reserved 22?21 t xp lpddr exit power down to next valid command delay. this control field determines the minimum delay between a valid command is issued to the lpddr after exiting power down mode. the value programmed in t xp is the number of clocks inserted after exiting power down mode and any subsequent new valid command. an example timing diagram for t xp can be found in figure 18-19 . 00 1 clock delay before new command issued to lpddr after power down mode exit 01 2 clock delay before new command issued to lpddr after power down mode exit 10 3 clock delay before new command issued to lpddr after power down mode exit 11 4 clock delay before new command issued to lpddr after power down mode exit 20 t wtr tlpddr write to read command delay. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be set as shown in figure 18-9 . the lpddrc will automatically induce a t wtr number of idle cycles between a write followed by a read command. the t wtr should be configured according to the lpddr device being used. the t wtr is referenced from the first positive clock edge after the last data-in pair. 0 1 clock 1 2 clocks 19?18 t rp sdram row precharge delay. this control bit determines the number of idle clocks inserted between a precharge command and the next row activate command to the same bank. hardware reset initializes the controller to insert 3 clocks. following a precharge command, a subsequent command to the same bank cannot be issued until t rp is met. 00 1 clock 01 2 clocks 10 3 clocks 1 11 4 clocks 17?16 t mrd tmrd. sdram load mode register to active command. this control bits determines the minimum number of idle clocks required between a load-mode-register (lmr) command to active. hardware reset initializes the controller to insert 2 clocks. 00 1 clock 01 2 clocks 2 10 3 clocks 11 4 clocks enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-20 freescale semiconductor 15 t wr sdram write to precharge command. data for a fixed length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. t wr control bit determines the number of idle clocks inserted between the last desired input data element and the next precharge command, as shown in figure 18-11 . the t wr bit field encoding is listed on table 18-14 . note: the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. 14?12 t ras sdram active to precharge command. these control bits determine the minimum number of clocks required between a active to precharge command to the same bank. hardware reset initializes the controller to insert 6 clocks. following a active command, a subsequent precharge command to the same bank cannot be issued until t ras is met. figure 18-12 presents an example of a single read (without auto precharge). it should be noticed that the precharge command is not allowed at t3 and at t4, since t ras will be violated (for t ras = 4 clock cycles). note that t ras also defines the minimum period of time that the sdram must remain in self refresh mode, as it shown in figure 18-13 . 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 5 clocks 101 6 clocks 2 110 7 clocks 111 8 clocks 11?10 t rrd active bank a to active bank b command. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum interval between successive active commands to different banks is defined by t rrd as shown in figure 18-14 (for t rrd =3). the t rrd bits field encoding is listed below and it determines the number of idle clocks inserted between consecutive active commands to different banks. 00 1 clock active to active (different banks) 01 2 clocks active to active (different banks) 2 10 3 clocks active to active (different banks) 11 4 clocks active to active (different banks) 9?8 t cas sdram cas latency. this field determines the latency between a read command and the availability of data on the bus, as shown in figure 18-15 . this field does not affect the second and subsequent data words in a burst. this control field has no effect on write cycles. cas latency is initialized to 3 clocks following a hardware reset. 00 3 clocks only for lpddr sdram cas latency 2 01 reserved 3 10 2 clocks sdr and lpddr sdram cas latency 11 3 clocks sdr and lpddr sdram cas latency 2 7 reserved table 18-13. esdcfg0/esdcfg1 field descriptions (continued) field description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-21 note esdramc configuration registers reset value defines timing parameters to meet the memory device optimal timing requirements at 133 mhz. if the external memory device operates at a lower frequency the user should reconfigure the timing parameters (according to the device electrical characteristics and operating conditions) for optimal performance. table 18-15 lists and summarizes the enhanced sdram cont roller configurable set of timing parameters for the sdram and lpddr devices. 6?4 t rcd sdram row to column delay. this field determines the number of clocks inserted between a row activate command and a subsequent read or write command to the same bank. hardware reset initializes the delay to 3 clocks. 000 1 clock row to column delay 001 2 clocks row to column delay 010 3 clocks row to column delay 4 011 4 clocks row to column delay 100 5 clocks row to column delay 101 6 clocks row to column delay 110 7 clocks row to column delay 111 8 clocks row to column delay 3?0 t rc sdram row cycle delay. this control field determines the minimum delay between a refresh and any subsequent refresh or read/write access. this delay corresponds to the minimum row cycle time captured in the t rc /t rfc memory timing specification. the value programmed in t rc is the number of clocks inserted between the refresh and subsequent refresh/activate command. an example timing diagram for t rc can be found in figure 18-18 . the bit field settings are listed on ta bl e 1 8 - 1 6 . note: the t rc control field is not used to enforce t rc timing for row activate to row activate within the same bank as this is implicitly guaranteed by the sum of t rcd + t cas + t rp .use regular paragraphs to summarize register function, then use the following special styles to define bit and field function. 1 reset value for csd0?optimal @ 133 mhz. 2 this is a lpddr sdram only configuration. the external lpddr sdram need to be configured to cas latency 3, and esdramc will delay the data (during read cycles) toward the master by and additional hclk cycle. 3 cas1 is not supported due to shared dqm pads in a system 4 reset value for esdcfg1: optimal @ 133 mhz. table 18-14. twr bit field encoding twr write to precharge (sdram) write to precharge (lpddr) 1 1 relevant in case that mddr_en bit is set, that is, the external memory device is a lpddr. 0 1 clock 2 clocks 1 2 clocks 2 2 reset value for csd0 and csd1. 3 clocks 2 table 18-13. esdcfg0/esdcfg1 field descriptions (continued) field description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-22 freescale semiconductor table 18-15. configurable sdram/lpddr timing parameters symbol description relevancy optimal values at 133 mhz t mrd load mode register command to active/refresh command always 2 cycles t wr write recovery time (write to precharge) commands to same bank 2 cycles t ras active to precharge command commands to same bank 6 cycles t rrd active bank a to active bank b command commands to different banks 2 cycles t cas read to data out period (known as cas latency) always 3 cycles t rp precharge command period commands to same bank 3 cycles t rcd active to read or write delay commands to same bank 3 cycles t rc active to active command period commands to same bank 10 cycles t wtr lpddr read to write command delay command to same bank 2 cycles t xp lpddr exit power down to next valid command delay always 4 cycles enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-23 figure 18-8. trp?precharge delay timing enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-24 freescale semiconductor figure 18-9. twtrtrp bit field encoding t figure 18-10. tmrd?sdram load mode register to active command timing diagram enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-25 figure 18-11. twr?write to precharge timing diagram figure 18-12. t ras ?sdram active to precharge command timing diagram enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-26 freescale semiconductor figure 18-13. t ras ?self refresh mode minimum time period figure 18-14. t rrd ?alternating bank read access enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-27 figure 18-15. sdr cas latency timing enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-28 freescale semiconductor figure 18-16. mobile lpddr cas latency timing enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-29 figure 18-17. t rcd ?row to column delay timing enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-30 freescale semiconductor figure 18-18. t rc ?row cycle timing table 18-16. t rc bit field encoding t rc [2:0] delay 0000 20 clocks 0001 2 clocks 0010 3 clocks 0011 4 clocks (reset value for csd0) 0100 5 clocks 0101 6 clocks 0110 7 clocks 0111 8 clocks 1000 9 clocks 1001 10 clocks 1 1 reset value for csd0. 1010 11 clocks 1011 12 clocks 1100 13 clocks 1101 14 clocks 1110 14 clocks 1111 16 clocks enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-31 figure 18-19. t xp ?new command after power down exit (4 cycles) 18.3.3.3 esdmisc miscellaneous register (esdmisc) this register controls various memory and settings for esdramc. the bit assignments for this register is shown in figure 18-20 and the field descriptions for the bit assignments are listed in table 18-17 . 0xd800_1010 (esdmisc) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sdra mrdy 00000000 0 0 0 0 0 0 0 w reset0 00000000 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 00000000 ma10 _sha re lhd mdd r_m dis 0 mdd r en 00 w mddr_ dl_rst rst reset0 00000000 0 0 0 0 0 0 0 figure 18-20. esdramc miscellaneous register (esdmisc) sdramx hclk haddr hwrite sdclk ma[1x:0] ras , cas , sdwe csdx dq nop ckex nop nop row a addr a column a addr b row a column b nop nop act read power down mode exit nop t xp = 4 cycles enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-32 freescale semiconductor table 18-17. enhanced sdram control register (esdctl0/1) field descriptions field description 31 sdramr dy external sdram/lpddr device status. this is a read-only status bit, that indicates the state of the external memory device(s). this bit is cleared at reset. this bit is set after the 200 s sdram/lpddr external memory wakeup period. after the wakeup period the software can start the external memory initialization (as described in section 18.5.4, ?sdram/lpddr initialization sequence ?). 0 sdram/lpddr external device is not ready for use. 1 sdram/mmdr external device is ready for use. 30?7 reserved 6 ma10_s hare ma10 share. need to be enabled if ma10 address line is shared with other memory controllers address line. if enabled, the esdramc will request the address line from the m3if before issuing the precharge all command (during auto refresh cycles). after the precharge all command is completed the esdramc will remove the request. if ma10 share is disable, the esdramc will execute the precharge all command without requesting the ma10 address line, by assuming that ma10 address line is dedicated to esdramc. 0 ma10 share disable 1 ma10 share enable 5 lhd latency hiding disable. this bit disables the command anticipation (latency hiding) mechanism. if this bit is set, the m3if/esdctl will operate in mif1 (non-optimized) mode as shown in figure 18-29 and figure 18-30 . the first memory command of a new access is sent to the memory only after the previous access is completed, for example: the last data word of a burst has been read or written. the reset value of this bit is 0, meaning that the latency bidding is enabled (m3if/esdctl works in mif2 mode) as described in section 18.4.1, ?enhanced sdram controller optimization strategy ?). 0 latency hiding enable 1 latency hiding disable 4 mddr_m dis lpddr delay line measure disable. this is a read/write bit, that, if set, disables the delay line measure unit. after reset, this bit is cleared, meaning the delay line measure unit is enabled. the measure time period is estimated to be around 2000 clock cycles of the ahb hclk. 0 lpddr delay line measure unit is enabled. 1 lpddr delay line measure unit is disabled. 3 mddr_d l_rst lpddr delay line soft reset. this is a write only bit, that if set the delay line unit is reset. after reset the delay unit will automatically (if lpddr_mdis is cleared) start a new measurement. 0 lpddr delay line is not reset. 1 lpddr delay line is reset. 2 mddren enable mobile/low power ddr sdram. this bits activates the lpddr interface and enable the pipeline to work in lpddr mode. 0 enable mobile sdr sdram operation. 1 enable mobile ddr sdram operation. 1 rst software initiated local module reset. this bit generate local module reset to the esdramc. writing a 1 to rst bit results in a one cycle reset pulse to the controller. this bit is always read as 0. all esdramc registers are not affected by the software reset, in order to keep the refresh mechanism active as initially configured, so the sdram/lpddr data is not violated. a burst terminate command is issued to the memory after the soft reset (to terminate any active bursts, in order to prevent potential contention on the data pads). during the software reset an error response (hresp[1]=1) is broadcast to all masters with active access to the esdramc by the multi master memory interface (m3if) module and the m3if arbitration pipeline is cleared. for detailed information on error response refer to m3if module specification. note: after soft reset, a precharge all command must be issued prior to normal usage of the esdramc. 0 soft reset is disabled. 1 soft reset is initiated. 0 reserved enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-33 18.3.3.4 mddr delay line 1?5 configuration debug register these debug registers controls delay line 1 to 5 functi onality, that is, dqs[0] to dqs[4] delays are used during read cycles for line 1 to 5 respectively. it a llows to override/manually set the delay of dqs[0] to dqs[4] lines, that is used during read cycles fo r byte[0] to byte[4] respectively. the delay line compensates for process variations, and produces a cons tant delay regardless of the process, temperature and voltage. the bit assignments for these registers are shown in figure 18-21 to figure 18-25 and the field descriptions for the bit assignments are listed in table 18-18 . figure 18-21. mddr delay line 1 configuration debug register figure 18-22. mddr delay line 2 configuration debug register 0xd800_1020 (esdcdly1) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sel_dly_ reg_1 0000 dly_corr_1 w reset 0 000000000011100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0000 dly_reg_1 w reset 0 000000000000000 0xd800_1024 (esdcdly2) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sel_dly _reg_2 0000 dly_corr_2 w reset0 000000000011100 15 14131211109876543210 r0 0000 dly_reg_2 w reset0 000000000000000 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-34 freescale semiconductor figure 18-23. mddr delay line 3 configuration debug register figure 18-24. mddr delay line 4 configuration debug register 0xd800_1028 (esdcdly3) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sel_dly _reg_3 0000 dly_corr_3 w reset0 000000000011100 15 14131211109876543210 r0 0000 dly_reg_3 w reset0 000000000000000 0xd800_102c (esdcdly4) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sel_dly _reg_4 0000 dly_corr_4 w reset0 000000000011100 15 14131211109876543210 r0 0000 dly_reg_4 w reset0 000000000000000 0xd800_1030 (esdcdly5) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sel_dly _reg_5 0000 dly_corr_5 w reset0 000000000011100 15 14131211109876543210 r0 0000 dly_reg_5 w reset0 000000000000000 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-35 figure 18-25. mddr delay line 5 configuration debug register table 18-18. enhanced mddr delay line 5 control register (esdcdly5) field descriptions 18.3.3.5 mddr delay line cycle length debug register mddr delay line cycle length de bug registers is a read only register that shows the number of inverters that ?fit? in a cycle. the reset value is unknown, because after reset the register value is updated from the measured delay. the register value represents the number of inverters required to achieve a delay of one clock cycle, as a function of the ic conditions (temperature, voltage, fre quency, process). the bit assignments for the register are shown in figure 18-26 and the field descriptions for the bit assignments are listed in table 18-19 . figure 18-26. mddr delay line cycle length debug register field description 31 sel_dly_reg_1?5 this bit selects the delay used by delay line 1?5. it selects between a quarter of a cycle (measured) minus delay line 1?5 correction factor field (dly_corr_1?5) and delay line 1?5 register value (dly_reg_1?5). 0 delay line 1value is, a quarter of a cycle (measured) minus the delay line 4 correction factor field. 1 delay line 1value is, the value of delay line 4 register field (skipping the measurement). 30?27 reserved 26?16 dly_corr_1?5 this field is the delay line 1?5 correction factor. the correction factor is used only if sel_dly_reg_1?5 is cleared. the correction factor value is used to compensate a minimum delay (in number of inverters units) from the measured delay (the minimum delay varies with the process, voltage and temperature changes). 15?11 reserved 10?0 dly_reg_1?5 this field is the delay (in number of inverters units) that will be used by delay line 1?5, if sel_dly_reg1?5 bit is set. since the delay is process, temperature and voltage dependent, for a given value of this filed we get different delay values. 0xd800_1034 (esdcdlyl) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r 0 0 0 0 0 dly_cycle_length w reset 0 0 0 0 0 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-36 freescale semiconductor table 18-19. enhanced mddr delay line cycle leng th debug register (esdcdlyl) field descriptions 18.4 functional description general enhanced sdram controller operating charac teristics are addressed in this section. the discussion starts with the optimization strategy (laten cy hiding/command anticipa tion), continues with one of the most basic of all dram controller features, the address multiplexor. following subsections explain operation out of reset, hardware refresh and the low power modes. more on, each of the enhanced sdram controller operating modes are described. the discussion includes details on basic operation, relationship to sdram/lpddr operating modes, and any special precautions which need to be observed. state and timing diagrams are included where appropriate. the enhanced sdram controller is designed to suppor t a broad range of broad range of jedec standard sdram/lpddr configurations in cluding devices of 64-mbyte, 128- mbyte, 256-mbyte, 512-mbyte, 1-gbyte and 2-gbyte densities. given the physical size constraints of the target applications, the design support memory devices with data widths of 16 and 32 bits. table 18-20 summarizes the devices supported by the design. only 4 bank devices are supported. 133- mhz system bus operation is possible with pc133 compliant single or double data rate memory devices. each of the enhanced sdram controller operating m odes are described in this section. the discussion includes details on basic operation, relationship to sdram/lpddr ope rating modes, and any special precautions which need to be observed. state a nd timing diagrams are included where appropriate. field description 31?11 reserved 10?0 dly_cycle_length dly_cycle_length shows the number of inverters that ?fit? in a cycle. table 18-20. jedec standard single/double data rate sdrams sdram configurations?4-bank devices size 64 mbit 128 mbit 256 mbit 512mbit 1 1 not ratified by jedec, row-column organization may change. 1-gbit 1 2-gbit 1 bus size 16 32 16 32 16 32 16 32 16 32 16 2 2 2-gb sdram/lpddr (16-bit) are not supported/available. 32 depth 4m 2m 8m 4m 16m 8m 32m 16m 64m 32m n/a 64m refresh rows 4096 4096 4096 4096 8192 8192 8192 8192 16384 16384 n/a 16384 refresh rate (us) 15.6 31.25 15.6 15.6 7.81 7.81 7.81 7.81 3.91 3.91 n/a 3.91 refresh cycles21224444 8 8n/a8 row address 1211121213131313 14 14 n/a 14 col. address88989810910 9n/a10 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-37 18.4.1 enhanced sdram controller optimization strategy sdram (sdr and lpddr) memories provide high sp eed access by hiding the latency of consecutive memory accesses through a pipeline interface architectur e. the resulting high bandwidth is achieved with a rather complex command interface and a large numbe r of timing constraints that must be kept by the memory controller. sdram are organized in severa l independent banks. by issuing a row address and bank number to the memory device, the corresponding me mory page is activated (opened). consecutive read commands (together with the column address) in to this memory page (same row address) have a low latency. accessing anothe r page in the same bank requires to close the open page by a precharge command, followed by the activation (active command) of the new memory page (new row address). in figure 18-27 and figure 18-28 examples for an sdr and lpddr sdram read bursts are shown. initially the cell in [col a, row a] is active/open. trying now to access/open the cell position [col b, row b] requires first to close the old sell in [col a, row a]. this is done with a precharge command (p on the figure). now the access row address (row b) can be activated (a on the figure) before the column address (col b) will be passed (read command r). the timing restrictions are: ? the active command can be issued only trp cycles after the precharge command. ? the read command can be issued only trcd cycles after the active command. ? the first data is available only tcas cycles after the read command has been issued. figure 18-27. sdr sdram read burst command sequence example enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-38 freescale semiconductor figure 18-28. lpddr sdram read burst command sequence example hence, in those examples a 4-word (8-word in lpddr will be converted to 4-word with twice data width) read burst requires 9 cycles (6 cycles latency from precharge command to the first word on the external bus) or 6-1-1-1. a read access from an already open row is shown as well, the read burst from target cell [row b, col c] on takes only 5 cycles (2 cycles latency from the read command to the first word on the external bus) or 2-1-1-1. figure 18-29 (sdr) and figure 18-30 (lpddr) shows two different opt imization strategies. first ?no optimization? strategy (referred as mif1) and second th e ?medium level optimization? (referred as mif2). for sdr sdram each strategy, two examples for two consecutive read accesses are given: ? an 8-word burst from the sdram with cas latenc y of 2 cycles followed by an 8-word burst from the same bank and row (different colu mn) with cas latency of 2 cycles. ? an 8-word burst from one bank in the sdram foll owed by an 8-word burst from a different bank to the same sdram. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-39 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-40 freescale semiconductor figure 18-29. sdr sdram optimization strategies?mif1 and mif2 examples for lpddr sdram each strategy, one example fo r two consecutive read accesses is given: ? a 8-word burst from one bank in the lpddr sd ram followed by a 8-word burst from a different bank to the same lpddr sdram. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-41 figure 18-30. mobile lpddr sdram optimization strategies?mif1 and mif2 examples the fact that enhanced sdram controller handles two devices and that each of them features 4 independent memory banks opens the opportunity fo r the controller to optimize the access timing of consecutive memory accesses by trying to hide as much as possible the latency of the first data word in a burst. the latency hiding is possible in the cases that are summarized in table 18-21 . 18.4.1.1 mif1?no optimization/sequential accesses this is the non-optimized case shown in figure 18-29 and figure 18-30 . the first memory command of a new access is sent to the memory only after the previous access is completed, that is, the last data word of a burst has been read or written. it can be seen in this example that although the 2 memory accesses follow with no delay between them, the bandwidth usage fo r the command (address) and data busses is far from being optimal. this no optimization/ sequentia l accesses occurs in the following cases; ? only one master active/present in a given syst em?in this case only sequential commands are possible since the given master need to receive /send (read/write) all data?s for one access before it can proceed to the next access, that is, command anticipation is not possible. ? low density accesses, such as non-overlapped/cons ecutive/continuos requests, means that the next sdram request starts after the previous request is completed. in this low sdram utilization only sequential accesses occurs. table 18-21. possibilities for latency hiding current burst access next burst access sdram bank x sdram bank y sdram bank x (row y, col z) sdram bank x (row y, col w) lpddr sdram bank x lpddr sdram bank y enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-42 freescale semiconductor ? large number of single or incr (aborted after one data) accesses instead of burst type accesses. single/incr refer to amba ahb bus protocol. ? the lhd (latency hiding disable) bit is set. 18.4.1.2 mif2?medium level optimization/command anticipation this strategy is shown in figure 18-29 and figure 18-30 . as soon as the address and command bus (refer as the sdram control bus) is no more used for issuing the previous memory access command, the controller can use this bus to start issuing the pr echarge/active commands for the next scheduled memory access while the previous one is still active on the data bus. two conditions limit the use of this optimization at a given time; ? memory timing constraints must not be violated. ? the execution of the previous command should not be affected (that is, truncated). this approach allows for hiding a part of the latency for the first data word or even the complete hiding of the latency in case that the burst length exceeds the maximal command sequence length. 18.4.1.3 latency hiding enhanced sdram controller optimization is based on command anticipation (mif2), that is, the next access control phase (memory address and command) is driven during the previous access data phase (data flow from/to the memory), thus an overlap between ac cesses is created and latency is partially or fully hidden. additional optimization (not implemented in esdramc) can be achieved by control phase interleaving, that is, during idle cycles in the cont rol phase (caused by memory timing constraints like trp, trcd) two accesses control phases ca n be interleaved so the latency is fully hidden. enhanced sdram controller optimization can occur only in multi master system with high sdram utilization (high density accesses). figure 18-31. sdr simple read after read latency hiding timing diagram as mentioned earlier, esdctl optimize command sequence toward the memories in order to hide latency, so data bus will be used as much as possibl e under the access required and sdram/system initial clock command prec active read read data bus d 1 d 2 d 3 d 4 d10 d11 get new address cs0-000000 cs0-000010 burst size 4 4 execute request enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-43 configuration. in figure 18-31 and figure 18-32 , latency hiding timing diagram example is shown when miss burst read from bank a is followed by a hit burst read request from same chip select. the second read command is issued during the first access data phase, so first data of the second access (d10) is valid immediately after the last data of the first access (d4 for sdr and d8 for lpddr). cas latency (tcas) is set to 2 cycles. the second access latency is fully hidden during the first access data phase. mobile/low power ddr needs another cycle to prevent conten tion on the dqs signals when two different lpddrs (two different chip selects) drive those data strobe signals (contention between the last two data cycles of the first transfer and the preamble of the second transfer). figure 18-32. mobile ddr simple read after read latency hiding timing diagram figure 18-33. sdr miss write to csd1 after read from csd0 at figure 18-33 and figure 18-34 , a burst read to csd0 is followed by a miss burst write access to csd1. due to command anticipation the control phase of the write command overlap the data phase of the read command, so again the second access latency is fu lly hidden during the first access data phase. the first write command to csd1 (d10) is issued immedi ately after the last data (d4 for sdr and d8 for lpddr) from csd0, although the access to csd1 is a miss access (csd0 cas latency is set to 3 cycles, clock command prec active read read data bus d1 d2 d3 d4 d5 d6 d7 d8 d10 d11 d12 dqs get new request address cs0-000000 cs0-000010 burst size 4 4 execute clock command to cs 0 read command to cs 1 prec active write data bus d 1 d 2 d 3 d 4 d10 d11 d 12 d 13 get new request address cs0-000000 cs1-000000 burst size 4 4 execute enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-44 freescale semiconductor and both csd burst length is set to 4 words. lpddr bur st length is 8 but is considered from the system point of view as a burst of 4 with double bus width). figure 18-34. mobile ddr miss write to csd1 after read from csd0 18.4.2 address multiplexing 18.4.2.1 multiplexed address bus table 18-22 illustrates several examples on how a cp u address is scrambled by enhanced sdram controller to implement a contiguous address space. table 18-22. cpu to sdram/lpddr translation cpu address 16-bit sdram 1 32-bit sdram 1 cpu address 16-bit sdram 1 32-bit sdram 1 a25 ? ba1 a17 r6 r5 a24 ba1 ba0 a16 r5 r4 a23 ba0 r11 a15 r4 r3 a22 r11 r10 a14 r3 r2 a21 r10 r9 a13 r2 r1 a20r9 r8a12r1 r0 a19r8 r7a11r0 c9 a18r7 r6a10c9 c8 a9 c8 c7 a4 c3 c2 clock command read command prec active write data bus d1 d2 d3 d4 d5 d6 d7 d8 d10 d11 d12 d13 dqs get new address cs0-000000 cs1-000000 burst size 4 4 execute request to cs 1 to cs 0 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-45 enhanced sdram controller multiplexed address bus is aligned to column addresses so that address line a1 and a2 always appears on pin ma0 for 16-bit and 32-bit memory devices respectively. with this alignment, ?folding point? in multiplexor is driven solely by the number of column address bits. column bus widths of 8 to 11 bits are supported. table 18-23 and table 18-24 summarizes controller multiplex options supported for 16 and 32-bit devices respecti vely. column addresses through a10 are driven regardless of multiplexor configuration, although some of the lines will be unused for smaller page sizes. a8 c7 c6 a3 c2 c1 a7 c6 c5 a2 c1 c0 a6 c5 c4 a1 2 c0 ? a5 c4 c3 a0 3 ?? 1 for sdram example a memory configuration with 10 columns and 12 rows is illustrated. the address translation is based on the following concept, column-row-bank. 2 cpu a1 defines how the data masks are driven, that is, it is used as the byte enable for non word accesses. this bit has a regular/normal use only in case of 16-bit memory, while cpu a0 defines the 2 bytes (low and high) in the 16-bit word. 3 cpu a0 defines how the data masks are driven, that is, it is used as the byte enable for non word accesses to 32-bit memory device. both cpu a0 and a1 defines the 4 bytes in the 32-bit word. 4. legend: c=column, s=segment, r=row, ba=bank table 18-23. address multiplexing by column/row width for 16-bit devices device pins esdctl pins 16-bit sdr and lpddr sdram memory device 64 mb 128 mb 256 mb 512 mb 1 gb 8 col 12 row 9 col 12 row 9 col 13 row 10 col 13 row 10 col 14 row col row col row col row col row col row ba1 ba1 a22 a22 a23 a23 a24 a24 a25 a25 a26 a26 ba0 ba0 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 ma13 ma13 ? ? ? ? ? ? ? ? ? a24 ma12 ma12 ? ? ? ? ? a22 ? a23 ? a23 ma11 ma11 ? a20 ? a21 ? a21 ? a22 ? a22 ma10 ma10 ? a19 ? a20 ? a20 ? a21 ? a21 ma9 ma9 ? a18 ? a19 ? a19 a10 a20 a10 a20 ma8 ma8 ? a17 a9 a18 a9 a18 a9 a19 a9 a19 ma7 ma7 a8 a16 a8 a17 a8 a17 a8 a18 a8 a18 ma6 ma6 a7 a15 a7 a16 a7 a16 a7 a17 a7 a17 ma5 ma5 a6 a14 a6 a15 a6 a15 a6 a16 a6 a16 table 18-22. cpu to sdram/lpddr translation (continued) cpu address 16-bit sdram 1 32-bit sdram 1 cpu address 16-bit sdram 1 32-bit sdram 1 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-46 freescale semiconductor ma4 ma4 a5 a13 a5 a14 a5 a14 a5 a15 a5 a15 ma3 ma3 a4 a12 a4 a13 a4 a13 a4 a14 a4 a14 ma2 ma2 a3 a11 a3 a12 a3 a12 a3 a13 a3 a13 ma1 ma1 a2 a10 a2 a11 a2 a11 a2 a12 a2 a12 ma0 ma0 a1 a9 a1 a10 a1 a10 a1 a11 a1 a11 table 18-24. address multiplexing by column/row width for 32-bit devices device pins esdctl pins 32-bit sdr and lpddr sdram memory device 64 mb 128 mb 256 mb 512 mb 1 gbyte 2 gbyte 8 col 11 row 8 col 12 row 8 col 13 row 9 col 13 row 9 col 14 row 10 col 14 row col row col row col row col row col row col row ba1 ba1 a22 a22 a23 a23 a24 a24 a25 a25 a26 a26 a27 a27 ba0 ba0 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 a26 a26 ma13 ma13 ? ? ? ? ? ? ? ? ? a24 ? a25 ma12 ma12 ? ? ? ? ? a22 ? a23 ? a23 ? a24 ma11 ma11 ? ? ? a21 ? a21 ? a22 ? a22 ? a23 ma10 ma10 ? a20 ? a20 ? a20 ? a21 ? a21 ? a22 ma9 ma9 ? a19 ? a19 ? a19 ? a20 ? a20 a11 a21 ma8 ma8 ? a18 ? a18 ? a18 a10 a19 a10 a19 a10 a20 ma7 ma7 a9 a17 a9 a17 a9 a17 a9 a18 a9 a18 a9 a19 ma6 ma6 a8 a16 a8 a16 a8 a16 a8 a17 a8 a17 a8 a18 ma5 ma5 a7 a15 a7 a15 a7 a15 a7 a16 a7 a16 a7 a17 ma4 ma4 a6 a14 a6 a14 a6 a14 a6 a15 a6 a15 a6 a16 ma3 ma3 a5 a13 a5 a13 a5 a13 a5 a14 a5 a14 a5 a15 ma2 ma2 a4 a12 a4 a12 a4 a12 a4 a13 a4 a13 a4 a14 ma1 ma1 a3 a11 a3 a11 a3 a11 a3 a12 a3 a12 a3 a13 ma0 ma0 a2 a10 a2 a10 a2 a10 a2 a11 a2 a11 a2 a12 table 18-23. address multiplexing by column/row width for 16-bit devices (continued) device pins esdctl pins 16-bit sdr and lpddr sdram memory device 64 mb 128 mb 256 mb 512 mb 1 gb 8 col 12 row 9 col 12 row 9 col 13 row 10 col 13 row 10 col 14 row col row col row col row col row col row enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-47 18.4.2.2 bank addresses bank address connections are summarized in table 18-25 . bank addressing utilizes the most-significant addresses to specify active bank, actual bits being de pendent on the density of memory system. page size and density for a number of potential configurations are documented in table 18-25 . for undocumented configurations, equation 18-1 and equation 18-2 can be used to calculate page size and density. page size (bytes) = 2 # column address bits x (memory width in bits / 8) eqn. 18-1 density (bytes) = 2 (#column address bits + # row address bits) x (memory width in bits / 2) eqn. 18-2 18.4.3 multiplexed address bus?duri ng ?special? mode (smode 1 or 3) during ?special? mode, that is, precharge mode (sm ode=1) or load mode registers (smode=3) there is no address shifting, means cpu addre ss a0 is mapped on ma0 at all memory width. for example, in order to drive ma10 bit (for precharge all command), cpu a1 0 bit should be set (for both 16 or 32 bit external devices). same logic is valid for lo ad mode register command, as seen on initialization routine example in section 18.5.4.1, ?sdram initialization .? note byte accesses are required (during precharge/load mode register modes) since address can be non-aligned, dependi ng on the load mode register data. 18.4.4 refresh enhanced sdram controller hardware satisfies all sdram refresh requirements after an initial configuration by user software. 0, 1, 2, 4, 8 or 16 refresh cycles are scheduled at 31.25 us (nominal 32 khz clock) intervals, providing 0, 2048, 4096, 8192, 16384, or 32768 refresh cycles every 64 ms. refresh rate is programmed through refr field in esdctl0 and esdc tl1 registers. each array can have a different rate, allowing a mix of sdram/lpddr devices, or different sdrams density. refresh is disabled by hardware reset. a refresh request is made pending at each rising edge on the 32 khz clock. in response to this request, the hardware gains control of the sd ram as soon as any in-process bus cycle completes. once it has gained control of the memory, commands are issued to precharge all banks. following a row precharge delay (t rp ), an auto-refresh command is issued. at t rc intervals, additional auto-refresh cycles are issued until the specified number of cycles have been run. table 18-25. bank address bit assignment density page size (bytes) ba1 ba0 8mb x a22 a21 16mb a23 a22 32mb a24 a23 64mb a25 a24 128mb a26 a25 256mb a27 a26 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-48 freescale semiconductor figure 18-35. hardware refresh timing diagram figure 18-36. hardware refresh with pending bus cycle timing diagram dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx pre-all refa hrdata hready >= t rp refa clk32 >= t rc a10=1 data a data a command dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx pre-all refa sdramx hrdata rowx hready t rp (minimum) act clk32 t rc (minimum) command enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-49 figure 18-35 illustrates 2 refresh sequence. burst transfers in progress when the refresh request arrives are allowed to complete prior to the refresh operation. sdram bus accesses queued after the refresh request are held off until refresh completes. in figure 18-36 , an access is queued just as the refresh begins. this cycle is delayed until the precharge and single refres h (refr=01) cycles are run. bus cycles targeted to other memory or peripheral devices are allowed to prog ress normally while the refresh is in progress. none of the pins shared between the sdram and other devices are required for the refresh operation. note since refresh commands (requires all banks to be in idle state, achieved by precharge all) are issued automatically by enhanced sdram controller at each 32 khz clock, address bits a10 (for both 16 and 32-bit devices) cannot be shared with other peripherals address bus in the system. 18.4.5 low power operating modes this section describes low power operating modes of enhanced sdram controller as a function of various memory devices. table 18-26 lists and summarizes low power modes supported by enhanced sdram controller. 18.4.5.1 self refresh mode for sdram/lpddr devices this operating mode (see figure 18-37 and figure 18-38 ) allows the software/user to control a self refresh mode entry of the external sdram/lpddr device if refresh has been enabled, during system run mode. when this mode is selected (smode=100 in the respective csd control register) and refresh is enabled the enhanced sdram controller will complete any active access and a self refresh command to the external device will be issued. no access is allowed to the respective csd during manual self refresh mode. if refresh has not been enabled, the enhanced sdram controller places the memory in a low table 18-26. esdramc low power operating modes memory device system operating mode memory device low power operating mode wakeup penalty sdram run power down mode 1 clock cycle run precharge bank(s) 1 clock cycle run manual self refresh mode 1 (smodex=100) 1 sdclk stops, only if both chip selects are in manual self refresh mode. 2 refresh period stop self refresh mode 2 refresh period lpddr run power down mode txp run precharge bank(s) 1 clock cycle run manual self refresh mode (smodex=100) txs + 2 refresh period stop self refresh mode txs + 2 refresh period enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-50 freescale semiconductor power consumption mode known as power down. th e lpack signal (low power mode acknowledge) will not be asserted if only one csd enters manual self refresh mode. figure 18-37. sdram/lpddr enter self re fresh mode during system sleep mode rowx hclk haddr hwrite hwdata hready sdclk addr ras , cas , sdwe csdx wack pre-all ref a t rp (minimum) ckex p_lpmd lpack system in sleep mode sdram self refresh mode entry ma10=1 rowx enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-51 figure 18-38. sdram/lpddr exit self re fresh mode during system sleep mode 18.4.5.2 manual self refresh mode for sdram/lpddr devices this operating mode allows the software/user to c ontrol a self refresh mode entry of the external sdram/lpddr device if refresh has been enabled, dur ing the system run mode. when this mode is selected (smode=100 in the respective csd control register) and refresh is enabled the enhanced sdram controller will complete any active access and a self refresh command to the external device will be issued. no access is allowed to the respective csd during manual self refresh mode. if refresh has not been enabled, the enhanced sdram controller places the memory in a low power consumption mode known as power down. the lpack signal (low power m ode acknowledge) will not be asserted if only one csd enters manual self refresh mode. note manual precharge all should be initiated by user before manual self refresh. rowx hclk haddr hwrite hwdata hready sdclk addr ras , cas , sdwe csdx wack ref a ckex sdram self refresh mode exit p_lpmd lpack system in run mode ref a t rp (minimum) t xs (minimum) enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-52 freescale semiconductor to exit manual self refresh mode, a different operati ng mode need to be selected by changing smode bits in the respective chip select control register. when a di fferent mode is selected, the controller will take the sdram device out of self refresh mode and will begin issuing auto refresh cycles (if the refresh has been enabled). illustrates the entry and exit from manual self refresh mode. see figure 18-39 and figure 18-40 for timing information. figure 18-39. manual self refresh entry timing diagram note sdclk stops, only if both chip selects are in manual self refresh. this is in order to allow the usage of one chip select, while the other is in manual self refresh (in case that both chip selects are in use). hclk haddr hwrite hwdata hready sdclk ma[1x:0] ras , cas , sdwe csdx smod=sref refresh ckex lpack sdram self refresh mode entry due to manual self refresh esdctl0 sdclk stops only if both cs enter manual self refresh mode enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-53 figure 18-40. manual self refresh exit timing diagram 18.4.5.3 precharge power down mode 18.4.5.3.1 sdram precharge power down mode all low power operating mode described in the above paragraphs will be activated only if the system enters low power operating mode, for example, sleep mode. enhanced sdram controller has the capability to reduce power consumption if sdram/lpddr memory utilization is low, by setting sdram device in power down mode. this mode is activated thr ough the pwdt bits in esdctl0 and/or esdctl1 registers. during this operating mode, esdramc auto matically issues the refresh commands toward the sdram/lpddr memories at the rate define d by srefr bits in esdctl0 and/or esdctl1 registers. programming pwdt[1:0] = 01 causes enhan ced sdram controller to place the memories in power down mode at anytime the controller detects th at no banks are active. this mode is useful in hwdata hclk haddr hwrite hready sdclk ma[1x:0] ras , cas , sdwe csdx nop >= t rc + 1 clock ckex lpack ref a nop nop smod!=sref esdctl0 sdram self refresh mode exit due to manual self refresh enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-54 freescale semiconductor applications where a memory array is accessed infreque ntly and chances of another access to same page are minimal. reading or writing to memory activate s a page within the addressed bank. reset, software generated precharge, and hardware initiated refresh are three ways to close an active bank. the periodically occurring refresh will be the normal means that invokes the power down mode. at each refresh interval, all banks will be closed by a pr echarge-all command, followed by the refresh operation. the controller will then issue the power down command to the memories. a few cycle delay is incurred with the first read or write cycle in order to restar t the clocks, but only on the first cycle. after that, the clocks will continue to run until the next refresh operation or until any active banks are manually precharged. page misses on read and write cycles cause the addre ssed bank to be closed (pre charged) and a new page opened within the bank. this operation does not cause the clocks to stop, nor does manually precharging only a single bank within the memory. all banks within the memory must be inactive before the power down mode is invoked. power down mode occurs if cke is registered low coincident with a nop or command inhibit, when no accesses are in progress. entering power down will deactivate the input and output buffers (excluding cke) of the device. the power down mode state is exited by registering a nop or command inhibit and cke high at the desired clock edge. for sdr sdram, figure 18-41 and figure 18-42 illustrates the power down mode entry and exit respectively. for lpddr sdram, figure 18-43 and figure 18-44 illustrates the power down mode entry and exit respectively. figure 18-41. sdr sdram precharge power down mode entry timing diagram rowx hclk haddr hwrite hwdata hready sdclk ma[1x:0] ras , cas , sdwe csdx pre-all ref a t rp (minimum) ckex nop pwdt=00 pwdt pwdt=01 power down mode entry enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-55 note since esdramc doesn?t issue auto precharge commands toward the sdram, software will have to issue a precharge all command in order to enter precharge low power down mode, to wait for precharge timer (prct) to close/precharge all active banks, or to wait for the next refresh cycle in order to enter this low power mode. (during the refresh cycle, the esdramc automatically issue the precharge all command). figure 18-42. sdr sdram precharge power down mode exit timing diagram sdramx hclk haddr hwrite hrdata hready sdclk ma[1x:0] ras , cas , sdwe csdx dq act t rcd minimum ckex nop nop data a row a data a addr a column a addr b column a column b tcas=2 nop read tbst read power down mode exit enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-56 freescale semiconductor figure 18-43. mobile ddr sdram precharge power down mode entry timing diagram power down mode for several mobile/low power ddrs require the clock ck (and ck ) to continue running. (the pwr ck en (power down clock en able for mobile/low power ddr sdram) should be set to ?1? in order to enable this option) rowx hclk haddr hwrite hwdata hready sdclk ma[1x:0] ras , cas , sdwe csdx pre-all ref a t rp (minimum) ckex nop pwdt=00 pwdt pwdt=01 power down mode entry sdclk enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-57 figure 18-44. mobile ddr sdram precharge power down mode exit timing diagram 18.4.5.4 active power down mode 18.4.5.4.1 sdram/lpddr active power down mode the second clock suspend mode is selected whenev er pwdt[1:0] = 1x. in this mode the sdclk is stopped after a selectable delay from the last access to the array. active banks are not closed prior to disabling the sdram/lpddr clock. either 64 (pwdt[ 1:0] = 10) or 128 (pwdt[1:0] = 11) cycle delays are possible. sdram/lpddr clocks are counted from the end of the last read or write access. subsequent read or write accesses, and self-re fresh modes reset the counter. auto-refresh cycles do not affect the counter; however, if the counter expires during a refres h operation the clock will be disabled immediately following the refresh. sdramx hclk haddr hwrite hrdata hready sdclk ma[1x:0] ras , cas , sdwe csdx dq act t rcd minimum ckex nop nop row a addr a column a addr b column a column b tcas=2 nop read tbst read power down mode exit sdclk d a d a dqs d b 2 x data a t xp enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-58 freescale semiconductor the distinguishing factor between precharge powe r down mode and active power down mode is whether banks remain active while the clock is stopped. active power down allows banks to remain activated, while precharge power down does not. figure 18-45 and figure 18-46 illustrates sdr and lpddr sdram active power down m ode entry and exit timing diagram. figure 18-45. sdr sdram active power down mode timing diagram sdramx hclk haddr hwrite hrdata hready sdclk ma[1x:0] ras , cas , sdwe csdx dq data a read 64 clocks tcas = 2 ckex data a addr b c0lumn b c0lumn a c0lumn a tbst nop read sdram active power down mode entry sdram active power down mode exit enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-59 figure 18-46. mobile ddr sdram active power down mode timing diagram power down mode for several mobile ddrs require the clock ck (and ck ) to continue running. (the pwr ck en (power down clock enable for mobile ddr sdram) should be set to ?1? in order to enable this option) sdramx hclk haddr hwrite hrdata hready sdclk ma[1x:0] ras , cas , sdwe csdx dq 2 x data a read 64 clocks tcas = 2 ckex addr b c0lumn b c0lumn a c0lumn a tbst nop read lpddr sdram active power down mode entry lpddr sdram active power down mode exit sdclk d a d a dqs sdclk sdclk clocks will continue running for pwr_clk_en=?1? clocks will stop running for pwr_clk_en=?0? t xp enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-60 freescale semiconductor 18.4.5.5 precharge bank(s)?low power mode ?closing? (due to precharge command) the last used/ open row in any non active bank within a chip select reduces the power consumption of the external memo ry device. the power saving is device dependent, and one should consult/examine the external memory device specification for more details on power consumption reduction. the precharge bank is activated if prct is enabled. a precharge command is issued after 2xprct clocks (hclk, up to 133 mhz) of no activity (as shown in table 18-12 ) to one of the sdram/lpddr banks. the number of cycles before the precharge command is issued depends on command bus (we, ras, cas and csd) availability (means there is no active access to other bank) and the memory timing parameters. 18.4.5.6 lpddr frequency change the following steps need to be performed prior to a frequency change in a lpddr based system, in order for the ddrc delay line re-calibration.locking. 1. issue precharge_all command. 2. enter the external memories in self_refresh operating mode. 3. change system frequency. 4. reset the delay line, by setting the mddr_dl_rst bit in the esdramc misc register. 5. wait ~4500 hclk cycles in order for the delay line to lock on the new frequency. 6. exit self_refresh mode. after the above 6 steps are performed the lpddr is ready for normal operation at the new frequency. 18.4.6 sdram (sdr and lpddr) command encoding table 18-27 summarizes the command encoding utilized by this controller. these commands represent a subset of the commands defined by the jedec standard. table 18-27. sdram (sdr and lpddr) command encoding function symbol cke n-1 cke n cs ras cas we a11 a10 ba[1:0] a[13:0] deselect dsel hxhxxxxx x x no operation nop h x l h h h x x x x read read hxlhlhvl v v write writ h x l h l l v l v v bank activate act h x l l h h v v v v burst terminate 1 tbst h x l h h l x x v x precharge select bank pre h x l l h l v l v x precharge all banks pall h x l l h l x h x x auto-refresh cbr h x l l l h x x x x self refresh entry slfrsh h l l l l h x x x x enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-61 18.4.6.1 reset assertion of the rst signal initializes the controller into the idle state, and disables the module. while disabled, the controller remains in the idle state with the internal clocks stopped. the reset state of the control register allows for basic read/write operations sufficient to fetch the re set vector and execute the initialization code. a complete initial ization of the controller should be performed as part of the start-up code sequence. read/write cycles, refresh and low-power mode requests, and power down time-outs will all trigger transitions out of the idle state. as shown in the simplified enhanced sdram controller state diagram pictured in figure 18-47 , state transitions due to a read or write request depend on the operating mode. other transitions require the corresponding function to be enabled in the esdctl registers. some state transitions have been removed from the figure to minimize complexity and allow an easier understanding of the basic controller operation. the following subsections document the ope ration of each of the operating modes. 18.4.7 normal read/write mode the normal read/write mode (smode = 000) is used for general read and write accesses (ahb light compliant) to the sdram/lpddr. single and r ead burst accesses are supported for both sdram/lpddr memories (although bursts requests are limited as shown in table 18-28 ). for sdram/lpddr memories single and burst write accesses are supported as well. read or write requests to enhanced sdram controller initiate a check to see whether the page is already open. this check consists of comparing request addr ess against last row accessed within the corresponding bank. if the rows are different, a precharge has occurred since the last access, or there has never been an access to the bank, then the access must follow the ?off-page? sequence. if the requested and last row match, the shorter ?on-page? access is used. an off-pa ge sequence must first activate the requested row, an operation which is analogous to a conventional dr am ras cycle. an activate cycle is the first operation depicted in figure 18-48 . during the activate cycle, the appropriate chip select is driven low, the row addresses are placed on the multip lexed address pins, the non-multiplexe d addresses are driven to their respective values, write enable is driven high, cas is driven high, and ras is driven low. these latter three pins form the sdram command word. the da ta bus is unused during the activate command. self refresh exit slfrshx l h h x x x x x x x power-down entry pwrdnhlxxxxxx x x power-down exit pwrdnx l h h x x x x x x x mode register set 2 mrs hxllllll v v 1 for mobile ddr, applies only to read bursts (with auto precharge disabled). 2 ba0?ba1 select either the mode register, the extended mode register or the low power extended mode register. table 18-27. sdram (sdr and lpddr) command encoding (continued) function symbol cke n-1 cke n cs ras cas we a11 a10 ba[1:0] a[13:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-62 freescale semiconductor figure 18-47. simplified enhanced sdram controller state diagram once the selected row has been activated, the read operation begins after the row to column delay (trcd) has been met. this delay is either 2 or 3 clocks, as determined by the trcd control field. during the read cycle, the chip select is once again asserted, the co lumn addresses are driven onto the multiplexed address bus, the non-multiplexed addresses rema in driven to the value presented during the activate cycle, the write enable is driven high (read), ras is driven hi gh, and cas is driven low. after the cas latency has expired, data is transferred across the data bus. cas latency is programmable vi a the tcas control field. as data is being returned across the ahb, transfer ack nowledge is asserted back to the cpu indicating that the cpu should latch data. while da ta is still on the bus, the enhanced sdram controller must begin monitoring transfer request since the cpu is free to i ssue the next bus request on the same edge that data is being latched. power on idle read write power down power down or row active self refresh active power down auto- refresh precharge all power down burst read burst precharge bank refresh request mode register set stop and refresh request write read or pre_cmd and mode reg set write (normal) page nop nop miss a10=1 pre_cmd and a10=0 read or write read or write burst reset or stop refr!= 0 (stop and refr=0) enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-63 data transfers can be either single operand or a burst (wrap or incr) of up to a full page. burst requests are designated as such by the hburst bus indicati ng the length of the access, when hburst equal to 0 a single access is required, otherwise th e access is a burst of hburst words. sdram memories assume that all transfers are burst tr ansfers unless terminated early. burst transfers can be terminated by a variety of mechanisms: another re ad or write cycle, a precharge operation, or through a burst terminate command. burst terminate commands are the general mechanism used by the esdctl for early burst termination, the burst terminate comm and is subject to the cas latency and must be pipeline similar to the read command, as shown in figure 18-48 to figure 18-68 . note the signals displayed in are internal signals, that is, interface signals between the m3if and the esdramc. all those figures are not cycle accurate and meant to show mainly the external pins activity. for cycle accurate diagrams, refer to figure 18-70 to figure 18-72 . sdram write cycles are different than read cycles in one important aspect. whereas read data was delayed by the cas latency, write data has no delay and is supplied at the same time as the write command. figure 18-56 illustrates an off-page write cycle followed by one that hits on-page. note that the write data is driven during the same clock that th e write command is issued. a burst terminate command cancels the burst operation, but again without the cas latency. table 18-28. sdram/lpddr burst access support internal ahb word access (32bit) external memory device 3 description 16-bit 32-bit hburst type bl=4 bl=8 bl=fp bl=4 bl=8 bl=fp 2 000 single 1 , 2 1 esdctl supports only burst of 32-bit (word size). byte (8 bits) or half words (16 bits) accesses are supported only in case of single transfer (single). the esdctl automatically splits (see example in table 18-29 ) the ahb bursts as a function of the external memory device, configured via the esdctl configuration registers (size and burst length), in such a way that a continuous flow of data is obtained (for both read or write bursts). 2 bl = burst length field in device mode register; fp = full page (wrap at external memory device row boundary). for both lpddr 16 and 32-bit devices only bl=8 is supported. n o ye s ye s ye s ye s ye s s i n g l e t r a n s f e r 001 incr no yes yes yes yes yes incrementing burst 010 wrap4 no yes yes yes yes yes 4-beat wrapping burst 011 incr4 no yes yes yes yes yes 4-beat incrementing burst 100 wrap8 no yes yes yes yes yes 8-beat wrapping burst 101 incr8 no yes yes yes yes yes 8-beat incrementing burst 110 wrap16 no no no no no no 16-beat wrapping burst 111 incr16 no no no no no no 16-beat incrementing burst enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-64 freescale semiconductor note esdramc handles the hunalign accesses in the following way. the m3if module converts the original access address to a word align address toward the esdramc. the hbstrb are used by the esdramc to drive the correct value on the dqm signals toward the external memory. figure 18-48. sdr and lpddr off-page single read timing diagram (32-bit memory for sdr and 16-bit for lpddr) ras, dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx read read tbst addr a hrdata row a sdramx addr b hready data a nop cas, we t rcd minimum column a act tcas nop data a nop column b column a dq[15:0] signals for lpddr data a data a dqs sdclk enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-65 figure 18-49. sdr and lpddr on-page single read timing diagram (32-bit memory for sdr, 16-bit for lpddr) ras, dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx read read tbst addr a hrdata sdramx addr b hready data a nop cas, we column a tcas nop data a nop column b column a dq[15:0] dqs data a data a sdclk signals for lpddr enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-66 freescale semiconductor figure 18-50. sdr and lpddr off-page burst read timing diagram (32-bit memory for sdr or 16-bit for lpddr) ras, dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx read read nop addr a hrdata row a addr b hready data a2 nop cas, we t rcd minimum column a act tcas=2 nop data a1 nop column b data a3 data a4 data a2 data a3 data a4 data a1 signals for lpddr dq[15:0] d a1 d a2 d a3 d a4 d a5 d a6 d a7 d a8 dqs sdclk enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-67 figure 18-51. ahb 32-bit read from a lpddr: off-page burst read timing diagram (32-bit) ras, sdclk hclk haddr hwrite ma[1x:0] csdx read nop addr a hrdata row a hready data a2 nop cas, we t rcd minimum column a act tcas=2 nop nop data a3 data a4 data a1 signals for mddr dq[31:0] d a1 d a2 d a3 d a4 d a5 d a6 d a7 d a8 dqs sdclk data a5 da t [31:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-68 freescale semiconductor figure 18-52. ahb 64-bit read from a lpddr: off-page burst read timing diagram (32-bit) ras, sdclk hclk haddr hwrite ma[1x:0] csdx read read nop addr a hrdata row a addr b hready d a3 d a4 nop cas, we t rcd minimum column a act tcas=2 nop nop column b d a5 d a6 d a7 d a8 d a1 d a2 signals for lpddr dq[31:0] d a1 d a2 d a3 d a4 d a5 d a6 d a7 d a8 dqs sdclk [63:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-69 figure 18-53. sdr and lpddr on-page burst read timing diagram (32-bit memory for sdr and 16-bit for lpddr) ras, dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx read read nop addra hrdata addrb hready dataa2 nop cas, we columna tcas=2 nop dataa1 nop columnb dataa3 dataa4 dataa2 dataa3 dataa4 dataa1 signals for lpddr dq[15:0] da1 da2 da3 da4 da5 da6 da7 da8 dqs sdclk enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-70 freescale semiconductor figure 18-54. on-page burst read timing diagram (16- bit memory for sdr, lpddr 8-bit is not supported) figure 18-55. off-page burst read timing diagram (16-bit memory, lpddr 8-bit is not supported) s1 scl coln read a1n d1n nop nop nop a2n a3n d1n+1 d2n d2n+1 a4n d3n nop nop nop nop nop d1n d2n d3n d3n+1 d4n+1 d4n d4n nop hclk haddr hsel_csx hwrite hrdata hready sdclk ma[1x:0] command dq[15:0] dqm[1:0] s1 scl srcd srcd bank, bank,coln active nop read a1n d1n nop nop nop a2n a3n d1n+1 d2n d2n+1 a4n d3n nop nop nop nop nop d1n d2n d3n d3n+1 d4n+1 d4n d4n nop hclk haddr hsel_csx hwrite hrdata hready sdclk ma[1x:0] command dq[15:0] dqm[1:0] row enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-71 figure 18-56. sdr off-page write followed by on-page write timing diagram ras, dq[31:0] sdclk hclk haddr hwrite ma[1x:0] csdx write write addra hwdata rowa sdramx addrb hready dataa cas, we trcd columna act tbst dataa columnb datab datab tbst columna columnb enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-72 freescale semiconductor figure 18-57. lpddr off-page write followed by on-page write timing diagram ras, sdclk hclk haddr hwrite ma[1x:0] csdx write write addra hwdata rowa sdramx addrb hready dataa cas, we trcd columna act nop columnb datab nop columna columnb signals for lpddr dq[15:0] db da da da da db db db dqm dqs sdclk [31:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-73 figure 18-58. off-page burst write timing diagra m (32-bit memory for sdr and 16-bit for lpddr) s1 srcd srcd bank,rown bank,coln active nop write d1n d1n a1n a2n a3n a4n nop nop nop d2n d3n d4n d4n d2n d3n hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] dq[15:0] d1n d2n d3n d4n d5n d6n d7n dqs sdclk lpddr signals enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-74 freescale semiconductor figure 18-59. ahb 64-bit write to lpddr: off-pa ge burst write timing diagram (32-bit memory) s1 srcd srcd bank,rown bank,coln active nop write d1n d2n a1n a2n a3n a4n nop nop nop d7n d8n d3n d4n d5n d6n hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] d1n d2n d3n d4n d5n d6n d7n dqs sdclk lpddr signals [63:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-75 figure 18-60. ahb 32-bit write to lpddr: off-pa ge burst write timing diagram (32-bit memory) s1 srcd srcd bank,rown bank,coln active nop write a1n a2n a3n a4n nop nop hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] d1n d2n d3n d4n d5n d6n d7n d8n dqs sdclk lpddr signals [63:0] d1n d4n d2n d3n d5n d8n d6n d7n nop a5n a6n a7n a8n nop enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-76 freescale semiconductor figure 18-61. on-page burst write timing diagram (32-bit memory for sdr and 16-bit for lpddr) s1 coln write d1n d1n a1n a2n a3n a4n nop nop nop d2n d3n d4n d4n d2n d3n hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] lpddr signals d1n d2n d3n d4n dq[15:0] d5n d6n d7n d8n dqs[1:0] sdclk enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-77 figure 18-62. off-page burst write timing diagram (sdr 16-bit memory, lpddr 8-bit is not supported) s1 srcd srcd rown coln active nop write a1n nop nop nop a2n a3n a4n nop nop nop d1n d2n d3n d4n nop hclk haddr hser_csx hwrite hwdata hready sdclk ma[1x:0] command dq[15:0] dqm[1:0] d1n d1n+ d2n d2n+ d3n+ d4n d4n+ d3n enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-78 freescale semiconductor figure 18-63. on-page burst write timing diagram (sdr 16-bit memory, lpddr 8-bit memory is not supported) coln write a1n nop nop nop a2n a3n a4n nop nop nop d1n d2n d3n d4n nop hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[15:0] dqm[1:0] d1n d1n+ d2n d2n+ d3n+ d4n d4n+ d3n s1 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-79 figure 18-64. sdr single write followed by on-page read timing diagram s1 scl srcd srcd row bank,col1 active nop write a1 d1 d1 tbrst a2 bank,col2 read tbrst d2 hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] d2 hrdata enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-80 freescale semiconductor figure 18-65. lpddr single write followed by on-page read timing diagram s1 scl srcd srcd row bank,col1 active nop write a1 d1 a2 bank,col2 read tbrst hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command hrdata nop dq[15:0] nop d2 d2 d1 d1 d1 d1 d2 dqs dqm lpddr signals sdclk_b enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-81 figure 18-66. sdr single read followed by on-page write timing diagram s1 scl srcd srcd bank,rown active nop read a1n d1n tbrst a2b bank,coln nop nop nop write tbrst d2b d2b bank,colb hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] dqm[3:0] d1n hrdata enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-82 freescale semiconductor figure 18-67. lpddr single read followed by on-page write timing diagram s1 scl srcd srcd bank, active nop read a1n tbrst a2b bank,coln nop nop nop write nop d2b bank,colb hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command d1n hrdata nop d1n d2b dq[15:0] dqm[3:0] lpddr signals d1n d2b d2b d dqs sdclk_b rown enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-83 figure 18-68. sdr burst read followed by on-page write timing diagram s1 scl srcd srcd bank, bank,coln active nop read a1n d1n nop nop nop a2n a3n d2n d3n d4n a4n nop nop nop nop write tbrst bank,colb a1b d1b d1b nop nop hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command dq[31:0] dqm[3:0] d2n d3n d4n d1n hrdata row enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-84 freescale semiconductor figure 18-69. lpddr burst read followed by on-page write timing diagram 18.4.7.1 sdr cycle accurate enhanced sdram controller accesses this section provides cycle accurate timing di agrams for several esdramc (amba ahb lite) supported read and write accesses to both 16 and 32-bit data width sd r memory devices from only one master. this diagrams are provided to emphasis esdramc performance for single master hit (active row) requests. the cas latency for a ll diagrams is 2 cycles and burst length is set to 4 words for 16-bit memory and 8 words for 32-bit memory. 18.4.7.1.1 single read word access to 16-bit memory the markers in figure 18-70 marks the request access time, for example, the time period between hready goes low (the esdramc starts to execute the request) and hready goes high (the esdramc request execution is completed). s1 scl srcd srcd bank,row bank,coln active nop read a1n nop nop nop a2n a3n a4n nop nop nop nop write bank,colb a1b d1b nop nop hclk haddr hsel_csx hwrite hwdata hready sdclk ma[1x:0] command d2n d3n d4n d1n hrdata d5n d6n d7n d8n dq[31:0] d1n d2n d3n d4n dqs d1b d1b nop dqm[3:0] sdclk lpddr signals enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-85 figure 18-70. single on page read?word access to 16-bit memory (cycle accurate) 18.4.7.1.2 misaligned incr4 burst read access to 16-bit memory the markers in figure 18-71 marks the request access time, for example, the time period between hready goes low (the esdramc starts to execute the request) and hready goes high (the esdramc request execution is completed). two read commands are issued toward the sdram me mory, since the misaligned read burst crosses the 16-bit sdram (4 words) memory boundary . the read addresses are 0x04, 0x08, 0x0c, and 0x10. without issuing the second read the last sdram data will come from address 0x00. the esdramc issue the second read command in such a way (at a specific timing) so continuous data flow is obtained. there is no timing difference between an aligned and a mis aligned access although the second one requires more commands. access starts here access ends here d0l?data bits [15:0] d0h- data bits [31:16] hclk htrans nseq haddr a0 hwrite hburst single hrdata d0 hready sdclk command read nop brst nop dq d0l d0h ma col0 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-86 freescale semiconductor figure 18-71. misaligned on page incr4 burst read access to 16-bit memory hclk htrans nseq haddr a4 a8 ac a10 hwrite hburst incr4 hrdata d4 d8 dc d10 hready sdclk command read nop read nop brst nop dq d4l d4h d8l d8h dcl dch d10l d10h ma cola4 cola10 access starts here access ends here dxl?data bits [15:0] dxh?data bits [31:16] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-87 18.4.7.1.3 misaligned wrap8 burst read access to 32-bit memory the markers in figure 18-72 marks the request access time, that is, the time period between hready goes low (the esdramc starts to execute the request) and hready goes high (the esdramc request execution is completed). only one read command is issued toward the sdram memory, since the misaligned read burst crosses the 32-bit sdram memory (8 words) boundary at th e memory ?natural? boundary. the read addresses are 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c and 0x00. without issuing the second read the last sdram data will come from address 0x00 si nce this is the ?natural? 32-bit memory device boundary as well. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-88 freescale semiconductor figure 18-72. misaligned wrap8 burst read access to 32-bit memory hclk htrans nseq seq haddr a4 a8 ac a10 a14 a18 a1c a0 hwrite hburst wrap8 hrdata d4 d8 dc d10 d14 d18 d1c d0 hready sdclk command read nop dq d4 d8 dc d10 d14 d18 d1c d0 ma cola4 access starts here access ends here dxl?data bits [15:0] dxh?data bits [31:16] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-89 18.4.7.2 single write word access to 32-bit memory the markers in figure 18-73 mark the request access time, for example, the time period between hready goes low (the esdramc starts to execute the request) and hready goes high (the esdramc request execution is completed). figure 18-73. single on page write?word access to 32-bit memory (cycle accurate) 18.4.7.2.1 incr4 burst write word access to 32-bit memory two write commands are issued toward the sdram memory, since the misaligned write burst crosses the 32-bit sdram (8 words) memory boundary. the write addresses are 0x14, 0x18, 0x1c, and 0x20. without issuing the second write the last sdram data will be written to address 0x00. the esdramc issue the second write command in such a way (at a sp ecific timing) so continuous data flow is obtained. there is no timing difference between an aligned and a misaligned access although the second one requires more commands. the markers in figure 18-74 mark the request access time. access starts here access ends here hclk htrans nseq haddr a0 hwrite hburst single hwdata d0 hready sdclk command write brst nop dq d0 ma col0 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-90 freescale semiconductor figure 18-74. incr4 burst on page write?word access to 32-bit memory (cycle accurate) 18.4.7.3 sdram command sequence for burst accesses table 18-29 show the commands that the esdramc will perform for wrap and incr accesses from the ahb. the controller will split the transaction wh en needed in cases that the access cross wrap boundaries of the sdram. the memory c onfigured to 8 beat burst (bl=8). unspecified incr burst accesses will be translated to single accesses to allow the burst to terminate at any length with no additional delays. the number in the brackets represent the address for read command and the last burst address for bterm command. access starts here access ends here hclk htrans nseq seq haddr a14 a18 a1c a20 hwrite hburst incr4 hwdata d14 d18 d1c d20 hready sdclk command write write brst nop dq d14 d18 d1c d20 ma cola14 cola20 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-91 18.4.8 precharge command mode the precharge command mode (smode=001) is used during sdram/lpddr device initialization, and to manually deactivate an active bank(s). while in this mode, an access (either read or write) to the sdram/lpddr address space will generate a prec harge command cycle. sdram/lpddr address bit a10 determines whether a single bank, or all banks, are precharged by the command. accessing an address with the sdram/lpddr address a10 low will precha rge only the bank selected by the bank addresses, as illustrated in figure 18-75 . conversely, accesses with a10 high wi ll precharge all banks regardless of the bank address, as illustrated in figure 18-76 . note that a10 is the sdram pin, not the a10 bit arm address bus. translation of the sdram a10 to the corresponding arm address is dependent on the memory configuration. the precharge command access is two clocks in length on the arm, and one cycle to the sdram/lpddr. table 18-29. sdram command sequence for burst accesses type bus address 0 4 8 c 10 14 18 1c wrap8 16-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) read(10) read(10) read(10) read( 10) read(0) read(0) read(0) read(0) read(0) read(0) read(0) read(10) read(10) read(10) bterm(0) bterm(4) bterm(8) bterm(10) bterm(14) bterm(18) 32-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) incr8 16-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) read(10) read(10) read(10) read(10) read(20) read(20) read(20) read(20) read(20) read(20) read(20) read(30) read(30) read(30) bterm(20) bterm(24) bterm(28) bterm(30) bterm(34) bterm(38) 32-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) read(20) read(20) read(20) read (20) read(20) read(20) read(20) bterm(20) bterm(24) bterm(28) bterm(2c) bterm(30) bterm(34) bterm(38) wrap4 16-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) 32-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) bterm(c) bterm(10) read(0) read(0) r ead(0) read(10) read(10) read(10) bterm(4) bterm(8) bterm(c) bterm(10) bterm(14) bterm(18) incr4 16-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) read(10) read(10) read(10) read(20) read(20) read(20) bterm(10) bterm(14) bterm(18) bterm(20) bterm(24) bterm(28) 32-bit read(0) read(4) read(8) read(c) r ead(10) read(14) read(18) read(1c) bterm(c) bterm(10) bterm(14) bterm(18) bterm(1c) read(20) read(20) read(20) bterm(20) bterm(24) bterm(28) enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-92 freescale semiconductor figure 18-75. precharge specific bank timing diagram ras, sdclk hclk haddr hwrite ma[1x:0] csdx pre nop act nop esdctl sdramx smode=pre_cmd hwdata sdramx, sdramx esdctl sdramx hready 0 smode=normal nop cas, we with a10=0 trp min applies only to same bank. row ba[1:0] bank, sdramx number row enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-93 figure 18-76. precharge all banks timing diagram 18.4.9 auto-refresh mode the auto-refresh mode (smode=010) is used to manually request sdram/lpddr refresh cycles and is normally used only during device initializati on, since the esdramc will automatically generate refresh cycles when properly configured. the auto-refresh command (see figure 18-77 ) refreshes all banks in the device, therefore the address supplied during the refresh command need only specify the correct sdram/lpddr device. the lower address lines are a don?t care. either a read or write cycle may be used. if a write is used, the data will be ignored a nd the external data bus will not be driven. the cycle will be 2 clocks on the arm and a single clock to the sdram/lpddr device. the esdramc doesn?t guarantees that the sdram/lpddr is in the idle state before the auto-refresh command is given. if one or more rows are active, a precharge-all command should be issued by the software prior to the auto-refresh command. ras, sdclk hclk haddr hwrite ma[1x:0] csdx pre nop act nop esdctl sdramx smode=pre_cmd hwdata sdramx, sdramx esdctl sdramx hready 0 smode=normal nop cas, we with a10=1 t rp min applies only to same bank. row ba[1:0] sdramx row enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-94 freescale semiconductor figure 18-77. software initiated auto-refresh timing diagram 18.4.10 manual self refresh mode manual self refresh mode (smode= 100) is used to enter sdram/lpddr external device in self refresh low power operating mode during run sy stem operating mode. for more details, see section 18.4.5.2, ?manual self refres h mode for sdram/lpddr devices .? 18.4.11 set mode register mode set mode register mode (smode=011) is used to program sdram/lpddr mode register (see example 18-1 and section 18.5.4.2, ?sdr sdram load mode register ?). this mode differs from normal sdram write cycles because data to be wr itten is transferred across the address bus. mode register reads are not allowed. after smode bits are set to 011, either a read or wr ite cycle may be used to write the external memory device mode register. in both cases (read or write), th e arm data will be ignored and the external data bus will not be driven. the row and bank address signals ar e used to transfer the data toward the external memory device mode register (see example 18-1 and section 18.5.4.2, ?sdr sdram load mode register ?). the cycle will be 2 clocks on the arm and a single clock to the sdram device. figure 18-78 illustrates the bus sequence for a mode regi ster set operation. mode register set commands must be issued while the sdram/lpddr is idle. the enhanced sdram controller does not guarantee that the sdrams have been returned to the idle state before issuing the mode register set command. software must generate a precharge all sequence before issuing the mode register set command if there is ras, dq sdclk hclk haddr hwrite ma[1x:0] csdx refresh nop refresh nop sdctl sdramx smode=ref hwdata sdramx sdramx sdramx hready 0 nop cas, we t rc minimum 0 nop nop sdramx enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-95 any possibility that one or more banks could be active. also note, the row cycle time (t rc ) must be met before the mode register set command is issued. section 18.5.4.2, ?sdr sdram load mode register ? provides a detailed example of the mode register da ta value calculation and mapping to the arm address. figure 18-78. set mode register state diagram figure 18-79. sdr and lpddr set mode register timing diagram idle precharge all set mode reg (read | write) and smode=set_mode active (read | write) and smode=pre_cmd (read | write) and smode = set_mode illegal sdram transition ras, sdclk hclk haddr hwrite ma[1x:0] csdx hwdata hready cas, we refresh sdramx sdramx 0 set mode sdctl sdramx smode=set_mode mode don?t care t rc minimum ?00? ba[1:0] for lpddr: to program the ?mode register? to program the ?extended mode register? ?01? ba[1:0] to program the ?low power extended mode register? ?10? ba[1:0] enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-96 freescale semiconductor 18.5 initialization/app lication information the following section provides details on selecting compatible sdram memories and configuring the controller to work with the memory system. 18.5.1 memory device selection many sdram/lpddr memory types are supported by the enhanced sdram controller. important characteristics to consider when choosing a memory device are: ? the page comparators expect 4 bank memories. 2 bank devices are not supported. their use will result in the memory and controller losing synchronization when crossing page boundaries. ? page (column) addressing must match one of the supported sizes. ? memory density can be larger or smaller than those directly supported, although some memory may be inaccessible or redundantly mapped. bank a ddresses are the most significant addresses and connecting a memory smaller than the selected density will result in one or more banks being inaccessible. ? controller is designed for memories meeting pc 133 timing specifications up to 133 mhz system operation. use of non-compliant memories require a thorough analysis of all timing parameters. 18.5.2 configuring controller for sdram memory array configuration register programmi ng options and controller-memory physical connections provide flexibility to accommodate different memory type s and system configurations. options are broadly grouped into 3 categories: ? physical characteristics: row and column address bus widths and data bus width. ? timing parametric: cas latency, row prech arge, cycle delays, refresh rate, etc. ? functional features: clock suspend t imer and supervisor/user protection. table 18-32 ? table 18-42 are provided to assist the designer with the selection of the correct physical parameters for a number of preferred memory confi gurations. timing parametric are addressed in the following subsections. 18.5.3 cas latency cas latency is determined by the operating frequenc y and access time of the memories. for a 133 mhz system clock frequency and pc133 compliant memories , the cas latency will ge nerally be programmed to 3 clocks, although the memory specifications should always be consulted to confirm this value. cas latency must be programmed in two places: the chip se lect control register and the device mode register. see table 18-17 for a description of the control register encoding, and section 18.4.11, ?set mode register mode ? for the details on programming the sdram mode register. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-97 18.5.4 sdram/lpddr init ialization sequence prior to normal operation (read/write accesses), external memory device must be initialized. the following paragraphs provide detailed info rmation covering device initializa tion. register definition, command descriptions and device operation information ha s been thoroughly described throughout the chapter. 18.5.4.1 sdram initialization sdr and lpddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified by sdram ma nufacture specification may results in undefined operation. 18.5.4.1.1 sdr sdram initialization once power is applied to the device and the clock is stable, the sdram requires a 200 s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 200 s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 200 s delay has been satisfied with at leas t one command inhibit or nop command have been applied (the sdram_rdy status bit will be asserted), a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. figure 18-80. sdr sdram initialization and load mode register sequence nop pre all auto ref normal auto ref auto ref auto ref auto ref auto ref auto ref auto ref mode set 200 s minimum sdram software initialization sequence vcc system clock dram reset hard_asyn_r eset sdclk sdram command cke[1:0] sdram_rdy enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-98 freescale semiconductor once in idle state, several (manufacture depende nt) auto refresh cycles must be performed. after the auto refresh cycles are complete, the sd ram is ready for mode register programming. because the mode register will power up in an unknow n state, it should be loaded prior to applying any operational command. figure 18-80 illustrates a sdram initialization routine with 8 auto refresh cycles. example 18-1 shows an initialization sdram example code. it is crucial that the dual parameters (those parameters that are defined both in the sdram device register and in esdramc registers, like cas latency, burst length, etc.) to be identical for proper operation of both sdram memory and e nhanced sdram controller. example 18-1. init_sdram example code (arm assembler) init_sdram: ldr r2, =esd_esdctl0 // base address of registers ldr r3, =pre_all_cmd // smode=001 str r3,(r2,#0x0) // put csd0 in precharge command mode ldr r4, =sdram_csd0 // csd0 precharge address (a10=1) str r1,(r4,#0x0) // precharge csd0 all banks ldr r3, =auto_ref_cmd // smode=010 str r3,(r2,#0x0) // put array 0 in auto-refresh mode ldr r4, =sdram_csd0_base // csd0 base address ldr r6,=0x7 // load loop counter 0: ldr r5,(r4,#0x0) // run auto-refresh cycle to array 0 subs r6,r6,#1 // decrease counter value bne 0b ldr r3, =set_mode_reg_cmd // smode=011 str r3,(r2,#0x0) // setup csd0 for mode register write ldr r3, =mode_reg_val0 // array 0 mode register value ldrb r5,(r3,#0x0) // new mode register value on address bus ldr r3, =normal_mode // smode=000 str r3,(r2,#0x0) // setup csd0 for normal operation esd_esdctl0 .long 0xxxxx_xxxx // system/external device dependent data sdram_csd0: .long 0xxxxx_xxxx // system/external device dependent data sdram_csd0_base: .long 0xxxxx_xxxx // system/external device dependent data pre_all_cmd .long 0xxxxx_xxxx // system/external device dependent data (smode=001) auto_ref_cmd .long 0xxxxx_xxxx // system/external device dependent data (smode=010) set_mode_reg_cmd .long 0xxxxx_xxxx // system/external device dependent data (smode=011) mode_reg_val0 .long 0xxxxx_xxxx // system/external device dependent data normal_mode .long 0xxxxx_xxxx // system/external device dependent data (smode=000) note to do load mode register, address starts from bit 0, so lrdb should be used. 18.5.4.1.2 lpddr sdram initialization ddr mobile sdram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to vdd and vddq according to the lpddr sdram manufacture data sheet. clock enable mast be driven through the sdram controller registers to cs0 and/or cs1. after all power supply voltages are stable, and the clock is stable, the ddr mobile-sdram requires a 200 s delay prior to applying a command other than deselect or nop. cke is driven high by the sdram contro ller on the first edge of the clock. enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-99 once the 200us delay has been satisfied, the follo wing command sequence shall be applied using the sdram controller registers: 1. a deselect or nop command. 2. a precharge all command should then be applied, placing the device in the all banks idle state. 3. once in the idle state, two auto refresh cycles must be performed (trfc must be satisfied). 4. two mode register set commands for the mode register and ex tended mode register. following these cycles, the ddr mobile -sdram is ready for normal operation. note a write access should be performed before the first read access to the lpddr (in order to assure that a 0 value will be driven on the dqs pins and held by the keeper of the ddr pads). figure 18-81. simplified lpddr sdram initiali zation and load mode register sequence nop pre all mod set normal 200 s minimum lpddr sdram software initialization sequence vcc system clock dram reset hard_asyn_r eset sdclk sdram command sdclk_b auto ref auto ref mo set cke extended mode reg mode reg sdram_rdy enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-100 freescale semiconductor 18.5.4.2 sdr sdram load mode register the mode register is used to set the sdram operati ng characteristics including cas latency, burst length, burst mode, and write data length. the settings depend on system characteristics including the operating frequency, memory device type, burst buffer/cache line length, and bus width. operating characteristics vary by device type, so the data sheet must be cons ulted to determine the actual value to be written. in order to demonstrate the procedure, the follo wing system characteristics will be used: ? micron mt48lc4m32b2 128mb (1m x 32 x 4 banks) sdr sdrams ? 133 mhz system clock frequency ? sequential burst, burst length of 8 ? single word writes (for example, no bursting on writes) figure 18-82 shows the mode register bit assignments for the micron 128 mb sdram and the bit field descriptions are listed in table 18-30 . 128 mb sdram mode register a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 type reserved* wb op mode cas latency bt burst length figure 18-82. 128 mbit sdr sdram mode register table 18-30. sdram mode register description name description a11-a10 reserved a9 write burst write burst mode (wb). selects between burst writes and single location writes. 0 programmed burst length 1 single location access 1 a8?a7 op mode operating mode. defines operating modes. 00 standard operation all other states reserved a6?a4 cas latency cas latency (cl). sets latency between column address and data 000 reserved 001 1 clock 1 010 2 clocks 011 3 clocks 1xx reserved enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-101 for this example: ? sequential burst (bt = 0) ? burst length of 8 (bl = 011) ? programmed burst length (during writes) (wb = 0) ? 3 clock latency (cas latency= 011) once the mode register value has been determined, it mu st be converted to an address. the mode register is written via the address bus and the memory data sheet will specify the sdram address bits on which to place the data. the enhanced sdram controller drives the lsb address bits to the pins, so the memory density and bus width don?t need to be ta ken into account during the conversion. table 18-31 provides an example conversion using the sa me system characteristics us ed in the previous example. 18.5.4.3 sdram memory configuration examples 15 different sdram (sdr and lpddr) configurations are demonstrated. these examples are 64 mb, 128 mb, and 256 mb sdram memories in single x16, dual x16, and single x32 configurations. all single-configuration 16-bit examples are shown connected to the lower half of the data bus. alternatively, the memory can be connected to the upper half of the data bus by swapping the data connections to d a3 burst type burst type (bt). selects burst type 0interleave 1 sequential a2?a0 burst length burst length (bl). a 16-bit wide sdram requires a burst length of eight because the four 32-bit line fill cycles will be decomposed into eight 16-bit accesses. 000 1 1 001 2 1 010 4 2 011 8 111 full page 10x reserved 1x0 reserved 1 not supported by the esdctl. 2 not supported by the esdctl for 16-bit external memory device. table 18-31. example address calculation for mode register mode register 0 0 wb 0 0 cas latency bt bl program value 0 0 0 000110011 sdram pin ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 arm address a11a10 a9 a8a7a6a5a4a3a2a1a0 table 18-30. sdram mode register description (continued) name description enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-102 freescale semiconductor [31:16] and the data qualifier mask connections to dq m3 and dqm2. in this case, it will be necessary to program the dsiz field in the control register to a va lue of 0 (configurations shown require a value of 1). 18.5.4.3.1 single 64mb (4mx16) sdram configuration figure 18-83. single 64 mb (4m x 16) sdram connection diagram table 18-32. single 4mx16 control register value control field value density 8 mb page size 512 row 12 col 8 dsiz 16 (d [15:0]) srefr 2 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] clk cke 4m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-103 18.5.4.3.2 single 128 mb (8 mbx16) sdram configuration figure 18-84. single 128 mb (8m x 16) sdram connection diagram table 18-33. single 8mbx16 control register value control field value density 16 mb page size 1024 row 12 col 9 dsiz 16 (d [15:0]) srefr 4 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] clk cke 8m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-104 freescale semiconductor 18.5.4.3.3 single 256 mb (16m bx16) sdram configuration figure 18-85. single 256 mb (16m x 16) connection diagram table 18-34. single 16mbx16 control register value control field value density 32 mb page size 1024 row 13 col 9 dsiz 16 (d [15:0]) srefr 4 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] clk cke 16m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller ma12 ma12 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-105 18.5.4.3.4 single 512 mb (32m bx16) sdram configuration figure 18-86. single 512 mb (32m x 16) sdram connection diagram table 18-35. single 32mbx16 control register value control field value density 32 mb page size 1024 row 13 col 10 dsiz 16 (d [15:0]) srefr 4 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] clk cke 32m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller ma12 ma12 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-106 freescale semiconductor 18.5.4.3.5 single 1-gb (64mbx16) sdram configuration figure 18-87. single 1-gb (64m x 16) sdram connection diagram table 18-36. single 64mbx16 control register value control field value density 64 mb page size 2048 row 14 col 10 dsiz 16 (d [15:0]) srefr 8 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] clk cke 64m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller ma12 ma12 ma13 ma13 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-107 18.5.4.3.6 dual 64 mb (4mbx16) sdram configuration figure 18-88. dual 64 mb (4m x 16 x 2) sdram connection diagram table 18-37. dual 4mbx16 control register value control field value density 16 mb page size 1024 row 12 col 8 dsiz 32 (d [31:0]) srefr 4 clk cke ba0 ma11 ma[10:0] ras cas cs we dqmh dqml dq[15:0] 4m x 16 sdram ma11 esdctl controller ba1 sdclk cke ba0 ma[10:0] ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:16] dq[15:0] ba1 clk cke ba0 ma11 ma[10:0] ras cas cs we dqmh dqml dq[15:0] 4m x 16 sdram ba1 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-108 freescale semiconductor 18.5.4.3.7 dual 128 mb (8mbx16) sdram configuration figure 18-89. dual 128 mb (8m x 16 x 2) sdram connection diagram table 18-38. dual 8mbx16 control register value control field value density 32 mb page size 2048 row 12 col 9 dsiz 32 (d [31:0]) srefr 4 clk cke ba0 ma11 ma[10:0] ras cas cs we dqmh dqml dq[15:0] 8m x 16 sdram ma11 sdram controller ba1 sdclk cke ba0 ma[10:0] ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:16] dq[15:0] ba1 clk cke ba0 a11 a[10:0] ras cas cs we dqmh dqml dq[15:0] 8m x 16 sdram ba1 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-109 18.5.4.3.8 dual 256 mb (16mbx16) sdram configuration figure 18-90. dual 256-mbyte (16m x 16 x 2) sdram connection diagram table 18-39. dual 16mbx16 control register value control field value page size 2048 row 13 col 9 dsiz 32 (d [31:0]) srefr 4 clk cke ba0 ma11 ma[10:0] ras cas cs we dqmh dqml dq[15:0] 16m x 16 sdram ma12 sdram controller ba1 sdclk cke ba0 ma[10:0] ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:16] dq[15:0] ba1 clk cke ba0 a11 a[10:0] ras cas cs we dqmh dqml dq[15:0] 16m x 16 sdram ba1 ma11 ma12 a12 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-110 freescale semiconductor 18.5.4.3.9 single 64-mbyte (2mbx32) sdram configuration figure 18-91. single 64-mbyte (2mbx32) sdram connection diagram table 18-40. single 2mbx32 control register value control field value density 2 mb page size 1024 row 11 col 8 dsiz 32 (d [31:0]) srefr 1 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 2m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-111 18.5.4.3.10 single 128-mbyte (4 mbx32) sdram configuration figure 18-92. single 128-mb (4mbx32) sdram connection diagram table 18-41. single 4mbx32 control register value control field value density 4 mb page size 1024 row 12 col 8 dsiz 32 (d [31:0]) srefr 2 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 4m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 ma11 ma11 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-112 freescale semiconductor 18.5.4.3.11 single 256-mb (8 mbx32) sdram configuration figure 18-93. single 256-mb (8mbx32) sdram connection diagram table 18-42. single 8mbx32 control register value control field value density 8 mb page size 1024 row 13 col 8 dsiz 32 (d [31:0]) srefr 4 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 8m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 ma11 ma11 ma12 ma12 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-113 18.5.4.3.12 single 512-mb (1 6mbx32) sdram configuration figure 18-94. single 512-mb (16mbx32) sdram connection diagram table 18-43. single 16mbx32 control register value control field value density 16 mb page size 1024 row 13 col 9 dsiz 32 (d [31:0]) srefr 4 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 16m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 ma11 ma11 ma12 ma12 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-114 freescale semiconductor 18.5.4.3.13 single 1-gb (32mx32) sdram configuration figure 18-95. single 1-gb (32mbx32) sdram connection diagram table 18-44. single 32mbx32 control register value control field value density 32 mb page size 1024 row 14 col 9 dsiz 32 (d [31:0]) srefr 8 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 32m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 ma11 ma11 ma12 ma12 ma13 ma13 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-115 18.5.4.3.14 single 2-gb (64mbx32) sdram configuration figure 18-96. single 2-gb (64mbx32) sdram connection diagram table 18-45. single 64mbx32 control register value control field value density 64 mb page size 1024 row 14 col 10 dsiz 32 (d [31:0]) srefr 8 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] clk cke 64m x 32 sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke sdram controller dqm3 dqm2 ma11 ma11 ma12 ma12 ma13 ma13 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-116 freescale semiconductor 18.5.4.3.15 single 512-mb (16mbx32) mobile ddr sdram configuration figure 18-97. single 512-mb (16mbx32) lpddr sdram connection diagram table 18-46. single 16mbx32 control register value control field value density 16 mb page size 1024 row 13 col 9 dsiz 32 (d [31:0]) srefr 4 ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqm1 dqm0 dq[31:0] ck cke 16m x 32 lpddr sdram ba1 ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[31:0] sdclk cke e. sdram controller dqm3 dqm2 ma11 ma11 ma12 ma12 ck sdclk_b dqs1 dqs0 dqs3 dqs2 dqs1 dqs0 dqs3 dqs2 enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 18-117 18.5.4.3.16 single 512-mb (32mbx16) mobile ddr sdram configuration figure 18-98. single 512-mb (32mbx16) lpddr sdram connection diagram table 18-47. single 32mbx16 control register value control field value density 32 mb page size 1024 row 13 col 10 dsiz 16 (d [15:0]) srefr 4 ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas cs we dqmh dqml dq[15:0] ck cke 32m x 16 sdram ba1 ba0 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras cas csd [0] sdwe dqm3 dqm2 dqm1 dqm0 dq[15:0] sdclk cke0 esdctl controller ma12 ma12 ma13 ma13 dqs1 dqs0 dqs3 dqs2 dqs1 dqs0 ck sdclk_b enhanced sdram controller (esdramc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 18-118 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-1 chapter 19 nand flash controller (nfc) composed of various control logic units and a 2-kbyte internal ram buffer, the nand flash controller (nfc) provides an interface to standard nand flash memory devices. see figure 19-1 for the nfc block diagram. figure 19-1. nand flash controller block diagram 19.1 overview the nfc interfaces standard nand flash devices to th e ic and hides the complexities of accessing the nand flash. it provides a glueless interface to both 8-bit and 16-bit nand flash parts with page sizes of 512 bytes or 2 kbytes, and densities up to 64 gbits per 2-kbyte page size nand flash, and 8 gbits per 512 byte page size nand flash. ahb bus read and write control host control data output control ram buffer (528x32) register (command address/ status) ecc control address control nand flash control ahb bus interface bootloader cle ale ce re we wp rb din dout logic nf8boot nf16boot nf_16bit_sel nfc_endian hreset nfc_fms nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-2 freescale semiconductor 19.2 operation nfc operation begins by ahb host initiating a read from the nand flash device by configuring the controller and then waiting for an interrupt from the nfc. when it receives the interrupt, nfc inputs a page from the nand flash device, and upon completion, generates an interrupt to ahb host. when ahb host receives this interrupt, it reads the content from nfc?s internal ram buffer. to complete the operation, ahb host checks the status of the operation by reading the nfc status registers. the 2 kbyte ram buffer is used as boot ram during a cold reset (if ic is configured for a boot to be carried out from nand flash device). after boot proce dure completes, ram is available as buffer ram. in addition, nand flash controller provides an x16 bit and x32 bit interface to the ahb bus on the chip side, and an x8/x16 interface to the nand flash device on the external side. 19.3 features ? 8-bits/16-bits (pin option) nand flash interface ? internal ram buffer (2 kbytes + 64 bytes) ? can be configured as boot ram and operates as a buffer during normal operation ? memory mapped (to the same ahb region) registers and internal ram buffer ? manual interface with nand flash devices ? supports all nand flash products regardless of density/organization (with pages of 512 bytes/2 kbytes) ? ahb host interface type ? read/write burst ? 16-bits/32-bits bus transfers ? programmable read latency for internal bus (directly affects ahb bus) ? ecc mode/bypass ecc ? multiple reset ? cold reset/ warm reset/hot reset (reset of nfc and nand flash device) ? internal bootcode loader during power-up (can be enabled/disabled), providing advanced data protection ? data protection ? write protection mode for ram buffer: write protection of ram buffer (lsb 1 kbyte of ram buffer). for more details see section 19.7.14, ?nand flash write protection status (nand_flash_wr_pr_st) .? ? write protection mode for nand flash device: block based write protection of nand flash ? automatic write protection for ram buffer and nand flash during power-up ? write protection: automatic write protection for ram buffer and nand flash during power-up, in addition to run-time write protection modes for both ram buffer and nand flash device. ? handshaking feature: int pin indicates ready/busy status of nfc ? io pins sharing support ? allows sharing of io pins with other memory controllers through special arbitration logic. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-3 19.4 external signal description 19.4.1 overview the signals shown in table 19-1 are used to configure and control th e nfc and its attached flash device. 19.4.2 detailed signal descriptions table 19-2 gives a detailed description of the nfc signals. table 19-1. nfc signal properties name port function i/o reset hclk_in ? ahb clock of 133 mhz i enable hreset ? warm reset (active low) i 0 ipi_int_nfc ? nand flash controller interrupt o 1 ipp_flash_clk ? clock for the flash side i enable ipp_nfc_ale_out nfale flash address latch enable o 0 ipp_nfc_ce_out nfce flash chip enable o 1 ipp_nfc_cle_out nfcle flash command latch enable o 0 ipp_nfc_rb_in nfrb flash ready/busy i 1 ipp_nfc_re_out nfre flash read enable o 1 ipp_nfc_read_data_in[15:0] io[15:0] nfc data input from the nand flash i xxxx ipp_nfc_we_out nfwe flash write enable o 1 ipp_nfc_wp_out nfwp flash write protect o 1 ipp_nfc_write_data_out[15:0] io[15:0] nfc data output towards the nand flash o 0000 ipp_reset ? power on reset for booting i 1 nf_16bit_sel ? use 8 or 16-bits nand flash i 1 nf8boot ? boot from 8-bit nand flash i 1 nfc_fms ? flash memory select (512 byte/2 kbyte page size) i0 ng16boot ? boot from 16-bit nand flash i 1 table 19-2. nfc detailed signal descriptions signal i/o description nfce o flash chip enable. this signal indicates the nand flash selection. when the nand flash device is in the busy state, or when the nand flash device is accessed, this signal is low. nfre o flash read enable. this output is the nand flash device serial data output control. when active, this signal drives the data from the nand flash device onto the nand flash i/o bus, allowing the nfc to read the data. when reading a burst from the nand flash device, this signal increments the nand flash internal column address counter by one. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-4 freescale semiconductor nfwe o flash write enable.this output controls writes to nand flash i/o port, thus allowing the nand flash device to read data. commands, address and data are latched on the rising edge of the we signal. nfcle o flash command latch enable. the cle output controls the activating path for commands sent to the command register of nand flash (nand_flash_cmd). when active high, commands are latched into the command register of nand flash through the i/o ports on the rising edge of the we signal. nfale o flash address latch enable. the ale output controls the activating path for addresses sent to the address register of nand flash (nand_flash_add). when active high, addresses are latched into the nand fc address register of nand flash through the i/o ports on the rising edge of the we signal. nfwp o flash write protect. this signal provides inadvertent program/erase protection during power transition and is automatically controlled by nfc. this pin status is only active (held low) during power-up. nfrb i flash ready/busy. this signal indicates the status of the nand flash operation. when low, it indicates that a program, erase, or random read operation of nand flash is in process. upon completion of the process, this signal returns to high state. note: this signal is connected to an open drain output, via a 100 k ? pull-up resister (outside the external nand flash memory device). hreset warm reset. this signal produces a warm reset causing nfc and the nand flash device to cease current operation, and set all internal registers to their default state. see figure 19-2 for a timing diagram of warm reset operation. ahb bus interface is connected directly to this signal (hreset ) and will cause a reset immediately when this line goes to low state. nfc will not be reset if hreset pulses are shorter than two ipp_flash_clk cycles (50 ns if the clock period is 25 ns), but nfc will be reset if hreset pulse is longer than 20 ipp_flash_clk cycles (500 ns if this clock period is 25 ns). warm reset has no effect on the contents of main/spare area buffers. nf8boot nf16boot nf_16bit_sel the nf8boot and nf16boot are boot signals that determine when the chip will boot from the nand flash device, in addition to indicating boot selection it is also used to controls the bus width of the nand flash (8-bit or 16-bit). if one of the boot inputs is asserted (nf8boot or nf16boot is low) at system power-on reset (ipp_reset rising), a 2 kbyte sized boot code is copied from the nand flash device to the ram buffer. if none of the boot signals are asserted, then the input signal nf_16bit_sel is read. this is part of the logic of the operating modes of the nfc. for more information on operating modes, see section 19.8.1, ?modes of operation .? note: the boot signals should remain at the same value before and after the boot process. nfc_fms i flash memory select. nfc_fms signal indicates size of nand flash page (512 byte or 2 kbyte). 0 nand flash page size is 512 bytes. 64mb/128mb/256mb/512mb/1gb ddp 1 nand flash page size is 2 kbytes. ipp_reset i this input is power on reset (por) signal in the nfc. when it is asserted high, a por takes place. ipi_int_nfc o nfc interrupt. this output is the nfc interrupt, and is asserted when an nfc event takes place. it sets itself to ?1? when basic operation and boot loading is done, or when a warm or hot reset is released. in addition, it is asserted when any of the following occur: nand flash command input nand flash address input nand flash data input nand flash data output hclk_in i h clock input. this is nfc clock signal, which arrives from the ahb side. its value can up to 133 mhz. ipp_nfc_write_d ata_out[15:0] o ahb host uses this path to write data to registers or to internal memory. table 19-2. nfc detailed signal descriptions (continued) signal i/o description nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-5 figure 19-2. warm reset operation 19.5 nfc buffer memory space table 19-3 shows the organization of the buffer memory space in the nfc. 19.5.1 main and spare area buffers main area buffer is a general data block. spare area buf fer is used for a variety of functions including error correction. memory is organized in a different ma nner depending on flash bus width (8-bit or 16-bit). table 19-4 shows an 8-bit organization, and table 19-5 shows a 16-bit configura tion. host can use all of the spare area except for bi and ecc code areas. for ex ample, ahb host can write data to a reserved area in spare area buffer upon program operation. nfc auto matically generates ecc code for both main and spare data during nfc?s data loading to nand flash, and nfc updates ecc code to nand flash spare area, but does not update ecc code to spare buffer. when programming/reading spare area, the spare area buffer number (sb0?sb3) must be selected using the ram buffer address register (nfc_ram_buff). ipp_nfc_read_d ata_in[15:0] i ahb host uses this path to read data from registers or from internal memory. ipp_flash_clk this clock signal controls nfc?s state machine when interfacing with a nand flash device. table 19-3. data (buffer) organization in memory address use access 0xd800_0000? 0xd800_01fe main area buffer 0 r/w 0xd800_0200?0xd800_03fe main area buffer 1 r/w 0xd800_0400?0xd800_05fe main area buffer 2 r/w 0xd800_0600?0xd800_07fe main area buffer 3 r/w 0xd800_0800?0xd800_080e spare area buffer 0 r/w 0xd800_0810?0xd800_081e spare area buffer 1 r/w 0xd800_0820?0xd800_082e spare area buffer 2 r/w 0xd800_0830?0xd800_083e spare area buffer 3 r/w 0xd800_0840?0xd800_0bfe reserved ? 0xd800_0e00?0xd800_0e1c registers r/w table 19-2. nfc detailed signal descriptions (continued) signal i/o description nfc operation hreset ipi_int_nfc idle idle warm reset operation nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-6 freescale semiconductor table 19-4. spare area buffer (with x8 i/o bus) address fedcba9876543210 0xd800_0800 (sb0) lsn(2nd) 1 1 lsn: logical sector number lsn(1st) 1 0xd800_0802 (sb0) wc(1st) 2 2 wc: wrap count and other bytes have same wrap count information and are used as error correction for wrap count itself. lsn(3rd) 1 0xd800_0804 (sb0) bi 3 3 bi: bad block information wc(2nd) 2 0xd800_0806 (sb0) ecc code for main area data (2nd) ecc code for main area data (1st) 0xd800_0808 (sb0) ecc code for spare area data (1st) ecc code for main area data (3rd) 0xd800_080a (sb0) reserved ecc code for spare area data (2nd) 0xd800_080c (sb0) reserved reserved 0xd800_080e (sb0) reserved reserved 0xd800_0810? 0xd800_081e (sb1) sb1?sb3 have same assignment like sb0. 0xd800_0820? 0xd800_082e (sb2) 0xd800_0830? 0xd800_083e (sb3) table 19-5. spare area buffer (with x16 i/o bus) address fedcba9876543210 0xd800_0800 (sb0) lsn(2nd) 1 1 lsn: logical sector number lsn(1st) 1 0xd800_0802 (sb0) wc(1st) 2 2 wc: wrap count and other bytes have same wrap count information and are used as error correction for wrap count itself. lsn(3rd) 1 0xd800_0804 (sb0) reserved wc(2nd) 2 0xd800_0806 (sb0) ecc code for main area data (2nd) ecc code for main area data (1st) 0xd800_0808 (sb0) ecc code for spare area data (1st) ecc code for main area data (3rd) 0xd800_080a (sb0) bi 3 3 bi: bad block information ecc code for spare area data (2nd) 0xd800_080c (sb0) reserved reserved 0xd800_080e (sb0) reserved reserved 0xd800_0810? 0xd800_081e (sb1) sb1?sb3 have same assignment like sb0. 0xd800_0820? 0xd800_082e (sb2) 0xd800_0830? 0xd800_083e (sb3) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-7 19.6 memory map and register definition section 19.7, ?register descriptions ? provides detail descriptions for all the nfc registers. 19.6.1 memory map table 19-6 provides the nfc memory map. 19.6.2 register summary figure 19-3 shows the key to the register fields and table 19-7 shows the register figure conventions. table 19-6. nfc module register memory map address register r/w reset value section/page 0xd800_0e00 (nfc_bufsiz) nand flash controller buffer size register r 0x0000_0001 19.7.1/19-9 0xd800_0e02 reserved ? ? ? 0xd800_0e04 (ram_buffer_address) ram buffer address register r/w 0x0000_0000 19.7.2/19-10 0xd800_0e06 (nand_flash_add) nand flash address register r/w 0x0000_0000 19.7.3/19-10 0xd800_0e08 (nand_flash_cmd) nand flash command register r/w 0x0000_0000 19.7.4/19-11 0xd800_0e0a (nfc_configuration) nfc internal buffer lock control r/w 0x0000_0001 19.7.5/19-11 0xd800_0e0c (ecc_status_result) controller status and result of flash operation r 0x0000_0000 19.7.6/19-12 0xd800_0e0e (ecc_rslt_main_area) ecc error position main area data error x8 ecc error position main area data error x16 r 0x0000_0000 19.7.7/19-12 19.7.8/19-13 0xd800_0e10 (ecc_rslt_spare_area) ecc error position spare area data error x8 ecc error position spare area data error x16 r 0x0000_0000 19.7.9/19-14 19.7.10/19-14 0xd800_0e12 (nf_wr_prot) nand flash write protection r/w 0x0000_0002 19.7.11/19-15 0xd800_0e14 (unlock_start_blk_add) address to unlock in write protection mode?start r/w 0x0000_0000 19.7.12/19-15 0xd800_0e16 (unlock_end_blk_add) address to unlock in write protection mode?end r/w 0x0000_0000 19.7.13/19-16 0xd800_0e18 (nand_flash_wr_pr_st) nand flash write protection status r/w 0x0000_0002 19.7.14/19-16 0xd800_0e1a (nand_flash_config1) nand flash operation configuration1 r/w 0x0000_0008 19.7.15/19-17 0xd800_0e1c (nand_flash_config2) nand flash operation configuration 2 r/w 0x0000_0000 19.7.16/19-18 nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-8 freescale semiconductor always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 19-3. key to register fields table 19-7. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 19-8. nfc register summary name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xd800_0e00 (nfc_bufsiz)r00000000 0 0 0 0 bufsize w 0xd800_0e02 (reserved) r00000000 0 0 0 0 0 0 0 0 w 0xd800_0e04 (ram_buffer_address) r00000000 0 0 0 0 rba w 0xd800_0e06 (nand_flash_add) r add w 0xd800_0e08 (nand_flash_cmd) r cmd w nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-9 19.7 register descriptions 19.7.1 internal sram size (nfc_bufsize) this 16-bit read-only register contains internal sram size installed in the ic. bit assignments for this register is shown in figure 19-4 and the field descriptions are shown in table 19-9 . 0xd800_0e0a (nfc_configuration) r00000000 0 0 0 0 0 0 bls w 0xd800_0e0c (ecc_status_result) r00000000 0 0 0 0 erm ers w 0xd800_0e0e (ecc_rslt_main_area) r 0 0 0 0 ecc result 1 ecc result2 w 0xd800_0e10 (ecc_rslt_spare_area) r 0 0 0 0 0 0 0 0 0 0 0 ecc result 4 ecc result 3 w 0xd800_0e12 (nf_wr_prot) r 0 0 0 0 0 0 0 0 0 0 0 0 0 wpc w 0xd800_0e14 (unlock_start_blk_add) r usba w 0xd800_0e16 (unlock_end_blk_add) r ueba w 0xd800_0e18 (nand_flash_wr_pr_st) r 0 0 0 0 0 0 0 0 0 0 0 0 0 us ls lts w 0xd800_0e1a (nand_flash_config1) r 0 0 0 0 0 0 0 0 nf_ ce nf c_ rs t nf_ big int_ msk ecc _en sp_ en 0 0 w 0xd800_0e1c (nand_flash_config2) r int 0 0 0 0 0 0 0 0 0 fdo fdi fad d fc md wint table 19-8. nfc register summary (continued) name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-10 freescale semiconductor 19.7.2 buffer number for page data transfer (ram_buffer_address) rba specifies which part of the ram buffer is transferred to/from flash memory. bit assignments for this register is shown in figure 19-5 and the field description is shown in table 19-10 . 19.7.3 nand flash address (nand_flash_add) nand flash address (nand_flash_add) register is a r ead-write register containing the address of nand flash device that will be read, progra mmed or erased. the address in nand_flash_add register is written to the flash device. bit assignments for this register is shown in figure 19-6 and the field descriptions are shown in table 19-11 . 0xd800_0e00 (nfc_bufsiz) access: user read-only 1514131211109876543210 r000000000000 bufsize w reset0000000000000001 figure 19-4. nfc_bufsize register table 19-9. nfc_bufsize register field description name description 15?4 reserved 3?0 bufsize buffer size. the size of the internal ram buffer. 0000 1 kbyte 0001 2 kbytes (default) 0010?1111 reserved 0xd800_0e04 (ram_buffer_address) access: user read/write 1514131211109876543210 r000000000000 rba w reset0000000000000000 figure 19-5. ram buffer address register table 19-10. ram buffer address field descriptions field description 15?4 reserved 3?0 rba ram buffer address. specifies the ram buffer number to use for data transfers to/from the nand flash device. 0000 1st internal ram buffer 0001 2nd internal ram buffer 0010 3rd internal ram buffer 0011 4th internal ram buffer nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-11 19.7.4 nand flash command (nand_flash_cmd) bit assignments for this register is shown in figure 19-7 and field descriptions are shown in table 19-12 . 19.7.5 nfc internal buffer lock control (nfc_configuration) bit assignments for this register is shown in figure 19-8 and field descriptions are shown in table 19-13 . 0xd800_0e06 (nand_flash_add) access: user read/write 1514131211109876543210 r add w reset0000000000000000 figure 19-6. nand flash address register table 19-11. nand flash address register field description field description 15?0 add nand flash address. nand flash address which will be read, programmed or erased. this address is written to the nand flash device. 0xd800_0e08 (nand_flash_cmd) access: user read/write 1514131211109876543210 r cmd w reset0000000000000000 figure 19-7. nand_flash_cmd register table 19-12. nand_flash_cmd register field description field description 15?0 cmd nand flash command. this field contains the cmd that is written to the nand flash device. 0xd800_0e0a (nfc_configuration) access: user read/write 1514131211109876543210 r00000000000000 bls w reset0000000000000001 figure 19-8. nfc_configuration register nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-12 freescale semiconductor 19.7.6 controller status and result of flash operation (ecc_status_result) this register shows the number of errors in a page for spare and main area as a result of ecc check upon a page read.bit assignment is shown in figure 19-9 and the field descriptions are shown in table 19-14 . 19.7.7 ecc error position of main area data error x8 (ecc_rslt_main_area) (nand flash x8 data bus case) this register contains ecc error position address which is used to select the bit to repair in main area for 8-bit nand flashbit assignments for this register is shown in figure 19-10 , and the field descriptions are shown in table 19-15 . table 19-13. nfc_configuration register field descriptions field description 15?2 reserved. 1?0 bls buffer lock set. this field specifies the buffer lock status of first 2 pages in the internal buffer. the other two pages are always unlocked. (for more details, see section 19.9.3, ?write protection operation .? ) 00 locked 01 locked (default) 10 unlocked 11 locked 0xd800_0e0c (ecc_status_result) access: user read-only 1514131211109876543210 r000000000000 erm ers w reset0000000000000000 figure 19-9. ecc_status_result table 19-14. ecc_status_result register field description field description 15?4 reserved 3?2 erm ecc error for main area data (erm) and spare area data (ers). these field shows the number of errors in a page as a result of ecc check upon page read. the ecc algorithm of nfc doesn?t correct if there are greater than two fault bits per page. it interprets any ecc error count greater than two as non-correctable. 00 no error 01 1-bit error (correctable error) 10 2-bits error or more (non-correctable error) 11 reserved 1?0 ers nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-13 19.7.8 ecc error position of main area data error x16 (ecc_rslt_main_area) (nand flash x16 data bus case) this register contains ecc error position address which is used to select the bit to repair in main area for 16-bit nand flash bit assignments for this register is shown in figure 19-11 , and the field descriptions are shown in table 19-16 . 0xd800_0e0e (ecc_rslt_main_area) access: user read-only 1514131211109876543210 r0000 ecc result1 ecc result2 w reset0000000000000000 figure 19-10. ecc_rslt_main_area register table 19-15. ecc_rslt_main_area register field descriptions field description 15?12 reserved 11?3 ecc result1 ecc result 1: ecc error position address which selects one of main area data bytes (one of 512 bytes). 2?0 ecc result2 ecc result 2: ecc error position address which selects one of the 8 data bits in the byte. 0xd800_0e0e (ecc_rslt_main_area) access: user read-only 1514131211109876543210 r0000 ecc result1 ecc result2 w reset0000000000000000 figure 19-11. ecc_rslt_main_area register table 19-16. ecc_rslt_main_area register field descriptions field description 15?12 reserved 11?4 ecc result1 ecc result 1: ecc error position address which selects one of the 16 data bits in the half word 3?0 ecc result2 ecc result 2: ecc error position address which selects one of the 8 data bits in the byte nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-14 freescale semiconductor 19.7.9 ecc error position of spare area data error x8 (ecc_rslt_spare_area) (nand flash x8 data bus case) this register contains ecc error positi on address which is used to select the bit to repair in spare area for 8-bit nand flash bit assignments for this register is shown in figure 19-12 , and the field descriptions are shown in table 19-17 . 19.7.10 ecc error position of spare area data error x16 (ecc_rslt_spare_area) (nand flash x16 data bus case) this register contains ecc error position address which is used to select the bit to repair in spare area for 16-bit nand flash. bit assignments for this register is shown in figure 19-13 and the field descriptions are shown in table 19-18 . 0xd800_0e10 (ecc_rslt_spare_area) access: user read-only 151413121110987654 3210 r 0 0 0 0 0 0 0 0 0 0 0 ecc result 4 ecc result 3 w reset0000000000000000 figure 19-12. ecc_rslt_spare_area register table 19-17. ecc_rslt_spare_area descriptions field description 15?5 reserved 4?3 ecc result4 ecc result 4: ecc error position address which selects one of logical sector number (3 bytes) 2?0 ecc result3 ecc result 3: ecc error position address which selects one of 8 data bits in the byte. 0xd800_0e10 (ecc_rslt_spare_area) access: user read-only 15141312111098765 4 3210 r 0 0 0 0 0 0 0 0 0 0 0 result4 result 3 w reset00000000000 0 0000 figure 19-13. ecc_rslt_spare_area register nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-15 19.7.11 nand flash write protection (nf_wr_prot) this register specifies the protection command that th e controller will perform: lock, unlock, or lock tight. bit assignments for this register is shown in figure 19-14 and field descriptions are shown in table 19-19 . 19.7.12 address to unlock in write protection mode?start (unlock_start_blk_add) starting address of block memory in the nand flash that is unlocked in the write protection mode. bit assignments for this register is shown in figure 19-15 and the field descriptions are shown in table 19-20 . table 19-18. ecc_rslt_spare_area descriptions field description 15?5 reserved 4 ecc result4 ecc result 4: ecc error position address which selects one of logical sector number (3 bytes) 3?0 ecc result3 ecc result 3: ecc error position address which selects one of the 8 data bits in the byte. 0xd800_0e12 (nf_wr_prot) access: user read/write 1514131211109876543210 r 0 0 0 0 0 0 0 0 0 0 0 0 0 wpc w reset0000000000000010 figure 19-14. nand flash write protection register table 19-19. nand flash write protection register field descriptions field description 15?3 reserved 2?0 wpc write protection command: this field specifies the operation which the controller will perform. 100 unlock nand flash block(s) according to given block address range 010 lock all nand flash block(s) 001 lock-tight locked blocks(s) (see section 19.9.3, ?write protection operation ? for more details.) 0xd800_0e14 (unlock_start_blk_add) access: user read/write 1514131211109876543210 r usba w reset0000000000000000 figure 19-15. unlock_start_blk_add register nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-16 freescale semiconductor 19.7.13 address to unlock in write protection mode?end (unlock_end_blk_add) end address of block memory in the nand flash that is unlocked in the write protection mode. bit assignments for this register is shown in figure 19-16 and the field descriptions are shown in table 19-21 . 19.7.14 nand flash write protection status (nand_flash_wr_pr_st) this status register reads the nand flash write protection status: lock, unlock or lock tight status. bit assignments for this register is shown in figure 19-17 and the field descriptions are shown in table 19-22 . table 19-20. unlock_start_blk_add register field description field description 15?0 usba unlock start block address. starting address of block memory in the nand flash that is unlocked in write protection mode. for more details on this, see section 19.9.3.4, ?write protection status .? 0xd800_0e16 (unlock_end_blk_add) access: user read/write 1514131211109876543210 r ueba w reset0000000000000000 figure 19-16. unlock_end_blk_add register table 19-21. unlock_end_blk_add register field description field description 15?0 ueba unlock end block address. ending address of block memory in the nand flash that is unlocked in write protection mode. for more details, see section 19.9.3.4, ?write protection status .? 0xd800_0e18 (nand_flash_wr_pr_st) access: user read-only 1514131211109876543210 r 0 0 0 0 0 0 0 0 0 0 0 0 0 us ls lts w reset0000000000000010 figure 19-17. nand_flash_wr_pr_st register table 19-22. nand_flash_wr_pr_st register field descriptions field description 15?3 reserved 0 lts lock-tight status. indicates if any of the locked block(s) is (are) have a lock-tight status. 0 locked block(s) is (are) not lock-tight. 1 locked block(s) is (are) lock-tight. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-17 there are four states for write protected: lock, unlock-lock, unlock-lockt, and lockt. 19.7.15 nand flash operation co nfiguration (nand_flash_config1) this register is a configuration register for nand flas h device to control the ecc enable or disable mask interrupt. bit assignments for this register is shown in figure 19-18 and the field descriptions are shown in table 19-24 . 1 ls locked status. this bit indicate whether all nand flash blocks are in locked status or in lock-unlock status. 0 not all nand flash blocks are in locked status. 1 there are unlocked block(s) in nand flash. 2 us unlocked status. this bit indicates whether there are any unlocked blocks in the nand flash. 0 there are no unlocked blocks in nand flash. 1 there are unlocked block(s) in nand flash. table 19-23. write protected states state status bits?us -ls -lts lock?all blocks are locked 010 unlock-lock?there are unlocked blocks 110 unlock-lockt?there are unlocked blocks: cant change to other state 101 lockt?all block are locked: cant change to other state 001 0xd800_0e1a (nand_flash_config1) access: user read/write 1514131211109876543210 r 0 0 0 0 0 0 0 0 nf_c e nfc_ rst nf_b ig int_ msk ecc_ en sp_e n 0 0 w reset0000000000001000 figure 19-18. nand_flash_config1 register table 19-24. nand_flash_config1 register field descriptions field description 15?8 reserved 7 nf_ce nand flash force ce. this bit forces the ce signal to the nand flash device to 0 when enabled. this bit allows a greater range of support new nand flash devices. 0 ce signal operates normally. 1 ce signal is asserted as long as this bit is set to 1. 6 nfc_rst nfc reset. this bit resets the nfc state machine. 0 do not reset the nfc state machine 1 reset the nfc state machine table 19-22. nand_flash_wr_pr_st register field descriptions (continued) field description nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-18 freescale semiconductor 19.7.16 nand flash operation configuration 2 (nand_flash_config2) this register controls the nand flash signals: cle, ale, we, re, ce . and sets the interrupt after command completion. bit assignments for this register is shown in figure 19-19 and the field descriptions are shown in table 19-25 . 5 nf_big nand flash big endian mode. this bit enables big endian mode when writing from internal ram to the nand flash device or reading from nand flash device to internal ram. 0 little endian mode 1 big endian mode 4 int_msk mask interrupt bit. this bit enables the interrupt by masking or not masking the interrupt bit. 0 mask interrupt is disabled (interrupt enabled). 1 mask interrupt is enabled (interrupt disabled). 3 ecc_en ecc operation enable. this bit determines whether ecc operation is executed or bypassed 0 ecc operation is bypassed. 1 ecc operation is executed. 2 sp_en nand flash spare enable. this bit determines whether host reads/writes are to nand flash spare data only or nand flash main and spare data. 0 nand flash main and spare data is enabled. 1 nand flash spare only data is enabled. 1?0 reserved 0xd800_0e1c (nand_flash_config2) access: user read/write 15141312111098765432 1 0 r int 0 0 0 0 0 0 0 0 0 fdo fdi fadd fcmd w reset000000000000010 0 figure 19-19. nand_flash_config2 register table 19-25. nand_flash_config2 register field descriptions field description 15 int interrupt. this field determines the state of the interrupt output of the nand flash controller. it is set by the controller when a basic operation is done. it is set cleared by the host writing ?0? to this field. (host can also set this bit by writing ?1? to this field). 0 basic operation or boot loading is still running. 1 basic operation or boot loading is done. 14?6 reserved 5?3 fdo nand flash data output. this bit enables nand flash data output 001 one page data out 1 010 nand flash id data out 100 nand flash status register data out table 19-24. nand_flash_config1 register field descriptions (continued) field description nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-19 note int bit reset value is 0, but soon after power-up it will change to 1. int will change from 0 to 1, when performing boot from nand flash, after boot code transfer is accomplished. for more information, see section 19.8.1, ?modes of operation .? when basic operation is completed, fcmd/fadd/fdi/fdo bits change to low automatically. only one of the bit fields (fcmd/fadd/fdi/fdo) can be set at any given time. 19.8 functional description this section provides the functional description for the nand flash controller. 19.8.1 modes of operation operating mode is determined by four input lines: nfc_fms, nf8boot , nf16boot , nf_16bit_sel, as shown in table 19-26 . it is possible to configure the i.mx31 to boot from a nand flash device. for this to occur, one of the signals nf8boot or nf16boot must be low (0). if both of these signals are high, a boot from the nand flash device does not occur. if both of these signals are low, the situation is undefined, and should not be used. the value of the nfc_fms determines the page size of nand flash: 512 bytes if nfc_fms is low (0), and 2 kbyte if nfc_fms is high (1). while booting from nand flash device, bus width is determined by the bus width used during boot. while not booting fr om nand flash device, bus width is determined by the value of nf_16bit_sel signal (0=8-bit bus, 1=16-bit bus). 2 fdi nand flash data input. this field enables nand flash data input 0 no nand flash data input operation 1 enable nand flash data input operation 1 fadd nand flash address input. this field enables nand flash address input 0 no nand flash address input operation 1 enable nand flash address input operation 0 fcmd nand flash command input. this field enables the nand flash command input 0 no nand flash command input operation 1 allow nand flash command input operation 1 page size is determined by sp_en register bit (main + spare or spare only). it is 528 bytes (main+spare) or 16 bytes (spare) regardless of the nfc_fms setting. table 19-25. nand_flash_config2 register field descriptions (continued) field description nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-20 freescale semiconductor 19.8.2 booting from a nand flash device booting from nand flash device proceeds as follows 1 : 1. bootloader copies 1 page of 2 kbytes or 4 pages of 528 bytes (depending on nfc_fms input value) from the nand flash to the nfc internal ram buffer. the transfer is done in the following order: ? for nand flash with 528-byte page depth case: 1st page read => 2nd page read => 3rd page read => 4th page read ? for nand flash with 2 k page depth case: one page read 2. ahb host then reads (after exiting from reset state) the first code from nfc internal ram buffer. table 19-26. nand flash controller operating modes nfc_fms nf8boot nf16boot nf_16bit_sel function 0 1 1 0 do not boot from nand flash. nand flash is configured to 8-bits i/o bus width and page size is 512 bytes. 0 1 1 1 do not boot from nand flash. nand flash is configured to 16-bits i/o bus width and page size is 512 bytes. 0 1 0 x boot from 16-bit nand flash. nand flash is configured to the same value as it booted from (16-bits) and page size is 512 bytes. 0 0 1 x boot from 8-bit nand flash. nand flash is configured to the same value as it booted from (8-bits) and page size is 512 bytes. 1 1 1 0 do not boot from nand flash. nand flash is configured to 8-bits i/o bus width and a page size is 2 kbyte. 1 1 1 1 do not boot from nand flash. nand flash is configured to 16-bits i/o bus width and a page size is 2 kbyte. 1 1 0 x boot from 16-bit nand flash. nand flash is configured to the same value as it booted from (16-bits) and page size is 2kbyte. 1 0 1 x boot from 8-bit nand flash. nand flash is configured to the same value as it booted from (8-bits) and page size is 2kbyte. x 0 0 x not defined (do not use this setting.) 1. a boot from the nand flash device will only occur if one of the boot inputs is asserted (nf8boot or nf16boot is low) at system power-on reset (ipp_resetb rising). nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-21 figure 19-20. boot mode operation note 2 kbytes of bootcode copy takes about 160 s. host must read bootcode in the ram buffer (2 kbytes) after bootcode copy completion. interrupt pin (ipi_int_nfc ) goes from high to low when the bootcode-copy is completed, and upon hreset rising edge. if hreset goes from low to high before bootcode-copy is done, interrupt pin (ipi_int_nfc ) goes from high to low as soon as bootcode-copy is completed. the interrupt can be relevant for cases of secured boot (booting from rom and then enabling the nfc boot). 19.8.3 nand flash control nand flash control generates all control si gnals that control the nand flash: ce (flash chip enable), re (read enable for read operations), we (flash write enable), cle (flash command latch enable), ale (flash address latch enable). it monitors r/nb (flash ready/busy indication) signal to check if the nand flash is in the middle of operation. bootl oader is part of nand flash control block. figure 19-21 , figure 19-22 , and figure 19-23 show nand flash read, program, and erase timing diagrams. ipp_resetb (por) nf8boot or nf16boot sleep bootcode-copy idle nfc operation hreset ipi_int_nfc bootcode-copy done 1) 2) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-22 freescale semiconductor figure 19-21. read operation figure 19-22. program operation nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-23 figure 19-23. erase operation 19.8.4 error code correction (ecc) control error code correction (ecc) block is responsible for co rrecting one bit per read, and for detecting if there is more then one bit with an error. when nfc accesses the nand flash device for program operation, it generates code (24-bits for main area data and 10-bits for spare area data). when it accesses the nand flash device for a read operation, it generates ecc code, and indicates how many errors were detected, and their positions in addition to correcting 1 error bit. the ecc code is updated by the nfc automatically. after a read operation, ahb host can know whether there is an error or not by re ading the status register (see ecc_status_result register in section 19.7.6, ?controller status and result of flash operation (ecc_status_result) ?). the indication in the status register is either a) no error, b) 1 bit error (correctable), or c) greater than 2 bit errors (uncorrectable). since the generated ecc code at read/program operation is not updated to the internal ram buffer, but is updated to the nand flash spare area upon program operation, the ahb host can read generated ecc code only from nand flash spare area. 19.8.5 address control this module is responsible for address control and generation. it define s the ram buffer address generation (ram buffer address for data in/ data out) . it generates and takes into account the lock state sequence (for more details see section 19.9.3, ?write protection operation ?) and therefore contains the flash memory lock address comparator, and ram buf fer lock address comparator which are used to determine if this area is protected or not. it also generates the ram buffer address for boot load and ram buffer address for error correction. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-24 freescale semiconductor 19.8.6 ram buffer (sram) the internal ram buffer is a 2112 byte single port ram buffer which is a synchronous high performance design. this memory has 528 words of 32-bits each, from which 512 words are used for the main buffer and the remaining 16 words are allotted to a spare ar ea, which is used for ecc (error correction). this memory is used as a bootram during boot from nand flash device, and as a buffer at normal operation. 19.8.7 registers (command, address, status, and others.) this module contains 15 registers of 16-bits each. using these registers, the ahb host can control the nfc, read status on various operations and perform a direct access of commands, and insert addresses to the nand flash device. for more details, refer to section 19.6.1, ?memory map .? 19.8.8 read and write control the read and write control block contains a connecti on to the internal bus (which is connected to the internal ram buffer and the registers). this internal bus is responsible for the internal synchronous read and asynchronous write. it supports bu rst read latency (3, 4, 5, 6, 7 cycle) and synchronous read burst length (4, 8, 16, 32, continuous word). it is also respons ible for ram buffer control and register control, ram buffer lock control and address and data latches. 19.8.9 data output control this module defines data output of 16-bits to the internal bus which is driven to the ahb interface. it includes ram buffer data output, register data out put and ram buffer synchronization for the read mode pipeline. 19.8.10 host control this module defines host control which is connected to the ahb interface though the internal bus. it detects chip enable and controls the reset and output enable, and generates the sram_we signal. 19.8.11 ahb bus interface ahb bus interface is an adapter between abma ahb bus and the internal bus. on the ahb bus side, it supports a 16-bit and 32-bit bus width, burst and non burst operations. on the internal bus side, it supports 32-bit bus width with a synchronous burst read a nd an asynchronous random write. it also supports programmable read latency for the internal bus (this also effects the latency on the ahb bus). 19.8.11.1 big/little endian ahb bus interface supports both big and little endian da ta types. the nfc_endian pin controls the endian mode. only the ahb side is controlled by nfc_endian pin; nand flash device side is always in little endian mode. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-25 19.8.11.2 burst access support when a data transaction from the ahb is a burst, it will create a synchronous burst read on the internal bus for read cycles, and several asynchronous random writes for write cycles. table 19-27 lists the nfc supported access burst types. t note nfc supports bursts of 16/32-bit words only. bursts of byte words (8-bits) is not supported. 19.8.12 i/o pins sharing nfc has logic that allows it to share i/o pins with pins of another memory controller. nfc?s state machine halts when a request to free the pins is asserte d. the nand flash signals when it finishes the existing transfer allowing the other memory controller to be able to control them. since the nand flash accesses are long and relatively slow, the priority is give n to the other memory controller and the nand flash controller will have to wait till the pins are free before it can continue with its accesses. one example for this pin muxing is sharing the 16 i/ o pins of the nand flash controller with the data pins of the weim when interfacing to the psram. 19.9 initialization/app lication information this section describes how to operate the nfc using its registers and its interrupts, and is divided into the following subjects: ? normal operation?in order to operate a nand flas h device using the nfc the user should use the instructions in section 19.9.1, ?normal operation .? ? ecc operation?ecc operation is used when an error is detected. ? write protection operation (both to the internal memory and the flash device)?write protection is used when the programmer wishes to protect pa rt of the nand flash device memory from being written except in certain cases. there are two levels of protection: software (for frequently-changed memory locations), and hardware (for memory locations whose contents are rarely changed). table 19-27. nand flash burst access support hburst burst type supported description 000 single yes single transfer 001 incr yes incrementing burst 010 wrap4 no 4-beat wrapping burst 011 incr4 yes 4-beat incrementing burst 100 wrap8 no 8-beat wrapping burst 101 incr8 yes 8-beat incrementing burst 110 wrap16 no 16-beat wrapping burst 111 incr16 yes 16-beat incrementing burst nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-26 freescale semiconductor 19.9.1 normal operation ?normal operations? are composed of fundamental building block operations (in section 19.9.1.1, ?fundamental building block operations ?), in addition to specific operations, as shown in the flowcharts below (in section 19.9.1.2, ?nand flash id read operation ? to section 19.9.1.7, ?hot reset (controller and nand flash reset) ?). 19.9.1.1 fundamental building block operations 19.9.1.1.1 preset operation figure 19-24 provides a flowchart of the nand flash preset operation. figure 19-24. flowchart of preset operation 19.9.1.1.2 nand flash command input operation figure 19-25 provides a flowchart of the nand flash command input operation. start set nfc configuration register (e0ah) if needed pre-setting is completed set nand flash write protection command register (e12h), unlock start block address register (e14h), unlock end block address register (e16h), if needed. set nand flash configuration1 register (e1ah) (set ecc_en and sp_e) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-27 figure 19-25. flowchart of nand fl ash command input operation 19.9.1.1.3 nand flash address input operation figure 19-26 provides a flowchart of the nand flash address input operation. figure 19-26. flowchart of nand flash address input operation start write nand flash command to nand flash command register (e08h) nand flash command input is completed set nand flash operation configuration2 register(e1ch) (set int to 0 and fcmd to 1 and other bits to 0) int = high? ye s wait no start write nand flash address to nand flash address register (e06h) nand flash address input is completed set nand flash operation configuration2 register (e1ch) (set int to 0 and fadd to 1 and other bits to 0) int = high? ye s wait no ye s no is address cycle completed? nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-28 freescale semiconductor 19.9.1.1.4 nand flash data input operation figure 19-27 provides a flowchart of the nand flash data input operation. figure 19-27. flowchart of nand flash data input operation 19.9.1.1.5 nand flash data output operation figure 19-28 provides a flowchart of the nand flash data output operation. start set ram buffer address register (e 04h) where data is loaded from host nand flash data input is completed set nand flash operation configuration2 register (e1ch) (set int to 0 and fdi to 1 and other bits to 0) int = high? ye s wait no write the nand flash data to ram buffer nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-29 figure 19-28. flowchart of nand flash data output operation 19.9.1.2 nand flash id read operation figure 19-29 provides a flowchart of the nand flash id read operation. start set nand flash operation configuration1 register (e1ah) (set ecc_en and sp_en) set ram buffer address register (e04h) where data is loaded from nand flash set nand flash operation configuration2 register (e1ch) (set int to 0 and fd0 to 1 and other bits to 0) int = high? ye s wait no read the nand flash data from ram buffer nand flash data output is completed nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-30 freescale semiconductor figure 19-29. flowchart of read nand flash id operation 19.9.1.2.1 nand flash id data formats format of nand flash id data stored in ram buffer (for x8 org. nand flash) is shown in figure 19-30 . the format of nand flash id data stored in ram buffer (for x16 org. nand flash) is shown in figure 19-31 . ram buffer of rba address 1st half-word 2nd half-word 3rd half-word 1st byte of id 2nd byte of id 3rd byte of id 4th byte of id 5th byte of id 6th byte of id lsb msb figure 19-30. nand flash id data format (x8) ram buffer of rba address 1st half-word 2nd half-word 3rd half-word 1st byte of id xxh 2nd byte of id xxh 3rd byte of id xxh lsb msb start preset operation. nand flash address input operation. end set ram buffer address register (e04h) (set rba to load nand flash id) nand flash command input operation (command: 90h) nand flash data output operation. read id data from assigned ram buffer (refer section 19.9.1.2.1, ?nand flash id data formats ?) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-31 19.9.1.3 nand flash status read operation figure 19-32. flowchart of read nand flash status operation 19.9.1.3.1 nand flash status data format the assignment of nand flash status data stored in the ram buffer (for both x8/x16 org. nand flash) is shown in figure 19-33 . ram buffer of rba address 4th half-word 5th half-word 6thhalf-word 4th byte of id xxh 5th byte of id xxh 6th byte of id xxh lsb msb figure 19-31. nand flash id data format (x16) ram buffer of rba address 1st half-word - - - - - - - - 1st byte of status xxh lsb msb figure 19-33. nand flash status data format start preset operation. end set ram buffer address register (e04h) (s et rba to load nand flash status data) nand flash command input operation (command: 70h) nand flash data output operation. read id data from assigned ram buffer (refer to section 19.9.1.3.1, ?nand flash status data format ?) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-32 freescale semiconductor 19.9.1.4 read nand flash data operation figure 19-34 shows a flowchart of the read nand flash data operation. figure 19-34. flowchart of read nand flash data operation 19.9.1.5 program nand flash data operation figure 19-35 shows a flowchart of the program nand flash data operation. start preset operation. end set ram buffer address register (e04h) (s et rba to load nand flash status data) nand flash command input operation (command: nand flash read command) nand flash data output operation. check ecc status register (e0ch) and do next step according to the result nand flash address input operation (a ddress: nand flash address to be read) nand flash command input operation (command: nand flash read confirm command, which is required with nand flas h devices that are 1 gbyte or larger) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-33 figure 19-35. flowchart of progr am nand flash data operation 19.9.1.6 erase nand flash data operation figure 19-36 shows a flowchart of the erase nand flash data operation. start preset operation. end set ram buffer address register (e04h) (set rba to load data to be programmed from host) nand flash command input operation (command: data loading command) nand flash status read operation. nand flash address input operation (addre ss: nand flash address to be programmed) nand flash command input operation (command: confirm command nand flash data input operation. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-34 freescale semiconductor figure 19-36. flowchart of erase nand flash operation 19.9.1.7 hot reset (controller and nand flash reset) a warm (or ?hot?) reset causes the nfc and the nand flash device cease their current operation and causes the internal registers to revert to their default state. figure 19-37 shows a flowchart of a hot reset operation. figure 19-37. flowchart of hot reset operation 19.9.2 ecc operation 19.9.2.1 ecc normal operation when nfc accesses the nand flash device for progr am operation, it generates ecc code (24 bits for main area data and 10 bits for spare area data). when nfc accesses the nand flash device for a read start preset operation. end nand flash command input operat ion (command: erase command) nand flash status read operation. nand flash address input operation nand flash command input operation (command: confirm command start preset operation. end nand flash command input operation (command: ffh) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-35 operation, it generates ecc code, detects the error num ber and position and corrects a 1-bit error, if applicable. table 19-28 shows ecc code assignment of nand fl ash spare area. this ecc code is updated by nfc automatically. after read operation, ahb host can know whether there is error or not by reading the status register (see ecc_status_result register in section 19.7.6, ?controller status and result of flash operation (ecc_status_result) ?). error type can be: a) no error, b) 1bit error (correctable), or c) 2 or more bit error (uncorr ectable). since generated ecc code at read/program operation is not updated to the internal buffer ram, but is updated to nand flash spare area immediately upon program operation, ahb host can read generate d ecc code only from nand flash spare area. 19.9.2.2 ecc bypass operation in ecc bypass operation, nfc generates an ecc result which indicates error position (refer ecc result table), but doesn?t correct the error. after a read ope ration, host can know whether there is an error or not by reading the status register (refer ecc status register table). error type is divided into no error, 1bit error (correctable), or 2bits error (uncorrectable). in 1bit error case, the host can correct the error by itself after reading the ecc result register (see ecc_status_result register in section 19.7.6, ?controller status and result of flash operation (ecc_status_result) ?). 19.9.2.3 how to operate ecc in order to generate ecc and carry out correcti on by nfc, program and read with ecc operation. in order to generate ecc by nfc and carry out corr ection by ahb host, program with ecc operation and read without ecc operation note ahb host can read ecc results from ecc_status_result register (see section 19.7.6, ?controller status and result of flash operation (ecc_status_result) ?) after a read operation in both ecc normal operation and ecc bypass cases. when nfc reads nand flash data, ecc code for read data is not updated into ram buffer. 19.9.3 write protection operation nfc offers a software write protection featur e, and a hardware write protection feature. table 19-28. ecc code/result readability operation read operation program operation ecc code from spare area buffer ecc result from register ecc code from spare area buffer ecc result from register ecc operation invalid (pre-written ecc code 1 ) 1 pre-written ecc code: ecc code which is previously written to nand flash spare area in program operation. valid invalid (old data 2 ) 2 old data: ecc code is not updated to spare buffer, so ecc code placement of spare buffer remains old data. ? ecc bypass invalid (pre-written ecc code) valid invalid (old data) ? nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-36 freescale semiconductor 19.9.3.1 write protection for ram buffer (lsb 1 kbyte) nfc offers a software write protection feature for the first 2 pages (main + spare area data) of ram buffer, which protects ram buffer data. this write protection is carried out by setting bls bit of the nfc_configuration register. the default state is lock ed state, and first 2 pages go to this state after a cold or warm reset. write protection availability for main/spare memory regions in the ram buffer are described on table 19-29 . a state diagram of ram buffer write protection is shown in figure 19-38 . figure 19-38. state diagram of ram buffer write protection 19.9.3.2 write protection modes nfc offers both hardware and software write prot ection options for the nand flash device. software write protection feature is used by executing l ock block command or l ock - tight block command, and hardware write protection feature is used by executi ng a cold or warm reset. the wp signal is asserted only upon por. 19.9.3.3 write protection commands there are two write protection states: locked and lock-tight. ? locked state means that memory block in question is write protected (it cannot be written to), but u nlock command can ?un?-lock it. useful for frequently changed memory blocks. table 19-29. write protection for main/spare ram buffer main area spare area 1st page ram buffer write protection available 2nd page ram buffer 3rd page ram buffer write protection not available 4th page ram buffer device in cold or warm reset unlocked locked initial state nfc_configuration register[1:0] = 00/01/11 nfc_configuration register[1:0] = 10 nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-37 ? lock-tight state is a higher level of protection, a nd means that memory block in question is write protected, but u nlock command cannot unlock it. useful for memory blocks whose contents are rarely changed. the following summarizes the locking functionality: ? all blocks power-up in a locked state. the unlock command can unlock these blocks. ? l ock - tight block command locks blocks and prevents it (them) from being unlocked. ? lock-tight state can be reverted to locked state only when cold/warm reset is executed. ? writing to unlock start/end address registers (unlock_start_blk_add and unlock_end_blk_add) while nfc is in lock-tight state does not affect the unlock address. 19.9.3.4 write protection status the current write protection status of the nfc can be read in nand flash write protection status register (nand_flash_wr_pr_st). there are three bits: us,ls, and lts, which are not cleared by hot reset. these write protection status bits are updated as soon as the write protection command is entered. figure 19-39 shows a state diagram for the write protection of the nfc. nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-38 freescale semiconductor figure 19-39. state diagram of nand flash write protection 19.9.3.4.1 lock sequence the following describes the ?lock? sequence: 1. command sequence: l ock block command (02h) 2. all blocks default to locked after initial cold reset or warm reset. 3. locking some of the blocks is not availa ble; all memory blocks are locked upon reset. 4. unlocked memory blocks can be locked by using the l ock block command. status of a locked memory block can be changed to unlocked or lo ck-tight using appropriate software commands. 19.9.3.4.2 unlock sequence the following describes the ?unlock? sequence: 1. command sequence: start block address + end block address + u nlock block command(04h) unlocked locked lock- tight cold or warm reset hreset pin: high and start block address + end block address + unlock block command hreset pin: high and start block address + end block address + unlock block command hreset pin: high and lock-tight block command hreset pin: high and lock-tight block command hreset pin: high and lock block command initial state hreset pin: rising edge (this occurs at cold reset or warm reset) nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-39 2. unlocked blocks can be programmed or erased. 3. status of unlocked block can be changed to locked / lock-tight using appropriate software command. 4. only one sequential area can be released to unlocked state from locked state; unlocking multi-areas is not available. 19.9.3.4.3 lock-tight sequence the following describes the ?lock-tight? sequence: 1. only locked blocks can be ?locked-tight? by the lock - tight block command. 2. command sequence: l ock - tight block command (01h) 3. unlocking multi area is not available 4. lock-tight blocks revert to the locked state at cold/warm reset. 19.9.4 memory configuration examples table 19-30 shows nfc pin configurations for various nand flash devices. figure 19-40 and figure 19-41 show memory connection for vari ous 8-bit and 16-bit configuration. note the nfc can support high speed (hs) nand flash by supplying higher frequencies (up to 50 mhz) to the flash clock input. table 19-30. examples for nfc pin configuration for selected memory devices device boot nfc_fms nf8boot nf16boot nf_16bit_sel samsung k9f5608 (32m x 8-bit) page size is 528 bytes. no 0 1 1 0 yes 0 0 1 x samsung k9f5616 (16m x 16bit) page size is 528 bytes. no 0 1 1 1 yes 0 1 0 x samsung k9f1g08 (128m x 8-bit) page size is 2112 bytes. no 1 1 1 0 yes 1 0 1 x samsung k9f1g16 (64m x 16bit) page size is 2112 bytes. no 1 1 1 1 yes 1 1 0 x nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-40 freescale semiconductor figure 19-40. 256-mbit (32 mbit x 8 bit) nand flash connection diagram ce cle i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 32 m x 8 nand flash ale re we wp r/b vccq vcc vss gnd vcc gnd ipp_nfc_ce_out ipp_nfc_cle_out ipp_nfc_ale_out ipp_nfc_re_out ipp_nfc_we_out ipp_nfc_wp_out ipp_nfc_rb_in n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. nfce nfcle nfale nfre nfwe nfwp nfrb ipp_nfc_read_data_in[15] ipp_nfc_read_data_in[14] ipp_nfc_read_data_in[13] ipp_nfc_read_data_in[12] ipp_nfc_read_data_in[11] ipp_nfc_read_data_in[10] ipp_nfc_read_data_in[9] ipp_nfc_read_data_in[8] ipp_nfc_read_data_out[15] ipp_nfc_read_data_out[14] ipp_nfc_read_data_out[13] ipp_nfc_read_data_out[12] ipp_nfc_read_data_out[11] ipp_nfc_read_data_out[10] ipp_nfc_read_data_out[9] ipp_nfc_read_data_out[8] 8 bits of the adress bus nfio7 nfio6 nfio5 nfio4 nfio3 nfio2 nfio1 nfio0 ipp_nfc_read_data_in[7] ipp_nfc_read_data_in[6] ipp_nfc_read_data_in[5] ipp_nfc_read_data_in[4] ipp_nfc_read_data_in[3] ipp_nfc_read_data_in[2] ipp_nfc_read_data_in[1] ipp_nfc_read_data_in[0] ipp_nfc_read_data_out[7] ipp_nfc_read_data_out[6] ipp_nfc_read_data_out[5] ipp_nfc_read_data_out[4] ipp_nfc_read_data_out[3] ipp_nfc_read_data_out[2] ipp_nfc_read_data_out[1] ipp_nfc_read_data_out[0] a25_nfio15 a24_nfio14 a23_nfio13 a22_nfio12 a21_nfio11 a15_nfio10 a14_nfio9 a13nfio8 nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 19-41 figure 19-41. 256 mbit (16 m x 16 bit) nand flash connection diagram ce cle i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 16m x 16 nand flash ale re we wp r/b vccq vcc vss gnd vcc gnd ipp_nfc_ce_out ipp_nfc_cle_out ipp_nfc_ale_out ipp_nfc_re_out ipp_nfc_we_out ipp_nfc_wp_out ipp_nfc_rb_in nfce nfcle nfale nfre nfwe nfwp nfrb ipp_nfc_read_data_in[15] ipp_nfc_read_data_in[14] ipp_nfc_read_data_in[13] ipp_nfc_read_data_in[12] ipp_nfc_read_data_in[11] ipp_nfc_read_data_in[10] ipp_nfc_read_data_in[9] ipp_nfc_read_data_in[8] ipp_nfc_read_data_out[15] ipp_nfc_read_data_out[14] ipp_nfc_read_data_out[13] ipp_nfc_read_data_out[12] ipp_nfc_read_data_out[11] ipp_nfc_read_data_out[10] ipp_nfc_read_data_out[9] ipp_nfc_read_data_out[8] 8 bits of the adress bus nfio7 nfio6 nfio5 nfio4 nfio3 nfio2 nfio1 nfio0 ipp_nfc_read_data_in[7] ipp_nfc_read_data_in[6] ipp_nfc_read_data_in[5] ipp_nfc_read_data_in[4] ipp_nfc_read_data_in[3] ipp_nfc_read_data_in[2] ipp_nfc_read_data_in[1] ipp_nfc_read_data_in[0] ipp_nfc_read_data_out[7] ipp_nfc_read_data_out[6] ipp_nfc_read_data_out[5] ipp_nfc_read_data_out[4] ipp_nfc_read_data_out[3] ipp_nfc_read_data_out[2] ipp_nfc_read_data_out[1] ipp_nfc_read_data_out[0] a25_nfio15 a24_nfio14 a23_nfio13 a22_nfio12 a21_nfio11 a15_nfio10 a14_nfio9 a13nfio8 i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 nand flash controller (nfc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 19-42 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-1 chapter 20 personal computer memory card international association (pcmcia) controller this chapter describes the personal computer me mory card international association (pcmcia) controller for the i.mx27 processor. the association standard is pcmcia 2.1, which defines the use of memory and i/o devices as insertable and exchange able peripherals for personal computers or pdas. examples of these types of devices include compact flash and wlan adapters. 20.1 overview the pcmcia host adapter module provides the control logic for pcmcia socket interfaces, and requires some additional external analog power switching l ogic and buffering. the additional external buffers allow the pcmcia host adapter module to support one pcmcia socket. figure 20-1 shows the pcmcia controller block diagram. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-2 freescale semiconductor figure 20-1. pcmcia controller interface block diagram static signals interface ahb bus int gen pcmcia controller pc card a[25:0] d[15:0] oe we iord iowr reg wait ce1 ce2 rdy/bsy iois16 /wp bvd1 bvd2 cd1 cd2 reset pull up to chip vcc pull up to card vcc r/w poe buffer with oe transparent latch transceiver vs1 vs2 interrupts endianness debug_signals pcmcia_access pwron card power circuit vcc/vpp ahb interface card interface access error personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-3 20.2 features the pcmcia controller includes the following features: ? a host adapter interface fully compliant with th e pcmcia standard release 2.1 (pc card -16). ? supports one pcmcia socket ? supports hot-insertion ? supports card detection ? provides mappings to common memory space, attribute memory space, and i/o space. each space is up to 64 mbyte in size. ? supports 5 memory windows ? generates a single interrupt to the arm9 core ? provides fully programmable pc card access timing ? handles interrupts from the card ? the pcmcia controller is part of the emi comp lex and shares its pins with the eim, sdramc, and nand flash controller. ? supports ata disk emulation 20.3 external signal description 20.3.1 detailed signal descriptions table 20-2 shows the pcmcia signal descriptions for the pins that are used to control the pcmcia interface. table 20-2. pcmcia signal descriptions signal in/out description standard pins a[25:0] output address bus. these address bus output lines allows direct addressing of up to 64 mbytes of linear memory on the pcmcia card. d[15:0] i/o data bus. bidirectional. pcmcia socket data i/o pins. ce1 , ce2 output card enable. when a pcmcia access is performed, ce1 enables even bytes, ce2 enables odd bytes. see also section 20.5.9, ?data and control signals relations ? and table 20-20 . oe output output enable. during pcmcia accesses, oe is used to drive memory read data from a pc card in a pcmcia socket. we output write enable. program during pcmcia access, we is used to latch memory write data to the pc card in a pcmcia socket. can also be used as the programming strobe for pc cards using programmable memory technologies. reg output register accesses attribute memory select. when reg is asserted during pcmcia access, card access is limited to attribute memory when a memory access occurs (we or oe are asserted) and to i/o ports when i/o access occurs (iord or iowr are asserted). if reg is asserted, accesses to common memory are blocked. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-4 freescale semiconductor iord output i/o read. this output goes active (low) for i/o reads from the socket. this signal is asserted together with reg and it is used to read data from the pc card i/o space. iord is valid only when reg and either ce1 or ce2 signals are also asserted. iowr output i/o write. this output goes active (low) for i/o write to the socket. asserted with reg during pcmcia accesses, used to latch data into the pc cards i/o space. iowr is valid only when reg and either ce1 and ce2 signals are also asserted. wait input extend bus cycle. input. asserted by the pc card to delay completion of the pending memory or i/o cycle. iois16 /wp input i/o port is 16-bits. when the card and its socket are programmed for i/o interface operation, this signal is used as iois16 and must be asserted by the pc card when the address on the bus corresponds to an address on the pc card and the i/o port being addressed supports 16-bit accesses. if the i/o region in which the address resides is programmed as 8-bit wide iois16 is ignored. write protect. when the card and socket are programmed for memory interface operation, this signal is used as wp. it reflects the state of the write protect of the pc card. the pc card must assert wp when the card switch is enabled. it must be negated when the switch is disabled. for a pc card that is writable without a switch, wp must be connected to ground.if the pc card is permanently write-protected, wp must be connected to vcc. vs1 , vs2 input voltage sense. input. generated by the card to notify the socket of the card?s cis vcc requirements. cd1 , cd2 input card detect. provide proper detection of card insertion. they must be connected to ground internally on the pc card, thus, these signals are forced low when a card is placed on the socket. these signals must be pulled up to system vcc to allow card detection to function when the card socket is powered down. bvd1/stschg , bvd2/spkr input these two lines can be used for battery voltage detection or status change/speaker. battery voltage detect. when the card and its socket are programmed for memory interface operation, these signals are generated by the pc card with on board battery to report the battery condition. see table 20-3 for a description of the logical combinations representing battery condition. status change. when the card is in i/o interface operation, bvd1 is used as status change and is generated by the i/o pc card. status change must be held negated when the ?signal on change? bit and the ?change? bit in the card status register are either or both zero. stschg must be asserted when both bits = 1. speaker. input. when the card is in i/o interface operation bvd2 is used as audio digital waveform. a card that does not this capability should drive spkr high. ready/ireq input ready. when the card and its socket are programmed for memory interface operation, this signal is used as rdy/bsy and must be asserted by a pc card to indicate that a pc card is busy processing a previous write command. when the card and its socket are programmed for i/o interface operation, this signal is used as ireq and must be asserted by a pc card to indicate that a device on the pc card requires service by host software. must be held negated when no interrupt is requested. reset output card reset. output. provided to clear the card?s configuration option register, thus placing the card in its default (memory only interface) state and beginning an additional card initialization. reset signal has inverted polarity when in trueide mode. see also section 20.5.10, ?true ide mode access .? table 20-2. pcmcia signal descriptions (continued) signal in/out description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-5 table 20-3 provides descriptions for the bvd1 and bvd2 signals. pcmcia controller module pins poweron input power is on. the card supply circuitry can use this signal as an interrupt to notify when the card?s power supply reaches the full required voltage. r/w output external transceiver direction. negated during read cycles and asserted during write. poe output pcmcia buffers output enable. an output line reflecting the value of pgcr[poe] bit. used to three-state control signals and to latch the address. see figure 20-1 for a simplified block diagram. spkrout output speaker output. provides a digital audio waveform to be driven to the system?s speaker. this signal is connected directly to the spkr input. endianness input endianness control. input. this input pin defines the endianness mode of the module. ?1? is big endian. this module should be tied high or low. see section 20.5.13, ?endianness support .? pcmcia_access output this output signal is used to indicate that a valid access to the card is performed. this signal is used by the emi muxing to select the pcmcia_if port and drive it to the pins. ipi_int_pcmcia output this is the interrupt line from the pcmcia_if module. this signal is a logical or of all interrupts generated by the pcmcia_if. ipi_int_vs1 output this interrupt is generated if the voltage sense #1 input signal from the card has changed. ipi_int_vs2 output this interrupt is generated if the voltage sense #2 input signal from the card has changed. ipi_int_wp output this interrupt is generated if the write protect input signal from the card has changed. ipi_int_cd1 output this interrupt is generated if the card detect #1 input signal from the card has changed. ipi_int_cd2 output this interrupt is generated if the card detect #2 input signal from the card has changed. ipi_int_bvd1 output this interrupt is generated if the battery voltage detect #1 input signal from the card has changed. ipi_int_bvd2 output this interrupt is generated if the battery voltage detect #2 input signal from the card has changed. ipi_int_rdy_l output this interrupt is generated if rdy/ireq pin is low. ipi_int_rdy_h output this interrupt is generated if rdy/ireq pin is high. ipi_int_rdy_r output this interrupt is generated if a rising edge was detected on the rdy/ireq pin. ipi_int_rdy_f output this interrupt is generated if a falling edge was detected on the rdy/ireq pin. ipi_int_poweron output this interrupt is generated if the poweron input signal from the card has changed ipi_int_sts output this status change interrupt is a logic and of the following: ipi_int_vs1 , ipi_int_vs2 , ipi_int_wp , ipi_int_cd1 , ipi_int_cd2 , ipi_int_bvd1 , ipi_int_bvd2 , ipi_int_poweron . ipi_int_ireq output this interrupt line is a logic and of the following: ipi_int_rdy_l , ipi_int_rdy_h , ipi_int_rdy_r , ipi_int_rdy_f. ipi_int_err output this interrupt is generated following an error detected by the pcmcia controller. see section 20.5.4.1, ?error interrupt conditions ? for detailed description of error cases. table 20-2. pcmcia signal descriptions (continued) signal in/out description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-6 freescale semiconductor 20.4 memory map and register definition table 20-4 shows the memory map of the pcmcia controller. table 20-3. bvd1 and bvd2 descriptions bvd1 bvd2 description 1 1 battery is in good condition 1 0 battery is in warning condition and should be replaced, although data integrity on the card is assured. 0 x battery is in no longer serviceable and data is lost. table 20-4. pcmcia controller memory map address register access reset value section/page 0xd800_4000 (pipr) pcmcia input pins register read only 0x0000_00?? 20.4.1.1/20-9 0xd800_4004 (pscr) pcmcia status changed register read/write 0x0000_0000 20.4.1.2/20-11 0xd800_4008 (per) pcmcia enable register read/write 0x0000_1018 20.4.1.3/20-12 0xd800_400c (pbr0) pcmcia base register 0 read/write 0x0000_0000 20.4.1.4/20-14 0xd800_4010 (pbr1) pcmcia base register 1 read/write 0x0000_0000 20.4.1.4/20-14 0xd800_4014 (pbr2) pcmcia base register 2 read/write 0x0000_0000 20.4.1.4/20-14 0xd800_4018 (pbr3) pcmcia base register 3 read/write 0x0000_0000 20.4.1.4/20-14 0xd800_401c (pbr4) pcmcia base register 4 read/write 0x0000_0000 20.4.1.4/20-14 0xd800_4028 (por0) pcmcia option register 0 read/write 0x0000_0000 20.4.1.5/20-15 0xd800_402c (por1) pcmcia option register 1 read/write 0x0000_0000 20.4.1.5/20-15 0xd800_4030 (por2) pcmcia option register 2 read/write 0x0000_0000 20.4.1.5/20-15 0xd800_4034 (por3) pcmcia option register 3 read/write 0x0000_0000 20.4.1.5/20-15 0xd800_4038 (por4) pcmcia option register 4 read/write 0x0000_0000 20.4.1.5/20-15 0xd800_4044 (pofr0) pcmcia offset register 0 read/write 0x0000_0000 20.4.1.6/20-19 personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-7 20.4.1 register summary table 20-2 shows the key to the register fields, and table 20-5 shows the register figure conventions. 0xd800_4048 (pofr1) pcmcia offset register 1 read/write 0x0000_0000 20.4.1.6/20-19 0xd800_404c (pofr2) pcmcia offset register 2 read/write 0x0000_0000 20.4.1.6/20-19 0xd800_4050 (pofr3) pcmcia offset register 3 read/write 0x0000_0000 20.4.1.6/20-19 0xd800_4054 (pofr4) pcmcia offset register 4 read/write 0x0000_0000 20.4.1.6/20-19 0xd800_4060 (pgcr) pcmcia general control register read/write 0x0000_0008 20.4.1.7/20-20 0xd800_4064 (pgsr) pcmcia general status register read/write 0x0000_0000 20.4.1.8/20-21 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 20-2. key to register fields table 20-5. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. table 20-4. pcmcia controller memory map (continued) address register access reset value section/page personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-8 freescale semiconductor table 20-6 shows the pcmcia register summary. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 20-6. pcmcia controller register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109 8 7 65 4 3210 0xd800_4000 (pipr) r000 0 0000000 0 0000 w r 000 0 0 0 0 po we ron t rdy bvd 2 bvd 1 cd wp vs w 0xd800_4004 (pscr) r000 0 0000000 0 0000 w r 000 0 po wc rdy r rdy f rdy h rdy l bvd c2 bvd c1 cdc2 cd c1 wp c vsc 2 vsc 1 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0xd800_4008 (per) r000 0 0000000 0 0000 w r0 0 0 erri nten po we ron en rdy re rdy fe rdy he rdy le bvd e2 bvd e1 cde2 cde 1 wp e vse 2 vse 1 w 0xd800_400c (pbr0) 0xd800_4010 (pbr1) 0xd800_4014 (pbr2) 0xd800_4018 (pbr3) 0xd800_401c (pbr4) r0 0 0 0 0 0 pba[25:16] w r pba[15:0] w table 20-5. register figure conventions (continued) convention description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-9 20.4.1.1 pcmcia input pins register (pipr) this register indicates the status of inputs from the pcmcia card to the host: battery voltage detect, card detect, ready, voltage sense, and write protect status (bvd, cd, rdy, vs, wp). pipr is a read-only register. the register should be clocked with a gated clock. this clock is active only when trying to access the peripheral. when accessing this register, a 2-wait state is added by the pcmcia controller. the reset values in figure 20-3 are the reset values of the pipr flip-flops. the actual data read reflects the value to the pcmcia controller. table 20-7 provides the register?s field descriptions. 0xd800_4028 (por0) 0xd800_402c (por1) 0xd800_4030 (por2) 0xd800_4034 (por3) 0xd800_4038 (por4) r 00 pv wpe n wp prs pps psl[6:0] pss t[5] w r psst[4:0] psht[5:0] 0 bsize w 0xd800_4044 (pofr0) 0xd800_4048 (pofr1) 0xd800_404c (pofr2) 0xd800_4050 (pofr3) 0xd800_4054 (pofr4) r0 0 0 0 0 0 pofa[25:16] w r pofa[15:0] w 0xd800_4060 (pgcr) r000 0 0000000 0 0000 w r000 0 0000000 0 lpm en spk ren poe res et w 0xd800_4064 (pgsr) r000 0 0000000 0 0000 w r000 0 0000000nwin e lpe se cde wp e w w1c w1c w1c w1c w1c table 20-6. pcmcia controller register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109 8 7 65 4 3210 personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-10 freescale semiconductor 0xd800_4000 (pipr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r 0000000 pow ero n rdy bvd2 bvd1 cd wp vs w reset0 0 0 0 0 0 0 0 ???????? figure 20-3. pcmcia input pins register (pipr) table 20-7. pipr field descriptions field description 31?9 reserved. 8 poweron power is on. this bit indicates the status of the power signal from the card. 0 card indicates that it did not reach its power supply requirements. 1 card indicates power is on. 7 rdy rdy/bsy /ireq . when the card and its socket are in memory interface operation, this bit functions as rdy/bsy indicating that the card is busy processing a previous write command. when the card and its socket are in i/o interface operation, this bit functions as ireq indicating that a device on the pc card requires service by host software. this interrupt could be either level or pulse and can have either high or low polarity. this data can be read in the cis of the card itself. 0 pc card is busy processing a previous command or performing initialization. 1 pc card is ready to accept a new data-transfer command. 6 bvd2 battery voltage detect 2/spkr in. when the card and its socket are in memory interface mode, this bit reflects the bvd2 signal. for details about settings, see ta bl e 2 0 - 3 . when the card and its socket are in i/o mode, this bit is used as spkr in (speaker in) for a binary audio signal, an optional signal which is available only when the card and the socket have been configured for the i/o interface. 5 bvd1 battery voltage detect 1/stschg in. when the card and its socket are in memory interface mode, this bit reflects the bvd1 signal. for details, see ta bl e 2 0 - 3 . when the card and its socket are in i/o mode, this bit is used as stschg (status change) indicator. 0 status has not changed. 1 status has changed. note: to find out the exact signals that changed value, the status change register of the card itself should be read. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-11 20.4.1.2 pcmcia status change register (pscr) each bit in the pscr register is set any time a change in the signal it monitors occurs. the status is cleared using a ?write 1 to clear? operation on the register. the contents of pscr, shown in figure 20-4 , are logically anded with the per register to generate a pcmcia interrupt. the register should be clocked with a gated clock. this clock is active only when trying to access the peripheral. when accessing this register, two wait states are added by the pcmcia. the inputs to the module are sampled twice before being read, to avoid me ta-stability. this is done in spite of the fact that interrupts are generated even when the clock is off. the bit assignments for the pscr register are shown in figure 20-4 . the bit field descriptions are provided in table 20-8 . each of the bits in table 20-8 (excluding rdyl and rdyhare) set (=1) when a change occurs in its corresponding parameter. it is zeroed on system reset. rdyl and rdyh are level sensitive and therefore, reflect the value of the rdy pin and have no reset value. 4?3 cd card detect 1 and card detect 2. card detect 1 and card detect 2 bits indicate a proper detection of card insertion. when both bits are ?0?, the card is inserted properly. 00 card is inserted properly. 01 card is inserted improperly. 11 card is inserted improperly. 11 card is not inserted. these bits are asynchronous. 2 wp write protect. this bit reflects the state of the write protect switch on the pc card. 0 write protect switch is disabled. 1 write protect switch is enabled. 1?0 vs voltage sensor. vs bits notify the host of the card?s card information structure (cis) vcc requirements. this data can be used by the host to control external voltage transceiver. for details see the pcmica pccard standard. 0xd800_4004 (pscr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000 0 0 0 0 0 0 0 0 0 0 0 0 1514131211109876543210 r 0000powcrdyrrdyfrdyhrdyl bvdc 2 bvdc 1 cdc2 cdc1 wpc vsc2 vsc1 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000 0 0 0??0 0 0 0 0 0 0 figure 20-4. pcmcia status change register (pscr) table 20-7. pipr field descriptions (continued) field description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-12 freescale semiconductor 20.4.1.3 pcmcia enable register (per) setting a bit in per, shown in figure 20-5 , enables the corresponding interrupt. when accessing this register, one wait state will be added by the pcmcia. table 20-9 shows the register?s field descriptions. table 20-8. pscr field descriptions field description 31?12 reserved. 11 powc poweron signal changed. 0 no change has occurred in the poweron signal since system reset. 1 a change has occurred in the poweron signal since system reset. 10 rdyr rdy/ireq pin rising edge detect. device and socket positive edge interrupt. 0 no rising edge has occurred in rdy since system reset. 1 a rising edge occurred in rdy since system reset. 9 rdyf rdy/ireq pin falling edge detect. device and socket negative edge interrupt. 0 no falling edge has occurred in rdy since system reset. 1 a falling edge occurred in rdy since system reset. 8 rdyh this bit reflects value of rdy signal. rdy/ireq pin is high indicating a device and socket high level interrupt. 7 rdyl rdy/ireq pin is low. device and socket loveless interrupt. this bit is the inverted value of rdy signal 6 bvdc2 battery voltage 2/spkr in changed. 0 no change has occurred in battery voltage #2 or spkr since system reset. 1 a change has occurred in battery voltage #2 or spkr since system reset. 5 bvdc1 battery voltage 1/stschg changed. 0 no change has occurred in battery voltage #1 since system reset. 1 a change has occurred in battery voltage #1 since system reset. 4 cdc2 card detect 2 hanged. 0 no change has occurred in card detect #2 since system reset. 1 a change has occurred in card detect #2 since system reset. 3 cdc1 card detect 1 changed. 0 no change has occurred in card detect #1 since system reset. 1 a change has occurred in card detect #1 since system reset. 2 wpc write protect changed. 0 no change has occurred in the write protect status since system reset. 1 a change has occurred in the write protect status since system reset. 1 vsc2 voltage sense2 changed. 0 no change has occurred in voltage sensor #2 since system reset. 1 a change has occurred in voltage sensor #2 since system reset. 0 vsc1 voltage sense1 changed. 0 no change has occurred in voltage sensor #1 since system reset. 1 a change has occurred in voltage sensor #1 since system reset. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-13 0xd800_4008 (per) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0 0 0 erri nten pow ero nen rdyr e rdyf e rdyh e rdyl e bvde 2 bvde 1 cde2 cde1 wpe vse2 vse1 w reset0001000000011000 figure 20-5. pcmcia enable register (per) table 20-9. per field descriptions field description 31?13 reserved. 12 errinten error interrupt enable. setting this bit enables the interrupt as a result of an error signal. 0 interrupt is disabled. 1 interrupt is enabled. note that the default is to enable the interrupt. 11 poweronen power is on interrupt enable. setting this bit enables the interrupt as a result of any power on signal change. 0 interrupt is disabled. 1 interrupt is enabled. 10 rdyre rdy/ireq pin rising edge interrupt enable. 0 interrupt is disabled. 1 interrupt is enabled. 9 rdyfe rdy/ireq pin falling edge interrupt enable. 0 interrupt is disabled. 1 interrupt is enabled. 8 rdyhe rdy/ireq pin is high level interrupt enable. 0 interrupt is disabled. 1 interrupt is enabled. 7 rdyle rdy/ireq pin is low level interrupt enable. 0 interrupt is disabled. 1 interrupt is enabled. 6 bvde2 battery voltage 2/spkr in interrupt enable. setting this bit enables the interrupt as a result of any signal change from battery voltage sensor #2 or from the spkr in signal. 0 interrupt is disabled. 1 interrupt is enabled. 5 bvde1 battery voltage 1/stschg interrupt enable. setting this bit enables the interrupt as a result of any signal change from the battery voltage sensor #1. 0 interrupt is disabled. 1 interrupt is enabled. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-14 freescale semiconductor 20.4.1.4 pcmcia base registers 0?4 (pbr0?pbr4) this is compared to the address bus to determine if a pcmcia window is being accessed by an internal bus master. pba is used in conjunction with por[bsi ze]. when accessing this register, 1-wait state will be added by the pcmcia. the field assignments for this register are shown in figure 20-6 . table 20-10 shows the register?s field descriptions. 4 cde2 card detect 2 interrupt enable. setting this bit enables the interrupt as a result of any signal change from card detect #2. note: the default setting enables the interrupt. 0 interrupt is disabled. 1 interrupt is enabled. 3 cde1 card detect 1 interrupt enable. setting this bit enables the interrupt as a result of any signal change from card detect #1 note: the default setting enables the interrupt. 0 interrupt is disabled. 1 interrupt is enabled. 2 wpe write protect interrupt enable. setting this bit enables the interrupt as a result of any signal change in the write protect status. 0 interrupt is disabled. 1 interrupt is enabled. 1 vse2 voltage sense2 interrupt enable. setting this bit enables the interrupt as a result of any signal change from voltage sensor #2. 0 interrupt is disabled. 1 interrupt is enabled. 0 vse1 voltage sense1 interrupt enable. setting this bit enables the interrupt as a result of any signal change from voltage sensor #1. 0 interrupt is disabled. 1 interrupt is enabled. table 20-9. per field descriptions (continued) field description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-15 20.4.1.5 pcmcia option registers 0?4 (por0?por4) the por registers shown in figure 20-7 handle time manipulation, provide the address mask for the bank size, and define the region, write pr otection, and validation. when accessi ng this register 1-wait state will be added by the pcmcia. table 20-11 shows the register?s field descriptions. 0xd800_400c (pbr0) 0xd800_4010 (pbr1) 0xd800_4014 (pbr2) 0xd800_4018 (pbr3) 0xd800_401c (pbr4) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 pba[25:16] w reset0000000000000000 1514131211109876543210 r pba[15:0] w reset0000000000000000 figure 20-6. pcmcia base registers 0?4 (pbr0?pbr4) table 20-10. pbr0?pbr4 field descriptions field description 31?26 reserved. 25?0 pba pcmcia base address. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-16 freescale semiconductor 0xd800_4028 (por0) 0xd800_402c (por1) 0xd800_4030 (por2) 0xd800_4034 (por3) 0xd800_4038 (por4) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 pv wpen wp prs pps psl[6:0] psst[5] w reset00 0 0 0 00 0 0000 0 0 0 0 1514 13 12 11109 8 7654 3 2 1 0 r psst[4:0] psht[5:0] bsize w reset00 0 0 0 00 0 0000 0 0 0 0 figure 20-7. pcmcia option registers 0?4 (por0?por4) table 20-11. por0?por4 field descriptions field description 31?30 reserved. 29 pv pcmcia valid. defines whether the contents of the pbr and por pair are valid (window enable). see also ta b l e 2 0 - 1 3 . 0 this bank is invalid. 1 this bank is valid. 28 wpen pcmcia write protect input enable. this bit is the write protect input signal enable bit, controlled by software. when this bit is cleared, the wp input to the pcmcia module is ignored. to see the relationship between this bit, the wp bit, and the wp signal coming from the card refer to section 20.5.7, ?write protect .? 0 write protect input (wp) signal is ignored. 1 write protect (wp) input signal is enabled. 27 wp pcmcia write protect enable this bit is the write protect enable bit controlled by software. to see the relationship between this bit, the wpen bit, and the wp signal coming from the card refer to section 20.5.7, ?write protect .? 0 not write protected. 1 write protected. attempting to write to this window causes an interrupt. 26?25 prs pcmcia region select. 00 common memory space. 01 trueide mode. 10 attribute memory space. 11 i/o space. 24 pps pcmcia port size. specifies the port size of the pcmcia window. refer to section 20.5.8, ?16-bit/8-bit support ? for more details. 0 16-bit port size 18-bit port size personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-17 23?17 psl pcmcia strobe length. determines the number of cycles the strobe is asserted during a pcmcia access for this window and, thus, it is the main parameter for determining cycle length. the cycle may be lengthened by asserting wait. note: to sample the wait signal it must be synchronized by two ff. this means that if the system must rely on the wait signal, the psl should be calculated as the maximum valid time on wait plus two. for example, suppose we have a 100 mhz clock (one period is therefore 10 ns) and the card specification says that the time from we/oe low to wait valid is 70 ns. the psl value should be at least: (70 ns/10 ns)+2=9. 0000000 strobe asserted 128 clocks cycles. 0000001 strobe asserted 1 clocks cycles. 0000010 strobe asserted 2 clocks cycles. ... 1111111 strobe asserted 127 clocks cycles. 16?11 psst pcmcia strobe set up time (address to strobe assertion). specifies when iowr or we is asserted during a pcmcia write access or when iord or oe are asserted during a pcmcia read access handled by the pcmcia controller. this helps meet address/setup time requirements for slow memories and peripherals. 000000 reserved. 000001 address to strobe assertion 1 clock. 000010 address to strobe assertion 2 clock. ... 111111 address to strobe assertion 63 clock. note: using psst=000001 is not allowed when wpen bit is set since the synchronization of wp signal takes 2 clocks. 10?5 psht pcmcia strobe hold time (strobe negation to address negation).specifies when iowr or we are negated during a pcmcia write or when iord or oe are negated during a pcmcia read. used to meet address/data hold time requirements for slow memories and peripherals. 000000 strobe negation to address change 0 clock. 000001 strobe negation to address change 1 clock. ... 111111 strobe negation to address change 63 clock. 4?0 bsize pcmcia bank size. determines the address mask field of each por and provides masking for any of the corresponding bits in the associated pbr. the bank size corresponds to values of this bit field as indicated in ta b l e 2 0 - 1 2 . bsize determines not only the bank size, but also how the address is compared with pbr[pba]. if bsize is a virtual field, the mask is defined as shown in table 20-13 . addr, and mask pba, and mask for a valid pcmcia access; otherwise, it is not a valid pcmcia access. table 20-12. bsize values value meaning value meaning value meaning 00000 1 byte 01111 1 kbyte 11110 1 mbyte 00001 2 byte 01110 2 kbyte 11111 2 mbyte 00011 4 byte 01010 4kbyte 11101 4 mbyte 00010 8 byte 01011 8 kbyte 11100 8 mbyte 00110 16 byte 01001 16 kbyte 10100 16 mbyte 00111 32 byte 01000 32 kbyte 10101 32 mbyte table 20-11. por0?por4 field descriptions (continued) field description personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-18 freescale semiconductor note bsize determines not only the bank si ze, but also how the address is compared with pbr[pba]. according to the virtual field, mask as defined as shown on table 20-13 . 00101 64 byte 11000 64 kbyte 10111 64 mbyte 00100 128 byte 11001 128 kbyte 01100 256 byte 11011 256 kbyte 01101 512 byte 11010 512 kbyte table 20-13. bsize mask bsize mask 00000 11111111111111111111111111111111 00001 11111111111111111111111111111110 00011 11111111111111111111111111111100 00010 11111111111111111111111111111000 00110 11111111111111111111111111110000 00111 11111111111111111111111111100000 00101 11111111111111111111111111000000 00100 11111111111111111111111110000000 01100 11111111111111111111111100000000 01101 11111111111111111111111000000000 01111 11111111111111111111110000000000 01110 11111111111111111111100000000000 01010 11111111111111111111000000000000 01011 11111111111111111110000000000000 01001 11111111111111111100000000000000 01000 11111111111111111000000000000000 11000 11111111111111110000000000000000 11001 11111111111111100000000000000000 11011 11111111111111000000000000000000 11010 11111111111110000000000000000000 11110 11111111111100000000000000000000 11111 11111111111000000000000000000000 table 20-12. bsize values (continued) value meaning value meaning value meaning personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-19 20.4.1.6 pcmcia offset registers 0?4 (pofr0?pofr4) the offset address of the window. pba is used in c onjunction with por[bsize]. the external address is ext_addr= pofa + haddr and mask. when accessi ng this register 1-wait state is added by the pcmcia/cf controller. the field definiti on of the pofrx registers is shown in figure 20-8 . table 20-14 shows the field descriptions. 11101 11111111110000000000000000000000 11100 11111111100000000000000000000000 10100 11111111000000000000000000000000 10101 11111110000000000000000000000000 10111 11111100000000000000000000000000 0xd800_4044 (pofr0) 0xd800_4048 (pofr1) 0xd800_404c (pofr2) 0xd800_4050 (pofr3) 0xd800_4054 (pofr4) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 pofa[25:16] w reset0000000000000000 1514131211109876543210 r pofa[15:0] w reset0000000000000000 figure 20-8. pcmcia offset registers 0?4 (pofr0?pofr4) table 20-14. pofr0?pofr4 field descriptions field description 31?26 reserved. 25?0 pofa pcmcia offset address. the offset address of the window. pofa is used in conjunction with por[bsize]. the external address is ext_addr= pofa + haddr and mask . table 20-13. bsize mask (continued) bsize mask personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-20 freescale semiconductor example 20-1. calculating offset address if: haddr[25:0] = 0x0000263, mask = 0x3ffffc0 pofa = 0x0000161 then: ext_addr = 0x0000161 + 0x0000263 & (0x3ffffc0) = 0x0000161 + 0x0000023 = 0x0000184 20.4.1.7 pcmcia general control register (pgcr) this is the general control register for the pcmcia controller. when accessing this register, 1-wait state is added by the pcmcia controller. field definitions of the pofrx registers are shown in figure 20-9 . table 20-15 shows the field descriptions. 0xd800_4060 (pgcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 0 0 0 0 w reset000000000000 0 0 0 0 151413121110987654 3 2 1 0 r000000000000 lpmen spkr en poe reset w reset000000000000 1 0 0 0 figure 20-9. pcmcia general control register (pgcr) table 20-15. pgcr field descriptions field description 31?4 reserved. 3 lpmen low power mode enable. this bit puts the module into low power mode. in this case external memory accesses are disabled. the reset value is ?1? (low power mode). 0 normal power mode. 1 low power mode. 2 spkren spkrout routing enable. this bit enables the routing of spkrin to spkrout. 0 routing disabled. 1 routing enabled. 1 poe card output enable. this bit enables the poe signal, used to three-state the external buffers. the poe signal will toggle as follows: po e (signal) pgcr[poe]&pcmcia_access (signal). 0 poe signal is disabled. 1 poe signal is enabled. 0 reset card reset. this bit provides a software reset to the card. this bit is not self clearing, software must modify this bit to take the card out of reset. 0 card is not in reset. 1 card is in reset. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-21 20.4.1.8 pcmcia general status register (pgsr) this is a general status register. if an error interrupt was generated to the host, the host can access this register to find out what caused the error interrupt. all the bits in this register are cleared by writing ?1? to the appropriate bit. when accessing this register, 1- wait state is added by the pcmcia controller. field definition of the pofrx registers are shown in figure 20-10 . table 20-16 shows the field descriptions. 0xd800_4064 (pgsr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000000000 nwin e lpe se cde wpe w reset0000000000000000 figure 20-10. pcmcia general status register (pgsr) table 20-16. pgsr field descriptions field description 31?5 reserved. 4 nwine no window error. attempt to access a card address to an address that is not mapped by any window. 0 no attempt to access a card address to an address that is not mapped by any window since the last system reset was made. 1 an attempt to access a card address to an address that is not mapped by any window since the last system reset was made. 3 lpe low power error. attempt to access a card when in low power mode. 0 no attempt to access a card when in low power mode was made since the last system reset 1 an attempt to access a card when in low power mode was made since the last system reset 2 se size error. a 16-bit access to an 8-bit card was made. 0 no 16-bit access to an 8-bit card was made since the last system reset. 1 a 16-bit access to an 8-bit card was made since the last system reset 1 cde card detect error. attempt to access a card when the card is not inserted. 0 no attempt to access a card when the card was not inserted has been made since last system reset. 1 an attempt to access a card when the card was not inserted has been made since last system reset. in addition, once set no accesses are enabled until it is cleared (even if a card was inserted). 0 wpe write protect error. attempt to write to a write protected address. 0 no attempt was made to write to a protected address since the last system reset. 1 an attempt was made to write to a protected address since the last system reset. personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-22 freescale semiconductor 20.5 functional description this section describes the operation of memory and i/o cards, interrupt detection and handling, power control, and reset. 20.5.1 modes of operation the following are the pcmcia modes of operation: ? memory-only card mode ? i/o card mode ? trueide mode ? low power mode 20.5.2 windowing capabilities the pcmcia i/f provides five memory windows. the user can define each memory window as a common memory space, i/o space or attribute memory space. this is done by programming the region select bits (prs) bits in each por register for each window. configuring a window is done by programming the window?s base address (pba bits in the corresponding pbr register), and by programming the bank size (bsize bits in the corresponding por register). 20.5.2.1 window overlapping window overlapping is not allowed. the pcmcia i/f does not indicate to the cpu about window overlapping, software responsible for this. havi ng overlapping windows will cau se unexpected results. 20.5.3 wait signal the wait signal is asserted by the pc card to delay co mpletion of the pending cycle. the access must terminate before the bus time out monitor generates a bus time error. 20.5.4 interrupts there are 14 interrupt sources in the pcmcia controll er. the pcmcia controller generates an interrupt signal for each interrupt source. in addition, the pcmc ia generates a signal which is a locator of all the possible interrupts. it is up to the system?s integrator to decide which signal(s) to connect to the system?s interrupt controller module. the pcmcia?s interrupt sources are described in table 20-17 . table 20-17. pcmcia i/f interrupt sources interrupt enabled with comments vs1 per.vse1 see ipi_int_vs1 on page 20-5 . vs2 per.vse2 wp per.wpe see ipi_int_wp on page 20-5 . personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-23 the pcmcia input pins register (p ipr) reports any change of inputs from the pcmcia card to the host (bvd,cd,rdy,vs). the content of the pcmcia controlle r status changed register (pscr) are logically anded with the pcmcia controller enable register (p er) to generate a pcmcia controller interrupt. the interrupt level is user programmable and the pcmc ia controller can generate an additional interrupt for rdy/ireq that can trigger upon a level (low or high) change or edge (fall or rise) of the input signal. 20.5.4.1 error interrupt conditions any of the following error conditions can cause an error interrupt: ? attempt to access a card when the card is in low power mode (lpm). ? attempt to write to a write protected area, see section 20.5.7, ?write protect .? ? attempt to access a card when the card is not inserted. ? attempt to do a 16-bit access to an 8-bit card violating the pps settings or 32-bit access. see section 20.5.8, ?16-bit/8-bit support .? ? attempt to access card with an a ddress which does not match any window. an access to the card which yields an error will take 0-3 wait states to complete according to the following conditions: ? card detect error when pgsr[cde] is cleared and write protect error which results from the wp signal from the card will take 2 wait states. in case these signals (wp cd) change during access, the access will end two cycles after. ? size error, no window error low power mode and write protect error which comes from por[wp] will take one wait state. cd1 per.cde1 see ipi_int_cd1 on page 20-5 . cd2 per.cde2 see ipi_int_cd2 on page 20-5 . bvd1 per.bvde1 see ipi_int_bvd1 on page 20-5 . bvd2 per.bvde2 see ipi_int_bvd2 on page 20-5 . poweron pgcr.poweronen this signal is not part of the pcmcia standard. see ipi_int_poweron on page 20-5 . status change ?or? of all the above interrupts. see ipi_int_sts on page 20-5 . rdy_l per.rdyle rdy_h per.rdyhe rdy_r per.rdre rdy_f per.rdyfe ireq this interrupt is an ?or? of rdy_l, rdy_h, rdy_r, and rdy_f. err per.errinten table 20-17. pcmcia i/f interrupt sources (continued) interrupt enabled with comments personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-24 freescale semiconductor due to the synchronization mechanism on cd signals and wp signal, a change in these signals during access less then two cycles before it finishes would not yield an error. that should not be a problem since these signals typically do not change too much. 20.5.5 power control when lpmen is set in the pgcr, the pcmcia i/f internal clocks should be gated off. the module is in ?listening mode.? it waits for an indication that a card has been inserted. a ll the static signals are synchronous in both cases and status change interrupts are generated as necessary (to wake up the core from stop on card detect, for example). in the first case (lpmen) read from pipr and read/write from/to pscr should take 2 wait states to complete because of the synchronizations of the static signals to the core?s clock. 20.5.6 reset and three-score control the card can be reset by software. this is done by writing to the reset bit in the pgcr register. output of external latches can be disabled by writing to the poe bit in pgcr register. 20.5.7 write protect write protect is handled in two ways: ? card?s write protect?the wp signal comes from the card. ? window?s write protect?the wp bit in the por register. when the wpen is cleared and the card is in memory interface mode, the wp signal coming from the card is ignored. this way it is possible to enable write pr otection on selected memory regions, even if the card?s wp pin is asserted. the settings for the write protect bits are shown in table 20-18 . when the card is in io mode (por.prs = 11 ),wpen bit is ignored. an interrupt is generated by the pcmcia controller at any attempt to access a write protected area. table 20-18. write protect por.prs por.wp bit wp signal por.wpen protect mode x0 (memory i/f) x 0 1 write enabled 1 1 write protected 0 x 0 write enabled 1 x 0 write protected 11(i/o mode) 0 x x write enabled 1 write protected personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-25 20.5.8 16-bit/8-bit support the pcmcia controller supports 16-bit/8-bit accesses. the access size is defined by the iois16 signal and the pps bit in the corresponding por register. the settings for the iois16 and pps bits are shown in table 20-19 . 20.5.9 data and control signals relations table 20-20 describes data and control signa l relations in different access modes. data bus (d) is the data bus of the pc-card. table 20-19. iois16 and pps bit relations iois16 pps access size 0 0 16-bit access to a 16-bit card, the host can generate 8-bit accesses and 16-bit access. 0 1 8-bit access although the card is 16-bit. the host should generate 8-bit accesses only. if the host tries to do a 16-bit access, an interrupt is generated 1 0 8-bit access although 16-bit access is selected by pps. if the host attempts to do a 16-bit access, the pcmcia i/f writes the lower part of the data to the card. 1 1 8-bit access to 8-bit card. the host should generate 8-bit accesses only. if the host tries to do a 16-bit access, an interrupt is generated. table 20-20. data and control signal relations function mode reg ce2 ce1 a0 oe we iord iowr d[15:8] d[7:0] standby mode x 1 1 x x x x x high-z high-z 8-bit read from common memory 1 1 1 1 1 0 0 0 1 0 1 x 0 0 0 1 1 1 1 1 1 1 1 1 high-z high-z odd-byte 1 even-byte odd-byte high-z 1 16-bit read from common memory 1 0 0 x 0 1 1 1 odd-byte even-byte 8-bit write to common memory 1 1 1 1 1 0 0 0 1 0 1 x 1 1 1 0 0 0 1 1 1 1 1 1 xxx xxx odd-byte 1 even-byte odd-byte xxx 1 16-bit write to common memory 1 0 0 x 1 0 1 1 odd-byte even-byte 8-bit read from attribute memory 0 0 0 1 1 0 0 0 0 0 1 x 0 0 0 1 1 1 1 1 1 1 1 1 high-z high-z not-valid even-byte not-valid even-byte 16-bit read from attribute memory 0 0 0 x 0 1 1 1 not-valid even-byte 8-bit write to attribute memory 0 0 1 0 0 0 0 x 1 1 0 0 1 1 1 1 xxx xxx even-byte even-byte personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-26 freescale semiconductor 20.5.10 true ide mode access in true ide mode windows, the selection of eith er task file or alt reg is made by haddr[3] haddr[3] = 0?will yield an access to task file or data register haddr[3] = 1?will yield a write to control re gister or read of alt. status register table 20-21 shows data, control and addr ess relations in trueide mode . 20.5.11 card extraction when the card is extracted the pcmcia controller?s registers are not reset. the registers settings remain the same as before the card?s extraction. this allows the host software to quickly activate the card once the cis indicates that it is the same card. 8-bit read from i/o 0 0 0 1 1 0 0 0 1 0 1 x 1 1 1 1 1 1 0 0 0 1 1 1 high-z high-z odd-byte 1 even-byte odd-byte high-z 1 16-bit read from i/o 0 0 0 x 1 1 0 1 odd-byte even-byte 8-bit write to i/o 0 0 0 1 1 0 0 0 1 0 1 x 1 1 1 1 1 1 1 1 1 0 0 0 xxx xxx odd-byte even-byte odd-byte xxx 16-bit write to i/o 0 0 0 x 1 1 1 0 odd-byte even-byte i/o inhibit 1 x x x x x 0 1 high-z high-z 1 note these are all the access modes which are supported by the standard. in the pcmcia controller, the 8-bit access to odd byte is done by ce1 and a0 only, that is, the data will be always driven on d[7:0]. table 20-21. data, control and address relations in trueide mode function mode ce2 ce1 a0-3 iord iowr d[15:8] d[7:0] standby mode 1 1 xx x x high-z high-z task file write 1 0 1-7h 1 0 xxx data in task file read 1 0 1-7h 0 1 high-z data out data register write 1 0 0 1 0 odd-byte even-byte data register read 1 0 0 0 1 odd-byte even-byte control register write 0 1 6h 1 0 xxx data in alt status read 0 1 6h 0 1 high-z data out invalid mode 0 0 x x x high-z high-z table 20-20. data and control signal relations (continued) function mode reg ce2 ce1 a0 oe we iord iowr d[15:8] d[7:0] personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-27 20.5.12 trueide support the ata standard specifies the at attachment interface between host systems and storage devices. the pcmcia controller can be dynamically configured to support a pcmcia-compatible ata disk interface (commonly known as ide) instead of the standard pcmcia card interface. using the trueide interface on the pcmcia controller changes the function of some card socket signals to support the needs of the ata disk interface. the trueide signals assignm ent on the pcmcia connector is described in table 20-22 . table 20-22. pcmcia card trueide signal names and assignments pc card signal trueide comment d[15:0] d[15:0] ce1 cs0 1 1 in trueide mode, #cs0 and #cs1 (task file chip select) behave differently from #ce1 and #ce2 (byte lane chip selects) task file register select in trueide mode. ce2 cs1 1 alternate status register select in trueide mode. oe atasel 2 2 dynamic change of atasel is not supported since it requires power up of the card. therefore the atasel pin of the card will grounded in the socket. the cf card samples this bit on power-on sequence. if low, the card will enter trueide mode, else it will enter pc card mode. a[2:0] a[2:0] address a[10:3] not used these bits should be connected to ?0? on trueide we we ready/ireq intrq interrupt request?intrq is the ata notation and is asserted high. wp/iois16 iocs16 cd1 cd1 cd2 cd2 vs1 vs1 vs2 vs2 reset reset this signal is asserted low in ata mode, high in other modes. wait iochrdy io channel ready?asserted high?polarity inversion of wait. reg not used this bit should be connected to ?1? on trueide bvd1/stschg pdiag diagnostics complete signal. bvd2/spkr dasp disk active iord iord iowr iowr personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-28 freescale semiconductor 20.5.13 endianness support the pcmcia controller supports big and little endi an. the endianness is defined according to the endianness input pin to the module. this input s hould be tied high or low by the chip integrator. connecting the input to ?1? means big endian.connecti ng the input to ?0? means little endian. dynamic endianness is not supported. 20.6 timing diagrams figure 20-11 and figure 20-12 show pcmcia typical accesses. figure 20-11. write accesses psht=1, psst =1 hclk haddr addr 1 control control 1 hwdata data write 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] data write 1 wait reg reg oe/we/iord/iowr ce1/ce2 poe setup hold pulse width r/w personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 20-29 figure 20-12. read cycle psht=1, psst =1 hclk haddr addr 1 control control 1 rwdata data read 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] wait reg reg w e/iord/iowr ce1/ce2 poe setup hold pulse width r/w personal computer memory card internat ional association (pcmcia) controller MCIMX27 multimedia applications processor reference manual, rev. 0.2 20-30 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 4: connectivity peripherals introduction the i.mx27 processor contains the following modules that provide communication with a variety of different peripheral using several different interfaces: chapter 21, ?1-wire interface (1-wire) ,? on page 21-1 chapter 22, ?advanced technology attachment (ata) ,? on page 22-1 chapter 23, ?configurable serial peripheral interface (cspi) ,? on page 23-1 chapter 24, ?inter-integrated circuit (i2c) ,? on page 24-1 chapter 25, ?keypad port (kpp) ,? on page 25-1 chapter 26, ?memory stick host controller (mshc) ,? on page 26-1 chapter 27, ?secured digital host controller (sdhc) ,? on page 27-1 chapter 28, ?universal asynchronous receiver/transmitters (uart) ,? on page 28-1 chapter 29, ?fast ethernet controller (fec) ,? on page 29-1 chapter 30, ?high-speed usb on-the-go (hs usb-otg) ,? on page 30-1 1-wire module the 1-wire module provides bidirectional communication between the arm9 core and the add-only-memory eprom (ds2502). the 1-kilobit ep rom is used to hold battery information and communicate with the arm9 platform using the ip interface. the arm9 (through the 1-wire interface) acts as the bus master and the ds2502 device is the slave. the 1-wire peripheral does not trigger interrupts; hence, it is necessary for the arm9 to poll of the 1-wire to manage the module. the 1-wire uses an external pin (to connect to the ds2502). timing requirements are met in hardware with the help of a 1-mhz clock. the clock divider generates a 1-mhz clock that is used as time reference by the state machine. timing requirements are crucial for prope r operation, and the 1-wire state machine and the internal clock provide the necessary signal. advanced technology attachment (ata) the advanced technology attachment (ata) module pr ovides an at attachment host interface for the i.mx27. its main use is to provide an interface with ide hard disc drives and atapi optical disc drives. it interfaces with the ata device using industry sta ndard ata signals. the ata interface is compliant to the ata-6 standard, and supports fo llowing ata standard protocols: ? pio mode 0, 1, 2, 3, and 4 MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor ? multiword dma mode 0, 1, and 2 ? ultra dma modes 0, 1, 2, 3, and 4 with a bus clock of 50 mhz or higher ? ultra dma modes 5 with bus clock of 80 mhz or higher the ata interface has 2 buses connected to it. the cpu bus provides communication with the arm9 host processor and the dma bus provides communication between the ata module and the host dma unit. all internal ata registers are visible from both buses, allowing smart direct memory access (sdma) access to program the interface. there are basically 2 protocols that can be active at the same time on the ata bus. the first and simplest protocol (pio mode access) can be started at any t ime by either the arm9 or the host sdma to the ata bus. the pio mode is a slow protocol, mainly intended to be used to program an ata disc drive, but also possible to use to transfer data to/from the disc drive. the second protocol is the dma mode access. dma m ode is started by the ata interface after receiving a dma request from the drive, and only if the ata interface has been programmed to accept the dma request. in dma mode, either multiword dma or ultra dma protocol is used on the ata bus. all transfers between fifo and host ip or dma ip bus are zero wait states transfer, so high speed transfer between fifo and dma/host bus is possible. configurable serial peripheral interface (cspi) there are three identical cspi modules in the i.mx27 ic . each cspi is equipped w ith data fifos, and is a master/slave configurable serial peripheral interface module, capable of interfacing to both spi master and slave devices. the cspi ready (spi_rdy ) and chip select (ss ) control signals enable fast data communication with fewer software interrupts. the cspi is used for fast data communication with fewer software interrupts. it includes the following features: ? full-duplex synchronous serial interface ? master/slave configurable ? four chip selects to support multiple peripherals ? transfer continuation function allows unlimited length data transfers ? 32-bit wide by 8-entry fifo fo r both transmit and receive data ? polarity and phase of the chip select (ss ) and spi clock (sclk) are configurable ? dma support inter-integrated circuit bus (i 2 c) the inter-integrated circuit bus (i 2 c) module provides a serial interface for controlling the sensor interface and other external devices. da ta rates of up to 100 kbps are supported. the i 2 c module provides functionality of a standard i 2 c slave and master. the i 2 c module is designed to be compatible with the standard phillips i 2 c bus protocol. the i 2 c is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. this bus is suitable for applications re quiring occasional communications over a short distance MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 3 between many devices. the flexible i 2 c allows additional devices to be connected to the bus for expansion and system development. keypad port (kpp) the keypad port (kpp) is designed to interface with ke ypad matrix with 2-contact or 3-point contact keys. the kpp is designed to simplify the software task of scanning a keypad matrix. wi th appropriate software support, the kpp is capable of detecting, debouncing, and decoding one or mult iple keys pressed simultaneously in the keypad. the kpp supports up to 8 x 8 external key pad matrices. its port pins can be used as general purpose i/o. using an open drai n design, the kpp includes glitch suppression circuit design, multiple keys, long key, and standby key detection. secure digital host controller (sdhc) the security digital host controller (sdhc) inte grates both multimediacard (mmc) support along with secure digital (sd) memory and i/o functions, including sd memory and i/o combo card. the multi media card (mmc), is a universal low cost data storage and communication media that is designed to cover a wide area of applications as, among others, electronic toys, organizers, pdas, and smart phones. the secure digital card (sd), is an evolution of mmc technology, with two additional pins in the form factor. it is specifically designed to meet the secur ity, capacity, performance, and environment requirement inherent in newly emerging audio and video consumer electronic devices. universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter ( uart) provides serial communication capability with external devices through an rs-232 cable or thr ough use of external circuitry that converts infrared signals to electrical signals (for rece ption), or transforms electrical signals to signals that drive an infrared led (for transmission) to provide low speed irda compatibility. the i.mx27 contains six uart modules. each ua rt module is capable of standard rs-232 non-return-to-zero (nrz) encoding format and irda-compatible infrared modes. the uart transmits and receives characters containi ng either 7 or 8 bits (program selectable). to transmit, data is written from the ip data bus (skyblue line interface) to a 32-byte transmitter fifo (txfifo). this data is passed to the shift register and shifted serially out on the transmitter pin (txd). to receive, data is received serially from the receiver pin (rxd) and stored in a 32-halfwords-deep receiver fifo (rxfifo). the received data is retrieved fr om the rxfifo on the ip data bus. the rxfifo and txfifo generate maskable interrupts as well as dma requests when the data level in each of the fifo reaches a programmed threshold level. universal serial bus, on-the-go (usbotg), high-speed the i.mx27 uses a universal serial bus, on-the -go (usbotg) module that provides all of the functionality required to support th ree independent usb ports, compatib le with the usb 2.0 specification. MCIMX27 multimedia applications processor reference manual, rev. 0.2 4 freescale semiconductor in addition to the normal usb functionality, the module also provides support for direct connections to on-board usb peripherals and supports multiple interfa ce types for serial transceivers. the usb module provides high performance usb on-the-go (otg) functionality, compliant with the usb 2.0 specification, the otg supplement, and th e ulpi 1.0 low pin count specification. fast ethernet controller (fec) the ethernet media access cont roller (mac) is designed to support both 10 and 100 mbps ethernet/ieee 802.3 networks. an exte rnal transceiver interface and transceiver function are required to complete the interface to the media. the fec s upports three different standard mac-phy (physical) interfaces for connection to an external ethernet tr ansceiver. the fec supports the 10/100 mbps mii and the 10 mbps-only 7-wire interface, using a subset of the mii pins. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 21-1 chapter 21 1-wire interface (1-wire) the 1-wire ? module is a peripheral device that communicates with the arm926ej-s core via the ip interface and provides a communication line to a 1 kbit add-only memory (ds2502). the ds2502 is a 1 kbit 1-wire eprom. the 1-wire interface is able to send or receive one bit at a time to the ds2502. the required protocol for accessing the ds2502 is defined by maxim-dallas semiconductor. figure 21-1 shows the 1-wire connection overview. a block-level description of th e 1-wire module is contained in figure 21-2 . figure 21-1. 1-wire connection 21.1 overview this chapter describes the 1-wire function, timing diag rams, port definitions as well as notes on testing the 1-wire module. the ds2502 is used to hold batte ry characteristic inform ation. the clock divider generates a 1 mhz clock used as a time reference by the state machine. transitions between the states of the state machine as well as actions triggered at pr ecise time deadlines are expressed using this 1-mhz clock. the state machine performs all required ac tions to dialog with the external device. ds2502 arm926t aipi r-ahb o-wire interface module i.mx27 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 21-2 freescale semiconductor figure 21-2. 1-wire block-level description 21.2 port definitions the inputs and outputs for the 1-wire are listed in table 21-1 . they are organized in such a way to show the major interfaces for the 1-wire. th e ds2502 input and output lines listed in table 21-1 are the lines that interface with the ds2502. table 21-1 lists the inputs and outputs relevant for the aipi bus protocol. in table 21-1 , the clocks are described. in table 21-1 , the test signals are described. note: the outputs above have been set for a standard i/o pad. the ds2502 specifies an external 5k pull-up should be used. the i.mx27 provides a 69k pull-up resistor on the 1-wire pin. an external pull-up is not required if the 1-wire module is connected within few inches to the ds2502. 21.3 pin configuration table 21-2 identifies the pin used for the 1-wire module. this pin is multiplexed with other functions on the device and must be configured for 1-wire operation. table 21-1. 1-wire port definitions: ds2502 signal i/o comments battery_line_in input 1-wire bus. battery_line_out output connected to gnd for open drain output_enable output enable for output driver 1-wire bus. in hdl model, represents ds2502 input table 21-2. 1-wire pin configuration module setting configuration procedure gpio alternate function of gpio port e [16] 1. clear bit 16 of port e gpio in use register (gius_e) 2. set bit 16 of port e general purpose register (gpr_e) clock divider peripheral registers state machine to pad from pad 1 mhz clock aipi 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 21-3 21.4 clock enable and aipi configuration 21.5 functional description the 1-wire interfaces with the 1kbit add-only me mory (ds2502) through a simple 1 bit bus. the ds2502 1 kbit add-only memory, manufactured by maxim-da llas semiconductor, uses the 1-wire line to program and read a 1024-bit eprom. the ds2502 also has a 64-bit lasered rom and status bytes. the ds2502 requires a special protocol to access the eprom. the protocol involves first issuing one of four rom function commands before the eprom is accessible: read rom, match rom, search rom and skip rom. through the 1-wire bus, the arm926ej-s core interfaces with the ds2502 and allows the required commands to be issued to control the ep rom. the arm926ej-s (through the 1-wire interface) is the bus master and the ds2502 device(s) are the slave(s). the 1-wire peripheral does not trigger interrupts; hence a polling of the 1-wire module register is necessary to manage a correct operation of the block. 21.5.1 low-power modes when the 1-wire module enters a low power mode it gates off its clock when it is not in use?that is, when the rpp, wr0, and wr1 bits in the control register are all cleared. 21.5.2 reset sequence with reset pulse presence pulse to begin any communications with the ds2502, it is requi red that an initialization procedure be issued. a reset pulse must be generated and then a presence pul se must be detected. the minimum reset pulse length is 480 us. the bus master (1-wire) will generate this pulse, then after the ds2502 detects a rising edge on the 1-wire bus, it will wait 15-60 s before it will tran smit back a presence pulse. the presence pulse will exist for 60?240 s. the timing diagram for this sequence is shown in figure 21-3 . figure 21-3. 1-wire initialization table 21-3. crm and api register descriptions module setting configuration procedure pll clock controller and reset module crm_pccr0 set bit [12] to enable the clock to 1-wire aipi aipi1_psr0 and aipi1_psr1 set aipi1_psr0 bit [9] and clear aipi1_psr1 bit [9] to match 1-wire bus width 16 bits. 1-wire bus ds2502 waits 15-60us ds2502 tx ?presence pulse? 60-240us 68us reset and presence pulses 1-wire simples (set pst) 512us autoclear rpp control bit set rpp 511 us 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 21-4 freescale semiconductor the reset pulse begins the initialization sequence and it is initiated when the rpp control register bit is set. when the presence pulse is detected, this bit will be cleared. the presence pulse is used by the bus master to determine if at least one ds2502 is connected. software will determin e if more than one ds2502 exists. the 1-wire module will sample for the ds2502 presence pulse. the presence pulse is latched in the 1-wire control register pst. when the pst bit is set to a one, it means that a ds2502 is present; if the bit is set to a zero, then no device was found. 21.5.3 write 0 the write 0 function simply writes a zero bit to the ds2502. the sequence takes 117 s. the 1-wire bus is held low for 100 s. figure 21-4 shows the write 0 timing. figure 21-4. write 0 timing the write 0 pulse sequence is initiated when the wr0 control bit register is set. when the write is complete, the wr0 register will be auto cleared. 21.5.4 write 1 and read data the write 1 and read timing is identical. the time sl ot is first driven low. according to the ds2502 documentation, the ds2502 has a delay circuit which is used to synchronize the ds2502 with the bus master (1-wire). this delay circuit is triggered by the falling edge of the data line and is used to decide when the ds2502 will sample the line. in the case of a write 1 or read 1, after a delay, a 1 will be transmitted/received. when a read 0 slot is issued, the delay circuit will hold the data line low to override the 1 generated by the bus master (1-wire). for the write 1 or read, the control register wr1/rd is set and auto-cleared wh en the sequence has been completed. after a read, the control register rdst bit is set to the value of the read. figure 21-5 shows the write 1 timing. figure 21-5. write 1 timing 100us 17us 1-wire bus write ?0? slot 128us autoclear wr0 set wr0 5us write ?1? slot 117us set wr1/rd auto c lear wr1 / rd 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 21-5 figure 21-6 shows the read timing. figure 21-6. read timing 21.5.5 program pulse the program pulse sequence is described in the ds 2502 documentation as one of the functions of the 1-wire signaling. the 12-volt programming pulse function is not used in the 1-wire. 21.6 memory map and register definition the 1-wire module includes three user-accessible 16-bit registers. table 21-6 summarizes these registers and their addresses. 21.6.1 register summary figure 21-7 shows the key to the register fields, and table 21-5 shows the register figure conventions. figure 21-7. key to register fields table 21-4. 1-wire memory map address register reset value access section/page 0x1000_9000 (control) control register 0x0000 r/w 21.6.1.1/21-6 0x1000_9002 (time_divider) time divider register 0x0000 r/w 21.6.2/21-7 0x1000_9004 (reset) reset register 0x0000 r/w 21.6.3/21-9 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 21-5. register figure conventions key to register fields convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. 60 s 1-wire 5 s bus read timing read ?0? slot 117 s read ?1? slot 117 s 13 s 5 s 13 s 1-wire samples 1-wire samples set wr1/rd auto clear wr1/rd set wr1/rd auto clear wr1/ r (set rdst) (set rdst) 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 21-6 freescale semiconductor table 21-6 shows the 1-wire register summary. 21.6.1.1 control register (control) the control register updates the status of the reset, presence, write0, write1, and read bits. when read, this register lets the user know whether the device (1-wire) is connected. figure 21-8 shows the control register, and table 21-7 shows the register?s field descriptions. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 21-6. 1-wire register summary name 1514131211109876543210 0x1000_9000 (control) r00000000 rpp pst wr 0 wr 1 rds t 000 w 0x1000_9002 (time_divider) r00000000 dvdr w 0x1000_9004 (reset) r000000000000000 res et w table 21-5. register figure conventions key to register fields (continued) convention description 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 21-7 21.6.2 time divider register (time_divider) 1-wire time divider register clock divider register used to generate the internal time base within the module. internal time generation is made up by a cl ock divider. the purpose of this internal time generation is to make a 1 mhz clock from the main clock. figure 21-9 shows the time_divider register, and table 21-8 shows the register?s field descriptions. table 21-9 shows the system timing requirements. 0x1000_9000 (control) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 rpp pst wr0 wr1 rdst 0 0 0 w reset00000000000000 00 figure 21-8. control register table 21-7. control register field descriptions field description 15?8 reserved 7 rpp reset presence pulse. this bit is self-clearing and is cleared after the presence is determined. 0 does nothing. reset pulse is complete. 1 generates a reset pulse and a sample for ds2502 presence pulse. 6 pst presence status. this bit is valid after the rpp bit is self-cleared. 0 device is not present. 1 device is present. 5 wr0 write 0. this bit is self-clearing and is cleared when the write of the bit is complete. 0 do nothing./ write sequence complete. 1 write a 0 bit to the interface. 4 wr1 write 1/ read. this bit is self-clearing and is cleared when the write of the bit is complete. this reads a bit, since the write 1 and read timing are identical. the value of the read bit is stored in rdst, and is valid after wr1/rd is self-cleared. 0 do nothing./write sequence complete. 1 write a 1 bit to the interface. 3 rdst read status. this bit is valid after the wr1/rd bit is self cleared. 0 a 0 was sampled during a read. 1 a 1 was sampled during a read. 2?0 reserved 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 21-8 freescale semiconductor note: it is the user?s responsibility to program this register so that the binary rate frequency is as close as possible to 1 mhz (1 mhz = clock / (divider + 1)). if the clock frequency is 30 mhz, then the proper value to write into the divider register is 2 9. 0x1000_9002 (time_divider) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 dvdr w reset00000000000000 00 figure 21-9. time divider register table 21-8. time divider register field descriptions field description 15?8 reserved 7?0 dvdr pre-divider factor. the 1-wire also contains a clock divider register used to generate the internal time base within the module. internal time generation is made up by a clock divider. the purpose of this internal time generation is to make a 1 mhz clock from the main clock. it is the user?s responsibility to program this register so that the binary rate frequency is as close as possible to 1 mhz (1 /(divider+1). if the clock frequency is 30 mhz, then the proper value to write to the divider register is 29. 00 1 (default) 01 2 - - - - - - ff 256 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 21-9 note the precision of the generated clock is very important to ensure the proper operation of the 1-wire module. this module is based on a state machine which undertakes actions at defined times. the most stringent constraint is 0.0645 as a relative time imprecision. the time relative precision is directly derived from the frequency of the derivative clock (f): time relative precision = 1/f ?1 = divider/clock (mhz) ?1 the table 21-10 shows the relative time precision for different main clock frequencies. this demonstrates that the user must use care when selecting the main clock fre quency if using the 1-wire module. if the main clock is an exact integer multip le of 1 mhz, then the generated frequency will be exactly 1 mhz. note a main clock frequency below 10 mhz could cause stability problems and incorrect operation in the 1-wire module. 21.6.3 reset register the reset register is used to reset the 1-wire module through software. this register is not self-clearing, therefore the programmer must write a 1 to reset the register and then write a 0 to release the reset signal. figure 21-10 shows the reset register, and table 21-11 shows the register?s field descriptions. table 21-9. system timing requirements times values ( s) minimum ( s) maximum ( s) absolute precision relative precision rstl 511 480 ? 31 0.0645 pst 68 60 75 7 0.1 rsth 512 480 ? 32 0.0645 low0 100 60 120 20 0.2 lowr 5 1 15 4 0.8 read_sample 13 ? 15 2 0.15 table 21-10. system clock requirements main clock frequency (mhz) 13 16.8 19.44 clock divide ratio 13 17 19 generated frequency (mhz) 1 0.9882 1.023 relative time imprecision 0 0.0117 0.023 1-wire interface (1-wire) MCIMX27 multimedia applications processor reference manual, rev. 0.2 21-10 freescale semiconductor 0x1000_9004 (reset) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000000000 0 rst w reset00000000000000 00 figure 21-10. reset register table 21-11. reset register field descriptions field description 15?1 reserved 0 rst software reset. the reset register is used to reset the module using the software. this register is not self-clearing; therefore, the programmer must write a ?1? to reset the registers and then write a ?0? to release the reset signal. 0 1-wire is out of reset. 1 1-wire is in reset. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-1 chapter 22 advanced technology attachment (ata) the ata host controller complies with the ata/atapi- 6 specification. its main use is to interface with ide hard disc drives and atapi optical disc drives . it interfaces with the ata device over a number of ata signals.see figure 22-1 for the block diagram of the ata host controller. figure 22-1. ata host controller block diagram. 22.1 overview the ata host controller consists of a bus interface co mpliant with ahb bus protocols, a control register for register setting, a 64x16 data fifo and an ata prot ocol engine. the ata block is an at attachment host interface. its main use is to interface with hard di sc drives and optical disc drives which compiles with ata/atapi-6 standard. it interfaces with the ata de vice over a number of ata signals. it is possible to connect a bus buffer between the host side and the device side. in this case, the ata_buffer_en signal should be used to control the direction the buffer is driving to. if ata_buffer_en is high, it drives outward to the device. if ata_buffer_en is low, it drives inward to the host. the ata host controller supports interface protocols as specified in ata/atapi-6 standard: ? pio mode 0, 1, 2, 3, and 4 fifo 64x16 ata_reset_b ata_dior ata_diow ata_cs1 ata_cs0 ata_da2 ata_da1 ata_da0 ata_dmarq ata_dmack ata_intrq ata_iordy ata_data[15:0] timing parameters control register interrupt interface fifo control bus interface ahb bus ata_buffer_en ata_ahb.v ata_top.v ata_reg.v ata_fifo.v ata protocol engine pio channel multiword dma channel ultra dma channel ata_controller.v drive register host side device side advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-2 freescale semiconductor ? multiword dma mode 0, 1, and 2 ? ultra dma modes 0, 1, 2, 3, and 4 with bus clock of 50 mhz or higher ? ultra dma mode 5 with bus clock of 80 mhz or higher before accessing the ata bus, the host must program the timing parameters to be used on the ata bus. the timing parameters control the timing on the ata bus. most timing parameters are programmable as a number of clock cycles (1 to 255). some are implied. all of the ata device internal registers are visible to users, and they are defined as mirror registers in ata host controller. as specified in ata/atapi-6 standard, all the features/functions are implemented by reading/writing to the device internal registers. after programming the timing parameters, there are two protocols that can be active at the same time on the ata bus: ? first protocol. this protocol is a pio mode acce ss that can be performed at any time by the host to the ata bus. during pio mode access, the incoming ahb bus cycle is translated into an ata bus cycle by the ata protocol engine. the ahb bus cy cle is stalled until completion of the ata bus cycle on read, or until putting the write data on the ata bus on write. the pio mode is a slow protocol, mainly intended to program the ata disc dr ive, but also possible to use to transfer data to/from the disc drive. during pio mode, the fifo is not active. ? second protocol. this protocol is the dma m ode access. dma mode is started by the ata interface after receiving a dma request from the drive, and only if the ata interface has been programmed to accept the dma request. in dma mode, either multiword dma or ultra dma protocol is used on the ata bus. once started, data transfer is organized between the ata bus and the fifo. data transfer will pause to prevent fi fo overflow/fifo underflow. data transfer will resume when there is again space in the fifo, or when the fifo has been refilled. during dma transfer, there is no direct data transfer betw een the ata bus and the host cpu or host dma bus. instead, the transfer takes place between the ata bus and the fifo; the fifo informs the host dma unit when it needs to be refilled or emptied. in this case, it sends an fifo alarm flag to the host dma. when the host dma receives the fifo_tx_alarm, it should write some data to the fifo. (typically 32 bytes). when the host dma receives the fifo_rcv_alarm, it should read some data from the fifo (typically 32 bytes). the fifo filling level at which the alarms are produced, is programmable. for completion, there is a thir d alarm associated with the host dma operation fifo_txfer_end_alarm. this alarm signals the end of the transfer, and requests the host dma to take steps to complete the transfer: transfer the bytes remaining in the fifo to the host memory, and inform the host cpu the transfer is completed. all transfers between fifo and host cpu or dma bus are zero wait states transfer, so high speed transfer between fifo and host dma bus is possible. when a pio access is performed during a running dma transfer, the dma transf er will be paused, the pio access done, and the dma transfer will resume again. 22.2 features the ata host controller includes the following major features: programmable timing on the ata bus. works with wide range of bus clock frequencies. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-3 ? compliant with ata/atapi-6 standard ? supports pio modes 0, 1, 2, 3, and 4 ? supports multiword dma modes 0, 1, and 2 ? supports ultra dma modes 0, 1, 2, 3, and 4 with bus clock of at least 50 mhz ? supports ultra dma mode 5 with bus clock of at least 80 mhz ? can be used with off-chip bus transceiver if pads are not compliant with ata voltage levels ? 64-halfword fifo part of interface ? fifo receive alarm, fifo transmit alarm, and fifo end of transmission alarm to host dma unit ? zero-wait cycles transfer between host dma bus and fifo allows fast fifo reading/writing 22.3 operation the interface offers two transfer modes that can be used together. 22.4 pio mode an access to the ata bus in pio mode occurs whenever a ata pio register is read or written by the host cpu or the host (smart) dma unit. during a pio transf er the incoming ahb bus cycle is translated into an ata pio bus cycle by the ata protocol engine. no buffering of data occurs, so the host cpu or host dma cycle is stalled until the ata bus read data is av ailable on read, or is sta lled until the ahb bus data can we put on the ata bus during write. pio accesses can be done to the bus at any time, ev en during a running ata dma transfer. in this case, the dma transfer is paused, the pio cycle is completed, and the dma transfer is resumed. 22.4.1 dma mode (multi-word dma and ultra dma) in dma mode, data is transferred between the ata bus and the fifo. two different dma protocols are supported on the ata bus: ultra dma mode and multi-wo rd dma mode. selection is by using a control register bit. a dma transfer will be started when dma mode transfer has been enabled by writing some control bit, and when the drive connected to the ata bus pulls its dmarq line high. during an ata bus dma transfer, data is transferred between the ata bus and the fifo. the transfer will pause to avoid fifo overflow and fifo underflow. it is the task of the host cpu or the host smart dma unit to read data or write data to the fifo to keep the transfer going. normal set-up is that the host (smart ) dma unit takes on this task. for this purpose, the fifo_rcv_alarm and fifo_tx_a larm signals are sent to the host dma unit. fifo_rcv_alarm informs the host dma unit that there is at least 1 packet of data wait ing in the fifo to be read by the host dma. whenever this signal is high, the host dma should transfer one pa cket of data from the fifo to the main memory. typical packet size is 32 bytes (8 long words), but other packet sizes can be handled too. fifo_tx_alarm informs the host dma unit that there is space for at least 1 packet to be written by the host dma. whenever this signal is high, the host dma should transf er one packet of data from main memory to the fifo. typical packet size is 32 bytes (8 long words), but other packet sizes can be handled too. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-4 freescale semiconductor 22.5 external signal description see table 22-1 for the list of signals entering and existing this module to peripherals within the i.mx27 chip. table 22-1. signal properties name port function reset state type external signals ipp_do_ata_reset_b out ata bus reset signal. active low. if active, ata device is reset 1 1 this signal is a standard ata bus signal. it conforms with the ata-6 standard. 0? ipp_do_ata_dior out ata bus read strobe 1 ? ipp_do_ata_diow out ata bus write strobe 1 ? ipp_do_ata_cs1 out ata bus chip select 1 1 ? ipp_do_ata_cs1 out ata bus chip select 0 1 ? ipp_do_ata_da2 out ata bus address line 2 0 ? ipp_do_ata_da1 out ata bus address line 1 0 ? ipp_do_ata_da0 out ata bus address line 0 0 ? ipp_ind_ata_dmarq in ata bus dma request ? ? ipp_do_ata_dmack out ata bus dma acknowledge 1 ? ipp_ind_ata_intrq in ata bus interrupt request ? ? ipp_ind_ata_iordy in ata bus iordy ? ? ipp_do_ata_data[15:0] out ata output data bus hi-z ? ipp_ind_ata_data[15:0] in ata input data bus hi-z ? ipp_obe_ata_data out data transmit tri-state control signal 0 ? ipp_do_ata_buffer_en out buffer enable for external bus transceiver 2 2 it is optional to put a 74xxx245 bus transceiver between the host side of the data bus and the device side of the data bus. if the transceiver is used, its enable should be tied low (always enable), and its direction pin should be tied to ata_buffer_en, in such a way that it drives from host to device when ata_buffer_en is high, and drives from device to host when ata_buffer_en is low. 0? interface signals ipbus_int out active high ata interrupt 0 ? dma signals ata_tx_fifo_alarm out dma transmit fifo alarm request 0 ? ata_rcv_fifo_alarm out dma receive fifo alarm request 0 ? ata_txfer_end_alarm out dma transfer end alarm 0 ? advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-5 22.5.1 detailed signal descriptions the following subsections describe each external signa ls separately. for a detaile d description of the ata bus signal, refer to the ata/atapi-6 standard. 22.5.1.1 ipp_do_ata_reset_b (out) this signal is the ata reset signal. when low, the ata bus is in reset state. when high, no reset. the ata bus is in reset whenever the appropriate bit in the c ontrol register is cleared. after system reset, the ata bus is in reset. 22.5.1.2 ipp_do_ata_dior (out) this signal correspond to ata signal dior. during pi o and multiword dma transfer, function is read strobe. during ultra dma in burst, function is hdm ardy. during ultra dma out burst, function is host strobe (hstrobe). 22.5.1.3 ipp_do_ata_diow (out) this signal corresponds to ata signal diow. during pio and multiword dma transfer, function is write strobe. during ultra dma burst, function is stop, signalling whenever host wants to terminate running ultra dma transfer. 22.5.1.4 ipp_do_ata_cs0, ipp_do_ata_cs1, ipp_do_ata_da2, ipp_do_ata_da1, ipp_do_ata_da0 (out) these signals are the address group of the ata bus. ata_ cs0, ata_cs1 are the chip selects; ata_da2, ata_da1 and ata_da0 are the 3 address lines. all these five lines follow the same timing. 22.5.1.5 ipp_ind_ata_dmarq (in) this signal is the ata bus device dma request (dma rq). its pulled high by the device if it wants to transfer data using multiword dma or ultra dma mode. 22.5.1.6 ipp_do_ata_dmack (out) this signal is the ata bus host dma acknowledge (d mack). its pulled low by the host when it grants the dma request. 22.5.1.7 ipp_ind_ata_intrq (in) this signal is the ata bus interrupt request (intrq). its pulled high by the device whenever it wants to interrupt the host cpu. 22.5.1.8 ipp_ind_ata_iordy (in) this signal is the ata bus iordy line. it has three functions: advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-6 freescale semiconductor ? iordy?active low wait during pio cycles. ? ddmardy?active low device ready during ultra dma out transfers. ? dstrobe?device strobe during ultra dma in transfers. 22.5.1.9 ipp_do_ata_data[15:0] (out) this is the module output data to ata bus. 22.6 memory map and register definition section 22.6.3, ?register descriptions ? provides the detailed descriptions for all of the ata registers. 22.6.1 memory map table 22-2 shows the ata memory map. table 22-2. ata memory map address description access reset value section/page 0x8000_1000 (time_config0) ata timing parameter 0 r/w 0x0101_0101 22.6.3.1.1/22-11 0x8000_1004 (time_config1) ata timing parameter 1 r/w 0x0101_0101 22.6.3.1.2/22-11 0x8000_1008 (time_config2) ata timing parameter 2 r/w 0x0101_0101 22.6.3.1.3/22-12 0x8000_100c (time_config3) ata timing parameter 3 r/w 0x0101_0101 22.6.3.1.4/22-13 0x8000_1010 (time_config4) ata timing parameter 4 r/w 0x0101_0101 22.6.3.1.5/22-14 0x8000_1014 (time_config5) ata timing parameter 5 r/w 0x0101_0101 22.6.3.1.6/22-14 0x8000_1018 (fifo_data_32) 32-bit wide data port to/from fifo r/w 0x0000_0000 22.6.3.2.1/22-15 0x8000_101c (fifo_data_16) 16-bit wide data port to/from fifo r/w 0x0000_0000 22.6.3.2.2/22-16 0x8000_1020 (fifo_fill) fifo filling in half words r 0x0000_0000 22.6.3.3/22-17 0x8000_1024 (ata_control) ata interface control register r/w 0x0000_0000 22.6.3.4/22-17 0x8000_1028 (int_pending) interrupt pending register r 0x0000_0010 22.6.3.5/22-19 0x8000_102c (int_enable) interrupt enable register r/w 0x0000_0000 22.6.3.5/22-19 0x8000_1030 (int_clear) interrupt clear register w 0x0000_00? ? 22.6.3.5/22-19 advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-7 22.6.2 register summary figure 22-2 shows the key to the register fields and table 22-3 shows the register figure conventions. figure 22-2. key to register fields 0x8000_1034 (fifo_alarm) fifo alarm threshold r/w 0x0000_0001 22.6.3.6/22-21 0x8000_a0 (ddtr) drive data register 16-bit rw ? ? ? ? 22.6.3.7/22-22 0x8000_a4 (dftr) drive features register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_a8 (dscr) drive sector count register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_ac (dsnr) drive sector number register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_b0 (dclr) drive cylinder low register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_b4 (dchr) drive cylinder high register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_b8 (ddhr) drive device head register r/w ? ? ? ? 22.6.3.7/22-22 0x8000_bc (dcdr) drive command register w ? ? ? ? 22.6.3.7/22-22 0x8000_bc (dcdr) drive status register r ? ? ? ? 22.6.3.7/22-22 0x8000_d8 (dctr) drive alternate status register r ? ? ? ? 22.6.3.7/22-22 0x8000_d8 (dctr) drive control register w ? ? ? ? 22.6.3.7/22-22 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 22-3. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. slfclr self-clearing bit. writing a one has some effect on the module, but it always reads as zero. reset values table 22-2. ata memory map (continued) address description access reset value section/page advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-8 freescale semiconductor table 22-4 shows the ata register summary. 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 22-4. ata register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109 8 7654 3 2 1 0 0x8000_1000 (time_config0) r time_2w time_1 w r time_on time_off w 0x8000_1004 (time_config1) r time_4 time_pio_rdx w r time_ax time_2r w 0x8000_1008 (time_config2) r time_d time_jn w r time_m time_9 w 0x8000_100c (time_config3) r time_rpx time_env w r time_ack time_k w 0x8000_1010 (time_config4) r time_dzfs time_dvh w r time_mlix time_zah w 0x8000_1014 (time_config5) r time_cyc time_ss w r time_cvh time_dvs w 0x8000_1018 (fifo_data_32) r fifo_data_32 w r w table 22-3. register figure conventions (continued) convention description advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-9 0x8000_101c (fifo_data_16) r000000 0 0 00000 0 0 0 w r fifo_data_16 w 0x8000_1020 (fifo_fill) r000000 0 0 00000 0 0 0 w r000000 0 0 fifo_fill[7:0] w 0x8000_1024 (ata_control) r000000 0 0 00000 0 0 0 w r000000 0 0fif o_ ata _r fif o_ fif o_ dm a_p dm a_u dm a_w ior dy_ w 0x8000_1028 (int_pending) r000000 0 0 00000 0 0 0 w r000000 0 0atafiffifcoata0 0 0 w 0x8000_102c (int_enable) r000000 0 0 00000 0 0 0 w r000000 0 0ata _in fif o_ fif o_ co nt ata _in 000 w 0x8000_1030 (int_clear) r000000 0 0 00000 0 0 0 w r000000 0 0 0 000 0 0 w fifo_u nder- fifo_o ver- 0x8000_1034 (fifo_alarm) r000000 0 0 00000 0 0 0 w r000000 0 0 fifo_alarm[7:0] w 0x8000_a0 (ddtr) r000000 0 0 00000 0 0 0 w r ddtr[15:0] w 0x8000_a4 (dftr) r000000 0 0 00000 0 0 0 w r000000 0 0 dftr[7:0] w 0x8000_a8 (dscr) r000000 0 0 00000 0 0 0 w r000000 0 0 dscr[7:0] w table 22-4. ata register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109 8 7654 3 2 1 0 advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-10 freescale semiconductor 22.6.3 register descriptions this section contains the detailed register descriptions for the ata host controller registers and mapped device registers. all ata host controller register s except fifo_data_16 are 32-bit size accessible. fifo_data_16 is only support 16-bit size accessible. all ata device registers except ddtr are 8-bit size accessible. the ddtr is only support 16-bit size accessible. 22.6.3.1 timing registers registers (ata_base +$00) till (a ta_base + $17) contain timing para meters. these timing parameters control the timing on the ata bus. every timing parameter is 8-bit wide and can assume valid values between 1 and 255. reset value is always 1. and all timing parameter registers are 32-bit size accessible. all figures in this section show timing registers. 0x8000_ac (dsnr) r000000 0 0 00000 0 0 0 w r000000 0 0 dsnr[7:0] w 0x8000_b0 (dclr) r000000 0 0 00000 0 0 0 w r000000 0 0 dclr[7:0] w 0x8000_b4 (dchr) r000000 0 0 00000 0 0 0 w r000000 0 0 dchr[7:0] w 0x8000_b8 (ddhr) r000000 0 0 00000 0 0 0 w r000000 0 0 ddhr[7:0] w 0x8000_bc (dcdr) r000000 0 0 00000 0 0 0 w r000000 0 0 dcdr[7:0] w 0x8000_d8 (dctr) r000000 0 0 00000 0 0 0 w r000000 0 0 dctr[7:0] w table 22-4. ata register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109 8 7654 3 2 1 0 advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-11 22.6.3.1.1 time_config0 see figure 22-3 for an illustration of valid bits in the ata time_config0 register and table 22-5 for descriptions of the bit fields. 22.6.3.1.2 time_config1 see figure 22-4 for an illustration of valid bits in the ata time_config1 register and table 22-6 for descriptions of the bit fields. 0x8000_1000 (time_config0) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_2w time_1 w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_on time_off w reset00000001000000 01 figure 22-3. ata time_config0 register table 22-5. ata time_config0 register field descriptions field description 31?24 time_2w pio mode time parameter counter for time of diow- pulse width (t2w or t2), these shall be used the max time of 8-bit and 16-bit. 23?16 time_1 pio mode time parameter counter for time of address valid to dior-/diow- setup(t1). 15?8 time_on time parameter counter for transceiver to turn on. 7?0 time_off time parameter counter for transceiver to turn off. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-12 freescale semiconductor 22.6.3.1.3 time_config2 see figure 22-5 for an illustration of valid bits in the ata time_config2 register and table 22-7 for descriptions of the bit fields. 0x8000_1004 (time_config1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_4 time_pio_rdx w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_ax time_2r w reset00000001000000 01 figure 22-4. ata time_config1 register table 22-6. ata time_config1 register field descriptions field description 31?24 time_4 pio mode time parameter counter for controlling the time of dior- data hold (t4). 23?16 time_pio_rdx pio mode time parameter counter for controlling the time of read data valid to iordy active (trd). 15?8 time_ax pio time parameter counter for timing of iordy setup time (ta). 7?0 time_2r pio mode time parameter counter for time of dior- pulse width (t2r or t2), these shall be used the max time of 8-bit and 16-bit. 0x8000_1008 (time_config2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_d time_jn w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_m time_9 w reset00000001000000 01 figure 22-5. ata time_config2 register advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-13 22.6.3.1.4 time_config3 see figure 22-6 for an illustration of valid bits in the ata time_config3 register and table 22-8 for descriptions of the bit fields. table 22-7. ata time_config2 register field descriptions field description 31?24 time_d multiword dma mode time parameter counter for time of dior-/diow- asserted pulse width (td). 23?16 time_jn multiword dma mode time parameter counter for time of diow- data hold time (th). 15?8 time_m multiword dma mode time parameter counter for time from cs valid to dior-/diow- (tm). 7?0 time_9 pio mode time parameter counter for controlling the dior-/diow- to address valid hold time. 0x8000_100c (time_config3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_rpx time_env w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_ack time_k w reset00000001000000 01 figure 22-6. ata time_config3 register table 22-8. ata time_config3 register field descriptions field description 31?24 time_rpx ultra dma mode time parameter counter for time of trp. 23?16 time_env ultra dma mode time parameter counter for min. time of tenv. 15?8 time_ack ultra dma mode time parameter counter for time of tack. 7?0 time_k multiword dma mode time parameter counter for time of diow- negated pulse width (tkw). advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-14 freescale semiconductor 22.6.3.1.5 time_config4 see figure 22-7 for an illustration of valid bits in the ata time_config4 register and table 22-9 for descriptions of the bit fields. 22.6.3.1.6 time_config5 see figure 22-8 for an illustration of valid bits in the ata time_config5 register and table 22-10 for descriptions of the bit fields. 0x8000_1010 (time_config4) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_dzfs time_dvh w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_mlix time_zah w reset00000001000000 01 figure 22-7. ata time_config4 register table 22-9. ata time_config4 register field descriptions field description 31?24 time_dzfs ultra dma mode time parameter counter for tdzfs. 23?16 time_dvh ultra dma mode time parameter counter for tdvh. 15?8 time_mlix ultra dma mode time parameter counter for tmli. 7?0 time_zah ultra dma mode time parameter counter for tzah. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-15 22.6.3.2 fifo data registers the fifo_data register is used to read or write data to the internal fifo. it can be accessed as a 16-bit register or as a 32-bit register. any long write to the register will put the four bytes written into the fifo. any word write will put the two bytes written into th e fifo. any long read will read four bytes from the fifo. any word read will read two bytes from the fifo. 22.6.3.2.1 fifo_data_32 register in 32-bit mode see figure 22-9 for an illustration of valid bits in the fifo_data_32 register in 32-bit mode and table 22-11 for descriptions of the bit fields. 0x8000_1014 (time_config5) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r time_cyc time_ss w reset00000001000000 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r time_cvh time_dvs w reset00000001000000 01 figure 22-8. ata time_config5 register table 22-10. ata time_config5 register field descriptions field description 31?24 time_cyc ultra dma mode time parameter counter for tcyc. 23?16 time_ss ultra dma mode time parameter counter for tss. 15?8 time_cvh ultra dma mode time parameter counter for tcvh. 7?0 time_dvs ultra dma mode time parameter counter for tdvs. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-16 freescale semiconductor 22.6.3.2.2 fifo_data_16 register see figure 22-10 for an illustration of valid bits in the fifo_data_16 register in 16-bit mode and table 22-12 for descriptions of the bit fields. 0x8000_1018 (fifo_data_32) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fifo_data_32[31:16] w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fifo_data_32[15:0] w reset00000000000000 00 figure 22-9. ata fifo_data_32 register table 22-11. ata fifo_data_32 register field descriptions field description 31?0 fifo_data_32 read/write 32-bit data from/to the fifo, reads from this register return zero when the fifo is empty. 0x8000_101c (fifo_data_16) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fifo_data_16[15:0] w reset00000000000000 00 figure 22-10. ata fifo_data_16 register advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-17 22.6.3.3 fifo_fill register see figure 22-11 for an illustration of valid bits in the fifo_fill register and table 22-13 for descriptions of the bit fields. 22.6.3.4 ata_control register see figure 22-12 for an illustration of valid bits in the ata_control register and table 22-13 for descriptions of the bit fields. table 22-12. fifo_data_16 register field descriptions field description 31?16 reserved. 15?0 fifo_data_16 read/write 16-bit data from/to the fifo, reads from this register return zero when the fifo is empty. 0x8000_1020 (fifo_fill) access: user read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 fifo_fill[7:0] w reset00000000000000 00 figure 22-11. ata fifo_fill register table 22-13. fifo_fill register field descriptions field description 31?8 reserved. 7?0 fifo_fill fifo_fill is a read-only register. any read to it returns the current number of half-words present in the fifo. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-18 freescale semiconductor 0x8000_1024 (ata_control) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 fifo _rst _b ata _ rst_ b fifo _tx_ en fifo _rcv _en dma_ pend ing dma_ ultr a_se lect ed dma_ write ior dy_ en w reset00000000000000 00 figure 22-12. ata_control register table 22-14. ata control register field descriptions field description 31?8 reserved 7 fifo_rst_b this field controls if the internal fifo is in reset or enabled 0 fifo reset 1 fifo normal operation 6 ata _ r s t _ b this bit controls the level on the ata_reset_b pin, and controls the reset of the internal ata protocol engine. 0 ata_rst_b = 0, ata drive is reset, and internal protocol engine reset. 1 ata_rst_b = 1, ata drive is not reset and internal protocol engine normal operation. 5 fifo_tx_en fifo transmit enable. this bit controls if the fifo will make transmit data requests to the dma. if enabled, the fifo will request the dma to refill it whenever fifo filling drops below the alarm level. 0 fifo refill by dma disabled 1 fifo refill by dma enabled 4 fifo_rcv_en fifo receive enable. this bit controls if the fifo will make receive data requests to the dma. if enabled, the fifo will request the dma to empty it whenever fifo filling becomes greater or equal to the alarm level. 0 fifo empty by dma disabled 1 fifo empty by dma enabled 3 dma_pending dma pending bit. this bit controls if the ata interface will respond to a dma request originating in the drive. if this bit is asserted, the ata interface will start a multi-word dma or ultra dma burst whenever the drive asserts ata_dmarq. 0 ata interface will not start dma burst 1 ata interface will start multi-word dma or ultra dma burst whenever drive asserts dmarq 2 dma_ultra_seleted this bit indicates if a dma burst started, the udma or mdma protocol will be used 0 multiword dma protocol will be used 1 ultra dma protocol will be used advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-19 22.6.3.5 int_pending, int_enable, int_clear registers these 3 registers control interrupts coming from the ata and going to the cpu and dma. see figure 22-13 for an illustration of valid bits in the int_pending register and table 22-15 for descriptions of the bit fields. see figure 22-14 for an illustration of valid bits in the int_enable register and table 22-15 for descriptions of the bit fields. 1 dma_write this bit indicates the data direction on any dma burst started 0 dma in burst, ata interface reads from drive 1 dma out burst, ata interface writes to drive 0 iordy_en this bit indicates if the ata_iordy handshake will be used during pio mode 0 iordy will be disregarded 1 iordy handshake will be used 0x8000_1028 (int_pending) access: user read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 00000000 ata _ i ntr q1 fifo _und erfl ow fifo _ove rflo w con trol ler_i dle ata _ i ntr q2 000 w reset000000000 1 1 interrupts ata_intrq1 and ata_intrq2 only reset to 0 if during reset the interrupt input is low. 00100 00 figure 22-13. ata int_pending register table 22-14. ata control register field descriptions field description advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-20 freescale semiconductor see figure 22-15 for an illustration of valid bits in the int_clear register and table 22-15 for descriptions of the bit fields. 0x8000_102c (int_enable) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 00000000 ata _ i ntr q1 fifo _und erfl ow fifo _ove rflo w con trol ler_i dle ata _ i ntr q2 000 w reset00000000000000 00 figure 22-14. ata int_enable register 0x8000_1030 (int_clear) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r000000000 000 00 w fifo _und erfl ow fifo _ove rflo w reset000000000??????? figure 22-15. ata int_clear register table 22-15. int_pending register field description field description 31?8 reserved. 7 ata _ i n t r q 1 ata interrupt request 1. this bit reflects the value of the ata_intrq interrupt input. it is set in the interrupt pending register when the drive interrupt is pending, cleared otherwise. when the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, fifo_txfer_end_alarm will be asserted, signalling the dma the end of the transfer. the interrupt clear register has no influence on this bit. advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-21 a group of three registers control the interrupt inte rface from the ata module and going to the cpu and dma. there are two interrupts controlled by these registers: ? ipbus_int. this interrupt is controlled by bits 3,4, 5 and 6 of the interrupt registers. it will be asserted if one of the 4 bits is set in the int_ pending register, while the same bit is set in the int_enable register. this interrupt goes to the cpu. ? fifo_txfer_end_alarm. this interrupt is controlled by bit 7 of the interrupt registers. if ata_intrq1 is set in both the interrupt enable and interrupt pending register, fifo_txfer_end_alarm will be asserted. the goal of this interrupt is to inform the dma that the running data transfer has ended. this interrupt goes to the smart dma. these three registers have mostly the same bits. if a bit is set in the interrupt pending register, its interrupt is pending, and will produce an interrupt if the same bit is set in the interr upt enable register. some bits in the interrupt pending register are sticky bits. writing a ?1? to the corresponding bit in the interrupt clear bit, will reset them. 22.6.3.6 fifo alarm register see figure 22-16 for an illustration of valid bits in the fifo_alarm register and table 22-16 for descriptions of the bit fields. 6 fifo_underflow fifo underflow. this bit reports fifo underflow. sticky bit. it is set in the interrupt pending register when there is a fifo underflow condition. it is cleared by writing a ?1? to this bit in the interrupt clear register. when the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the cpu. 5 fifo_overflow fifo overflow. this bit reports fifo overflow. sticky bit. it is set in the interrupt pending register when there is a fifo overflow condition. it is cleared by writing a ?1? to this bit in the interrupt clear register. when the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the cpu. 4 controller_idle controller idle. this bit reports controller idle. it is set when the ata protocol engine is idle, there is no activity on the ata bus. it is cleared when there is activity on the ata bus. when the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the cpu. the interrupt clear register has no influence on this bit. 3 ata _ i n t r q 2 ata interrupt request 2. this bit reflects the value of the ata_intrq interrupt input. it is set in the interrupt pending register when the drive interrupt is pending, cleared otherwise. it has exactly same functioning as ata_intrq1, but this bit affects ipbus_int, while the other affects interrupt to the dma. when the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be asserted, signalling the cpu the drive is requesting attention. the interrupt clear register has no influence on this bit. 2?0 reserved table 22-15. int_pending register field description (continued) field description advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-22 freescale semiconductor 22.6.3.7 drive registers mapped to host module device registers are addressable and all registers ex cept ddtr are 8-bit size accessible, the register ddtr is 16-bit size accessible, but all these registers are not present in the ata interface module. a list is given in table 22-17 . if a read or write access is made to one of these registers, the read or write is 0x8000_1034 (fifo_alarm) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 fifo_alarm w reset00000000000000 01 figure 22-16. ata fifo_alarm register table 22-16. ata fifo_alarm register field descriptions field description 31?8 reserved 7?0 fifo_alarm this register contains the threshold to generate fifo_rcv_alarm and fifo_tx_alarm to the dma interface. if (fifo_tx_en == 1 && fifo_fill < fifo_alarm): fifo_tx_alarm is set 1, request is made to dma to refill fifo. if (fifo_rcv_en == 1 && fifo_fill >= fifo_alarm): fifo_rcv_alarm is set 1, request is made to dma to empty fifo. table 22-17. drive registers connected to ata bus address name description access 0x8000_a0 (ddtr) drive_data drive data register r/w 0x8000_a4 (dftr) drive_features drive features register r/w 0x8000_a8 (dscr) drive_sector_count drive sector count register r/w 0x8000_ac (dsnr) drive_sector_num drive sector number register r/w 0x8000_b0 (dclr) drive_cyl_low drive cylinder low register r/w 0x8000_b4 (dchr) drive_cyl_high drive cylinder high register r/w 0x8000_b8 (ddhr) drive_dev_head drive device head register r/w 0x8000_bc (dcdr) drive_command drive command register when write w 0x8000_bc (dcdr) drive_status drive status register when read r 0x8000_d8 (dctr) drive_alt_status drive alternate status register when read r 0x8000_d8 (dctr) driver_control drive counter register when write w advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-23 mapped to a pio read or write cycle on the ata bus, and the corresponding register in the device attached to the ata bus is accessed. 22.7 functional description to best describe the organization of the ata host c ontroller module from a user?s point of view, it is instructive to view the module at a number of different levels of hierarchy. see figure 22-17 for an illustration of the organization of ata and connection to a hdd device. figure 22-17. block diagram for ata module the ata host controller module is complied with the ata/atapi-6 specification. the module consists of six main parts: ? ahb bus interface ? register block ? 64x16 fifo for data buffer ? pio/mdma/udma protocol engine ? crc block ? input signal synchronizer 22.8 initialization/app lication information the ata interface provides two ways to communicate with the ata peripherals connected to the ata bus ? pio mode read/write operation to the ata bus. fifo 64x16 ata_reset_b ata_dior ata_diow ata_cs1 ata_cs0 ata_da2 ata_da1 ata_da0 ata_dmarq ata_dmack ata_intrq ata_iordy ata_data timing parameters control register interrupt interface fifo control bus interface bus ata_buffer_en ata_ahb.v ata_reg.v ata_fifo.v pio channel multiword dma channel ultra dma channel ata_controller.v drive register buffer hard disk device advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-24 freescale semiconductor ? dma transfers with the ata bus the operation of the peripheral is describe d in detail in the following sections. 22.8.1 resetting ata bus the ata bus reset ata_reset_b is asserted whenever bit 6 ata_rst_b of register ata_control is cleared to 0. at the same time, the ata protocol engine is reset. when this bit is set to 1, the reset is released. 22.8.2 access to ata bus in pio mode access to the ata bus in pio mode is possible after: ? ata_rst_b bit in register ata_control is set. ? timing parameters ha ve been programmed. to access the drive in pio mode, simply read or write to the correct drive register. the bus cycle will be translated to an ata cycle, and the drive is accessed. when drive registers are accessed while the ata bus is in reset, the read or write is discarded, not done. 22.8.3 using dma mode to receive data from ata bus apart from pio mode, the ata interface supports al so mdma and udma mode to transfer data. dma mode can be used to receive data from the drive (dma in transfer). in dma receive mode, the protocol engine will transfer data from the drive to the fifo using multiword dma or ultra dma protocol. the transfer will pause when one of following occurs: ? the fifo is full. ? the drive deasserts its dm a request signal ata_dmarq. ? the bit dma_pending in the ata_control register is cleared. when the cause of the transfer pausing is removed, the transfer restarts. the end of the transfer is signalled by the drive to the host by asserting the ata_intrq signal. alternatively, the host can read the device status register. in this register, the drive will also indicate if the transfer has ended. the transfer of data from the fifo into the memo ry is handled by the host system dma. whenever the fifo filling is above the alarm threshold, the dma s hould read one packet of data from the fifo, and store this in main memory. in doing so, the dma pr events the fifo from getting full, and keeps the transfer from drive to fifo running. the steps for setting up a dma data transfer from device to host are: 1. make sure the ata bus is not in rese t and all timing registers are programmed. 2. make sure the fifo is empty by reading it until empty or by resetting it. 3. initialize the dma channel connected to fifo_r cv_alarm. every time fif o_rcv_alarm is high, the dma should read advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 22-25 4. write 2 * advanced technology attachment (ata) MCIMX27 multimedia applications processor reference manual, rev. 0.2 22-26 freescale semiconductor the steps for setting up a dma data transfer from device to host are: 1. make sure the ata bus is not in rese t and all timing registers are programmed. 2. make sure the fifo is empty by reading it until empty, or by resetting it. 3. initialize the dma channel connected to fif o_tx_alarm. every time fifo_tx_alarm is high, the dma should read MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-1 chapter 23 configurable serial peripheral interface (cspi) the i.mx27 processor contains three configurable seri al peripheral interface (cspi) modules that allow rapid data communication with fewer software interr upts than conventional serial communications. each cspi is equipped with two data fi fos and is a master/slave configur able serial peripheral interface module, allowing i.mx27 to interface with both external spi master and slave devices. this chapter describes how the cspi module communi cates with external devices. each cspi has one 8 32-bit data-in fifo and one 8 32-bit data-out fifo. in corporating the cspi1_rdy and ss control signals, it enables fast data communication with fewer software interrupts. figure 23-1 illustrates the configurable serial periphe ral interface block diagram. figure 23-1. configurable serial peripheral interface block diagram 23.1 features the primary features of the cspis include: ? master/slave configurable for cspi 1 and cspi2. cspi3 is only a master. ? cspi1 and cspi2 have three chip-selects (ss0-ss3) respectively. cspi3 has one chip select (ss0). ? up to 32-bit programmable data transfer sclk control ss ip bus interface miso mosi clock generator shift register rx fifo 8 32 tx fifo 8 32 cspi1_rdy 3 configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-2 freescale semiconductor ?8 32-bit fifo for both tx and rx data ? transfer continuation function allows unlimited length data transfers ? polarity and phase of the chip select (ss ) and spi clock (sclk) are configurable ? dma support ? full-duplex synchronous serial interface ? maximum spi clock frequency up to 22.167 mhz as a master, 16.625 mhz as a slave 23.1.1 external signals description the following signals are visible to external spi device s. they are used to control the serial peripheral interface: mosi?master out slave in bidirectional signal, which is txd output signal from the data shift register in master mode. in slave mode it is rxd input to the data shift register. ? miso?master in slave out bidirectional signal, which is rxd input signal to the data shift register in master mode. in slave mode it is txd output from the data shift register. ? sclk?cspi clock bidirectional si gnal, which is cspi clock output in master mode. in slave mode it is an input cspi clock signal. ? ss[2:0], slave select bidirecti onal signal, output in master mode, and input in slave mode. ? cspi1_rdy ?this input signal is used for hardware cont rol only in master mode. it indicates that external spi slave is ready to receive data. it will edge or level trigger a cspi burst if used. this signal is only available for cspi1: it is not present on cspi2 and cspi3. it is ignored in slave mode. this signal is controlled by drctl(controlreg[13: 12]) bits. if the hardware control enabled, cspi will transfer data only when external spi slave is ready. 23.2 module input/output signals table 23-1. signal listing signal in/out bits description pad level signals ipp_do_mosi out 1 tx data when cspi is in master mode. ipp_do_miso out 1 tx data when cspi is in slave mode.it is tri-stated if the selected ssn is not asserted. ipp_cspi_clk_out out 1 clock output when cspi is in master mode.max. frequency is ipg_clk_perclk/3. ipp_do_ss0 out 1 slave select0 generated by cspi in master mode when cs[1:0] bits are set to ?00? in the control register. ipp_do_ss1 out 1 slave select1 generated by cspi in master mode when cs[1:0] bits are set to ?01? in the control register. configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-3 ipp_do_ss2 out 1 slave select2 generated by cspi in master mode when cs[1:0] bits are set to ?10? in the control register. ipp_do_ss3 out 1 slave select3 generated by cspi in master mode when cs[1:0] bits are set to ?11? in the control register. ipp_obe_mosi out 1 output enable for ipp_do_mosi, ipp_cspi_clk_out, ipp_do_ss0, ipp_do_ss1 and ipp_do_ss2 ,ipp_do_ss3 when the cspi is in master mode. ipp_obe_miso out 1 output enable for ipp_do_miso. ipp_ind_mis0 in 1 rx data when cspi is in master mode. ipp_ind_mosi in 1 rx data when cspi is in slave mode. ipp_cspi_clk_in in 1 clock input when cspi is in slave mode. ipp_ind_ss0 in 1 slave select0 signal from an external master when cspi is in slave mode. ipp_ind_ss1 in 1 slave select1 signal from an external master when cspi is in slave mode. ipp_ind_ss2 in 1 slave select2 signal from an external master when cspi is in slave mode. ipp_ind_ss3 in 1 slave select3 signal from an external master when cspi is in slave mode. ipp_ind_dataready in 1 this input signal is used only in master mode. it will edge or level trigger a cspi burst if used. ipp_ind_force_master in 1 used to force cspi master mode from top level. ip bus interface signals ips_byte_31_24 in 1 module byte access enable. enables write to bits [31:24] of addressed register. ips_byte_23_16 in 1 module byte access enable. enables write to bits [23:16] of addressed register. ips_byte_15_8 in 1 module byte access enable. enables write to bits [15:8] of addressed register. ips_byte_7_0 in 1 module byte access enable. enables write to bits [7:0] of addressed register. ips_module_en in 1 peripheral module enable ips_addr in 11 address bus ips_rwb in 1 read access signal. active low. ips_wdata in 32 write data bus ips_rdata out 32 read data bus table 23-1. signal listing (continued) signal in/out bits description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-4 freescale semiconductor ips_xfr_wait out 1 wait signal to arm ips_xfr_err out 1 transfer error acknowledge. ips_xfr_err is generated when a write to a read-only register(rxdata register) is performed. it is not generated when the write-only register (txdata register) is read. interrupts ipi_int_cspi out 1 cspi interrupt request line to the core. dma interface signals ipd_req_cspi_tdma out 1 dma tx request ipd_req_cspi_rdma out 1 dma rx request global signals ipg_hard_neg_async_res et in 1 asynchronous, active low hardware reset for ffs clocked by inverted clocks. ipg_hard_pos_async_res et in 1 asynchronous, active low hardware reset ipg_clk_s in 1 clock gated by the or function of all the ips_module_en signals from aipi. ipg_clk in 1 continuous clock gated by the ipg_clk_en. ipg_clk in 1 inverted ipg_clk clock. ipg_clk_en out 1 used to gate off the ipg_clk depending on the module enable bit residing in the cspi that is, the spien bit. ipg_clk_perclk in 1 reference baud rate clock. it must be slower than or equal to ipg_clk. ipg_clk_32k in 1 32khz continuous clock used for counting purpose. resp_sel in 1 when this pin is ?1?, the module will always return an okay response (that is, ips_xfr_err is not asserted) when there is an access to any location within the 4kbyte boundary, whereas, if this pin is?0?, the module will return an error response (ips_xfr_err is asserted) when there is an access to an unused location within the 4kbyte boundary. test mode signals ipt_test_mode in 1 this is used to activate all scan testable logic into scan mode and non-scan logic into bypass mode. ipt_test_async_se in 1 used to handle internally generated resets. ipt_test_clk_se in 1 used to switch between 32khz clock and the ipg_clk. ipt_test_reset_b in 1 test mode reset. table 23-1. signal listing (continued) signal in/out bits description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-5 23.3 operation when cspi is configured as master, the ss (output) and cspi1_rdy (input) signals, are used for data transfer rate control. the sample period control register can be set if a fixed data transfer rate is required. when cspi is configured as slave, the ss signal be comes an input signal and can optionally be used for data latching and loading to the internal data shift registers, as well as incrementing internal data fifo pointers. figure 23-2 shows the generic cspi timing. figure 23-2. generic cspi timing 23.3.1 phase and polarity configurations the serial peripheral interface master uses the sclk signa l to transfer data in and out of the shift register. data is clocked using any one of four programmable clock phase and polarity combinations. during phase 0, polarity 0 and phase 1, polarity 1 operations, output data changes on the falli ng clock edge and input data is shifted in on the rising edge. the most-significant bit is output when the cpu loads the transmit data. during phase 1, polarity 0 and phase 0, polarity 1 operations, output data changes on the rising edges of the clock and is shifted in on falling edges. the mo st-significant bit is output on the first rising sclk edge. polarity inverts sclk , but does not change the edge-triggered ev ents that are internal to the serial peripheral interface master. this flexibility allows it to operate with most serial peripheral devices. figure 23-2 shows the cspi timing with vari ous pol and pha configurations. 23.3.2 master mode the cspi master uses the ss signal to enable an external spi device and uses sclk to transfer data in and out of the shift register. the spi_rdy enables fast data communication with fewer software interrupts. by using periodreg, the cspi can be us ed for a fixed data transfer rate. when cspi is in master mode the ss , sclk, and mosi are output signals and the miso is an input. figure 23-3 shows a typical spi transfer. sclk mosi b n ... ... b 1 b 0 sclk sclk sclk (pol=1, pha=1) (pol=1, pha=0) (pol=0, pha=1) (pol=0, pha=0) miso b n ... ... b 1 b 0 b n-1 b n-2 b n-1 b n-3 b n-3 b n-2 configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-6 freescale semiconductor figure 23-3. typical spi transfer (8-bit) in figure 23-3 , the ss signal enables the selected external spi device and the sclk synchronizes data transfer. mosi and miso change on rising edge of sclk and the miso is latched on the falling edge of the slck clock. the data shifted out is 0xd2, and the data shifted in is 0x66. 23.3.2.1 master mode with spi_rdy by default, the cspi does not use spi_rdy in master mode. a spi transfer begins when the following events happen: the cspi is enabled, txfifo has data in it, and controlreg[xch] is set. when controlreg[drctl] contains either 01 or 10, the spi_rdy controls when a spi burst starts. if controlreg[drctl] is set to 01, the spi burst can be triggered only if a falling edge of spi_rdy has been detected. figure 23-4 shows the relationship between a spi transfer and the falling edge of spi_rdy . figure 23-4. relationship between a spi transfer and the falling edge of spi_rdy a spi transfer does not start until the falling edge of spi_rdy is detected. the next spi burst starts when the next spi_rdy falling edge is detected, after the last transfer has finished. ss sclk mosi miso ss sclk mosi miso spi_rdy configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-7 if controlreg[drctl] is set to 10, the spi burst can be triggered only if spi_rdy is low. figure 23-5 shows the relationship between a spi transfer and spi_rdy . the spi transfer does not begin until spi_rdy goes low. the next spi transfer begins after the previous transfer has finished if spi_rdy remains low. figure 23-5. relationship between a spi transfer and spi_rdy 23.3.2.2 master mode with wait states wait states can be inserted between spi transfers. this provides a way for the user to slow down the spi transfer to meet the timing requirements of a slower spi device. figure 23-6 shows wait states inserted between spi bursts. figure 23-6. spi transfers with wait states in this case, the number of wait states is controlled by periodreg [wait] and the wait states? clock source is selected by periodreg [csrc]. ss sclk mosi miso spi_rdy ss sclk mosi miso ws configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-8 freescale semiconductor 23.3.2.3 master mode with continuation many transfers can be continuous without idle time in sertion. this provides a way for the user to maximize data rate wit hout any delay. figure 23-7 shows the detail timing. figure 23-7. spi continuous transfer with burst=1 to obtain the continuation function, the controlreg [burst] should be set to 1, with controlreg [ssctl] and periodreg [wait] set to 0. 23.3.2.4 master mode with ssctl control ssctl controls whether a ss pulse is inserted between two data transfers. when ssctl is set, a ss pulse will be inserted in multiple transfers. when ssctl is cleared, ss signal will stay asserted in multiple transfers. figure 23-8 and figure 23-9 show the detail timing. figure 23-8. spi transfer while ssctl is clear ss sclk mosi miso ss sclk mosi miso configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-9 figure 23-9. spi transfers while ssctl is set 23.3.2.5 master mode with various configurations of wait, burst and ssctl table 23-2 shows cspi behavior in master mode in various configurations of periodreg[wait], controlreg [burst] and controlreg [ssctl]. in this table, x means don?t care (0 or 1). 23.3.3 slave mode when the cspi module is configured as a slave, the us er can configure the cspi control register to match the external spi master?s timing. in this configuration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shif t registers, as well as to increment the data fifo. the ss , sclk, and mosi are inputs and miso is output. most of their timing diagrams are the same as in master mode, because the inputs come from a spi master device. however, it is different when ss is used to increment data fifo. when the ssctl is set while cspi is in slave mode, the data fifo will increment at ss rising edge. figure 23-10 shows a spi burst in which data fifo is incremented by ss rising edge. table 23-2. cspi behavior in master mode in various configurations wait burst ssctl sclk pin ss pin 0007*tsclk 1 idle time inserted between consecutive data transfers 1 tsclk is cspi sclk period no pulse 0 1 0 no idle time inserted between consecutive data transfers no pulse 0 x 1 7*tsclk idle time inserted between consecutive data transfers 2*tsclk width pulse non-zero x 0 (7*tsclk + wait*tsclk_32k 2 ) idle time inserted between consecutive data transfers 2 tsclk_32k is either sclk or 32khz clock period no pulse non-zero x 1 (7*tsclk + wait*tsclk_32k) idle time inserted between consecutive data transfers (2*tsclk + wait*tsclk_32k) width pulse ss sclk mosi miso configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-10 freescale semiconductor figure 23-10. increment data fifo by ss rising edge in this case, the data received is not 0xd2 but 0x69. only the most significant 7 bits are loaded to rxfifo. 23.3.4 interrupt control interrupt control is not a specific mode of operati on; however, it provides a basic method to utilize the cspi fifos. you can program the cspi to enable the txfifo em pty, txfifo half, and txfifo full interrupt. you can also use the interrupt service routine to fill the txfifo with data to be transferred. furthermore, you can also enable rxfifo ready, rx fifo half, and rxfifo full to retrieve data from rxfifo by using the interrupt service routine. three other interrupt sources can be used to cont rol/debug the spi transfer. the txfifo and tx shift register empty interrupt tells the user that there is not data left in txfifo and the data in the shift register is shifted out. the bit counter overflow interrupt tells th e user that the cspi received more than 32 bits in a spi burst and the remaining bits will be lost. the rxfifo overflow interrupt tells the user that the rxfifo received more than 8 words and will not accept any other word. figure 23-11 shows a program sequence of spi bursts using interrupt. ss sclk mosi miso configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-11 . figure 23-11. program sequence of spi burst using interrupt 23.3.5 dma control dma control provides another way to utilize the fifos in the cspi module. peripherals such as the cspi which support dma, use dma request and acknowle dge signals. larger amounts of data can be transferred using dma control, thereby reducing interrupts and cpu loading. when the appropriate conditions are matched, the module will send out a dma request, and the dma will deal with the following cases: txfifo empty, txfifo half, rxfifo half , and rxfifo full. figure 23-12 shows a program sequence of spi bursts using the dma. figure 23-12. program sequence of spi burst using dma enable cspi enable interrupts fill txfifo using interrupt service routine enable xch retrieve data using interrupt service routine wait until all needed data are transferred done tshfe interrupt enable cspi enable dma fill txfifo using dma enable xch retrieve data using dma wait until all needed data are transferred done tshfe interrupt configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-12 freescale semiconductor 23.4 initialization/app lication information this section provides initialization an d application information for cspi. figure 23-13 shows two flow charts for the master and slave mode of operations supported by the cspi. figure 23-13. flow chart of cspi operation example 23-1 shows a normal example code of cspi operation using arm instructions. example 23-1. cspi operation using arm instructions ldr r0, =cspi_base_address ; load cspi base address to r0 ldr r1, =0x00008c1f ; master mode, 32-bit transaction str r1, [r0, #0x08] ldr r1, =0x00000021 ; enable rxfifo half and txfifo empty str r1, [r0, #0x0c] ; interrupt (alternatively with dma mode) ldr r1, =0x00005000 ; enable rxfifo half and txfifo empty configure control reg configure intreg (optional) configure dmareg (optional) configure periodreg (optional) fill txfifo set xch bit polling xch bit or waiting tshfe interrupt read data from rxfifo fill txfifo configure controlreg transfer completed waiting rxfifo interrupt (ready, half full, full) read data from rxfifo transfer completed master mode slave mode configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-13 str r1, [r0, #0x18] ; dma (alternatively with interrupt) ldr r5, =0x05 ; r5 as number of words to be transferred. ldr r1, =0x11111111 ; r1 as increment to generate the data. ldr r2, =0x12345678 ; r2 load the data to be transferred. loop_00 str r2, [r0,#0x04] ; store data into txfifo. add r2, r2, r1 ; generating next data to be transferred. sub r5, r5, #1 ; decrease the r5. cmp r5, #0x00 ; check r5 if it is zero. bne loop_00 ; loop until r5 is zero. ldr r1, =0x00008e1f ; set xch bit to start transaction. str r1, [r0, #0x08] loop_01 ldr r1, [r0, #0x0c] ; check tshfe bit if it is set. ldr r2, =0x00000008 and r1, r2, r1 cmp r1, #0x00 bne pass_00 ; if tshfe bit is set then finish. b loop_01 ; if it isn?t set then continue loop ldr r1, [r0, #0x00] ; read data from rxfifo. 23.4.1 software restrictions the section should include software re strictions that impact the customer. ? all reserved bits cannot be written and always read as 0. ? writes to the txdata register are ignored when the cspi module is disabled (spien bit of cspi controlreg is cleared). ? the spi module enable control bit must be assert ed before writing to other registers or initiating an exchange. 23.5 memory map and register definition the cspi includes eight 32-bit registers. section 23.5.3, ?register descriptions ? provides the detailed descriptions for the cspi registers. the followi ng sections provide the register summary and the configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-14 freescale semiconductor programming model for the 3 cspi modules in the i.mx27. the register summary in table 23-3 lists all registers of the cspi module by ascending address. the abso lute address of each register is given, as is the value of each bit for reads and writes. 23.5.1 memory map table 23-1 shows the cspi memory map. 23.5.2 register summary figure 23-14 shows the key to the register fields, and table 23-2 shows the register figure conventions. figure 23-14. key to register fields table 23-1. cspi memory map address register access reset value section/page 0x1000_e0000 (rxdata) receive data register (rxdata) r 0x0000_0000 23.5.3.1/23-16 0x1000_e0004 (txdata) transmit data register (txdata) w 0x0000_0000 23.5.3.2/23-17 0x1000_e0008 (conreg) control register (conreg) r/w 0x0000_0000 23.5.3.3/23-18 0x1000_e000c (intreg) interrupt control register (intreg) r/w 0x0000_0000 23.5.3.4/23-20 0x1000_e0010 (dmareg) dma control register (dmareg) r/w 0x0000_0000 23.5.3.5/23-22 0x1000_e0014 (statreg) status register (statreg) r/w 0x0000_0003 23.5.3.6/23-23 0x1000_e0018 (periodreg) sample period control register (periodreg) r/w 0x0000_0000 23.5.3.7/23-24 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 23-2. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-15 reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 23-3. cspi register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxdatareg 0x1000 e000 0x1000 f000 0x1001 7000 r rxdata[31:16] w r rxdata[15:0] w txdatareg 0x1000 e004 0x1000 f004 0x1001 7004 r w tx data [31:16] r w tx data [15:0] controlreg 0x1000 e008 0x1000 f008 0x1001 7008 r00000 0 0 0 bur st sdh c_s pien sw ap cs[1:0] datarate[4:2] w r datarate[ 1:0] dr ctl[1:0] mo de spie n xch ssp ol ssc tl pha pol bit count[4:0] w intreg 0x1000 e00c 0x1000 f00c 0x1001 700c r00000 0 0 0 0 0 00 0 0 bo en roe n w r rfe n rhe n rr en tsh fee n tfe n the n teen bo ro rf rh rr tshf e tf th te w te s t r e g 0x1000 e010 0x1000 f010 0x1001 7010 r00000 0 0 0 0 0 00 0 00 0 w r lbc init ss_ ass ert sstatus[3:0] rxcnt[3:0] txcnt[3:0] w table 23-2. register figure conventions (continued) convention description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-16 freescale semiconductor 23.5.3 register descriptions the following section describes the detailed re gister descriptions for the cspi registers. 23.5.3.1 receive data register (rxdata) the receive data register (rxdata) is a read-only register that forms the top word of the 8 32 receive fifo. this register holds the data received from an external spi device during a data transaction. only word-sized read operations are allowed. figure 23-15 shows the rxdata register, and table 23-4 shows the register?s field descriptions. periodreg 0x1000 e014 0x1000 f014 0x1001 7014 r00000 0 0 0 0 0 00 0 000 w r csr c wait[14:0] w dmareg 0x1000 e018 0x1000 f018 0x1001 7018 r00000 0 0 0 0 0 00 0 000 w r thd en ted en rf d en rhd en 00 0 0 th dma te dma rf dm a rh dm a 0000 w resetreg 0x1000 e01c 0x1000 f01c 0x1001 701c r00000 0 0 0 0 0 00 0 000 w r00000 0 0 0 0 0 00 0 00 sta rt w table 23-3. cspi register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-17 23.5.3.2 transmit data register (txdata) the transmit data (txdata) register is a write-only data register that forms the top word of the 8 32 txfifo. the txfifo can be written to as long as it is not full, even when the xch bit in conreg is set. this allows the user write access to the txfifo during a spi data exchange process. writes to this register are ignored when the cspi module is di sabled (en bit of cspi conreg is cleared). figure 23-16 shows the cntrl register, and table 23-5 shows the register?s field descriptions. 0x1000_e0000 (rxdata) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rxdata[31:16] w reset0000000000000000 1514131211109876543210 r rxdata[15:0] w reset0000000000000000 figure 23-15. rxdata register diagram table 23-4. rxdata register field descriptions field description 31?0 rxdata receive data. this register holds the top word of the receive data fifo. the fifo is advanced for each read of this register. the data read is undefined when the receive data ready (rr) bit in the interrupt control/status register is cleared. zeros are read when cspi is disabled. 0x1000_e0004 (txdata) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w txdata[31:16] reset0000000000000000 1514131211109876543210 r w txdata[15:0] reset0000000000000000 figure 23-16. txdata register diagram configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-18 freescale semiconductor 23.5.3.3 control register (conreg) the control register (conreg) allo ws the user to enable the cspi module, configure its operating modes, specify the divider value, phase, and polarity of the clock, configure the ss and spi_rdy control signal, and define the transfer length. the reserved bits are always read as 0. figure 23-17 shows the cntrl register, and table 23-6 shows the register?s field descriptions. table 23-5. txdata register field descriptions field description 31?0 txdata transmit data. this register holds the top word of data loaded into the fifo. data written to this register must be a word operation. the number of bits actually transmitted is determined by the bit_count field of the corresponding spi control register. if this field contains more bits than the number specified by bit_count, the extra bits are ignored. for example, to transfer 10 bits of data, a 32-bit word must be written to this register. bits 9-0 are shifted out and bits 31-10 are ignored. when the cspi module is operating in slave mode, zeros are shifted out when the fifo is empty. zeros are read when cspi is disabled. 0x1000_e0008 (conreg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 chip select 00 drctl 0 data rate w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 bit count sspol ssctl pha pol smc xch mode en w reset00000000 0 0 000000 figure 23-17. cspi control register table 23-6. conreg register field descriptions field description 31?26 reserved, all bits should read zero. 25?24 chip select chip select. select one of four external spi master/slave devices. in master mode, these two bits select the external slave devices by asserting the ss n outputs.only the selected ss n signal will be active while the remaining 3 signals will be negated. chip select 00 ss 0 will be asserted. 01 ss 1 will be asserted. 10 ss 2 will be asserted. 11 ss 3 will be asserted. 23?22 reserved, all bits should read zero. configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-19 21?20 drctl spi data ready control. this 2-bit field selects the utilization of the spi_rdy in master mode. cspi will check this fields before it start a spi burst. 00 don?t care spi_rdy 01 burst will be triggered by failing edge of spi_rdy . 10 burst will be triggered by low level of spi_rdy . 11 rsv . 19 reserved, all bits should read zero. 18?16 data rate spi data rate control. this three-bit field selects the baud rate of the sclk based on a division of the ipg_clk. these bits allow cspi to synchronize with different external spi devices. the max frequency is one quarter of ipg_clk. the divide ratio is determined according to the following table using the equation: 2 (n+2) . spi data rate control (master mode only) 000 divide by 4. 001 divide by 8. 010 divide by 16. 011 divide by 32. 100 divide by 64. 101 divide by 128. 110 divide by 256. 111 divide by 512. 15-13 reserved, all bits should read zero. 12?8 bit count this field selects the length of a word to be transferred. a maximum of 32 bits can be transferred in a single spi transfer. multiple transfers may be chained together to form unlimited length messages using the ssctl bit to keep the ss asserted between transfers. in master mode, bitcount controls the number of bits per serial transfer. the transmit fifo transfers a 32-bit data word to the shift register, however only the n least-significant (n=bit count + 1) are shifted out. the remaining bits are ignored. in slave mode, provided ssctl= 0, this field controls the number of bits (bit count + 1) received in each data word. after bitcount + 1 bits have been shifted into the shift register, the contents are transferred to the receive fifo regardless of the state of the ss input. when ssctl bit is 1, data transfer to/from the fifo are controlled by the ss input and this field is ignored. spi data rate control (master mode only) 00000 least 1 bit of a word to be transferred. 00001 least 2 bits of a word to be transferred. ..... 01111 least 16 bits of a word to be transferred. 10000 least 17 bits of a word to be transferred. ..... 11110 least 31 bits of a word to be transferred. 11111 all 32 bits of a word to be transferred. 7 sspol spi ss polarity select. in both master and slave mode, this bit selects the polarity of the ss signal. 0active low 1 active high table 23-6. conreg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-20 freescale semiconductor 23.5.3.4 interrupt control register (intreg) the 32-bit interrupt control register (intreg) enab les the generation of interrupts to the mcu. the reserved bits cannot be written and always read as 0. if cspi is disabled, this register reads zero. figure 23-18 shows the cntrl register, and table 23-7 shows the register?s field descriptions. 6 ssctl in master mode, this bit selects the output wave form for the ss signal. 0 ss remains asserted between spi bursts. 1 negate ss between spi bursts. in slave mode, this bit controls the timing of data transfer from the shift register to the receive fifo. 0 rxfifo advanced by bit count. 1 rxfifo advanced by ss edge. (sspol = 0: rising edge; sspol = 1: falling edge) 5 pha spi clock/data phase control. this bit controls the clock/data phase relationship. 0 phase 0 operation. 1 phase 1 operation. 4 pol spi clock polarity control. this bit controls the polarity of the sclk signal. 0 active high polarity (0 = idle) 1 active low polarity (1 = idle) 3 smc start mode control. this bit is used in master mode only and it controls how cspi start a spi burst. 0 xch bit controls when a spi burst can start. write a 1 to xch bit will start a spi burst or multiple bursts. (controlled by ssctl) 1 immediately start a spi burst when data is written in txfifo. 2 xch spi exchange bit. if the smc bit is cleared, writing a 1 to this bit starts one spi bursts/multiple spi bursts according to ssctl bit. this bit remains set while either the exchange is in progress, or the cspi is waiting for active input if spirdy is enabled through drctl. this bit is cleared automatically when all data in the txfifo and shift register have been shifted out. in slave mode, this bit is ignored. 0idle 1 initiates exchange (write) or busy (read) 1 mode spi function mode select. this bit selects the operating mode of the cspi. 0slave mode 1master mode 0 en spi module enable control. this bit enables the cspi. this bit must be asserted before writing to other registers or initiating an exchange. writing zero to this bit disables the module and resets the internal logic with the exception of the conreg. the module?s internal clocks are gated off whenever the module is disabled. 0 cspi is disabled. 1 cspi is enabled. table 23-6. conreg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-21 0x1000_e000c (intreg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 0 0 0 0 0 0 0 0 w reset00000000 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000 tcen boen roen rfen rhen rren tfen then teen w reset00000000 0 0 0 0 0 0 0 0 figure 23-18. interrupt control register diagram table 23-7. intreg register field descriptions field description 31?9 reserved, all bits should read zero. 8 tcen transfer completed interrupt enable. this bit enables the transfer completed interrupt. 0 disable 1enable 7 boen bit counter overflow interrupt enable. this bit enables the bit counter overflow interrupt (more than 32 bits are received in a word). 0 disable 1enable 6 roen rxfifo overflow interrupt enable. the bit enables the rxfifo overflow interrupt. 0 disable 1enable 5 rfen rxfifo full interrupt enable. the bit enables the rxfifo full interrupt. 0 disable 1enable 4 rhen rxfifo half full interrupt enable. the bit enables the rxfifo half full interrupt. 0 disable 1enable 3 rren rxfifo ready interrupt enable. the bit enables the rxfifo ready interrupt. 0 disable 1enable 2 tfen txfifo full interrupt enable. the bit enables the txfifo full interrupt. 0 disable 1enable configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-22 freescale semiconductor 23.5.3.5 dma control register (dmareg) the dma control register (dmareg) provides the user a way to use the cspi in dma. direct memory access (dma) allows transfer of data between de vice and memory. peripherals such as the cspi supporting dma use dma request and acknowledge si gnals. the cspi sends out dma requests when the appropriate fifo conditions are matched. the reserv ed bits cannot be written to and are always read as 0. if the cspi is disabled, this register is also read as 0. figure 23-19 shows the cntrl register, and table 23-8 shows the register?s field descriptions. 1 then txfifo half empty interrupt enable. the bit enables the txfifo half empty interrupt. 0 disable 1enable 0 teen txfifo empty interrupt enable. the bit enables the txfifo empty interrupt. 0 disable 1enable 0x1000_e0010 (dmareg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0000000 0 0 0 0 0 0 0 0 w reset0 0000000 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0000000 0 0 rf den rh den 00 th den te den w reset0 0000000 0 0 0 0 0 0 0 0 figure 23-19. dma control register diagram table 23-8. dmareg register field descriptions field description 31?6 reserved, all bits should read zero. 5 rfden rxfifo full dma request enable. this bit enables/disables the rxfifo full dma request. 0 disable 1 enable 4 rhden rxfifo half full dma request enable. this bit enables/disables the rxfifo half full dma request. 0 disable 1 enable 3?2 reserved, should be cleared. table 23-7. intreg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-23 23.5.3.6 status register (statreg) the cspi status register (statreg) reflects the status of the cspi modul e operating condition. the reserved bits cannot be written and always read as 0. if the cspi is disabled, this register reads 0x0000_0003. figure 23-20 shows the cntrl register, and table 23-9 shows the register?s field descriptions. 1 thden txfifo half empty dma request enable. this bit enables/disables the txfifo half empty dma request. 0 disable 1 enable 0 teden txfifo empty dma request enable. this bit enables/disables the txfifo empty dma request. 0 disable 1 enable 0x1000_e0014 (statreg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 0 0 0 0 0 0 0 0 w reset00000000 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 tc bo ro rf rh rr tf th te w w1c w1c reset00000000 0 0 0 0 0 0 1 1 figure 23-20. status register diagram table 23-9. statreg register field descriptions field description 31?9 reserved, should be cleared. 8 tc transfer completed. when set, this bit indicates that all the data in txfifo has been loaded in the shift register, and the shift register has shifted out all the bits. writing 1 to this bit clears it. 0busy 1transfer completed 7 bo bit counter overflow. when set, this bit indicates that bit counter is overflows while the configurable serial peripheral interface is in slave mode (mode = 0) with ssctl = 1. writing 1 to this bit clears it. 0 bit counter is not overflowed. 1 bit counter is overflowed. table 23-8. dmareg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-24 freescale semiconductor 23.5.3.7 sample period control register (periodreg) the sample period control register (periodreg) provid es the user a way to insert delays (wait states) between consecutive spi transfers. control bits in this register select the clock source for the sample period counter and the delay count indicating the number of wait states to be inserted between data transfers. delay counts are only applicable when the cspi module is operating in master mode. figure 23-21 shows the cntrl register, and table 23-10 shows the register?s field descriptions. 6 ro rxfifo overflow. when set, this bit indicates that rxfifo has overflowed. 0 rxfifo is available. 1 rxfifo has overflowed. 5 rf rxfifo full. this bit is set when the rxfifo is full (8 words). 0not full 1full 4 rh rxfifo half full. this bit is set if the rxfifo is half full ( 4 words in rxfifo). 0 less than 4 words are stored in rxfifo. 1 four or more words are available in rxfifo. 3 rr rxfifo ready. this bit is set any time there is one or more words stored in rxfifo ( 1 words). 0 no valid data in rxfifo 1 more than 1 word in rxfifo 2 tf txfifo full. this bit is set when if the txfifo is full (8 words). 0 txfifo is not full. 1 txfifo is full. 1 th txfifo half empty. this bit is set if the txfifo is more than half empty ( 4 words in txfifo). 0 txfifo holds more than 4 words. 1 txfifo holds 4 or fewer words. 0 te txfifo empty. this bit is set if the txfifo is empty. 0 txfifo contains one or more words. 1 txfifo is empty. 0x1000_e0018 (periodreg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0000000 0 0 0 0 0 0 0 0 w reset0 0000000 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r csrc sample period w reset0 0000000 0 0 0 0 0 0 0 0 figure 23-21. sample period control register diagram table 23-9. statreg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-25 23.5.3.8 test control register (testreg) the test control register (testreg) provides the us er a mechanism to internally connect the receive and transmit devices of the cspi module, display the st atus of the state machine, monitor the contents of the receive and transmit fifo, and debug the cspi. figure 23-22 shows the cntrl register, and table 23-11 shows the register?s field descriptions. table 23-10. periodreg register field descriptions field description 31?16 reserved, all bits should read zero. 15 csrc clock source control. this bit selects the clock source for the sample period counter. 0 spi clock (sclk) 1 ckil (32.768 khz) 14?0 sample period sample period control. these bits control the number of wait states to be inserted in data transfers. during the idle clocks, the state of the ss output will operate according to the ssctl control field in conreg. 0x0000 0 wait states inserted 0x0001 1 wait state inserted ...... ...... 0x7ffe 32766 wait states inserted 0x7fff 32767 wait states inserted 0x1000_e01c0 (testreg) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0000000 0 0 0 0 0 0 0 0 w reset0 0000000 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r swap lbc 0 0 smstatus rxcnt txcnt w reset0 0000000 0 0 0 0 0 0 0 0 figure 23-22. test control register diagram table 23-11. testreg register field descriptions field description 31?16 reserved, all bits should be read as zero. 15 swap data swap. this bit is used to swap data as it is read from the rxfifo. when this bit is set, data read from rxfifo is swapped. rxdata[31:0] is swapped as follows: {rxdata[7:0],rxdata[15:8], rxdata[23:16],rxdata[31:24]} 0 data read from rxfifo is unchanged. 1 data read from rxfifo is swapped. configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-26 freescale semiconductor 23.6 timing diagrams figure 23-23 and figure 23-24 depict the master mode and slave mode timing diagrams of the cspi and table 23-12 lists the timing parameters. the values shown in timing diagrams were tested using a worst case core voltage of 1.1 v, slow pad volta ge of 2.68 v, and fast pad voltage of 1.65 v. 14 lbc loopback control. this bit is used in master mode only. when this bit is set, the cspi module connects the transmitter and receiver sections internally, and the data shifted out from the most-significant bit of the shift register is looped back into the least-significant bit of the shift register. in this way, a self-test of the complete transmit/receive path can be made. the output pins are not affected, and the input pins are ignored. 0 not connected. 1 internally connected. 13?12 reserved, all bits should read zero. 11?8 smstatus state machine status. these bits indicate status of the state machine for test purpose. 7?4 rxcnt rxfifo counter. these bits indicate the number of words in rxfifo. 0000 0 word in rxfifo 0001 1 word in rxfifo ...... ...... 0111 7 words in rxfifo 1000 8 words in rxfifo 3?0 txcnt txfifo counter. these bits indicate the number of words in txfifo. 0000 0 word in txfifo 0001 1 word in txfifo ...... ...... 0111 7 words in txfifo 1000 8 words in txfifo table 23-11. testreg register field descriptions (continued) field description configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 23-27 figure 23-23. cspi master mode timing diagram figure 23-24. cspi slave mode timing diagram table 23-12. cspi interface timing parameters id num parameter description symbol minimum maximum units t1 cspi master sclk cycle time t clko 45.12 - ns t2 cspi master sclk high time t clkoh 22.65 ? ns t3 cspi master sclk low time t clkol 22.47 ? ns t1 t10 t3 t2 ssn sclk mosi miso cspi1_rdy (input) (output) t8 t6 t4 t4 t5 t7 t9 (output) t11 t12 t13 t1? t10 t3? t2? ssn sclk miso mosi (input) t4 t4 t5? t7? (input) t11 t12 t13 t6? t14 t14 configurable serial peripheral interface (cspi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 23-28 freescale semiconductor t1? cspi slave sclk cycle time t clki 60.2 ? ns t2? cspi slave sclk high time t clkih 30.1 ? ns t3? cspi slave sclk low time t clkil 30.1 ? ns t4 cspi sclk transition time t pr 1 2.6 8.5 ns t5 ssn output pulse width t wsso 2t sclk 2 +t wait 3 ?? t5? ssn input pulse width t wssi t per 4 ?? t6 ssn output asserted to first sclk edge (ss output setup time) t ssso 3t sclk ?? t6? ssn input asserted to first sclk edge (ss input setup time) t sssi t per ?? t7 cspi master: last sclk edge to ssn deasserted (ss output hold time) t hsso 2t sclk ?? t7? cspi slave: last sclk edge to ssn deasserted (ss input hold time) t hssi 30 ? ns t8 cspi master: cspi1_rdy low to ssn asserted (cspi1_rdy setup time) t srdy 2t per 5t per ? t9 cspi master: ssn deasserted to cspi1_rdy low t hrdy 0?ns t10 output data setup time t sdatao (t clkol or t clkoh or t clkil or t clkih ) - t ipg 5 ?? t11 output data hold time t hdatao t clkol or t clkoh or t clkil or t clkih ?? t12 input data setup time t sdatai t ipg + 0.5 ? ns t13 input data hold time t hdatai 0?ns t14 pause between data word t pause 0?ns 1 the output sclk transition time is tested with 25pf drive. 2 t sclk = cspi clock period 3 t wait = wait time as per the sample period control register value. 4 t per = cspi reference baud rate clock period (perclk2) 5 t ipg = cspi main clock ipg_clock period table 23-12. cspi interface timing parameters (continued) id num parameter description symbol minimum maximum units MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-1 chapter 24 inter-integrated circuit (i 2 c) the inter-integrated circuit (i 2 c) module provides the functionality of a standard i 2 c slave and master. the i 2 c module is designed to be compatib le with the standard philips i 2 c bus protocol. the i.mx27 device contains two identical i 2 c modules. figure 24-1 shows the i 2 c block diagram. figure 24-1. i 2 c block diagram signals connected to pads address compare in/out data shift start, stop, input sync clock control registers interface address decode i 2 c address data mux sda scl address irq data and arbitration control register ip bus register (iadr) i 2 c frequency divider register (ifdr) i 2 c data i/o register (i2dr) i 2 c status register (i2sr) i 2 c control register (i2cr) inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-2 freescale semiconductor 24.1 overview the i 2 c is a two-wire, bidirectional serial bus that pr ovides a simple, efficient method of data exchange, minimizing the interconnection between devices. this bus is suitable for appli cations requiring occasional communications over a short distance between many devices. the flexible i 2 c allows additional devices to be connected to the bus for expansion and system development. figure 24-2 provides the connection diagram. figure 24-2. connection of devices to i 2 c bus the i 2 c operates up to 400 kbps, but it depends on the pa d loading and timing. for pad requirement details, refer to philips i 2 c bus specification, version 2.1. the i 2 c system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. 24.1.1 features the i 2 c module has the following key features: ? compatibility with i 2 c bus standard ? multiple-master operation ? software-programmable for one of 64 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt +vdd rp rp pull-up sda (serial data line) scl (serial clock line) resistors ipp_sda_out1 ipp_sda_in1 ipp_scl_out ipp_scl_in1 1 ipp_sda_in2 ipp_sda_out2 ipp_scl_out2 ipp_scl_in2 device1 device2 inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-3 ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection 24.2 external signal description two pins are required for i 2 c: ? i2c_scl bidirectional clock pin ? i2c_sda bidirectional data pin for i 2 c compliance, all devices connected to the scl and sda signals must have open-drain or open-collector outputs. the logic and function is exer cised on both lines with external pull-up resistors. the module port signals going to the pad are tabulated in table 24-2 . 24.2.1 detailed external signal descriptions the following three signals are connected to the bidirectional driver for the scl i/o pad (through the iomux module): ? ipp_scl_in?serial input clock ? ipp_scl_out?serial output clock ? ipp_scl_out_en?serial output clock enable the pad needs to have open-drain connectivity. i pp_scl_in will be the input signal from the pad. ipp_scl_out will be the output to the pad from the module. ipp_scl_out_en will act as the output enable. the following three signals are connected to the bi directional driver for the sda i/o pad (through the iomux module): ? ipp_sda_in?serial input data ? ipp_sda_out?serial output data ? ipp_sda_out _en?serial output data enable table 24-2. signal properties name port function reset state pull-up ipp_scl_in ? serial clock input 1 ? ipp_scl_out ? serial clock output 1 active ipp_scl_out_en ? serial clock output enable 0 ? ipp_sda_in ? serial data input 1 ? ipp_sda_out ? serial data output 1 active ipp_sda_out_en ? serial data output enable 0 ? inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-4 freescale semiconductor the pad should have open-drain connectivity. ipp_ sda_in will be the input signal from the pad. ipp_scl_out will be the output to the pad from module. ipp_sda_out_en will act as the output enable. 24.3 memory map and register definition the i 2 c module contains five 16-bit registers. section 24.3.3, ?register descriptions ? provides the detailed descriptions for all of the i 2 c registers. 24.3.1 i 2 c memory map table 24-3 shows the i 2 c memory map. note there are registers at addresses 0x1001_02, 0x1001_06, 0x1001_a, 0x1001_0e, which are reserved for future additions. 24.3.2 register summary figure 24-3 shows the key to the register fields, and table 24-5 shows the register figure conventions. figure 24-3. key to register fields table 24-3. i 2 c memory map address register access reset value section/page 0x1001_2000 (iadr1) 0x1001_d000 (iadr2) i 2 c address register r/w 0x0000 24.3.3.1/24-6 0x1001_2004 (ifdr1) 0x1001_d004 (ifdr2) i 2 c frequency divider register r/w 0x0000 24.3.3.2/24-6 0x1001_2008 (i2cr1) 0x1001_d008 (i2cr2) i 2 c control register r/w 0x0000 24.3.3.3/24-7 0x1001_200c (i2sr1) 0x1001_d008 (i2cr2) i 2 c status register r/w 0x0081 24.3.3.4/24-9 0x1001_2010 (i2dr1) 0x1001_d010 (i2dr2) i 2 c data i/o register r/w 0x0000 24.3.3.5/24-10 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 24-5. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-5 table 24-4 shows the i 2 c register summary. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 24-4. i 2 c register summary name 1514131211109876543210 0x1001_2010 (i2dr1) 0x1001_d010 (i2dr2) r0 0000000 adr 0 w 0x1001_2004 (ifdr1) 0x1001_d004 (ifdr2) r0 000000000 ic w 0x1001_2008 (i2cr1) 0x1001_d008 (i2cr2) r0 0000000 ien iien mst a mtx txa k 000 w rst a 0x1001_200c (i2sr1) 0x1001_d00c (i2sr2) r 0 0000000icf iaa s ibb ial 0 sr w iif rxa k w 0x1001_2010 (i2dr1) 0x1001_d010 (i2dr2) r0 0000000 data w table 24-5. register figure conventions (continued) convention description inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-6 freescale semiconductor 24.3.3 register descriptions this section contains the detailed register descriptions for the i 2 c registers in address order. 24.3.3.1 i 2 c address register (iadr) figure 24-6 shows the i 2 c address register; table 24-5 provides its field descriptions. the iadr holds the address the i 2 c responds to when addressed as a slave. note the slave address is not the address sent on the bus during the address transfer. this register is not reset by a software reset. 24.3.3.2 i 2 c frequency register (ifdr) the ifdr provides a programmable prescaler to confi gure the clock for bit-rate selection. the register does not get reset by software reset. figure 24-7 shows the i 2 c frequency register; table 24-6 provides its field descriptions. 0x1001_2000 (iadr1) 0x1001_d000 (iadr2) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 adr 0 w reset00000000000000 00 figure 24-6. i 2 c address register table 24-5. i 2 c address register field descriptions field description 15?8 reserved 7?1 adr slave address. contains the specific slave address to be used by the i 2 c module. slave mode is the default i 2 c mode for an address match on the bus. 0reserved 0x1001_2004 (ifdr1) 0x1001_d004 (ifdr2) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 ic w reset00000000000000 00 figure 24-7. i 2 c frequency register inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-7 24.3.3.3 i 2 c control register (i2cr) the i2cr is used to enable the i 2 c module and the i 2 c interrupt. it also contains bits that govern operation as a slave or a master. figure 24-8 shows the i 2 c control register; table 24-8 provides its field descriptions. table 24-6. i 2 c frequency register field descriptions field description 15?6 reserved 5?0 ic i 2 c clock rate. prescales the clock for bit-rate selection. due to potentially slow scl and sda rise and fall times, bus signals are sampled at the prescaler frequency. the serial bit clock frequency is equal to ipg_clk_patref divided by the divider shown in table 24-7 . note: the ic can be changed anywhere in a program. i 2 c protocol supports bit rates up to 400 kbps. the ic bits need to be programmed in accordance with this constraint. table 24-7. ifdr register field values ic divider ic divider ic divider ic divider 0x00 30 0x10 288 0x20 22 0x30 160 0x01 32 0x11 320 0x21 24 0x31 192 0x02 36 0x12 384 0x22 26 0x32 224 0x03 42 0x13 480 0x23 28 0x33 256 0x04 48 0x14 576 0x24 32 0x34 320 0x05 52 0x15 640 0x25 36 0x35 384 0x06 60 0x16 768 0x26 40 0x36 448 0x07 72 0x17 960 0x27 44 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0a 104 0x1a 1536 0x2a 64 0x3a 896 0x0b 128 0x1b 1920 0x2b 72 0x3b 1024 0x0c 144 0x1c 2304 0x2c 80 0x3c 1280 0x0d 160 0x1d 2560 0x2d 96 0x3d 1536 0x0e 192 0x1e 3072 0x2e 112 0x3e 1792 0x0f 240 0x1f 3840 0x2f 128 0x3f 2048 inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-8 freescale semiconductor 0x1001_2008 (i2cr1) 0x1001_d008 (i2cr2) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 ien iien msta mtx txak 000 w rsta reset00000000000000 00 figure 24-8. i 2 c control register table 24-8. i 2 c control register field descriptions field description 15?8 reserved 7 ien i 2 c enable. also controls the software reset of the entire i 2 c module. resetting the bit generates an internal reset to the module. if the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next start condition is detected. master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the i 2 c module to lose arbitration. after which, bus operation returns to normal. 0 the module is disabled, but registers can still be accessed. 1the i 2 c module is enabled. this bit must be set before any other i2cr bits have any effect. 6 iien i 2 c interrupt enable. 0i 2 c module interrupts are disabled, but the status flag i2sr[iif] continues to be set when an interrupt condition occurs. 1i 2 c module interrupts are enabled. an i2c interrupt occurs if i2sr[iif] is also set. 5 msta master/slave mode select bit. if the master loses arbitration, msta is cleared without generating a stop signal. note: module clock should be on for writing to the msta bit. 0 slave mode. changing msta from 1 to 0 generates a stop and selects slave mode. 1 master mode. changing msta from 0 to 1 signals a start on the bus and selects master mode. 4 mtx transmit/receive mode select bit. selects the direction of master and slave transfers. 0receive. when a slave is addressed, the software should set mtx according to the slave read/write bit in the i 2 c status register (i2sr[srw]). 1 transmit. in master mode, mtx should be set according to the type of transfer required. therefore, for address cycles, mtx is always 1. 3 txak transmit acknowledge enable. specifies the value driven onto sda during acknowledge cycles for both master and slave receivers. note: writing txak applies only when the i 2 c bus is a receiver. 0 an acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 no acknowledge signal response is sent (that is, the acknowledge bit = 1). 2 rsata repeat start. always reads as 0. attempting a repeat start without bus mastership causes loss of arbitration. 0 no repeat start 1 generates a repeated start condition 1?0 reserved inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-9 24.3.3.4 i 2 c status register (i2sr) the i2sr contains bits that indicate transaction direction and status. figure 24-9 shows the i 2 c address register; and table 24-9 provides its field descriptions. 0x1001_200c (i2sr1) 0x1001_d00c (i2sr2) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 00000000icfiaasibb ial 0srw iif rxa k w reset00000000100000 01 figure 24-9. i 2 c status register table 24-9. i 2 c status register field descriptions field description 15?8 reserved 7 icf data transferring bit. while one byte of data is transferred, icf is cleared. 0 transfer is in progress. 1 transfer is complete, and set by the falling edge of the ninth clock of a byte transfer. 6 iaas i 2 c addressed as a slave bit. the cpu is interrupted if the interrupt enable (i2cr[iien]) is set. the cpu must check the slave read/write bit (srw) and set its tx/rx mode accordingly. writing to i2cr clears this bit. 0 not addressed 1 addressed as a slave. set when its own address (iadr) matches the calling address. 5 ibb i 2 c bus busy bit. indicates the status of the bus. 0 bus is idle. if a stop signal is detected, ibb is cleared. 1 bus is busy. when start is detected, ibb is set. 4 ial arbitration lost. set by hardware in the following circumstances (ial must be cleared by software by writing a ?0? to it): sda input sampled low when the master drives high during an address or data-transmit cycle. sda input sampled low when the master drives high during the acknowledge bit of a data-receive cycle. for the above two cases, the bit is set at the falling edge of 9th scl clock during the ack cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected when the master did not request it. note: software cannot set the bit. 0 no arbitration is lost. 1 arbitration is lost. 3reserved 2 srw slave read/write. when the i 2 c is addressed as a slave, iaas is set, and the slave read/write bit (srw) indicates the value of the r/w command bit of the calling address sent from the master. srw is valid only when a complete transfer has occurred, no other transfers have been initiated, and the i 2 c module is a slave and has an address match. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-10 freescale semiconductor 24.3.3.5 i 2 c data register (i2dr) in master-receive mode, reading the data register (i2dr) allows a read to occur and initiates the next byte to be received. in slave mode, the same f unction is available after it is addressed. figure 24-10 shows the i 2 c data register; table 24-10 provides its field descriptions. note the core-written value in i2dr cannot be read back by the core: only data written by the i 2 c bus side can be read. 1 iif i 2 c interrupt. must be cleared by the software by writing a ?0? to it in the interrupt routine. note: the software cannot set the bit. 0no i 2 c interrupt is pending. 1 an interrupt is pending. this causes a processor interrupt request (if the interrupt enable is asserted [iien = 1]). the interrupt is set when one of the following occurs: one byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). an address is received that matches its own specific address in slave-receive mode. arbitration is lost. 0 rxak received acknowledge. this is the value received of the sda input for the acknowledge bit during a bus cycle. 0 an ?acknowledge? signal was received after the completion of an 8-bit data transmission on the bus. 1 a ?no acknowledge? signal was detected at the ninth clock. 0x1001_2010 (i2dr1) 0x1001_d010 (i2dr2) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 data w reset00000000000000 00 figure 24-10. i 2 c data register table 24-10. i 2 c data register field descriptions field description 15?8 reserved 7?0 data data byte. holds the last data byte received or the next data byte to be transferred. software writes the next data byte to be transmitted or reads the data byte received. table 24-9. i 2 c status register field descriptions (continued) field description inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-11 24.4 functional description 24.4.1 i 2 c system configuration out of a reset, the i 2 c module defaults to slave receive operations. thus, when not operating as a master or responding to a slave transmit address, the i 2 c module will default to the slave receiver state. for exceptions, see section 24.5.1, ?initialization sequence .? note the i 2 c module is designed to be co mpatible with the philips i 2 c bus protocol. for information on syst em configuration, protocol, and restrictions, refer to the i 2 c bus specification, version 2.1. the i 2 c module supports standard and fast modes only. 24.4.2 i 2 c protocol the i 2 c communication protocol consists of six components, as follows: ?start ? data source/recipient ? data direction ? slave acknowledge ? data acknowledge ?stop see figure 24-11 for the i 2 c standard communication protocol, as defined in the following sections. figure 24-11. i 2 c standard communication protocol 24.4.2.1 start signal when no other device is a bus master (both scl and sda lines are at logic high), a device can initiate communication by sending a start signal (see a in figure 24-11 ). a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a data transfer (each data transfer can be several byt es long) and awakens all slaves. 12345678 12345678 9 9 ad7 ad6ad5 ad4 ad3 ad2 ad1r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address r/w ack bit data byte no ack bit stop signal lsb msb lsb msb sda scl start signal a b d c e f inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-12 freescale semiconductor 24.4.2.2 slave address transmission the master sends the slave address in the first byte af ter the start signal (b). after the seven-bit calling address, it sends the r/w bit (c), which tells the slave data transfer direction. each slave must have a unique address. an i 2 c master must not transmit an address that is the same as its slave address; it cannot be master and slave at the same time. the slave whose address matches that sent by the master pulls sda low at the ninth clock (d) to return an acknowledge bit. 24.4.2.3 data transfer when successful slave addressing is achieved, the data transfer can proceed (e) on a byte-by-byte basis in the direction specified by the r/w bit sent by the calling master. data can be changed only while scl is low and must be held stable while scl is high, as shown in figure 24-11 . scl is pulsed once for each data bit, with the mishap being sent first. the receiving device must acknowledge each byte by pulling sda low at the ni nth clock; therefore, a data byte transfer takes nine clock pulses. if it does not acknowledge the master, the slave rece iver must leave sda high. the master can then generate a stop signal to abort the data transfer or generate a start signal (a repeated start, as shown in figure 24-12 ) to start a new calling sequence. if the master receiver does not acknowledge the slav e transmitter after a byte transmission, it means end-of-data to the slave. the slave releases sda for the master to generate a stop or start signal. 24.4.2.4 stop signal the master can terminate communication by generating a stop signal to free the bus. a stop signal is defined as a low-to-high transition of sda while scl is at logical high (f). note a master can generate a stop ev en if the slave has made an acknowledgment; at which point, the slave must release the bus. 24.4.2.5 repeat start instead of signalling a stop, the master can repeat the start signal, followed by a calling command (see a in figure 24-12 ). a repeated start occurs when a start signal is generated wi thout first generating a stop signal to end the communication. the master us es a repeated start to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-13 figure 24-12. repeated start 24.4.3 arbitration procedure if multiple devices simultaneously request the bus, the bus clock is determined by a synchronization procedure in which the low period equals the longe st clock-low period among the devices, and the high period equals the shortest. a data arbitration procedure determines th e relative priority of competing devices. a device loses arbitration if it sends l ogic high while another sends logic low; it immediately switches to slave-receive mode and stops driving sda. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, hardware sets the arbitration lost bit in the i 2 c status register (i2sr[ial] to indicate loss of arbitration. 24.4.4 clock synchronization because wire-and logic is used, a high-to-low tran sition on scl affects devices connected to the bus. devices start counting their low period when the master drives scl low. when a device clock goes low, it holds scl low until the clock high state is reached. ho wever, the low-to-high change in this device clock may not change the state of scl if another device cloc k is still in its low period. therefore, the device with the longest low period holds the synchronized clock sc l low. devices with shorter low periods enter a high wait state during this time (see figure 24-13 ). when all devices involved have counted off their low period, the synchronized clock scl is released and pulle d high. there is then no difference between device clocks and the state of scl, so all of the devices start counting their high periods. the first device to complete its high period pulls scl low again. figure 24-13. synchronized clock scl scl 1234567 8 12 5678 34 ad7 ad6ad5 ad4 ad3 ad2 ad1r/w ad7 ad6 ad5 ad4ad3 ad2 ad1r/w 99 xx new calling address r/w no stop ack bit stop signal repeated start signal ack bit r/w calling address start sda msb lsb msb lsb signal a internal counter reset scl1 scl2 scl wait start counting high period inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-14 freescale semiconductor 24.4.5 handshaking the clock synchronization mechanism can be used as a handshake in data transfers. slave devices can hold scl low after completing one byte transfer (9 bits). in such a case, the clock mechanism halts the bus clock and forces the master clock into a wait state until the slave releases scl. 24.4.6 clock stretching slaves can use the clock synchronization mechanism to slow down the transfer bit rate. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is longer than the master scl low period, the resulting scl bus signal low period is stretched. 24.4.7 ip bus accesses i 2 c is a 16-bit ip module. only halfword accesses should be performed to the module. 24.4.8 generation of transfer error on ip bus if an address is received on the ip slave bus interface that is not implemented, an access error is generated (ips_xfr_err is asserted). the input pin resp_sel pr ovides the configuration capa bility to generate this response. the resp_sel pin must be asserted to enable the ips_xfr_err signal. 24.5 initialization/app lication information 24.5.1 initialization sequence before the interface can transfer serial data, registers must be initialized, as follows: 1. set the data sampling rate (ifdr[ic] to obtai n scl frequency from the system bus clock. see section 24.3.3.2, ?i2c frequency register (ifdr) .? 2. update the address in the (iadr) to define its slave address (address can range from 0 to 0x7f). 3. set the i 2 c enable bit (i2cr[ien]) to enable the i 2 c bus interface system. 4. modify the bits in the i 2 cr to select master/slave mode, transmit/receive mode, and interrupt-enable or not. 24.5.2 generation of start after completion of the initialization procedure, seri al data can be transmitted by selecting the master transmitter mode. on a multiple-master bus system, the busy bus (i2sr[ibb]) must be tested to determine whether the serial bus is free. if the bus is free (ibb = 0), the start signal and the first byte (the slave address) can be sent. the data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction. the free time between a stop and the next start condi tion is built into the hardware that generates the start cycle. depending on the relative frequencies of the system clock and the scl period, it may be inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-15 necessary to wait until the i 2 c is busy after writing the calling address to the data register (i2dr) before proceeding to load data into the data register (i2dr). 24.5.3 post-transfer software response sending or receiving a byte sets the data transf erring bit (i2sr[icf]), which indicates one byte communication is finished. upon completion, the interrupt status (i2sr[iif]) is also set. an external interrupt is generated if the interrupt enable (i2cr[iien] ) is set. the software must first clear the interrupt status (i2sr[iif]) in the interrupt routine. (see the flowchart in figure 24-14 .) the data transferring bit (i2sr[icf]) is cleared either by read ing from i2dr in receive mode or by writing to this register in transmit mode. the software can service the i 2 c i/o in the main program by monitoring the interrupt status (i2sr[iif]) if the interrupt enable is de-asserted. in this case, the in terrupt status should be polled of the data transferring bit (i2sr[icf]) because the operation is different when arbitration is lost. when an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. if master receive mode is requi red, then (i2dr[r/w], i2cr[mtx] should be toggled. during slave-mode address cycles (i2sr[iaas] = 1), the slave read/write bit i2sr[srw] is read to determine the direction of the next transfer. the transmit/receive bit (i2cr[mtx]) should also be programmed accordingly. for slave-mode data cycles (iaas = 0), srw is invalid. mtx should be read to determine the current transfer direction. 24.5.4 generation of stop a data transfer ends when the master signals a stop, which can occur after all data is sent. for a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. this is done by setting the transmit acknowledge bit (i2cr[txak]) before reading the next-to-last byte. before the la st byte is read, a stop signal must be generated. 24.5.5 generation of repeated start after the data transfer, if the master still wants th e bus, it can signal another start followed by another slave address without signalling a stop. 24.5.6 slave mode in the slave interrupt service routine (see figure 24-14 ), the module addressed as slave bit (iaas) should be tested to check if a calling of it s own address has just been received. if iaas is set, software should set the transmit/receive mode select bit (i2cr[mtx]) according to the i2sr[srw]. writing to the i2cr clears the iaas automatically. the only time iaas is r ead as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have iaas cleared. a data transfer can now be initiated by writing information to i2dr for slave transmits, or read from i2dr in slave-receive m ode. a dummy read of i2dr in slave/receive mode releases scl, allowing the master to send data. inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-16 freescale semiconductor in the slave transmitter routine, the receive acknowle dge bit (i2sr[rxak]) must be tested before sending the next byte of data. setting rxak means an end-of-data signal from the master receiver, after which the software must switch it from transmitter to receiver m ode. reading the data register (i2dr) then releases scl so that the master can generate a stop signal. 24.5.7 arbitration lost if several devices try to engage the bus at the sa me time, one becomes master. hardware immediately switches devices that lose arbitration to slave receive mode. data output to sda stops, but scl is still generated until the end of the byte during which arbitrati on is lost. an interrupt occurs at the falling edge of the ninth clock of this transfer if the arbitration is lost (i2sr[ial] = 1), and the slave mode is selected (i2cr[msta] = 0). see the flowchart in figure 24-14 . if a device that is not a master tries to transmit or do a start, hardware inhibits the transmission, clears msta without signalling a stop, generates an interrupt to the cpu, and sets ial to indicate a failed attempt to engage the bus. when considering these cas es, the slave service routine should first test ial, and the software should clear it if it is set. for multi-master mode, when an i 2 c module is enabled when the bus is busy and asserts start, the ial bit gets set only for sda=0, scl=0/1, sda=1, and sc l=0, but not for sda=1 and sca=1, which is the same as bus idle state. inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 24-17 figure 24-14. flowchart of typical i 2 c interrupt routine clear master mode? tx/rx ? last byte transmitted ? rxak= 0 ? end of addr cycle (master rx) ? write next byte to i2dr switch to rx mode dummy read from i2dr generate stop signal read data from i2dr and store set txak =1 generate stop signal 2nd last byte to be last byte to be ? arbitration lost? clear ial iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to i2dr set rx mode dummy read from i2dr ack from receiver ? tx next byte read data from i2dr and store switch to rx mode dummy read from i2dr rte yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iif address cycle data cycle read read? inter-integrated circuit (i 2 c) MCIMX27 multimedia applications processor reference manual, rev. 0.2 24-18 freescale semiconductor note for a repeated start-only, the stop gene ration stage will not occur in master mode. a loop will repeat itself without stopping for the next start. 24.5.8 timing section figure 24-15 provides an illustration of the timing for the seri al data line (sda) and se rial clock line (scl) devices on the i 2 c bus. figure 24-15. definition of timing for devices on i 2 c bus table 24-11 provides a list of bus timing parameters. note see table 24-7 for details for divider values. table 24-11. i 2 c bus timing parameters reference number parameter maximum (w.r.t ipg_clk_patref) minimum (w.r.t ipg_clk_patref) 1 hold time (repeated) start condition ? 4 2 setup time for stop condition ? 4 3 data hold time (0.27) * divider ? 4 high of the scl period ? (0.4) * divider (master mode) 5 low period of the scl clock ? (0.4) * divider (master mode) 1 2 5 sda scl 3 4 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-1 chapter 25 keypad port (kpp) the keypad port (kpp) is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (i/o). figure 25-1 shows the kpp block diagram. figure 25-1. kpp peripheral block diagram 25.1 overview the kpp is designed to interface with the keypad matrix with 2-point contact or 3-point contact keys. the kpp is designed to simplify the software task of scanning a keypad matrix. w ith appropriate software kpdr (5:8) kddr (5:8) kpdr(7:0) keypad matrix up to 8x8 kpcr (5:8) kddr(7:0) glitch suppression logic kpsr to interrupt controller kpcr(7:0) 32 khz pad drivers row enable data direction (kddr) and open drain enable (kpcr) controls pull-up/data direction controls (kddr) controls (kpcr) keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-2 freescale semiconductor support, the kpp is capable of detecting, debouncing, and decoding one or mult iple keys pressed simultaneously on the keypad. 25.1.1 features the kpp includes these distinctive features: ? supports up to an 8 x 8 external key pad matrix ? port pins can be used as general purpose i/o ? open drain design ? glitch suppression circuit design ? multiple-key detection ? long key-press detection ? standby key-press detection ? synchronizer chain clear ? supports a 2-point and 3-point contact key matrix 25.1.2 modes of operation this module supports the following modes of operation: ? run mode?this is the normal func tional mode in which the kpp ca n detect any key press event. ? low power modes?the keypad can detect any ke y press even in low power modes (when there is no mcu clock). 25.2 external signal description 25.2.1 overview there are 16 pins dedicated to the kp p. keypads of any configuration up to eight rows and eight columns are supported through the software c onfiguration of the peripheral pins. any pins not used for the keypad are available as general purpose i/o. the registers are c onfigured such that the pins can be treated as an i/o port up to 16 bits wide. 25.2.1.1 input pins any of the 16 pins associated with the kpp can be co nfigured as inputs by writing a ?0? to the appropriate bits in the kddr. additionally, the least significant 8 bits (row inputs) corresponding to kddr7:0 have internal pull-ups, which are enabled when the pin is used as an input. 25.2.1.2 output pins any of these 16 kpp pins can be configured as output s by writing the appropriate bits in the kddr to a ?1?. additionally, the 8 most significant bits (15?8) can be designated as open drain outputs by writing a keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-3 ?1? to the appropriate bits in the kpcr. the lower 8 bi ts (7?0) are always in ?totem pole? style, driven when configured as outputs. see table 25-1 . note totem pole capability should be pr ovided for column pins. totem pole configuration helps for a faster disc harge of keypad capacitance when all columns need to be quickly brought to a ?1? during the scan routine. with this configuration, a time delay betw een the scanning of two subsequent columns is reduced. 25.3 memory map and register definition the kpp module contains four registers. section 25.3.3, ?register descriptions ? provides detailed descriptions of the kpp registers. 25.3.1 kpp memory map table 25-2 shows the kpp memory map. 25.3.2 register summary figure 25-2 shows the key to the register fields, and table 25-3 shows the register figure conventions. figure 25-2. key to register fields table 25-1. keypad port column modes kddr (15:8) kpcr (15:8) pin function 0 x input 1 0 totem-pole output 1 1 open-drain output table 25-2. kpp memory map address use access reset value section/page 0x1000_8000 (kpcr) keypad control register r/w 0x0000 25.3.3.1/25-5 0x1000_8002 (kpsr) keypad status register r/w 0x0000 25.3.3.2/25-5 0x1000_8004 (kddr) keypad data direction register r/w 0x0000 25.3.3.3/25-7 0x1000_8006 (kpdr) keypad data register r/w 0x? ? ? ? 25.3.3.4/25-8 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-4 freescale semiconductor table 25-4 shows the kpp register summary. 25.3.3 register descriptions this section consists of register descriptions. ea ch register is listed in the order of its address. table 25-3. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 25-4. kpp register summary name 1514131211109876543210 0x1000_8000 (kpcr) r kco 7 kco 6 kco 5 kco 4 kco 3 kco 2 kco 1 kco 0 kre 7 kre 6 kre 5 kre 4 kre 3 kre 2 kre 1 kre 0 w 0x1000_8002 (kpsr) r 00000 kpp _en kri e kdi e 000000 kpk r kpk d w krs s kds c w1c w1c 0x1000_8004 (kddr) r kcd d7 kcd d6 kcd d5 kcd d4 kcd d3 kcd d2 kcd d1 kcd d0 krd d7 krd d6 krd d5 krd d4 krd d3 krd d2 krd d1 krd d0 w 0x1000_8006 (kpdr) r kcd 7 kcd 6 kcd 5 kcd 4 kcd 3 kcd 2 kcd 1 kcd 0 krd 7 krd 6 krd 5 krd 4 krd 3 krd 2 krd 1 krd 0 w keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-5 25.3.3.1 keypad control register (kpcr) the keypad control register determines which of the eight possible column strobes are to be open drain when configured as outputs, and which of the eight row sense lines are considered in generating an interrupt to the core. it is up to the programmer to ensure that pins being used for functions other than the keypad are properly disabled. the kpcr register is byte- or halfword?addressable. figure 25-3 shows the valid bits in the kpcr register, and table 25-5 provides its field descriptions. 25.3.3.2 keypad status register (kpsr) the keypad status register reflects the state of the key press detect circuit. the kpsr register is byte- or halfword?addressable. figure 25-4 shows the kpsr register, and table 25-6 provides its field descriptions. 0x1000_8000 (kpcr) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kco7 kco6 kco5 kco4 kco3 kco2 kco1 kco0 kre7 kre6 kre5 kre4 kre3 kre2 kre1 kre0 w reset0000000000000000 figure 25-3. kpcr register table 25-5. keypad control register field descriptions field description 15?8 kco keypad column strobe open-drain enable. setting a column open-drain enable bit (kco7?kco0) disables the pull-up driver on that pin. clearing the bit allows the pin to drive to the high state. this bit has no effect when the pin is configured as an input. 0 column strobe output is totem pole drive. 1 column strobe output is open drain. note: configuration of external port control logic (for example, gpio) should be done properly so that the kpp module controls an open-drain enable of the pin. 7?0 kco keypad row enable. setting a row enable control bit in this register enables the corresponding row line to participate in interrupt generation. likewise, clearing a bit disables that row from being used to generate an interrupt. this register is cleared by a reset, disabling all rows. the row-enable logic is independent of the programmed direction of the pin. writing a ?0? to the data register of the pins configured as outputs will cause a keypad interrupt to be generated if the row enable associated with that bit is set. 0 row is not included in the keypad key press detect. 1 row is included in the keypad key press detect. keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-6 freescale semiconductor 0x1000_8002 (kpsr) access: user read/write 1514131211109 8 7654 3 2 1 0 r00000 kpp_ en krie kdie 0000 0 0 kpkr kpkd w krss kdsc w1c w1c reset000000 0 0 0000 0 0 0 0 figure 25-4. kpsr register table 25-6. keypad status register field descriptions field description 15?11 reserved 10 kpp_en keypad clock gating enable. the signal generated using this bit can be used by the ?chip clock-control module? to gate the module?s high frequency clock for register access and synchronization. output of this bit is not used anywhere inside kpp module. 0 disable high frequency clock to keypad module 1 enable high frequency clock to keypad module 9 krie keypad release interrupt enable. the software should ensure that the interrupt for a key release event is masked until it has entered the key pressed state, and vice versa, unless this activity is desired (as might be the case when a repeated interrupt is to be generated). the synchronizer chains are capable of being initialized to detect repeated key presses or releases. if they are not initialized when the corresponding event flag is cleared, false interrupts may be generated for depress (or release) events shorter than the length of the corresponding chain. 0 no interrupt request is generated when kpkr is set. 1 an interrupt request is generated when kpkr is set. 8 kdie keypad key depress interrupt enable. software should ensure that the interrupt for a key release event is masked until it has entered the key pressed state, and vice-versa, unless this activity is desired (as might be the case when a repeated interrupt is to be generated). the synchronizer chains are capable of being initialized to detect repeated key presses or releases. if they are not initialized when the corresponding event flag is cleared, false interrupts may be generated for depress (or release) events shorter than the length of the corresponding chain. 0 no interrupt request is generated when kpkd is set. 1 an interrupt request is generated when kpkd is set. 7?4 reserved, should be cleared 3 krss key release synchronizer set. self-clear bit. the key release synchronizer is set by writing a logic one into this bit. reads return a value of ?0?. 0 no effect 1 set bits which sets keypad release synchronizer chain 2 kdsc key depress synchronizer clear. self-clear bit. the key depress synchronizer is cleared by writing a logic ?1? into this bit. reads return a value of ?0?. 0 no effect 1 set bits that clear the keypad depress synchronizer chain keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-7 25.3.3.3 keypad data direction register (kddr) the bits in the kddr control the direction of the keypad port pins. the upper eight bits in the register affect the pins designated as column strobes, while the lower eight bits affect the row sense pins. setting any bit in this register configures the corresponding pin as an output. clearing any bit in this register configures the corresponding port pin as an input. for the keypad row ddr, an internal pull-up is enabled if the corresponding bit is clear. this register is cl eared by a reset, configuring all pins as inputs. the kddr register is byte- or halfword?addressable. note when a pin is used as row pin for keypad purposes, all corresponding pull-ups should be enabled at the upper level (for example, iomux) when the bit in row ddr is cleared. figure 25-5 shows the valid bits in the kddr register, and table 25-7 provides its field descriptions. 1 kpkr keypad key release. the keypad key release (kpkr) status bit is set when all enabled rows are detected high after synchronization (the kpkr status bit will be set when cleared by a reset). the kpkr bit may be used to generate a maskable key release interrupt. the key release synchronizer may be set high by software after scanning the keypad to ensure a known state. due to the logic function of the release and depress synchronizer chains, it is possible to see the re-assertion of a status flag (kpkd or kpkr) if it is cleared by software prior to the system exiting the state it represents. 0 no key release is detected. 1 all keys have been released. reset value of register is ?0? as long as reset is asserted. however when reset is de-asserted, the value of the register depends upon the external row pins and can become ?1?. 0 kpkd keypad key depress. the keypad key depress (kpkd) status bit is set when one or more enabled rows are detected low after synchronization. the kpkd status bit remains set until cleared by the software. the kpkd bit may be used to generate a maskable key depress interrupt. if desired, the software may clear the key press synchronizer chain to allow a repeated interrupt to be generated while a key remains pressed. in this case, a new interrupt will be generated after the synchronizer delay (4 cycles of the 32 khz clock) elapses if a key remains pressed. this functionality can be used to detect a long key press. this allows detection of additional key presses of the same key or other keys. due to the logic function of the release and depress synchronizer chains, it is possible to see the re-assertion of a status flag (kpkd or kpkr) if it is cleared by the software prior to the system exiting the state it represents. 0 no key presses have been detected. 1 a key has been depressed. 0x1000_8004 (kddr) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcd d7 kcd d6 kcd d5 kcd d4 kcd d3 kcd d2 kcd d1 kcd d0 krd d7 krd d6 krd d5 krd d4 krd d3 krd d2 krd d1 krd d0 w reset00000000000000 00 figure 25-5. kddr register table 25-6. keypad status register field descriptions (continued) field description keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-8 freescale semiconductor 25.3.3.4 keypad data register (kpdr) this 16-bit register is used to access the column and row data. data written to this register is stored in an internal latch, and for each pin configured as an output , the stored data is driven onto the pin. a read of this register returns the value on the pin for those bits configured as inputs. otherwise, the value read is the value stored in the register. the kpdr register is byte- or halfword?addressable. th is register is not initialized by a reset. valid data should be written to this register befo re any bits are configured as outputs. figure 25-6 shows the kpdr register, and table 25-8 provides its field descriptions. table 25-7. keypad data direction register field descriptions field description 15?8 kcdd keypad column data direction register. setting any bit configures the corresponding pin as an output. 0coln pin is configured as an input. 1coln 1 pin is configured as an output. 1 n=7?0 7?0 krdd keypad row data direction. setting any bit configures the corresponding pin as an output. 0 rown pin configured as an input. 1rown 2 pin configured as an output. 2 n=7?0 0x1000_8006 (kpdr) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcd7 kcd6 kcd5 kcd4 kcd3 kcd2 kcd1 kcd0 krd7 krd6 krd5 krd4 krd3 krd2 krd1 krd0 w reset???????????????? figure 25-6. kpdr register table 25-8. keypad data register field descriptions field description 15?8 kcd keypad column data. a read of these bits returns the value on the pin for those bits configured as inputs. otherwise, the value read is the value stored in the register. 0 read/write ?0? from/to column ports 1 read/write ?1? from/to column ports 7?0 krd keypad row data. a read of these bits returns the value on the pin for those bits configured as inputs. otherwise, the value read is the value stored in the register. 0 read/write ?0? from/to row ports 1 read/write ?1? from/to row ports keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-9 25.4 functional description the keypad port (kpp) is designed to simplify the software task of scanning a keypad matrix. with appropriate software support and ma trix organization, the kpp is capable of detecting, debouncing, and decoding one or more keys pre ssed simultaneously on the keypad. logic in the kpp is capable of detecting a key press even while the processor is in one of the low power standby modes providing that a 32 khz clock is on. th e kpp may generate a cpu interrupt any time a key press or key release is detecte d. this interrupt is capable of forcing the processor out of a low power mode. 25.4.1 keypad matrix construction the kpp is designed to interface to a keypad matrix, which shorts the intersecting row and column lines together whenever a key is depressed. the interface is not optimized for any other switch configuration. 25.4.2 keypad port configuration the software must initialize the kpp for the size of the keypad matrix. pins connected to the keypad columns should be configured as open-drain outputs. pins connected to the keypad rows should be configured as inputs. on-chip, pull-up resistors should be implemented for active keypad rows. in addition to enabled row inputs in the keypad control register, corresponding interrupt (depress or/and release) must also be enable d to generate an interrupt. discrete switches that are not part of the matrix may be connected to any unused row inputs. the second terminal of the discrete switch is connected to ground. the hardware detects closures of these switches without the need for software polling. 25.4.3 keypad matrix scanning keypad scanning is performed by a software loop that walks a zero across each of the keypad columns, reading the value on the rows at each step. the proce ss is repeated several times in succession, with the results of each pass optionally compared to those from the previous pass. when several (3 or 4) consecutive scans yield the same key closures, a valid key press has been detected. software then can decode exactly which switch was depressed and pa ss the value up to the next higher software layer. the basic debouncing period, which must be defined in th e software routine, may be controlled with an internal timer. the basic period is the period between the scan of two consecutive columns, so the debouncing time between two consecutive scans of th e whole matrix shall be the number of columns multiplied by the basic period. 25.4.4 keypad standby there is no need for the cpu to continually scan th e keypad. between key presses, the keypad can be left in a state that requires no software intervention until th e next key press is detect ed. to place the keypad in a standby state, software should write all column output s low. row inputs are left enabled. at this point, keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-10 freescale semiconductor the cpu can attend to other tasks or revert to a lo w power standby mode. the kpp will interrupt the cpu if any key is pressed. upon receiving a keypad interrupt, the cpu should set all the column strobes high, and begin a normal keypad scanning routine to determine which key was pr essed. it is important that open-drain drivers be used when scanning to prevent a possible dc pa th between power and ground through two or more switches. 25.4.5 glitch suppression on keypad inputs a glitch suppression circuit qualifie s the keypad inputs to prevent noise from inadvertently interrupting the cpu. the circuit is a 4-state synchronizer cl ocked from a 32 khz clock source. this clock must continue to run in any low power mode where the ke ypad is a wake-up source, as the cpu interrupt is generated from the synchronized input. an interrupt is not generated until all four synchronizer stages have latched a valid key a ssertion. this guarantees the filtering out of any noise less than three clock periods (for 32 khz clock: 93.75 s) in duration. noise filtering of the duration between three to four clock periods (for the 32 khz clock: between 93.75 s and 125 s) cannot be guaranteed. the interrupt output is latched in an s-r latch and remains asserted until cleared by the software. the set input of the latch is rising-edge clocked. see figure 25-7 . keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-11 figure 25-7. keypad synchronizer functional diagram 25.4.6 multiple key closures using the key press and key release interrupts, the so ftware can detect multiple keys or achieve n key rollover. the key scanning routine can be programmed accordingly. refer to section 25.5, ?initialization/application information ? for more information. see figure 25-5 and figure 25-9 for illustrations of the interfacing of a 2-contact keypad matrix with the kpp controller. with proper enabling of row lines and the performing scan-routine, multiple key presses can be detected. when keys present on the same ro w are pressed, corresponding row lines (multiple lines) become low when the column is driven low during a scan-routine. by reading th e data-register, pressed keys can be detected. similarly, when keys presen t on same row line are pressed, the corresponding row line (only one line) becomes low when logic ?0? is driven on the column line during a scan-routine. kpcr(7:0) keypad 32 khz matrix . ff dq ff dq ff dq d r clear kpkd status flag nand r r r kpkd ff dq ff dq ff dq d r s s s kpkr clear kpkr status flag clear kpkd synchronizer set kpkr synchronizer column pins row pins anding of pins with row-enable bits keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-12 freescale semiconductor figure 25-8. multiple key presses on sa me column line (simplified view) figure 25-9. multiple key presses on same row line (simplified view) keypad port controller column lines row lines output configuration input configuration with pull-ups switch matrix multiple key presses keypad port controller column lines row lines output configuration input configuration with pull-ups switch matrix multiple key presses keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-13 note an n key rollover is a technique the sy stem uses to recognize the order in which keys are pressed. 25.4.6.1 ghost key problem and correction the kpp module detects if one or multiple keys are pre ssed or released. in the case where a simple keypad matrix with two-contact switches is used, there is a chance of ?ghost? key detection when three or more keys are pressed. this is a limitation imposed by such a keypad matrix. as can be seen in figure 25-10 , three keys pressed simultaneously can cause a s hort between the column currently ?scanned? by the software and another column. depending on the location of the third key pressed, a ?ghost? key press may be detected. however, this can be corrected by using a keypad ma trix that provides ?ghost? key protection. such a matrix implements a one-way ?diode? at all keypad points between rows and columns. this way, the multiple pressing of three keys will not cause a short at a fourth key (see figure 25-11 ). figure 25-10. decoding wrong three-key presses column pulled down column not pulled down pulled down row pulled down row three real key presses ghost key press the path of the zero pull down that reaches the wrong row and so generates a ghost key press keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-14 freescale semiconductor figure 25-11. matrix with ?ghost? key protections 25.4.7 3-point contact keys support the kpp module supports interfacing to a matrix c onsisting of 3-point contact keys. as shown in figure 25-12 , two points of such a key are connected to keypad lines, while a third point is connected to ground (low logic). the keypad lines should be configur ed as input and a pull-up should to be present on these lines. when such a key is pressed, corresponding keypad lines go low and an interrupt is generated. there is no need to perform a scanning routine for iden tification of pressed key as it can be done by reading the keypad data-register. a limitation with such a matrix is that for every key at least one keypad row line should be used. column pulled down column not pulled down pulled down row pulled down row three real key presses diode prevents ghost key press the path of the zero pull down cannot reach the wrong row the path of zero pull down gets stopped at this point switches with diode keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 25-15 figure 25-12. kpp interface with 3-point contact key matrix (simplified view) 25.5 initialization/app lication information this section provides initializat ion and application information. 25.5.1 typical keypad configuration and scanning sequence perform the following steps to configure the keypad: 1. enable the number of rows in the keypad (kpcr[7:0]). 2. write 0s to kpdr[15:8]. 3. configure the keypad columns as open-drain (kpcr[15:8]). 4. configure columns as output and rows as input (kddr[15:0]). 5. clear the kpkd status flag and synchronizer chain. 6. set the kdie control bit, and clear the krie control bit (avoid false release events). (the system is now in standby mode, and awaiting a key press.) 25.5.2 key press interrupt scanning sequence perform the following steps to perform a keypad scanning routine: 1. disable both (depress and release) keypad interrupts. keypad port controller keypad input configuration with pull-ups lines 3-point contact keys gnd keypad port (kpp) MCIMX27 multimedia applications processor reference manual, rev. 0.2 25-16 freescale semiconductor 2. write 1s to kpdr[15:8], setting column data to 1s. 3. configure columns as totem pole outputs (for quick discharging of keypad capacitance). 4. configure columns as open-drain. 5. write a single column to 0, and other columns to 1. 6. sample row inputs and save data. multiple ke y presses can be detected on a single column. 7. repeat steps 2?6 for remaining columns. 8. return all columns to 0 in preparation for standby mode. 9. clear kpkd and kpkr status bit(s) by writing to a ?1?; set the kpkr synchronizer chain by writing a ?1? to the krss register; and clear the kpkd synchronizer chain by writing a ?1? to the kdsc register. 10. re-enable the appropriate keypad interrupt(s) so that the kdie detects a key hold condition, or the krie detects a key-release event. 25.5.3 additional comments the order of key press detection can be done in software only. therefore, the software may need to run the scan routines at very short intervals of time per the application?s demands. for the keys that require a very precise order (such as game keys), individual gpio pins may be more useful. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-1 chapter 26 memory stick host controller (mshc) the memory stick host controller (mshc) consists of two sub modules?the mshc gasket and the sony memory stick host controller (smsc). the smsc module, which is the actual memory stick host controller, is compatible with sony memory stick ve r. 1.x and memory stick pr o. the gasket connects the aipi ip bus to the smsc interface to allow ip tran sfers. the mshc is placed between the aipi and the sony memory stick to support data tr ansfer from the chip to the ms. the mshc top level block diagram with input and output signals is shown in figure 26-1 . figure 26-1. memory stick controller block diagram 26.1 overview this chapter describes the mshc gasket module in de tail. all details regarding the smsc module can be found separately in memory stick/memory stick pro host controller ip specification 1.3 . mshc mspdir data[3:0] mssdir bs xscko data[3:0] mshc gasket sony memory stick host controller ip bus clock and reset mem. stick if memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-2 freescale semiconductor 26.1.1 features the mshc includes the following features: ? a gasket between ip bus and smsc ? ip bus interface transfer functionality as slave ? three internal registers (timeout, interrupt status/clear, and interrupt enable register) ? gasket interrupt for transfer errors, or wait timeout ? timeout function for abnorma l transfer wait states ? fixed 32-bit data bus ? little endian to ip data bus and big endian to smsc data bus ? smsc to communicate to the sony memory stick ? four internal registers structured in 64-bit format ? fifo (4 x 64-bit) ? interrupt after memory stick communication completes ? dma in dual address mode (note: smsc supports single address mode as well) ? test mode and dft implementation 26.1.2 modes of operation the mshc gasket has a reduced ip interface and suppor ts the ip bus read/write transfers that include a back-to-back read or write. dma transfers also take place via the ip interface. a transfer can be initiated by the dma or the host (through aipi) in response to an mshc dma request or interrupt. the smsc has two dma address mode s, a single address mode and a dual address mode. the mshc is set to dual address mode for transfers with the dma. in dual address mode, when the mshc requests a transfer with the dma request (xdrq), the dma will initiate a transfer to the mshc. the mshc still has the external memory ports and the dma acknowledge input (xdak) even though the single address mode is not used in some chip. 26.2 external signal description 26.2.1 overview the mshc signals are listed in table 26-1 . table 26-1. mshc i/o signals name port active function data[3:0] input ? mshc data input from ms data[3:0] output ? mshc data output to ms ipp_do_ms_mdo[63:0] output ? mshc external memory output data memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-3 26.2.1.1 memory stick interface the mshc module supports memory stick pro, which mean s a data transfer can be done in serial mode or parallel mode. 26.3 memory map and register definition the mshc has seven internal regist ers; four registers in the smsc and three registers in the gasket. the gasket internal registers do not require any extra addresses as they share the address space for the smsc internal registers. ip bus accesses are 32-bit, but all smsc registers (except the data register) use only the upper 16 bits, so the gasket can utilize the lower 8 bits. the mshc internal registers are mapped to 64-bit st ructure, so the required address signal is [4:3]. due to this address sharing scheme, the host must ke ep the smsc register values as necessary while updating the gasket internal registers. table 26-2 shows the memory map for the mshc module. ipp_do_ms_mdsl output high mshc external memory data select. if set to one, external memory is selected. ipp_do_ms_mreq output high mshc external memory data request ipp_do_ms_mrws output ? mshc external memory read/write select (write if one) mspdir output ? mshc parallel data direction (write transfer?mshc to ms?if one, or read transfer if zero) mssdir output ? mshc serial data direction (write transfer?mshc to ms?if one, or read transfer if zero) xscko output ? mshc serial clock output table 26-2. mshc memory map memory map addr[4:3] data bit [63:57] [56:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] ?h00 0 smsc command register gasket timeout register not used ?h08 1 smsc data register not used table 26-1. mshc i/o signals (continued) name port active function memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-4 freescale semiconductor 26.3.1 register descriptions the mshc module uses big endian with 64-bit data while the chip system uses the little endian with 32-bit data. therefore, the data must be assigned as per table 26-3 . 26.3.1.1 smsc registers the smsc command register contains the ms transfer protocol command (tpc) and transfer data size. it must be set by either the host or dma before starting a transfer. the smsc data register is used to access the smsc in ternal fifo, which is of size 4 x 64-bit. it takes 8 32-bit transfers to fill or empty the fifo. the smsc status register reflects smsc status, such as fifo status, ready flag for transfers and crc error flag. the host needs to read this register in order to start and manage the transf er. this register is only readable through the ip bus. the smsc system register has a user command for smsc modes and options that are required for transfer and communication with the ms. this register must be set before starting a transfer and should not be changed during the communication with the ms. more details can be found in memory stick/ memory stick pro host controller ip specification, ver. 1.3 . 26.3.1.2 gasket register 26.3.1.2.1 gasket timeout register this register is readable or writable. the value af ter synchronous or asynchronous reset is 0. this register gives a mechanism to time-out if long wait states are encountered. ?h10 2 smsc status register gasket interrupt status/ clear register not used ?h18 3 smsc system register gasket interrupt enable register not used table 26-3. mshc data endianism and connection to ip bus bus endian connection mshc data big [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] ip bus data little [7:0] [15:8] [23:16] [31:24] ? ? ? ? table 26-2. mshc memory map (continued) memory map addr[4:3] data bit [63:57] [56:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-5 once the fifo becomes full while the ip bus has more data to be written, the gasket asserts the wait signal until the fifo space is available. the gasket will also start to decrement an internal counter from the timeout value for wait, tovw[7:0]. when the counter reaches zero, the ips_xfr_wait signal is deasserted and an interrupt is generated if the wait state is cleared before the timeout counter reaches zero the suspended transfer will be resumed. when the tovw[7:0] is set to zero the gasket will not produce wait states if th e fifo is full/empty, but will generate an interrupt. if the gasket interrupt enable bits - inten_wful and inten_remp - are disabled, the timeout counter has no functionality (it is effectively set to infinity). once the wait state is entered the mshc will stay in wait until either the aipi disables the module (usi ng ips_module_en) or the fifo becomes available for another transfer. 26.3.1.2.2 gasket interrupt status/clear register this register is readable or writable, and is rese t to 0 by asynchronous or sync hronous reset. bits should be written as 1 to clear an interrupt. the unused bits are read as zero. the smsc status register, which has the same address as this register, is a read-only register. the interrupt status/clear register reflec ts the transfer status. it is used for the gasket to decide if it supports a current transfer, and it can also be used for the gasket interrupt generation. the gasket provides four different interrupts, which are all directly related to the ip bus transfer. once an interrupts occurs the host needs to check this register to determine which interrupt occurred and also to clear the interrupt (by writing 1 to the register bit). ? ida (illegal data access) this bit is asserted if a transfer is not 32-bit, that is, if the ips_byte inputs are not all asserted. it is always readable and can be cleared (if the interr upt enable bit inten_ida is enabled) by writing to this register with ips_wdata[23] set to one. any illegal data access always asserts ida, but will not generate a gasket interrupt if the interrupt enable bit inten_ida is disabled. table 26-4. timeout register bit 4746454443424140 name tovw[7:0] reset value 0 r/w r/w table 26-5. interrupt status/clear register bit 4746454443424140 name ida ixfr ? ? wful remp ? ? reset value0 0??0 0?? r/w r/w r/w r/? r/? r/w r/w r/- r/- memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-6 freescale semiconductor ? ixfr (illegal transfer) this bit is asserted if a data tr ansfer direction is not consistent with the smsc fifo data direction. it is always readable and can be cleared (if th e interrupt enable bit inten_ixfr is enabled) by writing to this register with ips_wdata[22] set to one. any illegal data transfer always asserts ixfr, but will not generate a gasket interrupt if the interrupt enable bit inten_ixfr is disabled. ? wful (write to fifo when full) this bit is asserted if the smsc fifo is full a nd the current write transfer is not finished. it is always readable and can be cleared (if the inte rrupt enable bit inten_wful is set) by writing to this register with ips_wdata[19] set to one. the gasket asserts wful when a data write transfer is attempted while the fifo is full. the update time will be different depending on whether inten_wful is enabled and the value of tovw[7:0]. if inten_wful is disabled wful will be updated without the timeout delay. the gasket uses this bit to generate a transfer wait state as well as the interrupt. ? remp (read from fifo when empty) this bit is asserted if the smsc fifo is empty a nd the current read transfer is not finished. it is always readable and can be cleared (if the interr upt enable bit inten_remp is set) by writing to this register with ips_wdata[18] set to one. the gasket asserts remp when a normal data read transfer is attempted while the fifo is empty. the version number read after a reset also asserts remp as the fifo is empty at this time. the update time will be different depending on whet her inten_remp is enabled and the value of tovw[7:0]. if inten_remp is disabled remp w ill be updated without the timeout delay. the gasket uses this bit to generate a transfer wait state as well as the interrupt. 26.3.1.2.3 gasket interrupt enable register this register is readable or writable, and is reset to 0 by asynchr onous or synchronous reset. this register is used to enable the gasket interrupts. the gasket interrupts are disabled by the default. to enable the gasket interrupt the relevant bit should be set to 1. ? inten_ida illegal data access interrupt enable bit. if it is one it will enable the gasket interrupt for an illegal data access. table 26-6. interrupt enable register bit 4746454443424140 name inten_ ida inten_ ixfr ??inten_ wful inten_ remp ?? reset value0 0??0 0?? r/w r/w r/w r/? r/? r/w r/w r/- r/- memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-7 ? inten_ixfr illegal transfer interrupt enable bit. if it is set to one it will enable the gasket interrupt for an illegal data transfer. ? inten_wful interrupt enable bit for a write transfer to fifo with full. if it is set to one it will enable the gasket interrupt and the wait timeout function. ? inten_remp interrupt enable bit for a read transfer from fifo with empty. if it is set to one it will enable the gasket interrupt and the wait timeout function. 26.4 functional description 26.4.1 sony memory stick controller (smsc) the details of the smsc f unctionality can be found in memory stick/ memory stick pro host controller ip specification, ver. 1.3 . 26.4.2 mshc gasket this section describes mshc clocks, ms interface, the gasket state-machine, ip bus error and wait conditions, the gasket interrupt, and ip bus transfer. 26.4.2.1 resetting and clocking the mshc uses one asynchronous reset and one synchr onous reset to reset gasket internal registers. the asynchronous reset is the green-line hardware asynchronous reset that is active low while the synchronous reset is a soft reset from the mshc system register rst bit that is active high. once the soft reset is asserted the smsc will automatically clear th e rst bit in the system register after initializing all internal registers. during the soft reset period the behavior of any ip bus transactions is undefined. mshc has several clocks, as shown in figure 26-2 . the mshc has three clock inputs ipg_clk_s is directly connected to the gasket, and the others to smsc through muxing logic. the mshc also has one cl ock output that is inverted in the gasket. the muxing logic allows the mshc to have only two clock domains during test mode. ipg_clk_s in the gasket and hcki in the smsc are connected to one test clock, and all other clocks (scki, xscki, mscki, and xmscki) are connected to a different test clock. the test clocks are generated inside the crm. in normal operation, xscki is an inverted version of scki and mscki is an inverted version of xmscki. the gasket uses the ipg_clk_s for all logic that is s ynchronous to the ip interface signals. this clock is only active when the gasket modul e enable signal is asserted. memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-8 freescale semiconductor hcki in the smsc is the main clock for most of the internal registers and the fifo. the ms has a slower clock speed and is asynchronous to hcki, so xscko is generated by the smsc a nd is output to provide the ms clock. all logic shown in figure 26-2 is implemented in the gasket. figure 26-2. mshc clock structure 26.4.2.2 memory stick interface the gasket includes logic to generate the io signals for the ms. this logic is included in the gasket so that it does not need to be provided at the chip level. the multiplex logic and signal connections included in the gasket are shown in the table 26-3 . mshc gasket sony memory stick host controller xscko ipp_do_xscko hcki mscki xmscki xscki scki ipt_mode ipg_clk_s ipp_di_xmscki ipp_di_scki ipg_clk ipt_se_async ipg_clk_s ~mshc_fuse_dis clock gating cell clock gating cell clock gating cell clock gating cell memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-9 figure 26-3. gasket memory interface logic ipp_do_bs mspdir mspdo[1] srac sbs pbs mssdo mspdo[0] mssdir ipp_do_data[0] ipp_do_mssdir ipp_do_data[1] mspdo[2] ipp_do_data[2] mspdo[3] ipp_do_data[3] ipp_do_mspdir memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-10 freescale semiconductor figure 26-4. basic read/write timing diagram 26.4.2.2.1 back-to-back transfer the figure 26-5 shows the back-to-back timing for ip bus and the smsc interface. in the timing diagram there are three write transfer s (cycles 1?6) and two read transfers (cycles 8?11). the ip bus sends back-to-back transfers and the gasket inserts one cycle wait states for each data transfer. this allows the smsc read/write signa l to be asserted for one hcki cycle. ipg_clk ipg_module_en ips_rwb ips_byte_#_# ips_wdata ips_addr ips_xfr_err ips_xfr_wait xcs xwr xrd addr ips_rdata di do waddr wdata 4'b1111 rdata 01234567 raddr 8 9 1011121314 waddr raddr wdata rdata waddr raddr waddr wdata wdata rdata rdata raddr memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-11 figure 26-5. back-to-back write/read timing diagram 26.4.2.3 transfer error when the gasket detects a transfer er ror it generates an interrupt. the ip bus transfer error interrupt is an optional feature that can be enabled by the gasket interrupt enable register. two transfer error conditions are: ? illegal data access ? illegal transfer the data access error shows if the ip bus transfer is not 32-bit. the gasket checks all four byte enable signals and if any one of these becomes zero during a tr ansfer the gasket will set the interrupt status/clear bit, ida, and generate the interrupt. the illegal transfer error shows whether the ip bus data transfer direction is correct. the smsc system register includes the fifo data direction bit that must be set before the transfer is started. if this bit is set to one, the data direction is from aipi to mshc. then the next ip bus transfer must be a write. if the data direction and data transfer direction are not consiste nt, the gasket updates the interrupt status/clear bit, ixfr, to one and generates the interrupt. note that this error condition is applied onl y to transfers to the smsc data register. ipg_clk ipg_module_en ips_rwb ips_byte_#_# ips_wdata ips_addr ips_xfr_err ips_xfr_wait xcs xwr xrd addr ips_rdata di do waddr w1 4'b1111 raddr w2 w3 r1 r2 waddr raddr r1 r2 w1 w2 w3 01234567891011121314 memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-12 freescale semiconductor 26.4.2.4 transfer wait condition in normal transfers, a wait state may be inserted for one clock cycle for each 32-bit transfer, because of the read/write timing requirements for the smsc when the ip bus is dealing with back-to-back type transfers. if the transfer initiator ensures a maximum transfer burst to fill the smsc fifo there will be no multiple wait cycles. if ip bus performs a large transfer burst to the mshc, the smsc fifo will fill due to the slow transfer speed between the smsc and the ms. in this ca se, the gasket inserts wait states until the fifo is available for further transfers, that is, one space in the fifo is available. at this time the gasket will end the wait state and resume the next transfer. the behavi or is similar for read transfers when the fifo is empty. there are two conditions for multiple cycles of wait states: ? write transfers on the ip bus with the smsc fifo full ? read transfers on ip bus with the smsc fifo empty exceptional operations can also cause a long wait state. for instance, if one 32-bi t data write transfer is performed with the smsc fifo empty, the empty flag will remain set. thus, if the following transfer is a read operation it will not be processed due to the a sserted state of the fifo empty flag. therefore the gasket will stay in a wait state as long as the r ead transfer request remains pending on the ip bus. a minimum of two 32-bit write transfers are required to deassert the empty flag. the transfer initiator must make sure that a minimum of two write transfers are ma de in order to read back the data written to the fifo. another unexpected long wait state may happen if th e communication between the mshc and the ms is abnormally terminated. to prevent this behavior, th e gasket provides a wait timeout function, with which a timeout value can be used to disable the wait state a nd generate an interrupt if the transfer wait state goes for too long. this option is available when the in terrupt enable bits, inten_wful and inten_remp, are enabled as described in section 26.3, ?memory map a nd register definition .? the timeout counter has no functionality if the in ten_wful and inten_remp interrupts are disabled. in this case the transfer initiator is responsible for disabling the module to end a long wait state. 26.4.2.5 gasket interrupt the gasket interrupts are generated from transfer er ror and wait conditions and is ored with the smsc interrupt. table 26-6 is the flow chart that shows how the gasket inserts wait states and generates an interrupt. the flow chart also shows how the gasket timeout function performs. the interrupt enable bits inten_wful and inten_remp disable all the gasket status/clear and timeout register functions. memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 26-13 figure 26-6. gasket interrupt generation start xfr end type error discard xfr com_xfr, sta_xfr, sys_xfr dat_xfr direction write read fifo full no do xfr no wait do xfr do xfr end end end yes no timeout interrupt yes end yes yes discard xfr end yes do xfr end no no yes inten_wful wait fifo ful do xfr no no end yes yes discard xfr end timeout interrupt yes end fifo ful do xfr yes no no yes discard xfr end end no wait yes yes no discard xfr discard xfr interrupt no (version # read) wait fifo empty yes discard xfr end yes no no do xfr end xfr disabled xfr disabled xfr disabled xfr disabled fifo empty fifo empty inten_remp no memory stick host controller (mshc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 26-14 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-1 chapter 27 secured digital host controller (sdhc) the multimediacard (mmc) is a universal low-cost data storage and communi cation medium that is designed to cover a wide area of applications, such as electronic toys, organizers, pdas, and smart phones. the mmc communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. the secure digital card (sd), is an evolution of mmc technology, with two additional pins in the form factor. it is specifically designed to meet the secur ity, capacity, performance, and environment requirement inherent in newly emerging audio and video consumer electronic devices. the physical form factor, pin assignment, and data transfer pr otocol are forward-compatible with the multimediacard with some additions. under sd protocol, it ca n be categorized into memory card, i/o card, and combo card (has both memory and i/o functionality). the memory card invokes a copyright-protection mechanism that complies with the security of the sdmi standard, is faster, and provides the capability for a higher memory capacity. the i/o card provides high-speed data i/o with low-power consumption for mobile electronic devices. the security digital host controller (sdhc) inte grates both mmc support along with sd memory and i/o functions, including sd memory and i/o combo card. see the block diagram of sdhc in figure 27-1 . figure 27-1. secure digital host controller block diagram ip gasket (application adapter) register handler system state machine and dma handler 32*16 fifo cmd channel state machine logic control crc data channel state machine logic control crc cmd/ data channel tx/rx handler application bus ipg_perclk ipg_clk access clk data configuration channel control clk_20m internal clk clock controller clk_div internal clk mmc/sd bus clock secure digital host controller sdhc cmd dat3 dat2 dat1 dat0 mmc_sd_clk ipg_clk_s ipg_clk_32k ipd_dreq_b ipi_irq_b ipg_clk_en ipg_perclk_en secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-2 freescale semiconductor see figure 27-2 for the illustration of system interconnection with the sdhc module. figure 27-2. system interconnection with the secure digital host controller 27.1 overview the security digital host controller (sdhc) cont rols the mmc, sd memory, and i/o cards by sending commands to cards and performing data accesses to/from the cards. refer to section 27.4, ?functional description ? for a detailed description. 27.1.1 features the features of the secure digital host controller module include the following: ? full compatibility with the mmc system specification, version 3.2 ? compatibility with the sd memory card specification 1.01, and sd i/o specification 1.1 with 1/4 channel(s) ? 100 mbps maximum data rate in 4-bit mode, sd bus clock up to 25 mhz ? built-in programmable frequency counter for sdhc bus ? maskable hardware interrupt for sdio interrupt, internal status and fifo status ? built-in dual 16 x 32-bit data fifo buffer ? plug and play (pnp) support ? single/multi-block access to the card, including erase operation ? multi-sd function support, including multip le i/o and combined i/o and memory ? up to seven i/o functions, plus one memory supported on single sd i/o card (combo card) ? irq supported enable card to interrupt host ? support of sdio interrupt detection during 1/4-bit access ? support of sdio read/wait and suspend/resume operation ? controller core?freescale semiconductor ip bus compatible ? block-based data transfer between mmc card and sdhc (stream mode not supported) ? block length of data transfer capability betw een host and card of approximately 1 to 2048 bytes secure digital host controller dma interface ip bus transceiver ip gasket ip bus i/o memory card secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-3 27.2 external signal description the sdhc has a six-chip i/o. th e mmc_sd_clk is an internally generated clock used by the mmc/sd card. the cmd i/o is used to send commands and r eceive responses from the card. four data lines, dat3?dat0, are used to perform data transfers between the host controller and the card. see table 27-1 for the signal properties of the i/os. 27.3 memory map and register definition sdhc contains 16 32-bit registers. section 27.3.3, ?register descriptions ? provides the detailed descriptions for all of the sdhc registers. all the registers can be accessed only in 32-bit sizes. byte/half-word access is not allowed. 27.3.1 memory map table 27-3 shows the sdhc memory map. the sdhc memo ry map space is 4 kbytes. only address offsets from 0 x 00 to 0 x 44 are implemented. the addr ess space above the offset of 0 x 44 is reserved. for write access to the reserved address region, the access is ignored by sdhc. for read access to the reserved address region, 0 x 0 will be returned on the ip bus. the user should not access the reserved region to ensure compatibility with possible future revisions of this module. table 27-1. signal properties name port function reset state pull up mmc_sd_clk o clock for mmc/sd/sdio card 0 cmd i/o cmd line connect to card 1 pull up dat3 i/o card detect in power up data line in 4-bit mode not used in 1-bit mode 0 pull down dat3 if need card detection through this bit, otherwise pull up dat2 i/o data line or read wait in 4-bit mode read wait in 1-bit mode 1 pull up dat1 i/o data line or interrupt in 4-bit mode interrupt in 1-bit mode 1 pull up dat0 i/o data line both in 1-bit and 4-bit mode 1 pull up table 27-3. sdhc memory map address register access reset value section/page 0x1001_3000 (str_stp_clk1) 0x1001_4000 (str_stp_clk2) sdhc clock control register r/w 0x0000_0000 27.3.3.1/27-8 0x1001_3004 (status1) 0x1001_4004 (status2) sdhc status register r 0x3000_0000 27.3.3.2/27-9 0x1001_3008 (clk_rate1) 0x1001_4008 (clk_rate2) sdhc card clock rate register r/w 0x0000_0008 27.3.3.3/27-13 0x1001_300c (cmd_dat_cont1) sdhc command data control register r/w 0x0000_0000 27.3.3.4/27-15 secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-4 freescale semiconductor 27.3.2 register summary figure 27-3 shows the key to the register fields and table 27-4 shows the register figure conventions. figure 27-3. key to register fields 0x1001_3010 (res_to1) 0x1001_4010 (res_to2) sdhc response time-out register r/w 0x0000_0040 27.3.3.5/27-17 0x1001_3014 (read_to1) 0x1001_4014 (read_to2) sdhc read time-out register r/w 0x0000_ffff 27.3.3.6/27-18 0x1001_3018 (blk_len1) 0x1001_4018 (blk_len2) sdhc block length register r/w 0x0000_0000 27.3.3.7/27-19 0x1001_301c (nob1) 0x1001_401c (nob2) sdhc number of block register r/w 0x0000_0000 27.3.3.8/27-20 0x1001_3020 (rev_no1) 0x1001_4020 (rev_no2) sdhc revision number register r 0x0000_0400 27.3.3.9/27-21 0x1001_3024 (int_cntr1) 0x1001_4024 (int_cntr2) sdhc interrupt control register r/w 0x0000_0000 27.3.3.10/27-22 0x1001_3028 (cmd1) 0x1001_4028 (cmd2) sdhc command number register r/w 0x0000_0000 27.3.3.11/27-26 0x1001_302c (arg1) 0x1001_402c (arg2) sdhc command argument register r/w 0x0000_0000 27.3.3.12/27-27 0x1001_3034 (res_fifo1) 0x1001_4034 (res_fifo2) sdhc command response fifo access register r 0x0000_0000 27.3.3.13/27-28 0x1001_3038 (buffer_access1) 0x1001_4038 (buffer_access2) sdhc data buffer access register r/w 0x0000_0000 27.3.3.14/27-29 note: the following addresses are reserved: 0x1001_3030 0x1001_330c 0x1001_4030 0x1001_430c always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 27-4. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. table 27-3. sdhc memory map (continued) address register access reset value section/page secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-5 table 27-5 shows the sdhc register summary. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. slfclr self-clearing bit. writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 27-5. sdhc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1001_3000 (str_stp_clk1) 0x1001_4000 (str_stp_clk2) r0000000000000000 w r000000000000 slfcl r 0 sta rt_ cl k st op _cl k w sd hc res et table 27-4. register figure conventions (continued) convention description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-6 freescale semiconductor 0x1001_3004 (status1) 0x1001_4004 (status2) r ca rd _in se rti on ca rd _r em ov al yb uf_ em pt y xb uf_ em pt y yb uf_ ful l xb uf_ ful l bu f_u nd _r un bu f_ ov fl 00000000 ww1cw1c r0 sdi o_i nt_ ac tiv e en d_ cm d_ re sp wr ite _o p_ do ne re ad _tr an s_ do ne wr_crc _err_c ode ca rd _bu s_ cl k_ ru n bu f_r ea d_ rd y bu f_ wr _r dy re sp_ cr c_ er r 0 re ad _c rc _e rr wr ite _c rc _e rr tim e_ ou t_r es p tim e_ ou t_r ea d w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0x1001_3008 (clk_rate1) 0x1001_4008 (clk_rate2) r0000000000000000 w r clk_prescaler[15:4] clk_divider[3:0] w 0x1001_300c (cmd_dat_cont1) 0x1001_400c (cmd_dat_cont2) r0000000000000000 w r cm d_ re su me 00cm d_ re sp_ lo ng _o ff st op _r ea dw ait sta rt_ re ad wai t bus_wi dth init 00 wr ite _r ea d dat a_e na ble format_of_ response w 0x1001_3010 (res_to1) 0x1001_4010 (res_to2) r0000000000000000 w r00000000 response time out[7:0] w 0x1001_3014 (read_to1) 0x1001_4014 (read_to2) r0000000000000000 w r data_read_time_out[15:0] w table 27-5. sdhc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-7 0x1001_3018 (blk_len1) 0x1001_4018 (blk_len2) r0000000000000000 w r0 0 0 0 block length[11:0] w 0x1001_301c (nob1) 0x1001_401c (nob2) r0000000000000000 w r nob[15:0] w 0x1001_3020 (rev_no1) 0x1001_4020 (rev_no2) r0000000000000000 w r revision number[15:0] w 0x1001_3024 (int_cntr1) 0x1001_4024 (int_cntr2) r0000000000000 sdi o_i nt_ wk p_e n ca rd _in se rt_ wk p_e n ca rd _r em ov al_ wk p_e n w r ca rd _in se rti on _e n ca rd _r em ov al_ en sdi o_i rq _e n dat 0_e n 0000000 bu f_r ea d_ en bu f_ wr ite _e n en d_ cm d_ re s wr ite _o p_ do ne re ad _o p_ do ne w 0x1001_3028 (cmd1) 0x1001_4028 (cmd2) r0000000000000000 w r0000000000 command number w 0x1001_302c (arg1) 0x1001_402c (arg2) r arg[31:16] w r arg[15:0] w table 27-5. sdhc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-8 freescale semiconductor 27.3.3 register descriptions many of sdhc registers have reserved bits. reserved bits identified in the registers are read as zero and write to these bits are ignored. however, the user shoul d write zeros to these bits to ensure compatibility with possible future revisions of this module. 27.3.3.1 sdhc clock control register (str_stp_clk) the sdhc clock control register allows the user to reset the whole module and to enable or disable the mmc_sd_clk to card. see figure 27-4 for an illustration of valid bits in the sdhc clock control register and table 27-6 for descriptions of the bit fields. 0x1001_3034 (res_fifo1) 0x1001_4034 (res_fifo2) r0000000000000000 w r response_content[15:0] w 0x1001_3038 (buffer_access1) 0x1001_4038 (buffer_access2) r fifo content[31:16] w r fifo content[15:0] w 0x1001_3000 (str_stp_clk1) 0x1001_4000 (str_stp_clk2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 0 0 00 w reset000000000000 0 0 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r000000000000slfclr0 start _clk sto p_c lk w sdhc reset reset000000000000 0 0 00 figure 27-4. sdhc clock control register table 27-5. sdhc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-9 27.3.3.2 sdhc status register ( status ) the read-only sdhc status register provides the progr ammer with information about the status of sdhc operations, application fifo status, e rror conditions, and interrupt status. there are eight interrupt status bits, which are bit-31 ca rd insertion status bit, bit-30 card removal status bit, bit-14 sdio card interrupt status bit, bit- 13 end command and response status bit, bit-12 write operation done status bit, bit-11 read operation done status bit, bit-7 data buffer read ready status bit, and bit-6 data buffer write ready status bit. when the corresponding interrupt enable is enabled in sdhc interrupt control register for any of these interrupts, the sdhc will generate an interrupt request to the cpu. the user needs to clear the appropriate status bit to clear the corresponding interrupt. the interrupt status bits are cleared by using a write ?1? to clear operation except for the data buffer ready status bits which can be cleared only by the read or write operation on the data buffer. see figure 27-5 for an illustration of valid bits in the sdhc status register and table 27-7 for descriptions of the bit fields. table 27-6. sdhc clock control register field descriptions field description 31?4 reserved 3 sdhc reset sdhc reset. writes to the sdhc reset bit triggers the reset logic inside the sdhc. reads from this bit always return ?0?. to reduce the power consumption, the clock to the reset logic in sdhc is off in normal operation. when there is one access to this register, the clock will be enabled for one cycle. to complete the entire reset period, it will need at least 8 clock pulses to finish the reset cycle. to reset the sdhc module, it is recommended to write this register with value 0x0008, followed by 0x0009, and then 0x0001 eight times. refer to section 27.5.2.2, ?reset ? for detailed information on software reset. 0 no effect 1 reset the sdhc module 2 reserved 1 start_clk start clock. writing a ?1? to this bit starts the mmc_sd_clk clock. setting a value of 11 on bits [1:0] of this register is not allowed. note: the sdhc bus clock does not start immediately after writing to this bit. polling needs to be done on the status card_bus_clk_run bit to ensure the sdhc clock is running. refer to example 27-1 for procedures to start the sd bus clock. 0no effect 1 to start mmc/sd clock 0 stop_clk stop clock. stops the mmc_sd_clk clock when the user writes a value of ?1? to this bit. the mmc_sd_clk should not be stopped by software during a transmission period. setting a value of 11 on bits [1:0] of this register is not allowed. note: a transmission period is defined as the time from when a card data or access related command is submitted to the end of the access operation. note: the sdhc bus clock does not stop immediately after writing to this bit. polling needs to be done on the status card_bus_clk_run bit to ensure the sdhc clock is running. refer to example 27-1 for procedures to start the sd bus clock. 0no effect 1 to stop the mmc/sd clock secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-10 freescale semiconductor 0x1001_3004 (status1) 0x1001_4004 (status2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r car d_in sert ion car d_re mova l ybuf _emp ty xbuf _emp ty ybuf _ful l xbuf _ful l buf_ und_ run buf_ ovfl 000000 00 ww1c w1c reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 sdio _int_ acti ve end_ cmd _res p writ e_op _don e read _tra ns_d one wr_crc_e rr_code car d_bu s_cl k_ru n buf_ read _rdy buf_ wr_ rdy resp _crc _err 0 read _crc _err writ e_cr c_er r time_ out_ resp tim e_o ut_ rea d w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000000000 00 figure 27-5. sdhc status register table 27-7. sdhc status register field descriptions field description 31 card_insertion card insertion. when this bit is set, the sdhc detects a value transition on the sd_dat[3:0] from 0111 to 1111. this can be used to detect whether a card is inserted to the card socket based on sd_dat[3] pull-up resistor of the card dat3. when this bit is set, the sdhc will generate an interrupt request if the card detection interrupt is enabled. this bit is read-only and can be cleared by writing a ?1? to this bit. 0 no card insertion detected 1 card insertion detected based on logic level changed on sd_dat[3] 30 card_removal card removal. when this bit is set, the sdhc detects a logic transition on the sd_dat[3:0] from 1111 to b0111. this can be used to detect whether a card is removed from the card socket based on the sd_dat[3] pull-up resistor of the card dat3. when this bit is set, sdhc will generate an interrupt request if the card removal interrupt is enabled. this bit is read-only and can be cleared by writing a ?1? to it. the user needs to clear this bit to clear the interrupt request from sdhc when the card detection interrupt is enabled. 0 no card removal detected 1 card removal detected based on logic level changed on sd_dat[3] 29 ybuf_empty y data buffer empty. when this is set, it indicates that the y data buffer is empty during a write transfer. this bit is automatically cleared when the first byte of data is moved into the fifo. refer to section 27.4.1, ?data buffers ? for more information about the data buffers . 0 y buffer is not empty. 1 y buffer is empty. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-11 28 xbuf_empty x data buffer empty. when this is set, it indicates that the x data buffer is empty during a write transfer. this bit is automatically cleared when the first byte of data is moved into the fifo. refer to section 27.4.1, ?data buffers ? for more information about the data buffers. 0 x buffer is not empty. 1 x buffer is empty. 27 ybuf_full y data buffer full. when this is set, it indicates that the y data buffer is full during a read transfer. this bit is automatically cleared when the last byte of data is read out from the fifo. refer to section 27.4.1, ?data buffers ? for more information about the data buffers. 0 y buffer is not full. 1 y buffer is full. 26 xbuf_full x data buffer empty. when this is set, it indicates that the x data buffer is full during a read transfer. this bit is automatically cleared when the last byte of data is read out from the fifo. refer to section 27.4.1, ?data buffers ? for more information about the data buffers. 0 x buffer is not full. 1 x buffer is full. 25 buf_und_run buffer underrun. when this is set, it indicates that both x and y data buffers are empty during a write transfer. in this case, the card clock mmc_sd_clk will be stopped automatically by hardware to wait for the dma or cpu to put data into the buffers. an interrupt is triggered if the corresponding interrupt control bit is enabled. 0 no buffer underrun 1 buffer underrun during a write operation 24 buf_ovfl buffer overflow. when this is set, it indicates that both data buffers are full during a read operation. in this case, the card clock mmc_sd_clk will be stopped automatically by hardware to wait for the dma or cpu to remove data out of one of the buffers. an interrupt is triggered if the corresponding interrupt control bit is enabled. excess data will be ignored by the sdhc. 0 no buffer overflow 1 buffer overflow during a read operation 23?15 n/a 14 sdio_int_active sdio interrupt active. this indicates whether an interrupt from the sdio card has been detected. when this bit is set, the sdhc generates an interrupt request if the sdio interrupt is enabled. the user should clear the status to clear the interrupt request. a separate acknowledge command to the card may be required to clear the source of the sdio interrupt. writing a ?1? to this bit clears it. 0 no interrupt detected 1 interrupt detected using sdio card bus 13 end_cmd_resp end command response. this indicates that a command was successfully transmitted to the card and the corresponding response stored in the response fifo. this occurs after each command operation. when this bit is set, the sdhc generates an interrupt request if the end_cmd_resp interrupt is enabled. the user needs to clear this bit to negate the interrupt request. this bit is cleared by using a write ?1? to clear operation. 0 command not successful, incomplete, or not applicable (no response) 1 command transmitted successfully (response received) note: when this bit is set, the user also needs to check if the command send and response receive operation completed without error. the user also needs to check the resp_crc_err (status[5]) and time_out_resp(status[1]) bits to determine if an error occurred. table 27-7. sdhc status register field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-12 freescale semiconductor 12 write_op_done write operation done. this indicates that a write operation has completed. the flash card needs extra idle time for write accesses. this requires the sdhc module to wait until the card writes the buffered data to the inner flash memory. the sdhc module automatically detects the status. the write_op_done flag indicates the end of the write operation. when this bit is set, the pre-defined data bytes are written to the card. the user needs to send a stop command to the card if the write command is a mmc/sd card write multi-block command. when this bit is set, sdhc generates an interrupt request if the write_op_done interrupt enable is enabled. the user needs to clear this bit to clear the interrupt. this is accomplished by writing ?1? to this bit. 0 write operation in progress or incomplete 1 write operation complete note: when this bit is set, the user also needs to check if the write operation completed without a crc error. the user needs to check the wr_crc_err_code[1:0] (status[10:9]) and write_crc_err (status[2]) bits to determine if an error has occurred. 11 read_op_done read operation done. the read_op_done status bit is activated at the end of a read operation, which means all the data is received from the card. when this bit is set, the pre-defined data bytes are read from the card or a read timeout occurs. the software needs to send a stop command to card if the read command is a mmc or sd card read multi-block command. this bit can be cleared by writing ?1? to it. when this bit is set, sdhc generates an interrupt request if the read_op_done interrupt is enabled. the user needs to clear this bit to clear the interrupt request. writing ?1? to this bit clears the status. 0 read operation in progress or incomplete 1 read operation complete note: when this bit is set, the user also needs to check if the read operation complete without error. the user needs to check the read_crc_err (status[3])and time_out_read(status[0]) bits to determine if an error has occurred. 10?9 wr_crc_error_code write crc error code. this indicates the crc results from the card at the end of write operations. after receiving a block of data, the card checks the crc bit and sends the crc status. these two bits reflect the crc status of the recent written data. if the card returns a negative crc status, the data is not written to the card. these two bits can be cleared by writing a value of ?11? to them. 00 no transmission error, crc status is 010 (positive) 01 transmission error, crc status is 101 (negative) 10 no crc response 11 reserved note: these bits have valid value only when the write_crc_err status bit (status[2]) is set. 8 card_bus_clk_run card bus clock run. this indicates whether the mmc_sd_clk clock to the card is running. the clock rate setting and system configuration can be modified when the clock is turned off by setting the stop_clk bit in str_stp_clk register. this bit can only be cleared by writing ?1? to stop_clk bit in str_stp_clk clock control register to stop mmc_sd_clk. 0 mmc/sd clock is stopped. 1 mmc/sd clock is running. note: polling needs to be done on this bit to assure the sdhc clock is running or stopped. refer to example 27-1 . table 27-7. sdhc status register field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-13 27.3.3.3 sdhc clock rate register (clk_rate) refer to section 27.4.8, ?system clock controller ? for the clock scheme. 7 buf_read_ready buffer read ready. this status is set if a buffer (either x buffer or y buffer) is full during read operations. an interrupt is triggered for non-dma transfers if buf_read_en is set, or a dma request is asserted for dma transfers. note: the read_op_done status bit will be set once all the data is read from the card. at the end of read, the buffer read ready interrupt occurs the same time as the read done. the user can service the buffer read ready interrupt and then handle the read_op_done interrupt. 0 not ready to read buffer 1 ready to read buffer 6 buf_write_ready buffer write ready. this status is set if a buffer (either x buffer or y buffer) is available during write operations. an interrupt is triggered for non-dma transfers if the buf_write_en bit is set, or a dma request is asserted for dma transfers. this bit is set only when sdhc performs a write operation to the card. 0 not ready to write buffer 1 ready to write buffer 5 resp_crc_err response crc error. this indicates that a transmission error occurred on the sd_cmd line during a response transfer. write ?1? to this bit to clear it. 0 no error 1 response crc error occurred. 4n/a 3 read_crc_err read crc error. this indicates that a transmission error occurred on the sd_dat line during a card read. the user should re-try the transmission. write ?1? to this bit to clear it. 0 no error 1 crc read error occurred. 2 write_crc_err write crc error. this indicates that a transmission error occurred on the sd_dat line during a card write operation. the user should check the wr_crc_err_code field for more information about the crc error. write ?1? to this bit to clear it. 0 no error 1 crc write error occurred. 1 time_out_resp time out response. this indicates that the command response was not received in the time specified in the res_to register. this can be caused by: an unsupported command was received at the card(s). another mmc/sd_op_cond command submitted after all cards had already sent their voltage ranges and the power-up routine was finished. an identification command issued when all cards were already in standby state. no card is on the bus. write ?1? to this bit to clear this condition. 0 no error 1 time out response error occurred. 0 time_out_read time out read. indicates that the expected data from the card was not received in the time specified in the read_to register. the time_out_read is cleared by an internal status change or by removing the source of the error. write ?1? to this bit to clear it. 0 no error 1 time out read data error occurred table 27-7. sdhc status register field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-14 freescale semiconductor the high frequency input clock, ipg_perclk, is used to derive the low frequency clock to be used by the card and some of its internal logic. the divide ci rcuitry consists of a 4-bit divider followed by a 12-bit prescaler. the ipg_perclk is first divided by the 4-bit divider to derive the signal, clk_div. clk_div is then divided by the 12-bit prescaler to derive clk_20m, which is the source clock to be gated for internal logic and external cards. clk_20m is used internally by the sdhc. the mmc _sd_clk is a buffered and gated version of the clk_20m clock. see figure 27-6 for an illustration of valid bits in the sdhc clock rate register and table 27-8 for descriptions of the bit fields. 0x1001_3008 (clk_rate1) 0x1001_4008 (clk_rate2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r clk_prescaler[15:4] clk_divider[3:0] w reset00000000000010 00 figure 27-6. sdhc clock rate register table 27-8. sdhc clock rate register field descriptions field description 31?16 n/a secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-15 note the maximum frequency of mmc_sd_clk is ipg_perclk /2. 27.3.3.4 sdhc command and data control register (cmd_dat_cont) the sdhc command and data control register allows the user to specify the format of data and response, and to control the read/wait cycle. afte r configuring this register, enabling the mmc_sd_clk will cause the command and argument configured in the cmd number register and the cmd argument register to be sent out to the card. see figure 27-7 for an illustration of valid bits in the sdhc command and data control register and table 27-9 for descriptions of the bit fields. 15?4 clk_prescaler clock prescaler. specifies the divider value to generate clk_20m from clk_div. 0x000 clk_20m is clk_div 0x001 clk_20m is clk_div/2 0x002 clk_20m is clk_div/4 0x004 clk_20m is clk_div/8 0x008 clk_20m is clk_div/16 0x010 clk_20m is clk_div/32 0x020 clk_20m is clk_div/64 0x040 clk_20m is clk_div/128 0x080 clk_20m is clk_div/256 0x100 clk_20m is clk_div/512 0x200 clk_20m is clk_div/1024 0x400 clk_20m is clk_div/2048 0x800 clk_20m is clk_div/4096 others reserved 3?0 clk_divider clock divider. specifies the divider value to generate clk_div from input clock ipg_perclk. 0x1 clk_div is ipg_perclk/2 0x2 clk_div is ipg_perclk/3 0x3 clk_div is ipg_perclk /4 0x4 clk_div is ipg_perclk /5 0x5 clk_div is ipg_perclk /6 0x6 clk_div is ipg_perclk /7 0x7 clk_div is ipg_perclk /8 0x8 clk_div is ipg_perclk /9 0x9 clk_div is ipg_perclk /10 0xa clk_div is ipg_perclk /11 0xb clk_div is ipg_perclk /12 0xc clk_div is ipg_perclk /13 0xd clk_div is ipg_perclk /14 0xe clk_div is ipg_perclk /15 0xf clk_div is ipg_perclk /16 others reserved table 27-8. sdhc clock rate regist er field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-16 freescale semiconductor 0x1001_300c (cmd_dat_cont1) 0x1001_400c (cmd_dat_cont2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmd _res ume 00cmd _res p_lo ng_ off stop _rea dwai t star t_re adw ait bus_width init 00 writ e_re ad data _ena ble format_of_resp onse w reset00000000000000 00 figure 27-7. sdhc command and data control register table 27-9. sdhc command and data control register field description field description 31?16 n/a 15 cmd_resume command resume. used to restore command and data control register after read/wait cycle for sdio card. 0 issues command to card. 1 does not issue command to card. 14?13 n/a 12 cmd_resp_long_off command response long off. allows status[13] end_cmd_resp bit to be self cleared when the condition to generate this bit disappears. this is utilized in the read/wait cycle. for sd/mmc operation, the user should keep this bit set as ?0?. 0 bit was not cleared when read. 1 allows bit to be cleared. 11 stop_readwait stop read/wait. ends the read/wait cycle for sdio. when this bit is set, the sdhc will not drive dat2 output low so that the sdio card would end the read/wait cycle. for operation of sd/mmc, the user should keep this bit set as ?0?. 0no effect 1 ends read/wait cycle. 10 start_readwait start read/wait. starts the read/wait cycle for sdio. when this bit is set, the sdhc will make the dat2 output low and force the sdio card to enter readwait cycle. for sd/mmc operation, the user should keep this bit set as ?0?. 0no effect 1 starts read/wait cycle. 9?8 bus_width bus width. specifies the width of the data bus. these two bit s must be set according to current sd/sdio card bit mode. for mmc card, only 1-bit bus mode is supported. 00 1-bit 01 reserved 10 4-bit 11 reserved secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-17 27.3.3.5 sdhc response time out register (res_to) the mmc/sd response time out register defines an in terval within which a response must be returned, or a time-out error will occur. after the sdhc se nds out a command, if the card does not respond within the specified interval, the response timeout status bit (status[1]) and the end_cmd_resp status bit (status[13]) will be set. see figure 27-8 for an illustration of valid bits in the mmc/sd response time out register and table 27-10 for descriptions of the bit fields. 7 init initialize. specifies whether the additional 80-clock cycle prefix (to initialize the card) will occur before every command. init enables/disables the additional 80-clock initialization time. 0 disable 80 initialization clocks. 1 enable 80 initialization clocks. 6?5 n/a 4 write_read write/read. specifies whether the data transfer of the current command is a write or read. operation 0read 1write 3 data_enable data enable. specifies whether the current command includes a data transfer. 0 no data transfer included 1 date transfer included 2?0 format_of_response format of response. sets the expected response format for current command. refer to the sd i/o specification 1.0 for detail information of the response format. 000 no response for current command 001 48-bit response with crc7 check. for example: format r1/r1b/r5/r6. 010 136-bit, csd/cid read response. for example: format r2. 011 48-bit response without crc check. for example: format r3/r4. others reserved 0x1001_3010 (res_to1) 0x1001_4010 (res_to2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 response time out[7:0] w reset00000000010000 00 figure 27-8. mmc/sd response time out register table 27-9. sdhc command and data contro l register field description (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-18 freescale semiconductor 27.3.3.6 sdhc read time out register (read_to) the mmc/sd read time out register defines an interval that read data must be returned within or a time out error will occur. after the sdhc sends out the da ta read command, if no data is returned within the specified interval, the read timeout status b it (status[0]) and the read_op_done status bit (status[11]) will be set. see figure 27-9 for an illustration of valid bits in the sdhc read time out register and table 27-11 for descriptions of the bit fields. table 27-10. mmc/sd response time out register field descriptions field description 31?8 n/a 7?0 response time out response time out. this value determines the interval by which response time-out is detected. the clock starts counting when the last bit of the command is sent. the clock counts unit is mmc_sd_clk to card. 0x01 1 clock count 0x02 2 clock counts ... ... 0xff 255 clock counts 0x1001_3014 (read_to1) 0x1001_4014 (read_to2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data_read_time_out[15:0] w reset11111111111111 11 figure 27-9. sdhc read time out register secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-19 27.3.3.7 sdhc block length register (blk_len) the sdhc block length register defines the number of bytes in a block (block size). since the stream mode of mmc is not supported, the block length must be set for every transfer. the block length supported by the sdhc ranges from 1 bytes to 2048 bytes, but th e user needs to check the block size supported by the card before configuring this register. for the sdio, the block length must be less than the maximum block size defined in the card?s cccr. for the sd/ mmc, the block length must be less than the maximum block size defined in the card?s csd register. note the software should write to this register only when no sd bus transaction is executing. see figure 27-10 for an illustration of valid bits in the sdhc block length register and table 27-12 for descriptions of the bit fields. table 27-11. sdhc read time out register field descriptions field description 31?16 n/a 15?0 data_read_time_out data read time out. this value determines the interval by which read data time-outs are detected. the user needs to check the timeout limit of the card and the clock frequency to configure this register. for safety, 0xffff is recommended. the timeout clock starts counting when the last bit of the command is sent. the count unit is mmc_sd_clk/256. the maximum delay the sdhc can tolerate for a data timeout is related to the card clock. if the clock is 25 mhz and this register is 0xffff, the maximum delay which the sdhc waits will be about 670ms. if the card does not give data in 670 ms, sdhc will issue a data read time-out error and terminate the current data read operation. this is designed to meet the sd physical layer specification, with typical time-out limit to be 100ms~200ms. but for some sdio cards, the time-out limit may be up to 1 s. in such case, the user needs to lower the mmc_sd_clk frequency to accommodate the delay to 1 s, which requires configuring the mmc_sd_clk to about 16 mhz and setting this register for 0xffff. 0x1001_3018 (blk_len1) 0x1001_4018 (blk_len2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000 block length[11:0] w reset00000000000000 00 figure 27-10. sdhc block length register secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-20 freescale semiconductor 27.3.3.8 sdhc number of blocks register (nob) the sdhc number of blocks register defines the numbe r of blocks in the multi- block transfer mode. this register and the block length regi ster determines the number of byt es to be transferred during one command. the number is decremented ev ery time a block transfer is comp leted and stops when the count reaches zero. when all data transfers are complete d, the status[11] read_op_done is set if it is a read (from card) transfer, or the status[12] write_op_done is set if it is a write (to card) transfer. the software should write to this register only when no mmc/sd transaction is executing. the nob and the blk_len defines the maximum data to be transferred in a single data transfer command. maximum data size to be transferred in bytes = block length x number of blocks. see figure 27-11 for an illustration of valid bits in the sdhc number of blocks register and table 27-13 for descriptions of the bit fields. table 27-12. sdhc block length register field descriptions field description 31?12 n/a 11?0 block length block length. specifies the number of bytes in a block during data transfer (block size). for the mmc and sd cards, the value set must keep same as the blk_len set in the card. for the sdio, the io access is performed through the cmd53 io_rw_extend command. this command has two modes: byte mode. for byte mode, its operation is similar to a single block transfer command for sd where the block length is the byte count in the command argument. block mode. for block mode, its operation is similar to a multi-block transfer command for the sd where the block length is the block size defined in the command argument. for multi-block data transfers, a block length that is equal to an integer multiple of the data buffer size is preferred. otherwise, the buffer utilization would be poor. if the data size that needs to be transferred is not an integer multiple of the buffer size, there are two options to transfer the data: option 1: the user needs to split the transaction. the remainder of block size data is transferred by using a single block command for the last transfer. option 2: the user needs to add filler data in the last block to fill the block size to be as large as the buffer size. the data buffer size is 64 bytes in 4-bit mode and 16 bytes in 1-bit mode.refer to section 27.4.1, ?data buffers ? for more information about data buffers. 0x000 0 byte 0x001 1 byte ... ... 0x7ff 2047 bytes 0x800 2048 bytes 0x801?0xfff reserved secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-21 27.3.3.9 sdhc revision number register (rev_no) the read-only sdhc revision number register is a read-only register that displays the revision number of the module. see figure 27-12 for an illustration of valid bits in the sdhc revision number register and table 27-14 for descriptions of the bit fields. 0x1001_301c (nob1) 0x1001_401c (nob2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nob[15:0] w reset00000000000000 00 figure 27-11. sdhc number of blocks register table 27-13. sdhc number of blocks register field descriptions field description 31?16 n/a 15?0 nob specifies the number of blocks in a block transfer. one block should be set if the data transfer command is a single block transfer command or io_rw_extend (cmd53) in byte mode. for multi-block transfer commands to sd/mmc card and io_rw_extend (cmd53 ) in block mode to sdio card, this register should be set for the block count the software expected. the maximum block number to be transferred for command can be as large as 65535. blocks can range in length from 0 to 65535 bytes. for sd memory card or a memory parts of a sdio combo card, the user will need to send cmd12 to stop the multi-block transfer. for a sdio cmd53 in block mode and if user needs to abort the transfer earlier, the user needs to use cmd52 io-abort to abort the transfer. 0x0000 0 block 0x0001 1 block ... ... 0xffff 65535 blocks note: the maximum transfer blocks is 64 kbytes. if the user uses infinite transfer command to transfer data, such as multi-block transfer command for memory card or infinite block transfer cmd53 for sdio card, this register needs to be set to the real number of blocks that the user expected to transfer. the user also needs to abort the transfer through cmd12 or cmd52 io-abort to do this. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-22 freescale semiconductor 27.3.3.10 sdhc interrupt control register (int_cntr) when certain events occur in the module, the sdhc has the ability to set an interrupt as well as to set corresponding status register bits. the sdhc interrupt control register allows the user to control whether these interrupts should occur. see figure 27-13 for an illustration of valid bits in the sdhc interrupt control register and table 27-15 for descriptions of the bit fields. 0x1001_3020 (rev_no1) 0x1001_4020 (rev_no2) access: user read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r revision number[15:0] w reset00000100000000 00 figure 27-12. sdhc revision number register table 27-14. sdhc revision number register field descriptions field description 31?16 n/a 15?0 revision number revision number. specifies the revision number of the mmc/sd module. this is fixed at 0x0000_0400. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-23 0x1001_3024 (int_cntr1) 0x1001_4024 (int_cntr2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000 sdio _int_ wkp _en card _inse rt_w kp_en car d_r emo val _wk p_e n w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r car d_in sert ion_ en car d_re mova l_en sdio _irq _en dat0 _en 0000000 buf_ read _en buf_ writ e_en end_ cmd _res write _op_d one rea d_o p_d one w reset00000000000000 00 figure 27-13. sdhc interrupt control register table 27-15. sdhc interrupt control register field descriptions field description 31?19 n/a 18 sdio_int_wkp_en sdio interrupt wake-up enable. when int_cntr[13] is set to a ?1? (sdio interrupt enabled), this bit controls whether a sdio card interrupt is detected synchronously or asynchronously. to set this bit, the sdio card interrupt is detected asynchronously and the sdio card interrupt is used as a wake-up event. set this bit only in low power mode or when all the clocks to sdhc are off. 0 disable sdio card interrupt as wake-up event. 1 enable sdio card interrupt as wake-up event. 17 card_insertion_wkp_en card insertion wake-up enable. when int_cntr[15] is set to a ?1? (card insertion interrupt enabled), this bit controls whether a card insertion interrupt is detected synchronously or asynchronously. to set this bit, the card insertion interrupt is captured asynchronously and the interrupt is used as a wake-up event. set this bit only in low power mode or when all the clocks to sdhc are off. 0 disable card insertion as wake-up event. 1 enable card insertion as wake-up event. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-24 freescale semiconductor 16 card_removal_wkp_en card removal wake-up enable. when int_cntr[14] is set to a ?1? (card removal interrupt enabled), this bit controls whether the card removal interrupt is detected synchronously or asynchronously. to set this bit, the card removal interrupt is detected asynchronously and the interrupt is used as a wake-up event. set this bit only in low power mode or when all the clocks to sdhc are off. 0 disable card removal as wake-up event 1 enable card removal as wake-up event 15 card_insertion_en card insertion enable. setting this bit enables the card insertion interrupt. since the card detection is through the value of dat3 data line, if this card is in 4-bit mode, any data transfers in the dat3 line cause false card insertion interrupts to be generated. the card insertion interrupt should be disabled after the first time the card insertion is detected. to avoid the false status bit generation during data transfer, the card insertion status will be masked by this bit. it should be enabled only after the card is removed from the socket. the default of this bit is to disable the card insertion interrupt. when this interrupt is detected, the user needs to write a ?1? to the status[31] bit to clear the card insertion status interrupt. 0 card insertion interrupt disabled 1 card insertion interrupt enabled note: int_cntr[17] card_insertion_wkp_en controls whether this interrupt is detected asynchronously or synchronously. 14 card_removal_en card removal enable. setting this bit enables the card removal interrupt. since card detection is through the value of the dat3 data line, if this card is in 4-bit mode, the data transfer through the dat3 line causes false card removal interrupt to be generated. the card removal interrupt should be enabled only when there are no active data transfers on the dat3 line. to avoid the false status bit generation during data transfer, the card insertion status will be masked by this bit. the default of this bit is to disable the card removal interrupt. when this interrupt is detected, the user needs to write a ?1? to the status[30] bit to clear the card removal status interrupt. 0 card removal interrupt disabled 1 card removal interrupt enabled note: int_cntr[16] card_removal_wkp_en controls whether this interrupt is detected asynchronously or synchronously. 13 sdio_int_en sdio interrupt enable. masks the interrupt from the sd i/o card to the sdhc module interrupt. 0 sd i/o interrupt disabled 1 sd i/o interrupt enabled note: int_cntr[18] sdio_int_wkp_en controls whether this interrupt is detected asynchronously or synchronously. 12 dat0_en data enable. identifies how the sd i/o interrupt is detected. an interrupt is determined by sd_dat [1] low, but this bit is an option setting for the sdio bit. when sdhc is preforming data transfer and the sd bus mode is 1-bit mode, the user should set this bit to ?0?. 0 sd i/o?s interrupt detection based on sd_dat[3:0] = 110x 1 sd i/o?s interrupt detection based on sd_dat[3:0] = 1101 11?5 n/a table 27-15. sdhc interrupt control register field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-25 when an interrupt is generated, there may be some erro r bits in the status register set as well as the interrupt status. the user needs to check the error stat us bit to make sure there is no error in the sdhc operation. for example, when the read_op_done (status[11]) status is set or the read_op_done interrupt is detected, the user need s to check both the status[3] and status[0] bits as well to make sure the read operation completed without a crc error or a time out error. another example is a write operation, if both the wr ite_op_done(status[12]) and write_crc_err (status[2]) bits are set. this means the write operation ended with crc error. see table 27-16 for a summary of the relationship between the interrupt, inte rrupt control register, and status registers in the sdhc. 4 buf_read_en bus read enable. this bit controls the buffer read ready interrupt. if the bit is ?1?, the interrupt is enabled. when the buffer becomes full during a read operation, an interrupt is generated. the user needs to move the data out of the fifo and clear the buf_read_ready bit to clear the interrupt. 0 buffer status interrupt is disabled. 1 buffer status interrupt is enabled. 3 buf_write_en bus write enable. this bit controls the buffer write ready interrupt. if the bit is ?1?, the interrupt is enabled. when the buffer becomes empty during a write operation, an interrupt will be generated. the user needs to write data to the fifo and clear the buf_write_ready bit to clear the interrupt. 0 buffer status interrupt is disabled. 1 buffer status interrupt is enabled. 2 end_cmd_res end command response. this bit controls the interrupt generation on the status at the end of the command response. when this bit is ?1?, the sdhc generates an interrupt at the end of the command response status. 0 end command-response interrupt is disabled. 1 end command-response interrupt is enabled. 1 write_op_done write operation done. this bit controls the interrupt generation for the status of write operation. when the interrupt enabled, the sdhc generates an interrupt when the configured bytes of data are transferred to the card. 0 write_op_done interrupt is disabled. 1 write_op_done interrupt is enabled. 0 read_op_done read operation done. this bit controls the interrupt generation for the status of read operation completion. when the interrupt is enabled, the sdhc generates an interrupt when the pre-defined bytes of data are transferred from the card. 0 read_op_done interrupt is disabled. 1 read_op_done interrupt is enabled. table 27-15. sdhc interrupt control register field descriptions (continued) field description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-26 freescale semiconductor 27.3.3.11 sdhc command number register (cmd) the command to the sd card is always 48 bits long. it contains one start bit, one direction bit, six command number bits, 32 argument bits, seven crc bits, and one end bit. for more details on the format of the command, refer to the sd physical layer specification. refer to table 27-21 for mmc/sd/sdio cards command list and the related card specification fo r the detailed information about each command. in sdhc, the command start bit, direction bit, crc7 bits, and end bit are auto matically generated by the hardware. configure the sdhc command number regist er and sdhc command argument register to issue a command to the card. see figure 27-14 for an illustration of valid bits in the sdhc command number register and table 27-17 for descriptions of the bit fields. table 27-16. interrupt mechanisms source status bit name (status bit number) does this status generate interrupt directly? int_control register bit name (int_cntr bit number) interrupt/status clear method time_out_read (0) no, alert by using the read_op_done bit in the sdhc status register read_op_done (0) clear status by writing ?1?. time_out_resp (1) no, alert by using the end_cmd_resp bit in the sdhc status register end_cmd_res (2) clear status by writing ?1?. write_crc_err (2) no, alert by using the write_op_done bit in the sdhc status register write_op_done (1) clear status by writing ?1?. read_crc_err (3) no, alert by way of the read_op_done bit in the sdhc status register read_op_done (0) clear status by writing ?1?. resp_crc_err (5) no, alert by using the end_cmd_resp bit in the sdhc status register end_cmd_res (2) clear status by writing ?1?. buf_wr_rdy (6) yes buf_write_en (3) clear status by writing data to fifo buffer. buf_read_rdy (7) yes buf_read_en (4) clear status by reading data from fifo buffer. read_op_done(11) yes read_op_done (0) clear status by writing ?1?. write_op_done(12) yes write_op_done (1) clear status by writing ?1?. end_cmd_resp(13) yes end_cmd_resp (2) clear status by writing ?1?. sdio_int_active(14) yes sdio_int_en (13) clear status by writing ?1?. card_removal(30) yes card_removal_en (14) clear status by writing ?1?. card_insertion(31) yes card_insertion_e n (15) clear status by writing ?1?. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-27 27.3.3.12 sdhc cmd argument register (arg) this register contains the mmc/sd/sdio command argument. see figure 27-15 for an illustration of valid bits in the sdhc command argument register and table 27-18 for descriptions of the bit fields. 0x1001_3028 (cmd1) 0x1001_4028 (cmd2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 command number w reset00000000000000 00 figure 27-14. sdhc command number register table 27-17. sdhc command number register field descriptions field description 31?6 n/a 5?0 command number command number. the sdhc module communicates with the mmc/sd/sdio card(s) by sending commands and arguments. the command to send is set in the mmc/sd command number register (cmd) and the argument is defined in sdhc cmd argument register (arg). see ta bl e 2 7 - 2 1 for the brief information of the full list of mmc/sd/sdio commands. 0x00 cmd0 0x01 cmd1 ... ... 0x3f cmd63 note: the user should check the detailed information from the related card specification. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-28 freescale semiconductor 27.3.3.13 sdhc response fifo access register (res_fifo) there is an 8 x 16 bit fifo to store the response from the card in sdhc. this register is used to access this fifo. the msb 16 bits of the response is a ccessed first and the lsb 16 bits is accessed last. see figure 27-16 for an illustration of valid bits in th e sdhc response fifo access register and table 27-19 for descriptions of the bit fields. 0x1001_302c (arg1) 0x1001_402c (arg2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r arg[31:16] w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r arg[15:0] w reset00000000000000 00 figure 27-15. sdhc command argument register table 27-18. sdhc command argument register field descriptions field description 31?0 arg command argument. specifies the argument for the current command. note: the user should check the detailed command argument information from the related card specification. 0x1001_3034 (res_fifo1) 0x1001_4034 (res_fifo2) access: user read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r response_content w reset00000000000000 00 figure 27-16. sdhc response fifo register secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-29 27.3.3.14 sdhc data buffer access register (buffer_access) the sdhc uses two 64-byte data buffers in a ping-pong manner?while one buffer is receiving new transmission information, the other buffer is deleting th e previous transmission. data can be transferred by the dma and the sd card simultaneously to max imize throughput between the two clock domains (that is, the ip peripheral clock, ipg_perclk, and the host clock, clk_20m). these buffers are used as temporary storage for data being tran sferred between the host system and the card and vice versa. the user can read or write data to the buffers through this buffer access register. refer to section 27.4.1, ?data buffers ? for more information about the data buffers. in the read operation, the sdhc stores the data received from the card into the buffer. the user needs to move the data out of the buffer when the buffer is full. in the write operation, the sdhc fetches data from the buffer and transfers them to the card. the user can then access the data buffer through the sdhc data buf fer access register. the user needs to move data into the buffer when the buffer is empty. see figure 27-17 for an illustration of valid bits in the sdhc data buffer access register and table 27-20 for descriptions of the bit fields. table 27-19. sdhc response fifo register field descriptions field description 31?16 n/a 15?0 response_content response content fifo access register. there is a fifo in the sdhc that is used to store the command response received from card. every time the host sends a command to a card, the current contents stored in the fifo are cleared and new response arguments are stored into the response fifo. according to the sd card specification, the command response size can be 48 bits or 136 bits (r2 response). refer to the sd memory card specification for more detailed information about the command response format. the size of response fifo is 8 x 16 bits (128 bits). for a 48-bit response, only 48 bits of the fifo have valid contents. the user must perform three reads to this response fifo access register to retrieve the entire 48-bit response content. for a 136-bit r2 response (response for cid[127:0] or csd[127:0] register), only the contents of the 128-bit cid and csd register are stored in the response fifo. this first byte of the r2 response is not stored in the response fifo. the user can retrieve the cis/csd register from the response fifo through eight accesses to the fifo access register. all the crc bits in the response are not stored in the response fifo. this response fifo is read-only. note: the crc7 and end bit for response is hardware checked by sdhc and the corresponding field of the response will not be stored in the response fifos. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-30 freescale semiconductor 27.4 functional description the following sections provide a brie f functional description of the ma jor system blocks, including the dma interface, memory controller, logic/comma nd controller, and syst em clock controller. 27.4.1 data buffers the sdhc uses two data buffers in a ping-pong manne r so that data can be transferred by the dma and the sd card simultaneously to maximize throughput between the two clock domains (that is, the ip peripheral clock, ipg_perclck, and the host clock, clk_20m). see figure 27-18 for an illustration of the buffer scheme. these buffers are used as temporar y storage for data being transferred between the host system and the card. 0x1001_3038 (buffer_access1) 0x1001_4038 (buffer_access2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fifo content[31:16] w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fifo content[15:0] w reset00000000000000 00 figure 27-17. sdhc buffer access register table 27-20. sdhc buffer access register field descriptions field description 31?0 fifo content first in/first out content. these bits hold 32-bit data upon a read or write transfer. the size of the fifo is 4 x 32 bits (16 bytes in total) for sd 1-bit mode and 16 x 32 bits (64 bytes in total) for sd 4-bit mode. for reception, the sdhc controller generates a dma request when the fifo is full. upon receiving this request, dma starts transferring data from the sdhc fifo to system memory by reading the data buffer access register for a number of pre-defined bytes. for transmit, the sdhc controller generates a dma request when the fifo is empty. upon receiving this request, dma starts moving data from the system memory to the sdhc fifo by writing to the data buffer access register for a number of pre-defined bytes. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-31 figure 27-18. sdhc buffer scheme for a host-read operation, the sdhc automatically transfer s data into the next available buffer. it is then read out by the dma and written to the system memory when the dma request from sdhc becomes highest priority in the dma arbiter. conversely, fo r a host-write operation, the dma writes data into the next available buffer. the sdhc then reads the data out of the buffer and writes it to the card through the sd host interface. 27.4.1.1 data buffer access dma/cpu accesses the data buffer of sdhc thr ough the 32-bit data buffer access (dba) register. internally, the sdhc maintains a pointer into the data buffer. accesses to the dba register will increase the address value of the pointer. the pointer value of sdhc is not directly accessible by the software. the pointer refers to a 32-bit port-size fifo, so all the ac cess to the fifo must be 32-bit size. sequential and contiguous access is necessary to increase the point er address value correctly. random or skipped access is not allowed. in some cases, when the block length of the data transfer is not a multiple of 32 bits, the last data access to the fifo may be 24-bit, 16-bit or 8-bit. since sdhc fifo allows only 32-bit access sizes, the user must put/get the data bytes on the co rrect byte lanes of the sdhc 32-bit data bus. the byte arrangement order is little endian format. for an 8-bit data access to the fifo, it will be in bit[7?0] of the data bus. for 16-bit data access, the data will be in the bit[15?0] of the data bus . for a 24-bit data access, the data will be in the bit[23?0] of the data bus. when data goes to the card, the 32-bit data in the data buffer fifo will be shifted out to card from the lsb byte to the msb byte, but for each byte, the bit sequence of the shift will be from msb bit to lsb bit. when read data leaves the card, the data shifted in w ill be stored from lsb byte to msb byte in the data buffer fifo. see figure 27-19 for the bytes lane relationship betw een the card bus and sdhc ip bus. ip bus i/f sd bus i/f buffer control sdhc registers x buffer y buffer dma_req sdhc_irq secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-32 freescale semiconductor figure 27-19. byte lanes relationship between system ip bus and sd card bus 27.4.1.2 write operation sequence there are two ways to write data to the buffer when th e user transfer data to the card. one way is by using dma through the sdhc dma request signal. th e other way is by using the cpu through the buf_wr_rdy (status[6]) bit (interrupt or polling). the sdhc asserts a dma request when the data buffe r is empty and ready to receive new data. at the same time, the sdhc would set the buf_wr_rdy (s tatus[6]) bit. the buffer write ready interrupt will be generated if it is enabled by the software. the buffer accumulates the data writte n through the data port until the da ta count reaches the buffer size. the sdhc will not start data transmission until a full buf fer size of data is written to the data buffer. the sdhc will start data transmission when the sd bus is ready for new transfer. when the other buffer is empty and more data is to be transferred, the sdhc will assert a new dma request and set the buf_wr_rdy bit. in case the dma does not keep up with moving data into the fifos, the sdhc will stop the sd_clk at the block gap to avoid an data buffer underrun situation. 27.4.1.3 read operation sequence there are two ways to fetch data from the buffer when the user read data from the card. one way is by using dma through the sdhc dma request signal. the other way is by using the cpu through the buf_read_rdy (status[7]) bit (interrupt or polling). the sdhc asserts a dma request when data buffer is full and ready for dma/cpu to fetch the data out of the buffer. at the same time, the sdhc would set the buf_wr_rdy (status[7]) bit. the buffer write ready interrupt will be generate d if it is enabled by the software. the sdhc starts receiving data only when either of the dual data fifo is empty. the buffer accumulates data read from the card until the data count reaches the buffer size. the sdhc a sserts a dma request when either one of the data buffer is full. for multiple bl ock data transfers, while the dma/cpu is moving data by reading the dba register, the sdhc will receive data into the other fifo if it is empty and the sd bus is ready. in case the dma/cpu does not keep up with reading data out of the fifos, the sdhc will stop the sd_clk at the block gap to avoid an overflow situation. 27.4.1.4 data buffer size the user needs to know the buffer size for buffer operatio n during data transfer. in sdhc, both of two data buffers are 64 bytes in size. each data buffer is divi ded into four 16 bytes data buffers that correspond to 31?24 data on system ip bus 7?0 15?8 23?16 31?24 7?0 15?8 23?16 shift out to the card or shift in from the card secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-33 the four data lines of sd bus. thus, each data line in sdhc contains a dual 16- byte buffer. the data buffer size will be 64 bytes in 4-bit sd mode or 16 bytes in 1-bit sd mode. during multi-block data transfer, the block length, whic h is an integer multiple of the buffer size is preferred. the buffer would be ready to read by cpu/dma when either of the buffer is full (status[27] or status[26] is set, and status[7] is set) when full buffer data is written to either of the x or y buffer. the buffer would be ready to write by cpu/dma (status[29] or status[28] is set, and status[6] is set) when the full buffer of data is fetched out of the buffer. the buffer ready status bit and dma request would be set accordingly. for single-block data transfer, when the block length is smaller than the buffer size or when the block length is not an integer multiple of the buffer size, it is possible that the data size that needs to be written to the buffer or to be fetched out of the buffer is smaller than the buffer size. in this case, the buffer would be full (sdhc set status[27] or status[26]) when this data is written to the buffer. the buffer would be empty (sdhc set status[29] or status[28]) when this buffer of data is fe tched out of the buffer. the buffer ready status bit and dma request would be set accordingly. from the software aspect, the buffer size become variable and equal to the real data size that needs to be transferred. this will ease the software programming of sdhc. the user does not need to fill dummy data to make the buffer full. 27.4.1.5 dividing large data transfer this sdio command cmd53 definition limits the maximu m data size of data transfers according to the following formula: maximum data size = block size x block count the block size can be a multiple of the size of the data buffer. however, it is recommended the block size be set equal to the size of data buf fer. this allows the sdhc to stop the sd_clk during block gaps of an overflow or underrun condition occurs. stopping the sd_c lk while the data lines are active may cause data corruption (when the clock resumes) on some card designs available on the market. if an application or card driver is to transfer larger sizes of data, the host driver will divide larger data sizes into multiple blocks. the length of a multiple block transfer needs to be in block size units. if the total data le ngth cannot be divided evenly to a multiple of the block size, then there are two ways to transfer the data depending on the function and card design. one way is for the card driver to split the transaction. the remainder of block size data is then transferred by using a singl e block command at the end. another way is to add dummy data in the last block to fill the block size. in the second method, the card must be able to remove the dummy data. see figure 27-20 for an example that shows dividing of large data transfers. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-34 freescale semiconductor figure 27-20. example for dividing large data transfer 27.4.2 dma interface the dma interface block controls all data routing betw een the external data bus (dma access), internal sdhc module data bus, and internal system fifo access through dedicated state machine. this state machine monitors the status of fifo content (empty or full), fifo address, and byte/block counters for the sdhc module and the application. see figure 27-21 for an illustration of the dma interface block. fcs icv frame body iv 802.11 mac header data 64 bytes data 64 bytes data 64 bytes data 32 bytes sdio data block #1 sdio data block #2 sdio data block #8 sdio data 32 bytes sdio data block #1 sdio data block #2 sdio data block #8 sdio data 32 bytes 544 bytes wlan frame wlan frame is divided equally into 64-byte blocks plus the remainder 32 bytes eight 64-byte blocks are sent in block transfer mode and the remainder 32 bytes are sent in byte transfer mode cmd53 cmd53 secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-35 figure 27-21. dma interface block in addition, this block also handles the burst request to the external dma controller, internal register write-error detection, read/wait handling of sdio, and all ip-related output responses. 27.4.2.1 dma request if the sdhc is in the data transfer state, the sdhc generates dma requests according to its buffer status. during read operations, the sdhc generates dma request s if one of its data buffer is full. during write operations, the sdhc generates dma requests if one of its data buffers is empty. to avoid buffer under-run conditions during a write operation, the mmc_sd_clk stops automatically when both buffers are empty. after the dma or cpu completes writing data into one of the buffers, the mmc_sd_clk automatically resumes to continue the data transfer. similarly, to avoid buffer overflow during read operations, the mmc_sd_clk stops automatically when both buffers are full. after the dma or cpu moves the data out of the buffer, the mmc_sd_clk automatically resumes to continue the data transfer. 27.4.3 memory controller this controller provides the sdio-irq and re ad/wait service handli ng, card detection, command response handling, and all sdhc interrupt handling. th e memory controller also contains the register table. see figure 27-22 for an illustration of the block diagram for the memory controller. reg file ram 32x4 byte counter/ block counter fifo empty/full control host/dma r/w access handler fsm data path multiplexer ram_addr ram_rw ram_data efb, ffb for appl. efb, ffb for host mmc_dreq_b data_in data_out r/w from appl. r/w from host handshake to host host status fifo status efb/ffb control dma_inf secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-36 freescale semiconductor figure 27-22. memory controller block diagram a summary of events when a sdio card generates an in terrupt is detailed in this section. when an sdio card generates an interrupt request, it sets its interrupt pending bit in the csr register and asserts the interrupt line, which is shared with dat[1] line in 4-bit mode. the sdhc detects and steers the card?s interrupt to the selected irq line and to the interrupt controller. 27.4.4 sdio card interrupt 27.4.4.1 interrupts in 1-bit mode in this case, the sd_dat[1] pin is dedicated to provi ding the interrupt function. an interrupt is asserted by pulling the sd_dat[1] low until the host clears the interrupt. 27.4.4.2 interrupt in 4-bit mode since the interrupt and data line 1 share pin 8 in 4-b it mode, an interrupt will be sent by the card and recognized by the host only during a specific time. this is known as the interrupt period. the sdhc samples the level on pin 8 only during the interrupt pe riod. at all other times, the host interrupt controller ignores the level on pin 8. the definition of the interrupt period is different for operations with single block and multiple block data transfers. in the case of normal single data block transmissions, the interrupt pe riod becomes active two clock cycles after the completion of a data packet. this interrupt period lasts until after the card receives the end bit of the next command that has a data bl ock transfer associated with it. sdio-irq interrupter and card detection circuitry register handler sdio-read/wait logic configuration interrupt handler command response circuitry data data from post-processor operation pause operation resume memory controller application bus ipg_clk sdhc_irq_b cmd from post-processor secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-37 for multiple block data transfers in 4-bit mode, there is limited time that the interrupt period can be active because of the limited period of data line availability between the multiple blocks of data. this requires a more strict definition of the interrupt period. for th is case, the interrupt period is limited to two clock cycles. this period begins two clock cycles after th e end bit of the previous data block. during this two-clock cycle interrupt period, if an interrupt is pending, the sd_dat[1] line is held low for one clock cycle and the last clock cycle pulling sd_dat[1] hi gh. on completion of the interrupt period, the card releases the sd_dat[1] line into the high z state. when in 4-bit mode, the sdhc differentiates a data start bit and the interrupt period by checking that all four data lines are low for the start of new data. in the case of an interrupt, only the dat[1] should have gone low. after the last data block is sent, the interr upt period starts as normal. the interrupt period ends after the next command with data in stead of lasting only two cycles. refer to sdio card specification v1.0 for furt her information about sdio card interrupt. 27.4.4.3 card interrupt handling when the sdio bit in the interrupt control register is set to 0, the host controller clears the interrupt request to the system interrupt controller. the sdio in terrupt detection is stopped when this bit is cleared and restarted when this bit is set to ?1?. the host dr iver should clear the sdio interrupt enable bit before servicing the sdio interrupt. the host driver should se t this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. the sdio status bit is cleared by resetting the sdio in terrupt. writing to this bit has no effect in 1-bit mode, as the host controller detects the sdio inte rrupt with or without sd clock (to support wake-up). in 4-bit mode, the interrupt signal is sampled during the interrupt peri od. there are some sample delays between the interrupt signal from the sdio card and the interrupt to the host system interrupt controller. when the sdio status has been set and the host driver needs to start this interrupt service, the sdio bit in the interrupt control register is set to ?0? to clear the sdio interrupt status latched in the sdhc and to stop driving the interrupt signal to the system interr upt controller. the host driver must issue a cmd52 to clear the interrupts at the card. after completion of the card interrupt service, the sdio interrupt enable bit is set to ?1?. the sdhc starts sampling the interrupt signal again. ? figure 27-23 (a) shows the sdio card interrupt scheme. ? figure 27-23 (b) shows the sequences of software and hardware events that occur during the card interrupt handling procedure. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-38 freescale semiconductor figure 27-23. a) card interrupt scheme; b) card interrupt detection and handling procedure 27.4.5 card insertion and removal detection sdhc uses the sd_dat[3] pin to detect card inserti on or removal. to utilize this feature of the sdhc, the chip level integration needs to pull down this pa d as a default state. when there is no card on the mmc/sd bus, the sd_dat[3] defaults to a low voltage level. when any card is inserted or removed from the socket, sdhc detects the logic value changes on the sd_dat[3] pin and generates an interrupt. since the mechanism is based on the value of the sd_dat[3] line, only single-card systems can benefit from card detection. to avoid the conflict of card in sertion/removal de tection and the data value changes on sd_dat[3] because of data transfer, the user should disable the card insertion interrupt when there is a card detected in the socket but enable the interrupt when the card is removed from the socket. the card removal interrupt can be enabled only when there is no bus activity on sd_dat[3]. to avoid the false status bit generation during data transfer, the card insertion/removal is masked by the corresponding interrupt enable bit in int_cntr register. start enable card irq in host detect and steer card irq read irq status register disable card irq in host response error? clear card irq in card enable card irq in host end interrogate and service card irq ye s no command/ response handling sdio irq enable sdio irq status sdhc registers irq detecting and steering sdio card irq routing function 0 function 1 clear irq1 clear irq0 irq0 irq1 sd host sdio card ip bus irq to cpu b) a) secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-39 note the user can send a command (acmd42 for sdmem or cmd52 for sdio) to the card to disable the card internal pull-up resistor after card detection and identification. since the sd protocol requires that the dat line must be pulled up for data transfer, the user must disable the host side of the sd_dat[3] pull-down feature and conf igure it as pull-up. in the meantime, if the card internal pull-up resistor is disabled, the card removal interrupt can not be detected through sd_dat[3]. 27.4.6 power management and wake-up events when there is no operation between sdhc and the card through sd bus, the user can disable the ipg_clk and ipg_perclk in chip level clock control module to save power. when the user needs to use sdhc or communicate with the card, he or she can enable the clock and perform the operation. in some circumstances, when the clocks to sdhc ar e disabled, or when system is in low power mode, there are some events when the user needs to enable the clock and handle the event. these events are called wake-up interrupts. sdhc can generate these interr upts even if there are no clocks enabled. the three interrupts which can be used as wake-up events are: ? card removal interrupt ? card insertion interrupt ? sdio card interrupt the sdhc offers a power management feature. by cl earing the clock-enabled bits in the clock control register, the clocks are gated in the low position to the sdhc. for maximum power saving, the user can disable all the clocks to sdhc when there is no operation in progress. while in this state, it is possible that interrupt s can occur that require the sdhc to respond. these interrupts are called wake-up events and are defined as follows: ? wake-up event on sd card removal through card removal interrupt ? wake-up event on sd card insertion through card insertion interrupt ? wake-up event on card interrupt through sdio interrupt these three wake-up events (or wake-up interrupts) ca n be also used to wake the system from low-power modes. note to make the interrupt as a wake-up event when all the clocks to sdhc are disabled or when whole system is in low power mode, the corresponding wake-up enabled bit needs to be set. refer to section 27.3.3.10, ?sdhc interrupt control register (int_cntr) ? for more information on sdhc interrupt control register. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-40 freescale semiconductor note according to the sdio specification, if the user wants the card interrupt to wake up from low power mode (no clock to sdio card), the card should be set to 1-bit mode through cmd52. 27.4.6.1 dynamic voltage/frequency scaling (dvfs) operation any change in ipg_perclk impacts the mmc/sd/sdio transfer clock rate. 27.4.6.2 setting wake-up events for the sdhc to respond to a wake-up event, the software must set the respective wake-up enable bit before the cpu enters sleep mode. be fore the software disables the host clock, it should ensure that all of the following conditions have been met: ? no read or write transfer is active. ? data and command lines are not active. ? no interrupts are pending. ? internal fifos are empty. the software is responsible to ensure that the cl ock to the sdhc is fully operational before making accesses to the peripheral. 27.4.7 command/data interpreter command and data interpreters are based on similar principles. both devices consist of three parts: ? inner state machine ? sub-module controller ? crc hardware accelerator the cmd interpreter handles everything related to command line (cmd). the cmd interpreter includes command data sequence generation, command response extraction, crc generation and checking, and a response time-out detection. to achieve the above func tions, a state machine, a logic control, and a crc accelerator are used. see figure 27-24 for an illustration of the block diagram for the command interpreter. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-41 figure 27-24. block diagram for command interpreter see figure 27-25 for an illustration of the structure for the command crc shift register. figure 27-25. command crc shift register (dats has similar structure) to minimize the gate count, the internal command shift register is re-used for the crc shift register. the polynomials for the cmd and the dat are as follows: for the cmd: generator polynomial: g(x) = x 7 + x 3 + 1 m(x) = (first bit) * x n + (second bit) * x n-1 +...+ (last bit) * x 0 crc[6:0] = remainder [(m(x) * x 7 ) / g(x)] crc_in crc_reg cmd_sr cmd sampler cmd off fsm for cmd cmd port packet route and content extraction irq extractor fsm for dat dat_sr crc_reg crc_in dat sampler dat off dat port dat[3:0] cmd irq_cfg dat_reg dat_fifo dat_cfg readwait_cfg cmd_cfg resp_fifo cmd_reg crc out clr_crc zero crc_in crc bus [0] crc bus [1] crc bus [2] crc bus [3] crc bus [4] crc bus [5] crc bus [6] secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-42 freescale semiconductor for the dat: generator polynomial: g(x) = x 16 + x 12 + x 5 +1 m(x) = (first bit) * x n + (second bit) * x n-1 +...+ (last bit) * x 0 crc[15:0] = remainder [(m(x) * x 16 ) / g(x)] 27.4.8 system clock controller there are two clock domain in sdhc. one is ipg_perclk and the other is ipg_clk. on the ipg_perclk domain, there is one clock divide r and one clock prescaler in sdhc to divide the high frequency input clock ipg_perclk to a low fr equency clock, which can be used by card and most of the logic of sdhc. see figure 27-26 . the input clock first goes through a 4-bit divider and then a 12-bit prescaler to generate a clock named clk_20m. this clock is used internally by sdhc for dat line control, cmd line control and almost all the func tional logic. the mmc_sd_clk to the card, which is a gated version of clk_20m, has the same clock fre quency as clk_20m. clk_20m is derived from the clk_div by using the 12-bit prescaler. the clk_div is derived from the input clock ipg_perclk by using the 4-bit divider. sdhc clock rate register c ontrols the divide rate for both the divider and the prescaler. refer to section 27.3.3.3, ?sdhc clock ra te register (clk_rate) ? for the clock rate register information. the ipg_clk is of the mcu cloc k domain and used for sdhc regi sters/fifo read write access. to maximize power-saving during the operation, the sd hc bus clock pauses and resumes according to the sdhc status. for example, when the fifo is full during the card read operation, the bus clock is stopped if no further data is written to the fifo by the card. the bus clock is resumed when the fifo empty status is cleared by the user (dma). also, there are other conditions where the sdhc stops the clock to save power. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-43 figure 27-26. clock used in sdhc the controller controls the rate of the card clock mmc_sd_clk and checks whether it is on or off. the clock is turned off by setting the bit[0] of the str_st p_clk register and is turned on by setting the bit[1] of the str_stp_clk. to change the clock rate, the application must write a new value in the clk_rate register. 27.4.9 dat/cmd transceiver the transceiver unit is designed to do the following: ? control the i/o buffers. ? synchronize the input data to the system clock domain. the bi-directional signals cmd and dat are each connected by oe, oeb, in, and out. out and oeb are used for the high-impedance state output buffer, while oe and in are used for the input buffer. the use of oe allows the input to be disabled during floating and minimizes the current consumption. the data buffers are in the system clock domain but the input data is in the mmc_sd_clk clock domain. the transceiver will synchronize the input data to system clock domain. 27.5 initialization/application of sdhc this section provides initialization an d application information for sdhc. ipg_perclk clock prescaler dma handler fifo dat controller cmd controller memory controller register table clk_div gating mmc_sd_clk clk_20m clock divider dat/cmd transceiver ipg_clk secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-44 freescale semiconductor all communication between system and cards are cont rolled by the host. the host sends commands of two types: broadcast a nd addressed (point-to-point) commands. broadcast commands are intended for all card s, such as: ?go_idle_state?, ?send_op_cond?, ?all_send_cid? and ?set_relative_addr?. in broadcas t mode, all cards are in the open-drain mode to avoid bus contention. if the socket support only one card, the broadcast command is similar as the point-to-point command. after the broadcast command ?set_relative_addr? is issued, the cards enter standby mode. addressed type commands are used from this point. in this m ode, the cmd/dat i/o will return to push-pull mode, to have the driving capability for maximum frequency operation. the mmc and the sd are similar products. other th an the 4x bandwidth, they are being programmed similarly. the following example will show how to ?initialize? and perform ?content access? and ?content protection? on the cards. to improve the readability, we are going to use a program-like function for example 27-1 . example 27-1. mmc_sd_clk control 27.5.1 command submit?response receive basic operation this section shows the program flow used to submit a command to the card(s). the commands are as follows: ? secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-45 ? secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-46 freescale semiconductor figure 27-27. flow diagram for card detection ? write ?1? to int_cntr[15] to enable card detection interrupt ? write ?0? to int_cntr[15] to disable card detection interrupt 27.5.2.2 reset the host consists of three types of reset: ? hardware reset (card and host), which is driven by por (power on reset). ? software reset (host only), which is preceded by the write operation on register ?str_stp_clk?. follow the recommended sequence as specified in section 27.3.3.3, ?sdhc clock rate register (clk_rate) .? the reset will reset all the sdhc registers, but will not reset the card. the card reset is through cmd0. once the user applies the software reset to sdhc, it should also be using cmd0 to reset the card in case the card is in unknown state. ? card reset (card only). the command, go_idle_state , cmd0 is the software reset command for both the mmc and the sd memory card. this sets each card into idle state regardless of the current card state. when used as a sd i/o card, cmd52 is used to write io reset in cccr. the cards are initialized with a default relative card address (rca=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability). after the card is reset, the host needs to validate the voltage range of the card. see figure 27-28 for the software flow to reset both sdhc and the card. enable card detection irq wait sdhc interrupt check status[31] yes, card present no card present write int_cntr to disable card detection irq voltage validation (1) (2) secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-47 figure 27-28. flow chart for reset of sdhc and sd i/o card software_reset() { write_reg(str_stp_clk, 0x8); write_reg(str_stp_clk, 0x9);// 1. reset the sdhc host; write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1); write_reg(str_stp_clk, 0x1);// 2. write 0x1 to str_stp_clk 8 times; write_reg(clk_rate, 0x3f);// 3. set the lowest clock for initialization write_reg(read_to, 0x2db4);// 4. set read timeout register send_cmd_wait_resp(cmd_go_idle_state, 0x0,0x80, 0x40); //5. reset the card with cmd0 } 27.5.2.3 voltage validation all cards must be able to establish communications with the host using any operation voltage in the maximum allowed voltage range specified in th is standard. however, the supported minimum and maximum values for vdd are defined in operation conditions register (ocr) and might not cover the entire range. cards that store the ci d and csd data in the preload memory are able to communicate the information only under data transfer vdd conditions. that means if the host and card have non-compatible vdd ranges, the card will not be able to complete th e identification cycle, nor be able to send csd data. commands such as send_op_cont (cmd1 for mmc), sd_send_op_cont (cmd41 for sd memory), and io_send_op_cont (cmd5 for sd i/o) are designed to provide a mechanism to identify and reject cards that write 0x08 to str_stp_clk write 0x9 to str_stp_clk write 0x1 to str_stp_clk 8 times write 0x3f to clk_rate register send cmd0/cmd52 to card to reset card voltage validation secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-48 freescale semiconductor do not match the vdd range desired by the host. this is accomplished by the host sending the required vdd voltage window as the operand of this command. cards th at can not perform data transfer in the specified range must detach themselves from further bus operations and go into the inactive state. by omitting the voltage range in the command, the host can query ea ch card and determine the common voltage range before sending out-of-range cards into the inactive state. this query should be used if the host is able to select a common voltage range or if a notification to the application of non-usable cards in the stack is desired. the following steps show how to perform voltage validation when a card inserted: voltage_validation(voltage_range_arguement) { send_cmd_wait_resp(io_send_op_cond, 0x0, 0x04, 0x40); // cmd5, send sdio operation voltage, command argument is zero if(end command response true & no. of io functions> 0)// it is sdio and have io function {iordy = 0; while(!(iordy in i/o orc response)) {// set voltage range for each io send_cmd_wait_resp(io_send_op_cond, voltage_range_arguement, 0x04, 0x40);} if(memory present flag true) card = combo; // that is, sdio + sd memory, need to set operation voltage to memory portion as well send_cmd_wait_resp(app_cmd, 0x0, 0x01, 0x40);// cmd55, application command follows send_cmd_wait_resp(sd_app_op_cond, voltage_range_arguement, 0x01, 0x40);//acmd41 else card = sdio; // if no response to cmd5 io_send_op_cond or no. of io function is zero in response else// the card should be sd or mmc {send_cmd_wait_resp(app_cmd, 0x0, 0x01, 0x40);// cmd55, application command follows if(end command response true and no response timeout) {send_cmd_wait_resp(sd_app_op_cond, voltage_range_arguement, 0x01, 0x40); // acmd41, sd card found card = sd; } else // the card have no response to app_cmd, it is not sd card {send_cmd_wait_resp(send_op_cond, voltage_range_arguement, 0x01, 0x40); //cmd1, mmc card found if(end command response true and no response timeout) {card = mmc;} else{ card = no card or failed contact;} } } 27.5.2.4 card registry card registry between mmc and sd card is different. for the sd card, the identification process starts at cl ock rate fod (below 400 khz for most of the card) as defined by the card specification. after the bus is activated, the host requests the card to send valid operation conditions. the response to acmd41 is the operation condition register of the card. the same command is sent to all of the new cards in the system. incompatible cards are put into the inactive state. the host then issues the command, all_send_cid (cmd2), to each card to get its unique card secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-49 identification (cid) number. cards that are currently unidentified (that is, in ready state), send their cid number as the response. after the cid is sent by the card, the card goes into the identification state. the host then issues send_relative_addr (cmd3), requesting the card to publish a new relative card address (rca), which is shorter that cid. this id is used to address the card for future data transfer operations. once the rca is received, the card state cha nges to the stand-by state. at this point, if the host wants the card to have an alternative rca number, it may ask the card to publish a new number by sending another send_relative_addr command to the card. the last published rca is the actual rca of the card. the host repeats the identification process with cmd2 and cmd3 for each card in the system. for the mmc operation, the host starts the card identification process in open-drain mode with the identification clock rate fod. (fod is the initialization clock frequency defined by the card specification.) the open-drain driver stages on the cmd line allow parallel card operations during card identification. after the bus is activated, the host requests the card s to send their valid operation conditions (cmd1). the response to cmd1 is the ?wired or? operation on the condition restrictions of all cards in the system. incompatible cards are sent into inactive stat e. the host then issues the broadcast command all_send_cid (cmd2), asking all cards for their unique card identifi cation (cid) number. all unidentified cards (that is, those which are in ready state) simultaneously start sending their cid numbers serially, while bit-wise is monitoring their outgoing bitstream. these cards, for which outgoing cid bits do not match the corresponding bits on the command line in any one of th e bit periods, stop sending their cids immediately. they must wait for the next identification cycle. since the cid is unique for each card, only one card can successfully send its full cid to the host. this card th en goes into identification state. thereafter, the host issues set_relative_addr (cmd3) to assign a relative card addre ss (rca) to this card. once the rca is received, the card state changes to the stand-by state, does not react to further identification cycles, and its output switches from open-drain to push-pull. the hos t repeats the process, that is, cmd2 and cmd3, until the host receives the timeout condition to re cognize completion of the identification process. card_registry() { while (responseto from status){ if(card==combo or sdio) { send_cmd_wait_resp(set_relative_addr, 0x00, 0x01, 0x40); //card publish the rca in response rca = sdio_rca = address from response fifo; } else if(card==sd) { send_cmd_wait_resp(all_send_cid, 0x00, 0x02, 0x40); send_cmd_wait_resp(set_relative_addr, 0x00, 0x01, 0x40); //card publish the rca in response rca = sd_rca = address from response fifo; } else if(card==mmc) { send_cmd_wait_resp(all_send_cid, 0x00, 0x00, 0x02, 0x40); rca = mmc_rca = 0x1; send_cmd_wait_resp(set_relative_addr, mmc_rca_arguement, 0x01, 0x40); } secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-50 freescale semiconductor else exit due to card not identified; } send_cmd_wait_resp(select_card, rca_arguement, 0x41, 0x40); } 27.5.3 card access 27.5.3.1 block access?block write and block read 27.5.3.1.1 block write during block write (cmd24?27), one or more blocks of da ta are transferred from the host to the card with a crc appended to the end of each block by the host. a card supporting block write will always be able to accept a block of data defined by write_bl_len. if the crc fails, the card shall indicate the failure on the dat line. the transferred data is discarded a nd not written, and all further transmitted blocks (in multiple-block write mode) will be ignored. if the host uses partial blocks for which accumulated length is not block aligned and block misalignment is not allowed (csd parameter write_blk_misali gn is not set), the card detects the block misalignment error and aborts programming before th e beginning of the first misaligned block. the card sets the address_error error bit in the status regi ster, and, while ignoring all further data transfer, waits in the receive-data-state for a stop command. the write operation is aborted if the host tries to write over a write-protected area. in this case, however, the card sets the wp_violation bit. programming of the cid and csd registers does not require a previous block length setting. the transferred data is also crc-protected. if a part of the csd or cid register is stored in rom, this unchangeable part must match the corresponding part of the receive buffer. if this match fails, the card reports an error and does not change any register c ontents. some cards may require long and unpredictable times to write a block of data. after receiving a bl ock of data and completing the crc check, the card begins writing and holds the dat line low if its write buffer is full and unable to accept new data from a new write_block command. the host may poll the status of the card with a send_status command (cmd13) at any time, then the card responds with its status. the status bit ready_for_data indicates whether the card can accept new data or whether the write process is still in progress. the host may deselect the card by issuing cm d7 (to select a different card), which places the card into the disconnect state and releases the da t line without interrupting the write operation. when re - selecting the card, it reactivates the busy indication by pulling dat to low if programming is still in progress and the write buffer is unavailable. the software flow to write to the card with dma enable is: 1. start mmc_sd_clk if it is stopped. 2. check the card status, wait until card is ready for data. 3. for sd/mmc, set the card block length, using set_blocklen (cmd16). 4. set the sdhc block length register to be same as block length set to the card in step 2. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-51 ? for sdio, if the cmd53 is in byte mode, th e sdhc block length re gister should be set according to bytes count in cmd53; if the cm d53 is in block mode, the sdhc block length register should be set according to the block size in cccr registers. 5. set sdhc number block register (nob), nob is 1 for single block write or cmd53 in byte mode for sdio. 6. disable the buffer ready interrupt, configure th e dma setting and enable the sdhc dma channel: a) write ?0? to bit[3] of int_cntr register in sdhc to disable buffer write ready interrupt. b) set dma destination to be sdhc_buffer access register. c) set dma destination port size to be 32-bit. d) set dma burst length to be 16 bytes in 1-bit mode or 64 bytes in 4-bit mode. e) set dma transfer count to be number of byt es which is a multiple of the block_length (nob*blk_len = total number of bytes). 7. check the card status and wait until the card is ready for data. 8. set sdhc cmd register to any of the following: ? cmd24(write_block) ? cmd25(write_multiple_block) ? cmd53 in byte mode or block mode 9. set sdhc cmd argument register. 10. set sdhc command data control register. 11. wait for end command response and check if there any crc error or timeout error. 12. wait for dma done. 13. check for write_op_done and check status bit to see if write crc error occurred. 14. send stop_transmission command to the card if the write command is write_multiple_block (cmd25). 15. stop the mmc_sd_clk, finished the write operation. (this step is optional.) if the write operation is without dma, the system needs to write data to the buffer through buffer write ready interrupt or by polling the buffer write r eady status bit (status[6]: buf_wr_rdy). for high performance, data transfer using dma is preferred. 27.5.3.1.2 block read for block reads, the basic unit of data transfer is a block for which the maximum size is defined in the csd (read_bl_len). if read_bl_partial is set, sm aller blocks for which the starting and ending addresses are entirely contained wi thin one physical block (as defined by read_bl_len) may also be transmitted. a crc is appended to the end of eac h block, ensuring data transfer integrity. cmd17 (read_single_block) initiates a block read. after completing the transfer, the card returns to the transfer state. cmd18 (read_multiple_block) star ts a transfer of several consecutive blocks. blocks is continuously transferred until a stop command is issued. if the host uses partial blocks for which accumulated length is not block aligned and block mi salignment is not allowed, the card detects a block misalignment at the beginning of the first mis-aligned block, sets the address_error error bit in the status register, aborts transmission, and waits in the data state for a stop command. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-52 freescale semiconductor the software flow to write to card with dma enable is: 1. start mmc_sd_clk if it is stopped. 2. check the card status and wait until the card is ready for data. 3. for sd/mmc, set the card block length, using set_blocklen (cmd16). 4. set the sdhc block length register to be same as block length set to the card in step 3 . ? for sdio, if the cmd53 is in byte mode, th e sdhc block length re gister should be set according to bytes count in cmd53; if the cm d53 is in block mode, the sdhc block length register should be set according to the block size in cccr registers. 5. set sdhc number block register (nob) to 1 fo r single block write or cmd53 in byte mode for sdio. 6. disable the buffer ready interrupt, configur e the dma setting, and enable the sdhc dma channel: a) write ?0? to bit[4] of int_cntr register in sdhc to disable the buffer read ready interrupt. b) set dma source to be sdhc_buffer access register. c) set dma source port size to be 32-bit. d) set dma burst length to be 16 bytes in 1-bit mode or 64 bytes in 4-bit mode. e) set dma transfer count to be number of bytes that is a number of blocks multiple of the block_length (nob*blk_len). 7. check the card status and wait until the card is ready for data. 8. set sdhc cmd register to be cmd17(read_single_block) or cmd18 (read_multiple_block) or cmd53 in byte mode or block mode. 9. set sdhc cmd argument register. 10. set sdhc command data control register. 11. wait for end_cmd_resp interrupt and check response fifo, check crc error and timeout error. 12. wait for dma done. 13. check for read_op_done and check status bit to see if read crc error occurred. 14. send stop_transmission command to the card if the read command is read_multiple_block (cmd18). 15. stop the mmc_sd_clk, finished the read operation. if the read transfer operation does not use dma, the syst em will need to fetch data out of the data buffer through utilizing the buffer read ready interrupt or by polling the buffer read ready status bit (status[7]: buf_read_rdy). for high performance, da ta transfer using dma is preferred. 27.6 commands for mmc/sd/sdio see table 27-21 for the list of commands for mmc/sd/sdio. refer to corresponding card specifications for details about the command information. secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-53 table 27-21. commands for mmc/sd/sdio cmd index type argument response abbreviation description cmd0 bc [31:0] stuff bits ? go_idle_state resets all mmc and sd memory cards to idle state. cmd1 bcr [31:0] ocr without busy r3 send_op_cond asks all mmc and sd memory cards in idle state to send their operation conditions register contents in the response on the cmd line. cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line. cmd3 ac [31:6] rca [15:0] stuff bits r1 r6(sdio) set_relative_ad dr assigns relative address to the card. cmd4 bc [31:0] dsr [15:0] stuff bits ? set_dsr programs the dsr of all cards. cmd5 bc [31:0] ocr without busy r4 io_send_op_con d asks all sd i/o cards in idle state to send their operation conditions register contents in the response on the cmd line. cmd6 reserved cmd7 ac [31:6] rca [15:0] stuff bits r1b select/deselec t_card command toggles a card between the stand-by and transfer states or between the programming and disconnect states. in both cases, the card is selected by its own relative address and gets deselected by any other address; address 0 deselects all. cmd8 reserved cmd9 ac [31:6] rca [15:0] stuff bits r2 send_csd addressed card sends its card-specific data (csd) on the cmd line. cmd10 ac [31:6] rca [15:0] stuff bits r2 send_cid addressed card sends its card-identification (cid) on the cmd line. cmd11 adtc [31:0] data address r1 read_dat_until_ stop mmc reads data stream from the card, starting at the given address, until a stop_transmission follows. cmd12 ac [31:0] stuff bits r1b stop_transmiss ion forces the mmc/sd memory card to stop transmission. cmd13 ac [31:6] rca [15:0] stuff bits r1 send_status addressed mmc/sd card sends its status register. cmd14 reserved secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-54 freescale semiconductor cmd15 ac [31:6] rca [15:0] stuff bits ? go_inactive_sta te sets the card to inactive state in order to protect the card stack against communication breakdowns. cmd16 ac [31:0] block length r1 set_blocklen sets the block length (in bytes) for all following block commands (read and write). default block length is specified in the csd. cmd17 adtc [31:0] data address r1 read_single_bl ock reads a block of the size selected by the set_blocklen command. cmd18 adtc [31:0] data address r1 read_multiple_b lock continuously transfers data blocks from card to host until interrupted by a stop command. cmd19 reserved cmd20 adtc [31:0] data address r1 write_dat_until _stop mmc card writes data stream from the host, starting at the given address, until a stop_transmision follows. cmd21?23 reserved cmd24 adtc [31:0] data address r1 write_block writes a block of the size selected by the set_blocklen command. cmd25 adtc [31:0] data address r1 write_multiple_ block continuously writes blocks of data until a stop_transmission follows. cmd26 adtc [31:0] stuff bits r1 program_cid programming of the mmc card identification register. this command shall be issued only once per card. the card contains hardware to prevent this operation after the first programming. normally, this command is reserved for the manufacturer. cmd27 adtc [31:0] stuff bits r1 program_csd programming of the programmable bits of the csd. cmd28 ac [31:0] data address r1b set_write_prot if the card has write-protection features, this command sets the write-protection bit of the addressed group. the properties of write-protection are coded in the card specific data (wp_grp_size). table 27-21. commands for mmc/sd/sdio (continued) cmd index type argument response abbreviation description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-55 cmd29 ac [31:0] data address r1b clr_write_prot if the card provides write-protection features, this command clears the write-protection bit of the addressed group. cmd30 adtc [31:0] write protect data address r1 send_write_pro t if the card provides write-protection features, this command asks the card to send the status of the write-protection bits. cmd31 reserved cmd32 ac [31:0] data address r1 erase_wr_blk_s ta rt sets the address of the first sector of the erase group. cmd33 ac [31:0] data address r1 erase_wr_blk_e nd sets the address of the last sector of the continuous range of the erase group . cmd34 ac [31:0] data address r1 untag_sector removes one previously selected sector from the erase selection. cmd35 ac [31:0] data address r1 tag_erase_gro up_start sets the address of the first erase group within a range to be selected for erase. cmd36 ac [31:0] data address r1 tag_erase_gro up_end sets the address of the last erase group within a continuous range to be selected for erase. cmd37 ac [31:0] data address r1 untag_erase_g roup removes one previously selected erase group from the erase selection. cmd38 ac [31:0] stuff bits r1b erase erases all previously selected sectors. cmd39 ac [31:0] rca [15] register write flag [14:8] register address [7:0] register data r4 fast_io used to write and read 8-bit (register) data fields. the command address a card and a register and provides the data for writing if the write flag is set. the r4 response contains data read from the address register. this command accesses application dependent registers which are not defined in mmc standard. cmd40 bcr [31:0] stuff bits r5 go_irq_state sets the system into interrupt mode. cmd41 reserved table 27-21. commands for mmc/sd/sdio (continued) cmd index type argument response abbreviation description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-56 freescale semiconductor cdm42 adtc [31:0] stuff bits r1b lock_unlock used to set/reset the password or lock/unlock the card. the size of the data block is set by the set_block_len command. cmd43~51 reserved cmd52 ? [31] r/w flag [30:28] function number [27] raw (read after write) flag [26] stuff bit [25:9] register address [8] stuff bit [7:0] write data/stuff bits r5 io_rw_direct used to access a single register within the total 128 kbytes of register space in any i/o function. cmd53 ? [31] r/w flag [30:28] function number [27] block mode [26] op code [25:9] register address [8:0] byte/block count r5 io_rw_extended used to access a multiple i/o register with a single command, it allows the reading or writing of a large number of i/o registers. cmd54 reserved cmd55 ac [31:16] rca [15:0] stuff bits r1 app_cmd indicates to the card that the next command is an application-specific command rather than a standard command. cmd56 adtc [31:1] stuff bits [0]: rd/wr r1b gen_cmd used either to transfer a data block to the card or to get a data block from the card for general-purpose/application- specific commands. the size of the data block is set by the set_block_len command. cmd57~63 reserved acmds are preceded with app_cmd command. (command listed below are used for sd only. other unlisted sd commands are not supported in this module.) table 27-21. commands for mmc/sd/sdio (continued) cmd index type argument response abbreviation description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 27-57 acmd6 ac [31:2] stuff bits [1:0] bus width r1 set_bus_width defines the sd memory card data bus width (?00?=1-bit or ?10?=4-bit bus) to be used for data transfer. the allowed data bus widths are given in the scr register. acmd13 adtc [31:0] stuff bits r1 sd_status sends the sd memory card status. acmd22 adtc [31:0] stuff bits r1 send_num_wr_s ectors sends the number of the written (without errors) sectors. responds with 32-bit + crc data block. acmd23 ac [31:23] stuff bits [22:0] number of blocks r1 set_wr_blk_era se_count set the number of write blocks to be pre-erased before writing (to be used for faster multi-block write command). acmd41 bcr [31:0] ocr r3 sd_app_op_con d asks the accessed card to send its operating condition register (ocr) content in the response on the cmd line. acmd42 ac [31:1] stuff bits [0] set_cd r1 set_clr_card_d etect connects/disconnects the 50 k ? pull-up resistor on cd/dat3 of the card. acmd51 adtc [31:0] stuff bits r1 send_scr reads the sd configuration register (scr). table 27-21. commands for mmc/sd/sdio (continued) cmd index type argument response abbreviation description secured digital host controller (sdhc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 27-58 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-1 chapter 28 universal asynchronous re ceiver/transmitters (uart) the universal asynchronous receiver/transmitter (u art) module is capable of standard rs-232 non-return-to-zero (nrz) encoding format and ir da-compatible infrared modes. the uart provides serial communication capability with external device s through an rs-232 cable or through use of external circuitry that converts infrared signals to electrical si gnals (for reception) or tr ansforms electrical signals to signals that drive an infrared led (for transmission) to provide low speed irda compatibility. figure 28-1 shows the uart block diagram. figure 28-1. uart block diagram 28.1 overview the uart transmits and receives characters that are eith er 7 or 8 bits in length (program selectable). to transmit, data is written from the peripheral data bus to a 32-byte transmitter fifo (txfifo). this data is passed to the shift register and shifted serially out on the transmitter pin (txd). to receive, data is received serially from the receiver pin (rxd) and stored in a 32-half-words-deep receiver fifo (rxfifo). the universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-2 freescale semiconductor received data is retrieved from the rxfifo on the pe ripheral data bus. the rxfi fo and txfifo generate maskable interrupts as well as dma requests when the data level in each of the fifo reaches a programmed threshold level. the uart generates baud rates based on a progra mmable divisor and input clock. the uart also contains programmable auto baud det ection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. the receiver detects framing errors, idle c onditions, break characters, parity errors, and overrun errors. the uart module uses a software interface for contro l of modem operations and have a serial infrared (ir) module that decodes and encodes irda-compatible serial ir data. 28.1.1 features the uart includes the following features: ? high speed tia/eia-232-f compatible, up to 4.125mbit/s ? 7 or 8 data bits ? 1 or 2 stop bits ? programmable parity (even, odd, and no parity) ? hardware flow control support for request to send (rts) and clear to send (cts) signals ? edge selectable rts and edge detect interrupts ? status flags for various flow control and fifo states ? serial ir interface low speed, irda-compatible (up to 115.2 kbit/s). ? voting logic for improved noise immunity (16x oversampling) ? transmitter fifo empty interrupt suppression ? uart internal clocks enable/disable ? auto baud rate detection (up to 115.2 kbit/s) ? receiver and transmitter enable/disable for power saving ? rts, irda asynchronous wake (airint), receive asynchronous wake (awake), interrupts wake the mcu from sleep mode ? maskable interrupts ? two dma requests (txfifo dma re quest and rxfifo dma request) ? escape character sequence detection ? software reset (srst ) ? dedicated brm clock (ipg_perclk) to allow fre quency scaling on main clock (ipg_clk) without reprogramming brm registers 28.1.2 modes of operation the following are the uart modes of operation: ? serial rs-232 nrz format ? irda universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-3 28.2 external signal description 28.2.1 overview figure 28-1 provides external signal descriptions. 28.3 memory map and register definition 28.3.1 memory map and register summary the uart supports 8-bit and 16-bit accesses to 32-bit memory-mapped addresses only. all the memory mapped registers are 32 bits wide, however as the 16 msb are not used: ? for 32-bits write access, the 16 msb will not be taken into account. table 28-1. interface signals signal name i/o active state description reset state reset ipg_hard_async_reset_b i low asynchronous reset interrupts ipi_uart_rx_b o low receiver interrupt high ipi_uart_tx_b o low transmitter interrupt high ipi_uart_mint_b o low common interrupt high ipi_uart_anded_b o low anded interrupt (see below for comment) high dma requests ipd_uart_rx_dmareq_b o low receiver dma request high ipd_uart_tx_dmareq_b o low transmitter dma request high serial/irda signals ipp_uart_rxd_mux i serial/infrared data receive ipp_uart_txd_mux o serial/infrared data transmit high modem control signals ipp_uart_cts_b o low clear to send high ipp_uart_rts_b i low request to send clocks ipg_clk i main clock ipg_clk_s i bus clock ipg_perclk i binary rate multiplier (brm) clock universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-4 freescale semiconductor ? for 32-bits read access the 16 msb will be read as 0. 28.3.2 memory map table 28-2 shows the memory map. table 28-2. uart memory map address register access reset value section/page 0x1000_a000 (urxd1) ? 0x1001_c000 (urxd6) uart receiver registers 1?6 r 0x8000 28.3.4.1/28-7 0x1000_a040 (utxd1) ? 0x1001_c040 (utxd6) uart receiver registers 1?6 w 0x00? ? 28.3.4.2/28-9 0x1000_a080 (ucr1_1) ? 0x1001_c080 (ucr1_6) uart control registers 1_1?1_6 r/w 0x0000 28.3.4.3/28-9 0x1000_a084 (ucr2_1) ? 0x1001_c084 (ucr2_6) uart control registers 2_1?2_6 r/w 0x0001 28.3.4.4/28-11 0x1000_a088 (ucr3_1) ? 0x1001_c088 (ucr3_6) uart control registers 3_1?3_6 r/w 0x0700 28.3.4.5/28-14 0x1000_a08c (ucr4_1) ? 0x1001_c08c (ucr4_6) uart control registers 4_1?4_6 r/w 0x8000 28.3.4.6/28-15 0x1000_a090 (ufcr1) ? 0x1001_c090 (ufcr6) uart fifo control registers 1?6 r/w 0x0801 28.3.4.7/28-17 0x1000_a094 (usr1) ? 0x1001_c094 (usr6) uart status registers 1_1?1_6 r/w 0x2040 28.3.4.8/28-18 0x1000_a098 (usr2_1) ? 0x1001_c098 (usr2_6) uart status registers 2_1?2_6 r/w 0x4008 28.3.4.9/28-20 0x1000_a09c (uesc1) ? 0x1001_c09c (uesc6) uart escape character registers 1?6 r/w 0x002b 28.3.4.10/28-22 0x1000_a0a0 (utim1) ? 0x1001_c0a0 (utim6) uart escape timer registers 1?6 r/w 0x0000 28.3.4.11/28-23 0x1000_a0a4 (ubir1) ? 0x1001_c0a4 (ubir6) uart brm incremental registers 1?6 r/w 0x0000 28.3.4.12/28-23 0x1000_a0a8 (ubmr1) ? 0x1001_c0a8 (ubmr6) uart brm modulator registers 1?6 r/w 0x0000 28.3.4.13/28-24 universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-5 28.3.3 register summary the conventions in figure 28-3 and table 28-3 serve as a key for the register summary and individual register diagrams. table 28-3 provides a key for register figures and tables and the register summary. 0x1000_a0ac (ubrc1) ? 0x1001_c0ac (ubrc6) uart baud rate count registers 1?6 r 0x0000 28.3.4.14/28-24 0x1000_a0b0 (onems1) ? 0x1001_c0b0 (onems6) uart one millisecond registers 1?6 r/w 0x0000 28.3.4.15/28-25 0x1000_a0b4 (uts1) ? 0x1001_c0b4 (uts6) uart test registers 1?6 r/w 0x0060 28.3.4.16/28-26 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 28-2. key to register fields table 28-3. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero (previously designated slfclr). reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 28-2. uart memory map (continued) address register access reset value section/page universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-6 freescale semiconductor all registers described in this section are for 16 lsb. figure 28-3 shows the key to the register fields. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 28-3. key to register fields table 28-4. uart register summary name 151413 1211109876543210 0x1000_a000 (urxd1) ? 0x1001_c000 (urxd6) r 0 err ovrr un frm err brk pre rr 0 0 rx_data w 0x1000_a040 (utxd1) ? 0x1001_c040 (utxd6) r w00 0 0 0 000 tx_data 0x1000_a080 (ucr1_1) ? 0x1001_c080 (ucr1_6) r ade n adb r trdy en iden icd rr dye n rxd ma en ire n txm pty en rts den snd brk txd ma en 0 doz e uar ten w 0x1000_a084 (ucr2_1) ? 0x1001_c084 (ucr2_6) r esc i irt s ctsc cts esc en rtec pre n pro e stp b ws rts en at e n txe n rxe n srs t w 0x1000_a088 (ucr3_1) ? 0x1001_c088 (ucr3_6) r0 0 0 pare rre n fra err en 000adn imp rxd sen airi nte n aw ake n 0rxd mu xse l inv t aci en w 0x1000_a08c (ucr4_1) ? 0x1001_c08c (ucr4_6) r ctstl inv r eni ri wk en 0irs c lpb yp tce n bke n or en dre n w 0x1000_a090 (ufcr1) r txtl rfdiv 0 rxtl w 0x1000_a090 (ufcr1) ? 0x1001_c090 (ufcr6) rpar ity err rts s trdy rtsd esc f fra me rr rr dy agt im 0rxd s airi nt aw ake 0000 w universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-7 28.3.4 register descriptions 28.3.4.1 uart receiver register (urxd) figure 28-4 shows the urxd register, and table 28-5 shows the register?s field descriptions. 0x1000_a098 (usr2_1) ? 0x1001_c098 (usr2_6) rade t txf e 0 idle acs t 00 irin t wa ke 00 rts f txd cbrc d or e rd r w 0x1000_a09c (uesc1) ? 0x1001_c09c (uesc6) r 00 0 0 0 000 esc_char w 0x1000_a0a0 (utim1) ? 0x1001_c0a0 (utim6) r 00 0 0 tim w 0x1000_a0a4 (ubir1) ? 0x1001_c0a4 (ubir6) r inc w 0x1000_a0a8 (ubmr1) ? 0x1001_c0a8 (ubmr6) r mod w 0x1000_a0ac (ubrc1) ? 0x1001_c0ac (ubrc6) r bcnt w 0x1000_a0b0 (onems1) ? 0x1001_c0b0 (onems6) r onems w 0x1000_a0b4 (uts1) ? 0x1001_c0b4 (uts6) r 0 0 frcp err loop dbg en loo pir rxd bg 00txe mpt y rxe mpt y txf ull rxf ull 00sof trs t w table 28-4. uart register summary (continued) name 151413 1211109876543210 universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-8 freescale semiconductor 0x1000_a000 (urxd1) 0x1000_b000 (urxd2) 0x1000_c000 (urxd3) 0x1000_d000 (urxd4) 0x1001_b000 (urxd5) 0x1001_c000 (urxd6) access: user read-only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0err ovr run frm err brk prer r 00 rx_data w reset10000000???????? figure 28-4. uart receiver register (urxd) table 28-5. receiver register field descriptions name description 31?16 reserved 15 reserved. this bit is reserved and should read 1. note: reset value is read at 1 for compatibility with existing software (previously charrdy was bit 15 and always read as 1). 14 err error detect. indicates whether the character present in the rx_data field has an error (ovrrun, frmerr, brk or prerr) status. the err bit is updated and valid for each received character. 0 no error status was detected. 1 an error status was detected. 13 ovrrun receiver overrun. this read-only bit, when high, indicates that the corresponding character was stored in the last position (32nd) of the rxfifo. even if a 33rd character has not been detected, this bit is set to ?1? for the 32nd character. 0 no rxfifo overrun was detected. 1 a rxfifo overrun was detected. 12 frmerr frame error. indicates whether the current character had a framing error (a missing stop bit) and is possibly corrupted. frmerr is updated for each character read from the rxfifo. 0 the current character has no framing error. 1 the current character has a framing error. 11 brk break detect. indicates whether the current character was detected as a break character. the data bits and the stop bit are all 0. the frmerr bit is set when brk is set. when odd parity is selected, prerr is also set when brk is set. br k is valid for each character read from the rxfifo. 0 the current character is not a break character. 1 the current character is a break character. 10 prerr parity error. indicates if the current character was detected with a parity error and is possibly corrupted. prerr is updated for each character read from the rxfifo. when parity is disabled, prerr always reads as 0. 0 no parity error was detected for data in the rx_data field. 1 a parity error was detected for data in the rx_data field. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-9 28.3.4.2 uart transmitter register (utxd) figure 28-5 shows the utxd register, and table 28-6 shows the register?s field descriptions. 28.3.4.3 uart control register 1 (ucr1) figure 28-6 shows the ucr1 register, and table 28-7 shows the register?s field descriptions. 9?8 reserved 7?0 rx_data received data. holds the received character. in 7-bit mode, the most significant bit (msb) is forced to 0. in 8-bit mode, all bits are active. 0x1000_a040 (utxd1) 0x1000_b040 (utxd2) 0x1000_c040 (utxd3) 0x1000_d040 (utxd4) 0x1001_b040 (utxd5) 0x1001_c040 (utxd6) access: user write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r w00000000 tx_data reset00000000???????? figure 28-5. uart transmitter (utxd) register table 28-6. uart transmitter register field descriptions field description 31?16 reserved 15?8 reserved 7?0 tx_data transmit data. holds the parallel transmit data inputs. in 7-bit mode, d7 is ignored. in 8-bit mode, all bits are used. data is transmitted least significant bit (lsb) first. a new character is transmitted when the tx_data field is written. the tx_data field must be written only when the trdy bit is high to ensure that corrupted data is not sent. table 28-5. receiver register field descriptions (continued) name description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-10 freescale semiconductor 0x1000_a080 (ucr1_1) 0x1000_b080 (ucr1_2) 0x1000_c080 (ucr1_3) 0x1000_d080 (ucr1_4) 0x1001_b080 (ucr1_5) 0x1001_c080 (ucr1_6) access: user read/write 1514131211109876543210 r aden adbr trdy en iden icd rrdy en rxd mae n iren txmp tyen rtsd en sndb rk txd mae n 0 doz e uar ten w reset0000000000000000 figure 28-6. uart control register 1 (ucr1) table 28-7. uart control register 1 (ucr1) field descriptions field description 31?16 reserved 15 aden automatic baud rate detection interrupt enable. enables/disables the automatic baud rate detect complete (adet) bit to generate an interrupt (ipi_uart_mint = 0). 0 disable the automatic baud rate detection interrupt 1 enable the automatic baud rate detection interrupt 14 adbr automatic detection of baud rate. enables/disables automatic baud rate detection. when the adbr bit is set and the adet bit is cleared, the receiver detects the incoming baud rate automatically. the adet flag is set when the receiver verifies that the incoming baud rate is detected properly by detecting an ascii character ?a? or ?a? (0x61 or 0x41). 0 disable the automatic baud rate detection 1 enable the automatic baud rate detection 13 trdyen transmitter ready interrupt enable. enables/disables the transmitter ready interrupt (trdy) when the transmitter has one or more slots available in the txfifo. the fill level in the txfifo at which an interrupt is generated is controlled by txtl bits. when trdyen is negated, the transmitter ready interrupt is disabled. 0 disable the transmitter ready interrupt 1 enable the transmitter ready interrupt 12 iden idle condition detected interrupt enable. enables/disables the idle bit to generate an interrupt (ipi_uart_rx = 0). 0 disable the idle bit 1 enable the idle bit 11?10 icd idle condition detect. controls the number of frames rxd is allowed to be idle before an idle condition is reported. 00 report idle of more than 4 frames 01 report idle of more than 8 frames 10 report idle of more than 16 frames 11 report idle of more than 32 frames 9 rrdyen receiver ready interrupt enable. enables/disables the rrdy interrupt when the rxfifo contains data. the fill level in the rxfifo at which an interrupt is generated is controlled by the rxtl bits. when rrdyen is negated, the receiver ready interrupt is disabled. 0 disable the rrdy interrupt 1 enable the rrdy interrupt universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-11 28.3.4.4 uart control register 2 (ucr2) figure 28-7 shows the ucr2 register, and table 28-8 shows the register?s field descriptions. 8 rxdmaen receive ready dma enable. enables/disables the receive dma request ipd_uart_rx_dmareq when the receiver has data in the rxfifo. the fill level in the rxfifo at which a dma request is generated is controlled by the rxfl bits. when negated, the receive dma request is disabled. 0 disable the dma request 1 enable the dma request 7 iren infrared interface enable. enables/disables the ir interface. 0 disable the ir interface 1 enable the ir interface 6 txmptyen transmitter empty interrupt enable. enables/disables the transmitter fifo empty (txfe) interrupt ipi_uart_tx . when negated, the txfe interrupt is disabled . 0 disable the transmitter fifo empty interrupt 1 enable the transmitter fifo empty interrupt 5 rtsden rts delta interrupt enable. enables/disables the rtsd interrupt. the current status of the ipp_uart_rts pin is read in the rtss bit. 0 disable the rtsd interrupt 1 enable the rtsd interrupt 4 sndbrk send break. forces the transmitter to send a break character. the transmitter finishes sending the character in progress (if any) and sends break characters until sndbrk is reset. because the transmitter samples sndbrk after every bit is transmitted, it is important that sndbrk is asserted high for a sufficient period of time to generate a valid break. after the break transmission completes, the uart transmits 2 mark bits. the user can continue to fill the txfifo. any characters remaining are transmitted when the break is terminated. 0 does not send a break character 1 send a break character (continuous 0s) 3 txdmaen transmitter ready dma enable. enables/disables the transmit dma request ipd_uart_tx_dmareq when the transmitter has one or more slots available in the txfifo. the fill level in the txfifo that generates the ipd_uart_tx_dmareq is controlled by the txtl bits. 0 disable the transmit dma request 1 enable the transmit dma request 2 reserved 1 doze doze. determines the uart enable condition in the doze state. when ipg_doze input pin is at ?1?, meaning the cpu executes a doze instruction and the system is placed in the doze state, the doze bit affects operation of the uart. while in the doze state, if this bit is asserted, the uart is disabled. refer to the description in section 28.4.8, ?uart operation in low-power system states .? 0 enable the uart when it is in doze state 1 disable the uart when it is in doze state 0 uarten uart enable. enables/disables the uart. if uarten is negated in the middle of a transmission, the transmitter stops and pulls the txd line to a logic 1. uarten must be set to 1 before any access to utxd and urxd registers; otherwise, an ipg_xfr_error is returned. output ipg_uart_clk_en is internally connected to uarten and can be used for software controlled clock gating purpose. 0 disable the uart 1 enable the uart table 28-7. uart control register 1 (ucr1) field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-12 freescale semiconductor 0x1000_a084 (ucr2_1) 0x1000_b084 (ucr2_2) 0x1000_c084 (ucr2_3) 0x1000_d084 (ucr2_4) 0x1001_b084 (ucr2_5) 0x1001_c084 (ucr2_6) access: user read/write 1514131211109876543210 r esci irts ctsc cts escen rtec pren proe stpb ws rtse n aten txen rxen srst w reset0000 000000000001 figure 28-7. uart control register 2 (ucr2) summary table 28-8. uart control register 2 field descriptions field description 15 esci escape sequence interrupt enable. enables/disables the escf bit to generate an interrupt. 0 disable the escape sequence interrupt 1 enable the escape sequence interrupt 14 irts ignore rts pin. forces the rts input signal presented to the transmitter to always be asserted (set to low), effectively ignoring the external pin. when in this mode, the rts pin serves as a general purpose input. 0 transmit only when the rts pin is asserted. 1 ignore the rts pin 13 ctsc cts pin control. controls the operation of the ipp_uart_cts_b output pin. when ctsc is asserted, the ipp_uart_cts_b output pin is controlled by the receiver. when the rxfifo is filled to the level of the programmed trigger level and the start bit of the overflowing character (trigger level + 1) is validated, the ipp_uart_cts_b output pin is negated to indicate to the far-end transmitter to stop transmitting. when the trigger level is programmed for less than 32, the receiver continues to receive data until the rxfifo is full. when the ctsc bit is negated, the ipp_uart_cts_b output pin is controlled by the cts bit. on reset, because ctsc is cleared to 0, the ipp_uart_cts_b pin is controlled by the cts bit, which again is cleared to 0 on reset. this means that on reset the ipp_uart_cts_b signal is negated. 0 the ipp_uart_cts_b pin is controlled by the cts bit. 1 the ipp_uart_cts_b pin is controlled by the receiver. 12 cts clear to send. controls the ipp_uart_cts_b pin when the ctsc bit is negated. cts has no function when ctsc is asserted. 0 the ipp_uart_cts_b pin is high (inactive). 1 the ipp_uart_cts_b pin is low (active). 11 escen escape enable. enables/disables the escape sequence detection logic. 0 disable escape sequence detection 1 enable escape sequence detection 10?9 rtec request to send edge control. selects the edge that triggers the rts interrupt. this has no effect on the rts delta interrupt. rtec has an effect only when rtsen = 1. 00 trigger interrupt on a rising edge 01 trigger interrupt on a falling edge 1x trigger interrupt on any edge universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-13 8 pren parity enable. enables/disables the parity generator in the transmitter and parity checker in the receiver. when pren is asserted, the parity generator and checker are enabled, and disabled when pren is negated. 0 disable parity generator and checker 1 enable parity generator and checker 7 proe parity odd/even. controls the sense of the parity generator and checker. when proe is high, odd parity is generated and expected. when proe is low, even parity is generated and expected. proe has no function if pren is low. 0 even parity 1 odd parity 6 stpb stop. controls the number of stop bits transmitted after a character. when stpb is high, 2 stop bits are sent. when stpb is low, 1 stop bit is sent. stpb has no effect on the receiver, which expects 1 or more stop bits. 0 1 stop bit transmitted 1 2 stop bits transmitted 5 ws word size. controls the character length. when ws is high, the transmitter and receiver are in 8-bit mode. when ws is low, they are in 7-bit mode. the transmitter ignores bit 7 and the receiver sets bit 7 to 0. ws can be changed in-between transmission (reception) of characters, however not when a transmission (reception) is in progress, in which case the length of the current character being transmitted (received) is unpredictable. 0 7-bit transmit and receive character length (not including start, stop, or parity bits) 1 8-bit transmit and receive character length (not including start, stop, or parity bits) 4 rtsen request to send interrupt enable. controls the rts edge sensitive interrupt. when rtsen is asserted and the programmed edge is detected on the ipp_uart_rts_b pin, the rtsf bit is asserted. 0 disable request to send interrupt 1 enable request to send interrupt 3 at e n aging timer enable. this bit is used to enable the aging timer interrupt (triggered with agtim). 0 agtim interrupt is disabled. 1 agtim interrupt is enabled. 2 txen transmitter enable. enables/disables the transmitter. when txen is negated the transmitter is disabled and idle. when the uarten and txen bits are set the transmitter is enabled. if txen is negated in the middle of a transmission, the uart disables the transmitter immediately, and starts marking 1s. the transmitter fifo cannot be written when this bit is cleared. 0 disable the transmitter 1 enable the transmitter 1 rxen receiver enable. enables/disables the receiver. when the receiver is enabled, if the rxd input is already low, the receiver does not recognize break characters, because it requires a valid 1-to-0 transition before it can accept any character. 0 disable the receiver 1 enable the receiver 0 srst software reset. resets the transmitter and receiver state machines, all fifos, and all status registers. once the software writes 0 to srst , the software reset remains active for 4 clock cycles of ckih before the hardware deasserts srst . the software can only write 0 to srst . writing 1 to srst is ignored. 0 reset the transmit and receive state machines, all fifos and all status registers 1 no reset table 28-8. uart control register 2 field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-14 freescale semiconductor 28.3.4.5 uart control register 3 (ucr3) figure 28-8 shows the ucr3 register, and table 28-9 shows the register?s field descriptions. 0x1000_a088 (ucr3_1) 0x1000_b088 (ucr3_2) 0x1000_c088 (ucr3_3) 0x1000_d088 (ucr3_4) 0x1001_b088 (ucr3_5) 0x1001_c088 (ucr3_6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 par err en fraer ren 000 adni mp rxds en airin ten awak en 0rxd mux sel invt acie n w reset0000 0 1110 0 0 000 0 0 figure 28-8. uart control register 3 (ucr3) summary table 28-9. uart control register 3 (ucr3) field descriptions field description 15?14 reserved. 13 reserved. 12 parerren parity error interrupt enable. enables/disables the interrupt. when asserted, parerren causes the parityerr bit to generate an interrupt. 0 disable the parity error interrupt 1 enable the parity error interrupt 11 fraerren frame error interrupt enable. enables/disables the interrupt. when asserted, fraerren causes the framerr bit to generate an interrupt. 0 disable the frame error interrupt 1 enable the frame error interrupt 10 reserved. 9 reserved. 8 reserved. 7 adnimp autobaud detection not improved. disables new features of autobaud detection (see section 28.4.6.2, ?baud rate automatic detection protocol improved ? for more details). 0 autobaud detection new features selected 1 keep old autobaud detection mechanism universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-15 28.3.4.6 uart control register 4 (ucr4) figure 28-9 shows the ucr2 register, and table 28-10 shows the register?s field descriptions. 6 rxdsen receive status interrupt enable. controls the receive status interrupt (ipi_uart_rx_b). when this bit is enabled and rxds status bit is set, the interrupt ipi_uart_rx_b will be generated. 0 disable the rxds interrupt 1 enable the rxds interrupt 5 airinten asynchronous ir wake interrupt enable. controls the asynchronous ir wake interrupt. an interrupt is generated when airinten is asserted and a pulse is detected on the uart_rx pin. 0 disable the airint interrupt 1 enable the airint interrupt 4 awaken asynchronous wake interrupt enable. controls the asynchronous wake interrupt. an interrupt is generated when awaken is asserted and a falling edge is detected on the rxd pin. 0 disable the awake interrupt 1 enable the awake interrupt 3 reserved 2 rxdmuxsel rxd muxed input selected. selects the ipp_uart_rxd_mux input pin for serial and infrared input signal 0 serial input pin is ipp_uart_rxd and irda input pin is ipp_uart_rxd_ir 1 input pin is ipp_uart_rxd_mux for serial and ir interfaces in i.mx27, this bit should always be set to 1. otherwise, uart receiver will not work. 1 invt inverted infrared transmission. sets the active level for the transmission. when invt is cleared, the infrared logic block transmits a positive ir 3/16 pulse for all 0s and 0s are transmitted for 1s. when invt is set (invt = 1), the infrared logic block transmits an active low or negative infrared 3/16 pulse for all 0s and 1s are transmitted for 1s. 0 active low transmission 1 active high transmission 0 acien autobaud counter interrupt enable. this bit is used to enable the autobaud counter stopped interrupt (triggered with acst (usr2[11]). 0 acst interrupt disabled 1 acst interrupt enabled table 28-9. uart control register 3 (ucr3) field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-16 freescale semiconductor 0x1000_a08c (ucr4_1) 0x1000_b08c (ucr4_2) 0x1000_c08c (ucr4_3) 0x1000_d08c (ucr4_4) 0x1001_b08c (ucr4_5) 0x1001_c08c (ucr4_6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ctstl inv r eniri wke n 0 irsc lpbyp tcen bken oren dren w reset10000000000 0 0000 figure 28-9. uart control register 4 (ucr4) summary table 28-10. uart control register 4 (ucr4) field descriptions field description 15?10 ctstl cts trigger level. controls the threshold at which the ipp_uart_cts_b pin is deasserted by the rxfifo. after the trigger level is reached and the ipp_uart_cts_b pin is deasserted, the rxfifo continues to receive data until it is full. the ctstl bits are encoded as shown in the settings column. 000000 0 characters received 000001 1 characters in the rxfifo ... 100000 32 characters in the rxfifo (maximum) all other settings reserved 9 invr inverted infrared reception. determines the logic level for the detection. when cleared, the infrared logic block expects an active low or negative ir 3/16 pulse for 0s and 1s are expected for 1s. when invr is set (invr = 1), the infrared logic block expects an active high or positive ir 3/16 pulse for 0s and 0s are expected for 1s. 0 active low detection 1 active high detection 8 eniri serial infrared interrupt enable. enables/disables the serial infrared interrupt. 0 serial infrared interrupt disabled 1 serial infrared interrupt enabled 7 wken wake interrupt enable. enables/disables the wake bit to generate an interrupt. the wake bit is set at the detection of a start bit by the receiver. 0 disable the wake interrupt 1 enable the wake interrupt 6 reserved 5 irsc ir special case. selects the clock for the vote logic. when set, irsc switches the vote logic clock from the sampling clock to the uart reference clock. the ir pulses are counted a predetermined amount of time depending on the reference frequency. see section 28.4.7.3, ?infrared special case (irsc) bit .? 0 the vote logic uses the sampling clock (16x baud rate) for normal operation 1 the vote logic uses the uart reference clock 4 lpbyp low power bypass. allows to bypass the low power new features in uart. to use during debug phase. 0 low power features enabled 1 low power features disabled universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-17 28.3.4.7 uart fifo control register summary (ufcr) figure 28-10 shows the uart fifo register, and table 28-11 shows the register?s field descriptions. 3 tcen transmit complete interrupt enable. enables/disables the txdc bit to generate an interrupt (ipi_uart_tx_b = 0). 0 disable txdc interrupt 1 enable txdc interrupt 2 bken break condition detected interrupt enable. enables/disables the brcd bit to generate an interrupt. 0 disable the brcd interrupt 1 enable the brcd interrupt 1 oren receiver overrun interrupt enable. enables/disables the ore bit to generate an interrupt. 0 disable ore interrupt 1 enable ore interrupt 0 dren receive data ready interrupt enable. enables/disables the rdr bit to generate an interrupt. 0 disable rdr interrupt 1 enable rdr interrupt 0x1000_a090 (ufcr1) 0x1000_b090 (ufcr2) 0x1000_c090 (ufcr3) 0x1000_d090 (ufcr4) 0x1001_b090 (ufcr5) 0x1001_c090 (ufcr6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txtl rfdiv 0 rxtl w reset0000100000000001 figure 28-10. uart fifo control register (ufcr) summary table 28-10. uart control register 4 (ucr4) field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-18 freescale semiconductor 28.3.4.8 uart status register 1 summary (usr1) figure 28-11 shows the register, and table 28-12 shows the register?s field descriptions. table 28-11. uart fifo control register description field description 15?10 txtl transmitter trigger level. controls the threshold at which a maskable interrupt is generated by the txfifo. a maskable interrupt is generated whenever the data level in the txfifo falls below the selected threshold. the bits are encoded as shown in the settings column. 000000 = reserved 000001 = reserved 000010 = txfifo has 2 or fewer characters ... 011111 = txfifo has 31 or fewer characters 100000 = txfifo has 32 characters (maximum) all other settings reserved 9?7 rfdiv reference frequency divider. controls the divide ratio for the reference clock. the input clock is ipg_perclk. the output from the divider (ref_clk) is used by brm to create the 16x baud rate oversampling clock. 000 divide input clock by 6 001 divide input clock by 5 010 divide input clock by 4 011 divide input clock by 3 100 divide input clock by 2 101 divide input clock by 1 110 divide input clock by 7 6 reserved. 5?0 rxtl receiver trigger level?controls the threshold at which a maskable interrupt is generated by the rxfifo. a maskable interrupt is generated whenever the data level in the rxfifo reaches the selected threshold. the rxtl bits are encoded as shown in the settings column. 000000 0 characters received. 000001 rxfifo has 1 character. ... 011111 rxfifo has 31 characters. 100000 rxfifo has 32 characters (maximum). all other settings are reserved. 0x1000_a094 (usr1) 0x1000_b094 (usr2) 0x1000_c094 (usr3) 0x1000_d094 (usr4) 0x1001_b094 (usr5) 0x1001_c094 (usr6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pa r i t y err rtss trdy rts d esc f fram err rrdy agtim 0 rxds airint awake 0000 w reset 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 figure 28-11. uart status register 1 (usr1) summary universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-19 table 28-12. uart status register 1 (usr1) field descriptions field description 15 parityerr parity error interrupt flag. indicates a parity error is detected. parityerr is cleared by writing 1 to it. writing 0 to parityerr has no effect. when parity is disabled, parityerr always reads 0. at reset, parityerr is set to 0. 0 no parity error detected 1 parity error detected 14 rtss rts pin status. indicates the current status of the ipp_uart_rts_b pin. a ?snapshot? of the pin is taken immediately before rtss is presented to the data bus. rtss cannot be cleared because all writes to rtss are ignored. at reset, rtss is set to 0. 0 the ipp_uart_rts_b pin is high (inactive). 1 the ipp_uart_rts_b pin is low (active). 13 trdy transmitter ready interrupt/dma flag. indicates that the txfifo emptied below its target threshold and requires data. trdy is automatically cleared when the data level in the txfifo goes beyond above the set threshold level by txfl bits. at reset, trdy is set to 1. 0 the transmitter does not require data. 1 the transmitter requires data (interrupt posted). 12 rtsd rts delta. indicates whether the ipp_uart_rts_b pin changed state. it (rtsd) generates a maskable interrupt. when in sleep mode, rts assertion sets rtsd and can be used to wake the arm9 core. the current state of the ipp_uart_rts_b pin is available on the rtss bit. clear rtsd by writing 1 to it. writing 0 to rtsd has no effect. at reset, rtsd is set to 0. 0 ipp_uart_rts_b pin did not change state since last cleared. 1 ipp_uart_rts_b pin changed state (write 1 to clear) 11 escf escape sequence interrupt flag. indicates if an escape sequence was detected. escf is asserted when the escen bit is set and an escape sequence is detected in the rxfifo. clear escf by writing 1 to it. writing 0 to escf has no effect. 0 no escape sequence detected 1 escape sequence detected (write 1 to clear) 10 framerr frame error interrupt flag. indicates that a frame error is detected. the ipi_uart_mint_b interrupt generated by this. clear framerr by writing 1 to it. writing 0 to framerr has no effect. 0 no frame error detected 1 frame error detected 9 rrdy receiver ready interrupt/dma flag. indicates that the rxfifo data level is above the threshold set by the rxfl bits. (see the rxfl bits description in table 28-11 for setting the interrupt threshold.) when asserted, rrdy generates a maskable interrupt or dma request. in conjunction with the charrdy bit in the urxdn_1 or urxdn_2 register, the software can continue to read the rxfifo in an interrupt service routine until the rxfifo is empty. rrdy is automatically cleared when data level in the rxfifo goes below the set threshold level. at reset, rrdy is set to 0. 0 no character ready 1 character(s) ready (interrupt posted) 8 agtim aging timer interrupt flag. indicates that data in the rxfifo has been idle for a time of 8 character lengths (where a character length consists of 7 or 8 bits, depending on the setting of the ws bit in ucr2, with the bit time corresponding to the baud rate setting) and fifo data level is less than rxfifo threshold level (rxtl in the ufcr). clear by writing a 1 to it. 0 agtim is not active. 1 agtim is active (write 1 to clear). 7 reserved. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-20 freescale semiconductor 28.3.4.9 uart status register 2 (usr2) figure 28-12 shows the register, and table 28-13 shows the register?s field descriptions. 6 rxds receiver idle interrupt flag. indicates that the receiver state machine is in an idle state, the next state is idle, and the receive pin is high. rxds is automatically cleared when a character is received. rxds is active only when the receiver is enabled. 0 receive is in progress. 1 receiver is idle. 5 airint asynchronous ir wake interrupt flag. indicates that the ir wake pulse was detected on the ipp_uart_rxd_ir pin, or on ipp_uart_rxd_mux if rxdmuxsel is set to 1. clear airint by writing 1 to it. writing 0 to airint has no effect. 0 no pulse was detected on the rxd irda pin. 1 a pulse was detected on the rxd irda pin. 4 awake asynchronous wake interrupt flag. indicates that a falling edge was detected on the ipp_uart_rxd pin, or on ipp_uart_rxd_mux if rxdmuxsel is set to 1. clear awake by writing 1 to it. writing 0 to awake has no effect. 0 no falling edge was detected on the rxd serial pin. 1 a falling edge was detected on the rxd serial pin. 3?0 reserved. 0x1000_a098 (usr2_1) 0x1000_b098 (usr2_2) 0x1000_c098 (usr2_3) 0x1000_d098 (usr2_4) 0x1001_b098 (usr2_5) 0x1001_c098 (usr2_6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r adet txfe 0 idle acs t 00 irint wake 00 rtsf txd c brc d ore rd r w reset0 1000000 0 0001000 figure 28-12. uart status register 2 (usr2) summary table 28-12. uart status register 1 (usr1) field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-21 table 28-13. uart status register 2 field descriptions field description 15 adet automatic baud rate detect complete. indicates that an ?a? or ?a? was received and that the receiver detected and verified the incoming baud rate. clear adet by writing 1 to it. writing 0 to adet has no effect. 0 ascii ?a? or ?a? was not received. 1 ascii ?a? or ?a? was received (write 1 to clear). 14 txfe transmit buffer fifo empty. indicates that the transmit buffer (txfifo) is empty. txfe is cleared automatically when data is written to the txfifo. even though txfe is high, the transmission might still be in progress. 0 the transmit buffer (txfifo) is not empty. 1 the transmit buffer (txfifo) is empty. 13 reserved. 12 idle idle condition. indicates that an idle condition has existed for more than a programmed amount frame (see section 28.4.4.2.1, ?idle line detect ?). an interrupt can be generated by this idle bit if iden (ucr1[12]) is enabled. idle is cleared by writing 1 to it. writing 0 to idle has no effect. 0 no idle condition is detected. 1 idle condition is detected (write 1 to clear). 11 acst autobaud counter stopped. in autobaud detection (adbr=1), indicates the counter which determines the baudrate was running and is now stopped. this means either start bit is finished (if adnimp=1), or bit0 is finished (if adnimp=0). see section 28.4.6.3.1, ?new autobaud counter stopped bit and interrupt ? for more details. an interrupt can be flagged on ipi_uart_mint_b if acien=1. 0 measurement of bit length is not finished (in autobaud). 1 measurement of bit length is finished (in autobaud). (write a ?one? to clear.) 10 reserved. 9 reserved. 8 irint serial infrared interrupt flag. when an edge is detected on the rx pin during sir mode, this flag will be asserted. this flag can cause an interrupt on ipi_uart_mint_b which can be masked using the control bit eniri: ucr4 [8]. 0 no edge was detected. 1 valid edge was detected (write a ?one? to clear). 7 wake wake. indicates the start bit is detected. wake can generate an interrupt on ipi_uart_mint_b that can be masked using the wken bit. clear wake by writing 1 to it. writing 0 to wake has no effect. 0 start bit was not detected. 1 start bit was detected (write 1 to clear). 6 reserved. 5 reserved. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-22 freescale semiconductor 28.3.4.10 uart escape character register summary (uesc) figure 28-13 shows the register, and table 28-14 shows the register?s field descriptions. 4 rtsf rts edge triggered interrupt flag. indicates if a programmed edge is detected on the ipp_uart_rts_b pin. the rtec bits select the edge that generates an interrupt. rtsf can generate an interrupt on ipi_uart_mint_b that can be masked using the rtsen bit. clear rtsf by writing 1 to it. writing 0 to rtsf has no effect. 0 programmed edge is not detected on ipp_uart_rts_b. 1 programmed edge is detected on ipp_uart_rts_b (write 1 to clear). 3 txdc transmitter complete. indicates that the transmit buffer (txfifo) and shift register is empty; therefore the transmission is complete. txdc is cleared automatically when data is written to the txfifo. 0 transmit is incomplete. 1 transmit is complete. 2 brcd break condition detected. indicates that a break condition was detected by the receiver. clear brcd by writing 1 to it. writing 0 to brcd has no effect. 0 no break condition was detected. 1 a break condition was detected (write 1 to clear). 1 ore overrun error. when set to 1, ore indicates that the receive buffer (rxfifo) was full (32 chars inside), and a 33rd character has been fully received. this 33rd character has been discarded. clear ore by writing 1 to it. writing 0 to ore has no effect. 0 no overrun error 1 overrun error (write 1 to clear) 0 rdr receive data ready. indicates that at least 1 character is received and written to the rxfifo. if the urxd register is read and there is only 1 character in the rxfifo, rdr is automatically cleared. 0 no receive data ready 1 receive data ready 0x1000_a09c (uesc1) 0x1000_b09c (uesc2) 0x1000_c09c (uesc3) 0x1000_d09c (uesc4) 0x1001_b09c (uesc5) 0x1001_c09c (uesc6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0000000 esc_char w reset0 0000000 0 0101011 figure 28-13. uart escape character register summary (uesc) table 28-13. uart status register 2 field descriptions (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-23 28.3.4.11 uart escape timer register summary (utim) figure 28-14 shows the register, and table 28-15 shows the register?s field descriptions. 28.3.4.12 uart brm incremental register (ubir) figure 28-15 shows the register, and table 28-16 shows the register?s field descriptions. table 28-14. uart escape character register field descriptions name description 15?8 reserved. 7?0 esc_char uart escape character. holds the selected escape character that all received characters are compared against to detect an escape sequence. 0x1000_a0a0 (utim1) 0x1000_b0a0 (utim2) 0x1000_c0a0 (utim3) 0x1000_d0a0 (utim4) 0x1001_b0a0 (utim5) 0x1001_c0a0 (utim6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 0 tim w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 28-14. uart escape timer register summary (utim) table 28-15. uart escape timer register (utim) field descriptions name description 15?12 reserved. 11?0 tim uart escape timer. holds the maximum interval allowed between escape characters. 0x1000_a0a4 (ubir1) 0x1000_b0a4 (ubir2) 0x1000_c0a4 (ubir3) 0x1000_d0a4 (ubir4) 0x1001_b0a4 (ubir5) 0x1001_c0a4 (ubir6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r inc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 28-15. uart brm incremental register summary (ubir) universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-24 freescale semiconductor 28.3.4.13 uart brm modulator register summary (ubmr) figure 28-13 shows the register, and table 28-17 shows the register?s field descriptions. 28.3.4.14 uart baud rate count register summary (ubrc) figure 28-14 shows the register, and table 28-18 shows the register?s field descriptions. table 28-16. uart brm incremental register field descriptions name description 15?0 inc incremental numerator. holds the numerator value minus one of the brm ratio (see section 28.4.5, ?binary rate multiplier (brm) ?). the ubir register must be updated before the ubmr register for the baud rate to be updated correctly. if only one register is written to by software, the brm will ignore this data until the other register is written to by software. updating this field using byte accesses is not recommended and is undefined. 0x1000_a0a8 (ubmr1) 0x1000_b0a8 (ubmr2) 0x1000_c0a8 (ubmr3) 0x1000_d0a8 (ubmr4) 0x1001_b0a8 (ubmr5) 0x1001_c0a8 (ubmr6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r mod w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 28-16. uart brm modulator register summary (ubmr) table 28-17. uart brm modulator register field descriptions field description 15?0 mod modulator denominator. holds the value of the denominator minus one of the brm ratio (see section 28.4.5, ?binary rate multiplier (brm) ?). the ubir register must be updated before the ubmr register for the baud rate to be updated correctly. if only one register is written to by software, the brm will ignore this data until the other register is written to by software. updating this register using byte accesses is not recommended and undefined. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-25 28.3.4.15 uart one millisecond register (onems) figure 28-15 shows the register, and table 28-19 shows the register?s field descriptions. 0x1000_a0ac (ubrc1) 0x1000_b0ac (ubrc2) 0x1000_c0ac (ubrc3) 0x1000_d0ac (ubrc4) 0x1001_b0ac (ubrc5) 0x1001_c0ac (ubrc6) access: user read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bcnt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 figure 28-17. uart baud rate count register summary (ubrc) table 28-18. uart baud rate count register field descriptions field description 15?0 bcnt baud rate count register. this read only register is used to count the start bit of the incoming baud rate (if adnimp=1), or start bit + bit0 (if adnimp=0). when the measurement is done, the baud rate count register contains the number of uart internal clock cycles (clock after divider) present in an incoming bit. bcnt retains its value until the next automatic baud rate detection sequence has been initiated. the 16-bit baud rate count register is reset to 4 and stays at hex ffff in the case of an overflow. 0x1000_a0b0 (onems1) 0x1000_b0b0 (onems2) 0x1000_c0b0 (onems3) 0x1000_d0b0 (onems4) 0x1001_b0b0 (onems5) 0x1001_c0b0 (onems6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r onems w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 28-18. uart one millisecond register summary (onems) table 28-19. uart one millisecond register field descriptions field description 15?0 onems one millisecond register. this 16-bit register must contain the value of the uart internal frequency divided by 1000. the internal frequency is obtained after the uart internal divider. in fact this register contains the value corresponding to the number of uart internal clock cycles are present in one millisecond. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-26 freescale semiconductor 28.3.4.16 uart test register (uts) figure 28-16 shows the register, and table 28-20 shows the register?s field descriptions. 0x1000_a0b4 (uts1) 0x1000_b0b4 (uts2) 0x1000_c0b4 (uts3) 0x1000_d0b4 (uts4) 0x1001_b0b4 (uts5) 0x1001_c0b4 (uts6) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 00 frcp err loop dbg en loo pir rxd bg 00 txe mpt y rxe mpt y txfu ll rxf ull 00 sof trs t w reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 figure 28-19. uart test register summary (uts) table 28-20. uart test register description field description 15?14 reserved. these bits are reserved and should read 0. 13 frcperr force parity error. forces the transmitter to generate a parity error if parity is enabled. frcperr is provided for system debugging. 0 generate normal parity 1 generate inverted parity (error) 12 loop loop tx and rx for test. controls loopback for test purposes. when loop is high, the receiver input is internally connected to the transmitter and ignores the rxd pin. the transmitter is unaffected by loop. if rxdmuxsel (ucr3[2]) is set to 1, the loopback is applied on serial and irda signals. if rxdmuxsel is set to 0, the loopback is only applied on serial signals. 0 normal receiver operation 1 internally connect the transmitter output to the receiver input 11 dbgen debug_enable_b. this bit controls whether to respond to the debug_b input signal. 0 uart will go into debug mode when debug_b is low. 1 uart will not go into debug mode even if debug_b is low. 10 loopir loop tx and rx for ir test (loopir). this bit controls loopback from transmitter to receiver in the infrared interface. 0 no ir loop 1 connect ir transmitter to ir receiver 9 rxdbg rx_fifo_debug_mode. this bit controls the operation of the rx fifo read counter when in debug mode. 0 rx fifo read pointer does not increment. 1 rx_fifo read pointer increments as normal. 8?7 reserved. these bits are reserved and should read 0. 6 txempty txfifo empty. indicates that the txfifo is empty. 0 the txfifo is not empty. 1 the txfifo is empty. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-27 28.4 functional description 28.4.1 interrupts and dma requests table 28-21 lists all of the different interrupts signals available on the interrupt pins. see the individual register descriptions for explanation of available enables and status flags. 5 rxempty rxfifo empty. indicates the rxfifo is empty. 0 the rxfifo is not empty. 1 the r xfifo is empty. 4 txfull txfifo full. indicates the txfifo is full. 0 the txfifo is not full. 1 the txfifo is full. 3 rxfull rxfifo full. indicates the rxfifo is full. 0 the rxfifo is not full. 1 the rxfi fo is full. 2?1 reserved. these bits are reserved and should read 0. 0 softrst software reset. indicates the status of the software reset (srst ). 0 no software reset 1 generate software reset table 28-21. interrupts and dma interrupt output interrupt enable enable register location interrupt flag flag register location ipi_uart_rx_b rrdyen iden dren rxdsen at e n ucr1 (bit 9) ucr1 (bit 12) ucr4 (bit 0) ucr3 (bit 6) ucr2 (bit 3) rrdy idle rdr rxds agtim usr1 (bit 9) usr2 (bit 12) usr2 (bit 0) usr1 (bit 6) usr1 (bit 8) ipi_uart_tx_b txmptyen trdyen tcen ucr1 (bit 6) ucr1 (bit 13) ucr4 (bit 3) txfe trdy txdc usr2 (bit 14) usr1 (bit 13) usr2 (bit 3) table 28-20. uart test register description (continued) field description universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-28 freescale semiconductor 28.4.2 clocking considerations 28.4.2.1 minimum and maximum clock frequencies uart module receives the following three clocks: ipg_clk ipg_clk_s ipg_perclk ipg_clk is the main clock and must always be running when uart is enabled. there is an exception in sleep mode (see section 28.4.2.2, ?clocking in low-power modes ?). ipg_clk_s is the bus clock, it is active only when there a bus access (read/write) to uart registers. ipg_clk and ipg_clk_s are synchronous and have the same frequency. but uart receives also another clock, ipg_perclk. this clock is the binary multiplier clock and it must always be running when uart is sending or receiving ch aracters. this clock has been added in order to allow frequency scaling on ipg_clk (and ipg_clk_s ) without changing configuration of brm ( ipg_perclk staying at a fixed frequency). constraints: ? ipg_clk , ipg_clk_s , and ipg_perclk must be synchronous and their cl ock trees must be balanced. but ipg_perclk frequency is not necessa ry equal to ipg_clk frequency (and ipg_clk_s ).this specific relationship between ipg_perclk and ipg_clk is obtained by extracting those clocks from the same source clock but on which different dividers have been applied. the dividers ratios must always be integer values. with this constraint uart receives either ipg_perclk and ipg_clk rising edges at the same time or separated by at minimum a fixed guard-band. ipi_uart_mint_b oren bken wken aden acien esci eniri airinten awaken fraerren parerren rtsden rtsen ucr4 (bit 1) ucr4 (bit 2) ucr4 (bit 7) ucr1 (bit 15) ucr3 (bit 0) ucr2 (bit 15) ucr4 (bit 8) ucr3 (bit 5) ucr3 (bit 4) ucr3 (bit 11) ucr3 (bit 12) ucr1 (bit 5) ucr2 (bit 4) ore brcd wake adet acst escf irint airint awake fraerr parityerr rtsd rtsf usr2 (bit 1) usr2 (bit 2) usr2 (bit 7) usr2 (bit 15) usr2 (bit 11) usr1 (bit 11) usr2 (bit 8) usr1 (bit 5) usr1 (bit 4) usr1 (bit 10) usr1 (bit 15) usr1 (bit 12) usr2 (bit 4) ipd_uart_rx_dmareq_b rxdmaen ucr1 (bit 8) rrdy usr1 (bit 9) ipd_uart_tx_dmareq_b txdmaen ucr1 (bit 3) trdy usr1 (bit 13) table 28-21. interrupts and dma interrupt output interrupt enable enable register location interrupt flag flag register location universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-29 for example: main source clock frequency is 270 mhz. ipg_perclk frequency is fixed at 16.8 mhz (270 mhz/16). ipg_clk (and ipg_clk_s ) frequency can vary from 16.8 mhz to a maximum value. this maximum frequency must always comes from an integer divisi on of main source clock (270 mhz/n). it must also be used to constrain th e design during synthesis phase. ? at any moment, ipg_clk (and ipg_clk_s ) frequency must be higher or equal to ipg_perclk frequency. see figure 28-20 for examples of working configurations. ? due to the 16x oversampling of the incoming characters, ipg_perclk frequency must always be greater or equal to 16x the maximum baud rate. for example, if max baud rate is 1.875 mbit/s, ipg_perclk must be greater or equal to 1.875 m x 16 = 30 mhz. note if the architecture of the ic does not require a clock dedicated to brm, ipg_perclk input pin must receive same clock than ipg_clk . clock trees between both pins must be balanced. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-30 freescale semiconductor figure 28-20. examples of working relati onships between ipg_clk and ipg_perclk source clock ipg_clk ipg_perclk source clock ipg_clk ipg_perclk source clock ipg_clk ipg_perclk ipg_clk frequency higher than ipg_perclk frequency ipg_clk and ipg_perclk are equivalent (same frequency and in phase) ipg_clk and ipg_perclk have the same frequency but are not in phase universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-31 28.4.2.2 clocking in low-power modes the uart supports 2 low-power modes: doze and stop. in sleep mode (input pin ipg_stop is at ?1?), the uart does not need any clock. in this mode the uart can wake-up the mcu with the asynchronous interrupts (see section 28.4.8, ?uart operation in low-power system states ?). an application of this feature is when the system must be waken-up by the arrival of a frame of characters. ? if before entering in sleep mode the software has enabled rtsden interrupt, then when rts will change state (put at ?0? by external device star ted to send), the asynchronous interrupt will wake-up the system, and ipg_clk (and ipg_perclk ) will be provided to the uart before first start bit, so that no data will be lost. ? if rts does not change state (already at ?0? before entering in sleep mode), then wake-up interrupt (awake) will be sent at the arrival of first start bit (on falling edge). in this case, the uart must receive the ipg_clk and ipg_perclk during the first half of start bit to correctly receive this character (for example, at 115.2 kbit/s, uart must receive ipg_clk and ipg_perclk at maximum 4.3 microseconds after falling edge of start bit). if the uart receives ipg_clk and ipg_perclk too late, first character will be lost, and so should be dropped. also, if autobaud detection is enabled, the first character will not be correctly received and another autobaud detection will need to be initiated. in doze mode, uart behavior is programmable thr ough doze bit (ucr1[1]). if doze bit is set to ?1?, then uart is disabled in doze mode, and in conseque nce, uart clocks can be switched-off (after being sure uart is not transmitting nor receiving). on the contrary, if doze bit is set to ?0?, uart is enabled and it must receive ipg_clk and ipg_perclk (and ipg_clk_s during accesses to registers). 28.4.3 general uart definitions definitions of terms that occur the following discussions are given in this section. ? bit time?the period of time required to serially transmit or receive 1 bit of data (1 cycle of the baud rate frequency). ? start bit?the bit time of a logic 0 that indicates the beginning of a data frame. a start bit begins with a 1-to-0 transition, and is preceded by at least 1 bit time of logic 1. ? stop bit?1 bit time of logic 1 that indicates the end of a data frame. ? break?a frame in which all of the data bits, including the stop bit, are logic 0. this type of frame is usually sent to signal the end of a message or the begi nning of a new message. ? frame?a start bit followed by a specified number of data or information bits and terminated by a stop bit. the number of data or information bits depends on the format specified and must be the same for the transmitting device and the receiving device. the most common frame format is 1 start bit followed by 8 data bits (least significant bit first) and terminated by 1 stop bit. an additional stop bit and a parity bit also can be included. ? framing error?an error condition that occurs when the stop bit of a received frame is missing, usually when the frame boundaries in the received b it stream are not synchronized with the receiver bit counter. framing errors can go undetected if a da ta bit in the expected stop bit time happens to be a logic 1. a framing error is always present on the receiver side when the transmitter is sending universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-32 freescale semiconductor breaks. however, when the uart is programmed to expect 2 stop bits and only the first stop bit is received, this is not a framing error by definition. ? parity error?an error condition that occurs when the calculated parity of the received data bits in a frame does not match the parity bit received on the rxd input. parity error is calculated only after an entire frame is received. ? idle?one in nrz encoding format and selectable polarity in irda mode. ? overrun error?an error condition that occurs when the latest character received is ignored to prevent overwriting a character already present in the uart receive buffer (rxfifo). an overrun error indicates that the software reading the buf fer (rxfifo) is not keeping up with the actual reception of characters on the rxd input. 28.4.3.1 rts ?uart request to send the uart request to send input controls the tran smitter. the modem or other terminal equipment signals the uart when it is ready to receive by setting rts to ?0? on the ipp_uart_rts_b pin. normally, the transmitter waits until this signal is active (low ) before transmitting a character, however when the ignore rts (irts) bit is set, the transmitter sends a char acter as soon as it is ready to transmit. an interrupt (rtsd) can be posted on any transition of this pin and can wake the mcu from sleep mode on its assertion. when rts is set to ?1? during a transmission, the uart transmitter finishes transmitting the current character and shuts off. the contents of th e txfifo (characters to be transmitted) remain undisturbed. 28.4.3.2 rts edge triggered interrupt the input to the ipp_uart_rts_b pin can be programmed to generate an interrupt on a selectable edge. the operation of the rts edge triggered interrupt (rtsf) is summarized in table 28-22 . to enable the ipp_uart_rts_b pin to generate an interrupt, set the request to send interrupt enable (rtsen) bit (ucr2[4]) to 1. writing 1 to the rts edge triggere d interrupt flag (rtsf) bit (usr2[4]) clears the interrupt flag.the interrupt can occur on the rising edge, falling edge, or either edge of the rts input. the request to send edge control (rtec) field (ucr2[10:9] ) programs the edge that generates the interrupt. when rtec is set to 0x00 and rtsen = 1, the interrupt occurs on the rising edge (default). when rtec is set to 0x01 and rtsen = 1, the interrupt occurs on the falling edge. when rtec is set to 0x1x and rtsen = 1, the interrupt occurs on either edge.this is a synchronous interrupt. the rtsf bit is cleared by writing 1 to it. writing 0 to rtsf has no effect. table 28-22. rts edge triggered interrupt truth table rts rtsen rtec [1] rtec [0] rtsf interrupt occurs on: ipi_uart_mint_b x 0 x x 0 interrupt disabled 1 1?>0 1 0 0 0 rising edge 1 0?>1 1 0 0 1 rising edge 0 1?>0 1 0 1 1 falling edge 0 0?>1 1 0 1 0 falling edge 1 universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-33 there is another rts interrupt that is not program mable, however it asserts the rts delta (rtsd) bit when the rts pin changes state. the status bit rtsd asserts the ipi_uart_mint_b interrupt when the rts delta interrupt enable = 1. this is an asynchronous inte rrupt. the rtsd bit is cleared by writing 1 to it. writing 0 to the rtsd bit has no effect. 28.4.3.3 clear to send (cts ) this output pin serves two purposes. normally, the receiver indicates that it is ready to receive data by asserting this pin (low). when the cts trigger level is programmed to trigger at 32 characters received and the receiver detects the valid start bit of the 33 character, it de-asserts this pin. 28.4.3.4 programmable cts deassertion the cts output can also be programmed to deassert wh en the rxfifo reaches a certain level. setting the cts trigger level (ucr4[15:10]) at any value less than 32 deasserts the cts pin on detection of the valid start bit of the n + 1 character (where n is the trigge r level setting). however, the receiver continues to receive characters until the rxfifo is full. 28.4.3.5 txd?uart transmit this is the transmitter serial output. when operati ng in normal mode, nrz encoded data is output. when operating in infrared mode, a 3/16 bit-period pulse is output for each 0 bit transmitted, and no pulse is output for each 1 bit transmitted. for rs-232 applica tions, this pin must be connected to an rs-232 transmitter. 28.4.3.5.1 rxd?uart receive this is the receiver serial input. when operating in normal mode, nrz encoded data is expected. when operating in infrared mode, a narrow pulse is expected for each 0 bit received and no pulse is expected for each 1 bit received. external circuitry must conve rt the ir signal to an electrical signal. rs-232 applications require an external rs- 232 receiver to convert voltage levels. 1?>0 1 1 x 1 either edge 0 0?>1 1 1 x 1 either edge 0 table 28-22. rts edge triggered interrupt truth table (continued) rts rtsen rtec [1] rtec [0] rtsf interrupt occurs on: ipi_uart_mint_b universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-34 freescale semiconductor figure 28-21. uart simplified block and clock generation diagrams 28.4.4 sub-block description the uart module contains seven working registers separated in 2 status registers (usr1 and usr2) and five control registers (ucr1, ucr2, ucr3, ucr4, uf cr). a separate test register is provided for applications (test, verification, and so on) that requi re it. the binary rate multiplier registers (ubir, ubmr) control the uart bit rate. ref_clk brm_clk bit stream to auto baud transmitter data path binary rate multiplier (brm) programmable divider receiver data path rts cts tx rx dce/dte interface txfifo rxfifo ip bus interface uart data control ipg_clk bit 0 bit 1 bit 2 ubir = 0, ubmr= 1 ?> ratio = 0.5 = 1/2 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd/txd bit 3 start bit stop bit next start bit standard data 8-bit data format possible parity bit -15- -16- -1- -2- -3- -4- -5- -6- -7- -8- -9- -10- -11- -12- -13- -14- -15- -16- -1- -2- -3- ref_clk ufcr:rfdiv[2:0] ipg_perclk ipg_clk_s universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-35 there is also a transmitter register (utxd) and a receiver register (urxd). the registers are optimized for a 16-bit bus. all status bits associated with the received data are accessible along with the data in a single read. except for the transmit data register (u txd), all register bits are readable and most are read/write. the uart baud rate count register (u brc) performs automatic ba ud rate detection. there are also two registers for the escape sequence detect ion, the uart escape character register (uesc) and the uart escape timer register (utim). and finally , the one millisecond register (onems) must be filled with appropriate value when the module needs to measure a duration (escape detection mode or ir special case). the following sections describe the basic functionality of the mains blocks of uart module. 28.4.4.1 transmitter the transmitter accepts a parallel character from the mcu and transmits it serially. the start, stop, and parity (when enabled) bits are added to the character. when the ignore rts bit (irts) is set, the transmitter sends a character as soon as it is ready to transmit. rts can be used to provide flow-control of the serial data. when rts is set to ?1?, the transmitter finishes sendi ng the character in progress (if any), stops, and waits for rts to be set to ?0? again. generation of bre ak characters and parity errors (for debugging purposes) is supported. the transmitter operates fro m the clock provided by the brm. normal nrz encoded data is transmitted when the ir interface is disabled. the transmitter fifo (txfifo) contains 32 bytes. the data is written to txfifo by writing to the utxd register with the byte data to the [7:0] bits. the data is written consecutively if the txfifo is not full. it is read (internally) consecutively if the txfifo is not em pty. if the txfifo is full and data is again attempted to be written to the fifo, a bus xfr_error is generated. 28.4.4.1.1 transmitter fifo empty interrupt suppression the transmitter fifo empty interrupt suppression logi c suppresses the txfe inte rrupt between writes to the txfifo. when txfifo is empty, the software can either send one or several characters. if the software sends one character, it writes it into utxd register and this character is immediately transferred to the transmitter shift register (when the transmitter is en abled). without interrupt suppression logic, the txfe interrupt would be set immediately. but, with this logic, the interrupt is set when the last bit of the character has been transmitted, that is, before the transmission of the parity bit (if exists) and the stop bit(s). so, the suppression logic does not immediately send the txfe interrupt. it allows the software to write another character to the txfifo before the interrupt is asserted. when the transmitter shift register empties before another character is written to the txfifo, the interrupt is asserted. writing data (even a single character) to the txfifo releases the interrupt. the interrupt is asserted on the following conditions: ? system reset ? uart module reset ? when a single character has been written to transmitter fifo and then the transmitter fifo and the transmitter shift register become empty until another character is written to the transmitter fifo universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-36 freescale semiconductor ? the last character in the txfifo is transferred to the shift register, when txfifo contains two or more characters. see figure 28-22 . figure 28-22. transmitter fifo empty interrupt suppression flow chart 28.4.4.1.2 transmitti ng a break condition to send a break, bit 4 of the ucr1 reg (sndbrk) should be asserted. this bit forces the transmitter to send a break character (continuous zeros). the transmitter will finish sending the character in progress (if any) then send break until this bit is reset. the user is responsible to ensure that this bit is high for long enough to generate a valid break. the transmitte r samples sndbrk after every bit is transmitted. assert transmitter fifo empty flag transmitter fifo empty deassert transmitter fifo empty flag deassert transmitter fifo empty flag deassert transmitter fifo empty flag transmitter fifo empty transmitter fifo empty deassert transmitter fifo empty flag transmitter shift register empty transmitter fifo contains > 2 characters reset = peripheral reset or software reset reset reset reset reset reset y y n y y y n n n n universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-37 following completion of the break transmission, the uart will transmit two mark bits. the user can continue to fill the fifo and any character remaining will be transmitted when the break is terminated. 28.4.4.2 receiver the receiver accepts a serial data stream and converts it into parallel characters. when enabled, it searches for a start bit, qualifies it, and samples the following data bits at the bit-center. jitter tolerance and noise immunity are provided by sampling at a 16x rate and using voting techniques to clean up the samples. once the start bit is found, the data bits, parity bit (if en abled), and stop bits (either 1 or 2 depending on user selection) are shifted in. parity is checked and its status reported in the urxd register when parity is enabled. frame errors and breaks are also checked a nd reported. when a new character is ready to be read by the mcu from the rxfifo, the receive data ready (rdr = usr2[0]) bit is asserted and an interrupt is posted (if dren = ucr4[0] = 1). if the receiver trigger level is set to 2 (rxtl[5:0] = ufcr[5:0] = 2), and 2 chars have been received into rxfifo, the receiver ready interrupt flag (rrdy = usr1[9]) is asserted and an interrupt is posted if th e receiver ready interrupt enable bit is set (rrdyen = ucr1[9] = 1). if the uart receiver register (urxd) is read once, and in consequence there is only 1 character in the rxfifo, the interrupt generated by the rrdy bit is automatically cleared. the rrdy bit is cleared when the data in the rxfifo falls below the programmed trigger level. normal nrz encoded data is expected when the ir interface is disabled. the rxfifo contains 32 half-words. the data is read from the rxfifo by reading the half-word data in the [15:0] bits in the urxd register. the data is written consecutively if the rxfifo is not full, or is read consecutively if the rxfifo is not empty. when additional data is written to the rxfifo while it is full, the write operation cannot complete unless a read is perf ormed. if a write is perf ormed on the rxfifo when it is full, the ore bit (usr2[1]) register is set. the ore bit is cleared by writing 1 to it. 28.4.4.2.1 idle line detect the receiver logic block includes the ability to detect an idle line. idle lines indicate the end or the beginning of a message. for an idle condition to occur: ? rxfifo must be empty and ? rxd pin must be idle for more than a confi gured number of frames (icd[1:0] = ucr1[11:10]). when the idle condition detected interrupt enable (i den = ucr1[12]) is set and the line is idle for 4 (default), 8, 16, or 32 (maximum) frames, the detection of an idle condition flags an interrupt. when an idle condition is detected, the idle (usr2[12]) bit is set. clear the idle bit by writing 1 to it. writing 0 to the idle bit has no effect. 28.4.4.2.2 idle condition detect configuration the idle condition detect icd [1:0] field is located in the ucr1[11:10]. if the bits are set to 00b, rxd must be idle for more than 4 frames before the idle bit is asserted. if the bits are set to 01b, rxd must be idle for more than 8 frames before the idle bit is asserted. if the bits are set to 10b, rxd must be idle for more than 16 frames before the idle bit is asserted. if the bits are set to 11b, rxd must be idle for more than 32 frames before the idle bit is asserted (see table 28-23 ). universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-38 freescale semiconductor during a normal message there is no idle time between fra mes. when all of the information bits in a frame are logic 1s, the start bit ensures that at least one l ogic 0 bit time occurs for each frame so that the idle bit is not asserted. 28.4.4.2.3 aging character detect the receiver block also includes the possibility to detect when at least one character has been sitting into the rxfifo for a time corresponding to 8 characters. this aging character capability allows the uart to inform the mcu that there is less character into the rxfifo than the rx trigger and, no new character has been detected on the rxd line. the aging capability is a timer which starts to count as soon as there is one character in rxfifo. this counter is reset when eith er a rxfifo read is performed or another character has been received in rxfifo. if none of those two events occurs, the bit agtim (usr1[8]) is set when the counter has measured a time corresponding to 8 characters. agtim is cleared by writing a 1 to it. agtim can flag an interrupt to mcu on ipi_uart_rx_b if aten (ucr2[3]) has been set. to summarize, agtim is set when: ? there is at least one character into rxfifo. ? no read has occurred on rxfifo and rxd line has stayed high, for a time corresponding to 8 characters. ? the rxfifo trigger is not reached (rrdy=0). 28.4.4.2.4 receiver wake the wake bit (usr2[7]) is set when the receiver detects a qualified the start bit, that is, which has lasted more than a half-bit duration. when the wake inte rrupt enable wken (ucr4[7]) bit is enabled, the receiver flags an interrupt ( ipi_uart_mint_b ) if the wake status bit is set. the wake bit is cleared by writing 1 to it. writing 0 to the wake bit has no effect. when the asynchronous wake interrupt (awake) is enabled (awaken = ucr3[4] = 1), and the mcu is in sleep mode, and uart clocks have been shut-o ff, then a falling edge detected on the receive pin (rxd) asserts the awake bit (usr1[4]) and the ipi_uart_mint_b interrupt to wake the mcu from sleep mode. re-enable uart clocks and clear the awake bit by writing 1 to it. writing 0 to the awake bit has no effect. table 28-23. detection truth table iden icd [1] icd [0] idle ipi_uart_rx_b 0x x 0 1 1 0 0 asserted after 4 idle frames asserted after 4 idle frames 1 0 1 asserted after 8 idle frames asserted after 8 idle frames 1 1 0 asserted after 16 idle frames asserted after 16 idle frames 1 1 1 asserted after 32 idle frames asserted after 32 idle frames note: this table assumes that no other interrupt is set at the same time this interrupt is set for the ipi_uart_rx_b signal. this table shows how this interrupt affects the ipi_uart_rx_b signal. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-39 if the asynchronous ir wake interrupt is enabled (a irinten = ucr3[5] = 1), the uart is configured for ir mode, and if mcu is in sleep mode, and uart clocks have been shut-off, and a falling edge is detected on the receive pin (rxd_ir), then this asserts the airint bit (usr1[5]), and the ipi_uart_mint_b interrupt wakes the mcu from sleep mode. re-enable uart clocks and clear the airint bit by writing 1 to it. writing 0 to the airint bit has no effect. recommended procedure for programming the asynchronous interrupts is to first clear them by writing 1 to the appropriate bit in the uart status register 1 (usr1). poll or enable the interrupt for the receiver idle interrupt flag (rxds) in the usr1. when asserted, the rxds bit indicates to the software that the receiver state machine is in the idle state, the next state is idle, and the rxd pin is idle (high). after following this procedure, enable the as ynchronous interrupt and enter sleep mode. 28.4.4.2.5 receiving a break condition a break condition is received when the receiver detects all 0s (including a 0 during the bit time of the stop bit) in a frame. the break condition asserts the brcd bit (usr2[2]) and writes only the first break character to the rxfifo. clear the brcd bit by writing 1 to it. writing 0 to the brcd bit has no effect. when asserted brcd can generate an interrupt on ipi_uart_mint_b . the interrupt generation can be masked using the control bit bken (ucr4[2]). receiv ing a break condition will also effect the following bits in the receiver register urxd: urxd(11) = brk. while high this bit indicates th at the current char was detected as a break. urxd(12) = frmerr. the frame error bit will always be set when brk is set. urxd(10) = prerr. if odd parity was selected the par ity error bit will also be set when brk is set. urxd(14) = err. the error detect bit indicates that the character present in the rx data field has an error status. this can be asserted by a break. 28.4.4.2.6 vote logic the vote logic block provides jitter tolerance and noi se immunity by sampling with respect to a 16x clock (brm_clk) and using voting techniques to clean up the samples. the voting is implemented by sampling the incoming signal constantly on the rising edge of the brm_clk. the receiver is provided with the majority vote value, which is 2 out of the 3 samples. examples of the majority vote results of the vote logic are shown in table 28-24 . table 28-24. majority vote results samples vote 000 0 101 1 001 0 111 1 universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-40 freescale semiconductor the vote logic captures a sample on every rising edge of brm_clk, however the receiver uses 16x oversampling to take its value in the middle of the sample character. the receiver starts to count when the start bit is set however it does not capture the contents of the rxfifo at the time the start bit is set. the start bit is validated when 0s are received for 7 consecutive 1/16 of bit times following the 1-to-0 transition. once the counter reaches 0xf, it starts counting on the next bit and captures it in the middle of the sampling frame (see table 28-24 ). all data bits are captured in the same manner. once the stop bit is detected, the receiver shift register (sipo_out) data is parallel shifted to the rxfifo. figure 28-23. majority vote results a new feature has been recently implemented, it al lows to re-synchronize the counter on each edge of rxd line. this is automatic and allows to impr ove the immunity of uart against signal distortion. there is a special case when the brm_clk frequency is too low and is unable to capture a 0 pulse in irda. in this case, the software must set the irsc bit so that the reference clock (a fter internal divider) is used for the voting logic. the pulse is va lidated by counting the length of the pulse. 28.4.5 binary rate multiplier (brm) the brm sub-module receives ref_clk ( ipg_perclk clock after divider). form this clock, and with integer and non-integer division, brm generates all baud ra tes. the input and output frequency ratio is programmed in the uart brm incremental register (ubir) and uart brm mod register (ubmr). the output frequency is divided by the input frequenc y to produce this ratio. for integer division, set the ubir = 0x000f and write the divisor to the ubmr register. all values written to these registers must be 111 111 111 111 111 111 110 100 000 000 000 000 000 000 000 000 000 000 000 000 000 001 011 111 110 101 011 111 111 111 111 111 111 brm_clk rx_pin vote_sr [2:0] vote start bit 110 100 000 110 101 011 noise i1i2i3i4i5i6i7ssssssssssssssssssssssssss universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-41 one less than the actual value to eliminate division by 0 (undefined), and to increase the maximum range of the registers. updating the brm registers requires writing to both regist ers. the ubir register must be written before writing to the ubmr register. if only one register is written to by the software, the brm continues to use the previous values. the following examples show how to determine what values are to be programmed into ubir and ubmr for a given reference frequency and desired baud ra te. the following equation can be used to help determine these values: with reffreq (hz): uart reference frequency ( ipg_perclk after rfdiv divider). baudrate (bit/s): desired baudrate. example 28-1. integer division 21 reference frequency = 19.44 mhz ubir = 0x000f ubmr = 0x0014 baudrate = 925.7 kbit/s note notice each value written to the registers is one less than the actual value. example 28-2. non-integer division reference frequency = 16 mhz desired baudrate = 920 kbits/s eqn. 28-1 ratio = 1.087 = 1087 / 1000 ubir = 999 (decimal)= 0x3e7 ubmr = 1086 (decimal)= 0x43e example 28-3. non-integer division reference frequency = 25 mhz desired baudrate = 920 kbit/s baudrate reffreq 16 ubmr 1 + ubir 1 + ---------------------------- ?? ?? ---------------------------------------------- - = ubmr 1 + ubir 1 + --------------------------- - reffreq 16 baudrate ----------------------------------------- - 16 6 10 16 920 3 10 ----------------------------------- 1.087 === universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-42 freescale semiconductor ratio = 1.69837 = 625 / 368 ubir = 367 (decimal)= 0x16f ubmr = 624 (decimal)= 0x270 example 28-4. non-integer division reference frequency: 30 mhz desired baudrate = 115.2 kbit/s ratio = 16.276043 = 65153 / 4003 ubir = 4002 (decimal) = 0x0fa2 ubmr = 65152 (decimal) = 0xfe80 28.4.6 baud rate automatic detection logic when the baud rate automatic detection logic is en abled, the uart locks onto the incoming baud rate. to enable this feature, set the automatic detection of baud rate bit (adbr = ucr1[14] = 1) and write 1 to the adet bit (usr2[15]) to clear it. when adet=0 and adbr =1, the detection starts. then, once the beginning of start bit (transition from 1-to-0 of rxd) has been detected, uart start a counter (ubrc) working at reference frequency. once the end of start bit is detected (transition from 0-to-1 of rxd), the value of ubrc - 1 is directly copied into ubmr register. ubir register is filled with 0x000f. so, at the end of start bit, re gisters gets following values: ubrc = number of reference clock peri ods (after divider) during start bit. ubir = 0x000f ubmr = ubrc - 1 the updated values of the 3 registers can be read. table 28-25. baud rate automatic detection adbr adet baud rate detection ipi_uart_mint_b 0 x manual configuration 1 1 0 auto detection started 1 1 1 auto detection complete 0 note: this table assumes that no other interrupt is set at the same time this interrupt is set for the ipi_uart_mint_b signal. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-43 figure 28-24. baud rate detection protocol diagram if any of the uart brm registers are written to simultaneously by the baud rate automatic detection logic and peripheral data bus, the pe ripheral data bus has priority. 28.4.6.1 baud rate automatic detection protocol the receiver must receive an ascii character ?a? or ?a? to verify proper detection of the incoming baud rate. when an ascii character ?a? (0x41) or ?a? (0x61) is received and no error occurs, the automatic detect baud rate bit is set (adet= 1) and if the interrupt is enabled (aden=ucr1[15]=1), an interrupt ipi_uart_mint_b is generated. when an ascii character ?a? or ?a? is not received (because of a bit error or the reception of another character), the auto detection sequence restarts and waits for another 1-to-0 transition. as long as adet = 0 and adbr = 1, the uart continues to try to lock onto the incoming baud rate. once the ascii character ?a? or ?a? is detected and the adet bit is set, the receiver ignores the adbr bit and continues normal operation with the calculated baudrate. the uart interrupt is active ( ipi_uart_mint_b = 0) as long as adet = 1 and adbr = 1. this can be disabled by clearing the automatic ba ud rate detection interrupt enable bit (aden = 0). before starting an automatic baud rate detection se quence, set adet = 0 and adbr = 1. the rxfifo must contain the ascii character ?a? or ?a? following the automatic baud rate detection interrupt. the 16-bit uart baud rate count register (ubrc) is reset to 4 and stays at 0xffff when an overflow occurs. the ubrc register counts (measures) the durati on of start bit. when the start bit is detected and counted, the uart baud rate count re gister retains its value until the next automatic baud rate detection sequence is initiated. the read only baud rate count register c ounts only when auto detection is enabled. 28.4.6.2 baud rate automatic detection protocol improved several issues have been reported for ics using the aut obaud protocol like it is described above, especially for 57.6 kbit/s and 115.2 kbit/s. in consequence this protocol has been improved. the old one is still available in the current uart ip, but several modificati ons can also be used in order to make this autobaud stop bit start bit idle transition from 0-to-1 note: lsb transmitted first. 1 1 1 0 0 0 0 0 universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-44 freescale semiconductor detection more reliable. if the user wants to keep with the old method, he has to set the bit adnimp (ucr3[7]) to 1. if this bit is not set (default), the autobaud improvements will be used. those improvements are mainly grouped in two categories: the new baudrate measurement and the new acst bit (and associated interrupt). 28.4.6.3 new baudrate determination in order to fight against the problems caused by the distortion and the noise on the rxd line, the duration of the baudrate measurement has been extended. previ ously, as described above, this determination was based on the measurement of the start bit duration. no w, this measurement is based on the duration of start bit + bit0. bit0 is the first bit following the start bit. in fact, the counter which is started at the falling edge of start bit is no longer stopped at next ri sing edge (end of start bit), but it is stopped at the next falling edge (end of bit0). as the character se nt is always a ?a? (41h) or a ?a? (61h), this second falling edge will be always be presen t and it will indicate the end of bi t0. once this counter is stopped, the result is divided by 2 and used by the br m to determine the incoming baud rate. note: ubrc register contains the result of this di vision by two, in consequence it reflects the measurement of the duration of one bit. 28.4.6.3.1 new autobaud count er stopped bit and interrupt a new bit has been added in usr2 register: acst (usr2[11]). this bit is set immediately after the determination of the baud rate, so, ? if adnimp is not set (default), acst is set to 1 after the end of bit 0, ? if adnimp is set to 1, acst is set to 1 at the end of start bit. if acien (ucr3[0]) is set to 1, acst will flag an interrupt on ipi_uart_mint_b signal. this interrupt informs the mcu the brm has just been set with the result of the bit length measurement. if needed, the mcu can perform a read of ubmr (or ubrc) register and determine by itself the baudrate measured. then the mcu has the possibility to correct the brm registers with the nearest standardized baudrate. note ? acst is set only if adbr is set to 1, that is, the uart is autobauding. ? clear the acst bit by writing 1 to it. writing 0 to the acst bit has no effect. 28.4.7 escape sequence detection an escape sequence typically consists of 3 character s entered in rapid succession (such as +++). because these are valid characters by themselves, the time between characters determines if it is a valid escape sequence. too much time between two of the ?+? characters is interpreted as two ?+? characters, and not part of an escape sequence. the software chooses the escape character and write s its value to the uart escape character register (uesc). the software must also enable escape det ection feature by setting escen (ucr2[11]) to 1. the hardware compares this value to incoming characters in the rxfifo. when an escape character is detected, the internal escape timer starts to count. th e software specifies a time-out value for the maximum universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-45 allowable time between 2 successive escape characters. the escape timer is programmable in intervals of 2 ms to a maximum interval of 8.192 seconds. the escape sequence detection feature is available for all the reference frequencies. before using escape sequence detection, the user must fill the onems regist er. this 16-bit register must contain the value of the uart internal frequency divided by 1000. the internal frequency is obtained after the uart internal divider which is applied on ipg_perclk clock. example: ? if the uart brm ( ipg_perclk ) input clock frequency is 66.5 mhz. ? and if the uart input clock is divided by 2 with the internal divider: ufcr[9:7] = 3?b100 eqn. 28-2 table 28-26. escape timer scaling utim register maximum time between specified escape characters 0x000 2 ms 0x001 4 ms 0x002 6 ms 0x003 8 ms 0x004 10 ms ?? 0f8 498 ms 0f9 500 ms ?? 9c3 5 s ?? ffd 8.188 s ffe 8.190 s fff 8.192 s note: to calculate the time interval: (utim_value + 1) 0.002 = time_interval example: (09c3 + 1) 0.002 = 5 sec. onems 66.5 6 10 2 1000 ----------------------- - 33250 81e2h === universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-46 freescale semiconductor the escape sequence detection feature asserts the es cape sequence interrupt flag (escf) bit when the escape sequence interrupt enable (esci) bit is set and an escape sequence is detected. clear the escf bit by writing 1 to it. writing 0 to the escf bit has no effect. 28.4.7.1 generalities the infrared interface is selected when iren (ucr1[7]) is set to 1. the infrared interface is compatible with irda seri al infrared physical laye r specification. in this specification, a ?zero? is represented by a positive pulse, and a ?one? is represented by no pulse (line remains low). in the uart: in tx: for each ?zero? to be transmitted, a narrow pos itive pulse which is 3/16 of a bit time is generated. for each ?one? to be transmitted no pulse is generated (output is low). external circuitry has to be provided to drive an infrared led. in rx: when receiving, a narrow negative pulse is expe cted for each ?zero? transmitted while no pulse is expected for each ?one? transmitted (input is high). note that rx part of ir block expects to receive an inverted signal compared to irda specification. circuitr y external to the ic transforms the infrared signal to an electrical signal. the ir interface has an edge triggered interrupt (irint) . this interrupt validates a zero bit being received. this interrupt is enabled by writing a ?one? to eniri bit. the behavior of infrared interface is determined by three bits invt (ucr3[1]), invr (ucr4[9]), and irsc (ucr4[5]). 28.4.7.2 inverted transmission and reception bits (invt and invr) the values of invt and invr depend of the irda transceiver connected on the txd_ir and rxd_ir pins of the uart. if this transceiver is not inverti ng on both paths tx and rx (like in irda specification), that is, a zero is represented as a positive pulse a nd a one is represented by no pulse (line remains low) for tx and rx, the bit invt must be set to 0 and the bit invr must be set to 1 (because rx ir block expects an inverted signal). on th e contrary user must set invt=1 and invr=0 if both paths of the transceiver are inverting (a zero is represented as a negative pulse and a one is represented by no pulse (line remains high). the transceiver can also be inver ting on only one path (tx or rx), in this case invt and invr must be together equal to 1 or to 0 (depending on which path is inverted). 28.4.7.3 infrared special case (irsc) bit the value to apply to irsc bit depends essentially of two parameters: the baudr ate and the minimum pulse duration (mpd) of the transceiver. as already written, in irda a zero is represented by a positive pulse. the irda specification says that for sir (serial ir) baudrates (from 2.4 kbit/s to 115.2 kbit/s) this nominal pulse duration is equal to 3/16 of a bit duration (at the selected baudrate). but, for all the baudrates a minimum pulse duration is also specified. for si r, the mpd is constant and equal to 1.41 us. in order to understand the meaning of bit irsc, me mu st have an idea of how works the rx path in irda. universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-47 when uart is in irda mode, a zero is not only detect ed by the state of the rxd_ir line, but also with the duration of the pulse. this pulse duration can be me asured with 2 different clocks. the choice of the clock is done with irsc bit. ? if irsc = 0, the clock used is the brm clock. ? if irsc = 1, the clock used is the uart intern al clock (uart clock after the divider (rfdiv)). in normal operation, irsc=0. this means at any time, th e user must be sure the frequency of brm_clock is high enough to measure the pulse. in the uart and for irsc=0, the pulse must last at least 2 brm clock cycles . if this condition is not fulfilled, irsc must be set to 1. let?s take two examples, with the minimum pulse duration equals to the mpd of the irda specification (in sir). example 28-5. clock example #1 the user wants to receive irda data at 115.2 kbit/s. the ubir and ubmr registers are set in order to create the brm_clock with a frequency of 16*baudrat e = 16 * 115.2 = 1.843 mhz. but at the same time, in order to correctly detect the pulse, the user must be sure that 2* brm_clock period is lower than 1.41us. lets check: brm_clock period = 1/1843000 = 542 ns so 2*brm_clock period = 1.09 us < 1.41 us. it is fine. example 28-6. clock example #2 this time the user wants to receive at 19.2 kbit/s. so, the brm_clock is set to 16*19200 = 307.2 khz. let?s check if 2* brm_clock period < 1.41 us: brm_clock period =1/307200 = 3.25 us so 2*brm_clock period = 6.50 us >> 1.41 us. it does not work. so, in this case, the brm clock can not be used to me asure the pulse duration, and the user must select the uart internal clock by setting irsc =1. note like for escape character detection, when ir special case is enabled (irsc=1), the uart must measure a duration. in order to do that, the user must fill the onems register. see section 28.4.7, ?escape sequence detection .? 28.4.7.4 irda interrupt serial infrared mode (sir) uses an edge triggere d interrupt flag irint (usr2[8]). when invr =0, detection of a falling edge on the uart_rxd pin asse ts the irint bit. when invr=1, detection of a rising edge on the uart_rxd pin assets the irint bit. when irint and eniri bits are both asserted, universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 28-48 freescale semiconductor the ipi_uart_mint_b interrupt is asserted. clear the irint bit by writing 1 to it. writing 0 to the irint bit has no effect. 28.4.7.5 conclusion about irda before using the uart in irda, the baud rate limit must be calculated. this baud rate limit will inform the user if irsc bit has to be set or not. let?s determine this limit: as already written, if irsc = 0 the follo wing condition must always be fulfilled: so, so, knowing brm_clock frequency = 16 * baudrate, we get: so, the user needs to set irsc = 0 when: if minimum pulse duration = 2.5 us and baudrate > 50 kbit/s. if minimum pulse duration = 2.0 us and baudrate > 62.5 kbit/s. if minimum pulse duration = 1.41 us and baudrate > 88.6 kbit/s. for baud rates lower than the limit, irsc must be set to 1. 28.4.8 uart operation in low-power system states the uart?s serial interface will operate as long as ipg_clk and ipg_perclk are provided. the rxen (ucr2[1]), txen (ucr2[2]), and uarten (ucr1[0]) b its are set by the user and provide software control of low-power modes. the table below shows the uart functionality while in hardware controlled low-power modes. these modes are controlled by the signals ipg_doze and ipg_stop. table 28-27. uart low power state operation normal state doze state stop state doze bit = 0 doze bit = 1 uart-clock on on on off uart serial/irda on on off off 2 brmclockperiod minpulseduration < brmclockfrequency 2 mpd ------------- - > baudrate 1 8 minpulseduration ------------------------------------------------------------- - > universal asynchronous receiver/transmitters (uart) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 28-49 while in doze state, the uart behavior depends on the doze (ucr1[1]) control bit. while the doze bit is negated, the uart serial interface is operational. while the system is in the doze state, and the doze bit is asserted, the uart is disabled. if the doze state is entered with the doze bit asserted while the uart serial interface was receiving or transmitting data, it will complete the receive/transmit of the current character and signal to the far-end transmitter/receiver to stop sending/receiving. the control/status/data registers will not change when getting into/out of low power modes. the following uart interrupts wake the mcu processor from sleep mode: ?rts (rtsd) ? irda asynchronous wake (airint) ? asynchronous wake (awake) setting the uarten (ucr1[0]) bit to 0 shuts off the receiver and transmitter logic and the associated clocks. if the uart is used only in transmit mode, uarten and txen must be set to 1. if the uart is used only in receive mode, uarten and rxen must be set to 1. setting txen or rxen to 0 allows to save a lot of power. when an asynchronous wake interrupt exits the mcu from sleep mode, make sure that a dummy character is sent first because the first character may not be received correctly. 28.4.9 uart operation in system debug state the bit uts [11] controls whether the uart will respond to the input signal ipg_debug, or whether it will continue to run as normal. if the uart is programmed to respond to ipg_debug: 1. the uart will halt all operations upon detecting the ipg_debug input. 2. a transfer in progress, either to/from a core (via the ip bus interface) or to/from an external device, will be completed before halting. this means a single byte/word transfer, not an entire fifo. reception of any further data from an external device will be disabled. 3. internal registers will continue to be writable and readable via the ip bus interface. a read will leave the contents unaffected. 4. the rx fifo is affected in debug mode in the following way: a) all writes into the rx fifo are prevented. b) the bit rxdbg (uts[9]) is used to select th e readability of the rx fifo during debug mode: ?rxdbg = 0: hold the read pointer at the location it had upon entering debug mode, and urxd register returns only the data value at that location, no matter how many reads attempted. ?rxdbg = 1, selectable at any time: allow to read th e characters received in rx fifo. it will not be possible to re-read previously read locations, nor will it be possible to readjust the read pointer to the value it had prior to entering debug mode. programming irda interface MCIMX27 multimedia applications processor reference manual, rev. 0.2 a-50 freescale semiconductor appendix a programming irda interface a.1 high speed as an example, the following sequence can be used to program the irda interface in order to send and receive characters at 115.2 kbit/s. assumptions: ? input uart clock = 90 mhz ? internal clock divider = 3 (divide input uart clock by 3) ? baud rate = 115.2 kbit/s ? irda transceiver is not inverting on both channe ls: for tx and rx, a zero is represented by a positive pulse, and a one is represented by no pulse (line stays low). ? interrupt: sent to mcu when 1 char is received into the rx fifo (rdr) registers values and programming orders: ucr1 = 0x0085 ucr1[7] = iren = 1: enable ir interface ucr1[0] = uarten = 1: enable uart uts = 0x0000 ufcr = 0x0981 txtl[5:0] = 0x02: default value rfdiv[2:0] = 0x3: divide input uart clock by 3 (resulting internal clock is 30 mhz) rxtl[5:0] = 0x01: default value ubir = 0x0202 ubmr = 0x20be baud rate = 115.2 kbit/s with internal clock = 30 mhz ucr2 = 0x4027 ucr2[14] = irts = 1: ignore level of rts input signal ucr2[5] = ws = 1: characters are 8-bit length ucr2[2] = txen = 1: enable rx path ucr2 [1] = rxen = 1: enable tx path ucr2[0] = srst_b = 1: no software reset ucr3 = 0x0000 ucr4 = 0x8201 ctstl[5:0] = 0x20: default value ucr4[9] = invr = 1: inverted infrared reception (because irda transceiver is not inverting) ucr4[1] = dren = 1: to enable rdr interrupt (sent when one char is received) the uart is ready to send a character as soon as there is a write into utxd register. and an interrupt will be sent to mcu when a character is received. programming irda interface MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor a-51 a.2 low speed this time, we keep the same assumptions but the spee d is now 9.6 kbit/s. so, this baud rate is below the limit (even with a min. pulse duration of 2.5 us) and thus irsc and ref30 must be set to 1. assumptions: ? input uart clock = 90 mhz ? internal clock divider = 3 (divide input uart clock by 3) ? baud rate = 9.6 kbit/s ? irda transceiver is not inverting on both channe ls: for tx and rx, a zero is represented by a positive pulse, and a one is represented by no pulse (line stays low). ? interrupt: sent to mcu when 1 char is received into the rx fifo (rdr) registers values and programming orders: ucr1 = 0x0085 ucr1[7] = iren = 1: enable ir interface ucr1[0] = uarten = 1: enable uart ufcr = 0x0981 ufcr[15:10] = txtl[5:0] = 0x02: default value rfdiv[2:0] = 0x3: divide input uart clock by 3 (resulting internal clock is 30 mhz) ufcr[5:0] = rxtl[5:0] = 0x01: default value ubir = 0x00ff ubmr = 0xc354 baud rate = 9.6 kbit/s with internal clock = 30 mhz ucr2 = 0x4027 ucr2[14] = irts = 1: ignore level of rts input signal ucr2[5] = ws = 1: characters are 8-bit length ucr2[2] = txen = 1: enable rx path ucr2 [1] = rxen = 1: enable tx path ucr2[0] = srst_b = 1: no software reset ucr3 = 0x0004 ucr3[2] = ref30 = 1: internal uart clock = 30 mhz ucr4 = 0x8221 ucr4[15:10] = ctstl[5:0] = 0x20: default value ucr4[9] = invr = 1: inverted infrared reception (because irda transceiver is not inverting) ucr4[5] = irsc = 1: because data rate is below the limit and thus the uart internal clock is used to measure the pulse duration. ucr4[1] = dren = 1: to enable rdr interrupt (sent when one char is received) the uart is now ready to send a character as soon as th ere is a write into utxd register. and an interrupt will be sent to mcu when a character is received. programming irda interface MCIMX27 multimedia applications processor reference manual, rev. 0.2 a-52 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-1 chapter 29 fast ethernet controller (fec) 29.1 introduction this chapter provides a feature-set overview, a f unctional block diagram, a nd transceiver connection information for both the 10 and 100 mbps mii (media inde pendent interface), as well as the 7-wire serial interface. additionally, detailed descriptions of operation and the programming model are included. 29.2 overview the ethernet media access cont roller (mac) is designed to support both 10 and 100 mbps ethernet/ieee 802.3 networks. an exte rnal transceiver interface and transceiver function are required to complete the interface to the media. the fec s upports three different standard mac-phy (physical) interfaces for connection to an external ethernet tr ansceiver. the fec supports the 10/100 mbps mii and the 10 mbps-only 7-wire interface, wh ich uses a subset of the mii pins. 29.2.1 features the fec incorporates the following features: ? support for three different ethernet physical interfaces: ? 100-mbps ieee 802.3 mii ? 10-mbps ieee 802.3 mii ? 10-mbps 7-wire interface (industry standard) ? ieee 802.3 full duplex flow control ? programmable max frame length suppor ts ieee 802.1 vlan tags and priority ? support for full-duplex operation (200mbps throughput ) with a minimum system clock rate of 50mhz ? support for half-duplex operation (100mbps throughput ) with a minimum system clock rate of 25 mhz ? retransmission from transmit fifo following a collision (no processor bus utilization) ? automatic internal flushing of the receive fifo for runts (collision fragments) and address recognition rejects (no processor bus utilization) ? address recognition ? frames with broadcast a ddress may be always accepted or always rejected ? exact match for single 48-bit individual (unicast) address ? hash (64-bit hash) check of individual (unicast) addresses fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-2 freescale semiconductor ? hash (64-bit hash) check of group (multicast) addresses ? promiscuous mode 29.3 modes of operation the primary operational modes ar e described in this section. 29.3.1 full and half duplex operation full duplex mode is intended for use on point to point links between switches or end node to switch. half duplex mode is used in connections between an end node and a repeater or betw een repeaters. selection of the duplex mode is controlled by tcr[fden]. when configured for full duplex mode, flow contro l may be enabled. refer to the tcr[rfc_pause] and tcr[tfc_pause] bits, the rcr[fce] bit, and section 29.5.10, ?full duplex flow control ,? for more details. 29.3.2 interface options the following interface options are supported. a detailed discussion of the interface configurations is provided in section 29.5.5, ?network interface options .? 29.3.2.1 10 mbps and 100 mbps mii interface mii is the media independent interface defined by the ieee 802.3 standard for 10/100 mbps operation. the mac-phy interface may be configured to ope rate in mii mode by asserting rcr[mii_mode]. the speed of operation is determined by the fec_tx _clk and fec_rx_clk pins which are driven by the external transceiver. the transceiver will either auto-negotiate the speed or it may be controlled by software via the serial management interface (fec _mdc/fec_mdio pins) to the transceiver. refer to the mmfr and mscr register descriptions as well as the section on the mii for a description of how to read and write registers in the transceiver via this interface. 29.3.2.2 10 mpbs 7-wire interface operation the fec supports a 7-wire interface as used by many 10 mbps ethernet transceivers. the rcr[mii_mode] bit controls this functionality. if this bit is deasserted, the mii mode is disabled and the 10 mbps, 7-wire mode is enabled. 29.3.3 address recognition options the address options supported are pro miscuous, broadcast reject, individua l address (hash or exact match), and multicast hash match. a ddress recognition options are discussed in detail in section 29.5.8, ?ethernet address recognition .? fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-3 29.3.4 internal loopback internal loopback mode is selected via rcr[l oop]. loopback mode is discussed in detail in section 29.5.13, ?internal and external loopback .? 29.4 fec top-level functional diagram the block diagram of the fec is shown below. the fec is implemented with a combination of hardware and microcode. the off-chip (ethernet) interfaces are compliant with industry and ieee 802.3 standards. figure 29-1. fec block diagram the descriptor controller is a risc-based controller that provides the following functions in the fec: ? initialization (those internal registers not initialized by the user or hardware) ? high level control of the dma channels (initiating dma transfers) sif csr fifo dma descriptor controller mii receive transmit bus controller controller fec_mdc fec_mdio fec_rx_clk fec_rx_dv fec_rxd[3:0] fec_rx_er fec_tx_clk fec_tx_en fec_txd[3:0] fec_tx_er fec_crs mib (risc + microcode) i/o pad mdo mden mdi counters mii/7-wire data option ram ram i/f fec bus fec_col fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-4 freescale semiconductor ? interpreting buffer descriptors ? address recognition for receive frames ? random number generation for transmit collision back-off timer note for dma references in this section, refer to the fec?s dma engine. this dma engine is for the transfer of fec data only, and is not related to the dma controller described in chapter 37, ?direct memory access controller (dmac) .? the ram is the focal point of all data flow in the fast ethernet controller and is divided into transmit and receive fifos. the fifo boundaries are programmable using the frsr register. user data flows to/from the dma block from/to the receive/transmit fifos. tr ansmit data flows from the transmit fifo into the transmit block and receive data flows from the receive block into the receive fifo. the user controls the fec by writing, through the sif (slave interface) module, into control registers located in each block. the csr (control and status register) block provides global control (for example, ethernet reset and enable) and interrupt handling registers. the mii block provides a serial channel for control/s tatus communication with the external physical layer device (transceiver). this serial channel consis ts of the fec_mdc (management data clock) and fec_mdio (management data input/output) lines of the mii interface. the dma block provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently. the transmit and receive blocks provide the ethernet mac functionality (with some assist from microcode). the message information block (mib) maintains counter s for a variety of network events and statistics. it is not necessary for operation of the fec but pr ovides valuable counters fo r network management. the counters supported are the rmon (rfc 1757) ethern et statistics group and some of the ieee 802.3 counters. see section 29.6.3, ?mib block counters memory map ? for more information. 29.5 functional description this section describes the operation of the fec, be ginning with the hardware and software initialization sequence, then a detailed descript ion of the functions of the fec. 29.5.1 initialization sequence this section describes which registers are reset due to hardware reset, which are reset by the fec risc, and what locations the user must initialize prior to enabling the fec. 29.5.1.1 hardware controlled initialization in the fec, registers and control logic that genera te interrupts are reset by hardware. a hardware reset deasserts output signals and rese ts general configuration bits. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-5 other registers reset when the ecr[ether_en] bit is cleared. ecr[ether_en] is deasserted by a hard reset or may be deasserted by software to ha lt operation. by deasserting ecr[ether_en], the configuration control registers such as the tcr and rcr will not be reset, but the entire data path will be reset. 29.5.2 user initialization (prior to asserting ecr[ether_en]) the user needs to initialize portions the fec prior to setting the ecr[ether_en] bit. the exact values will depend on the particular applic ation. the sequence is not important. ethernet mac registers requiring initialization are defined in table 29-2 . fec fifo/dma registers that requi re initialization are defined in table 29-3 . table 29-1. ecr[ether_en] de-assertion effect on fec register/machine reset value xmit block transmission is aborted (bad crc appended) recv block receive activity is aborted dma block all dma activity is terminated rdar cleared tdar cleared descriptor controller block halt operation table 29-2. user initialization (before ecr[ether_en]) description initialize eimr clear eir (write 0xffff_ffff) tfwr (optional) ialr/iaur gaur/galr palr/paur opd (only needed for full duplex flow control) rcr tcr mscr (optional) clear mib_ram (locations $1002_b000+ 0x200-0x2fc) table 29-3. fec user initialization (before ecr[ether_en]) description initialize frsr (optional) initialize emrbr initialize erdsr fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-6 freescale semiconductor 29.5.3 microcontroller initialization in the fec, the descriptor control risc initializes some registers after ecr[ether_en] is asserted. after the microcontroller initialization sequence is complete, the hardware is ready for operation. table 29-4 shows microcontroller initialization operations. 29.5.4 user initialization (after asserting ecr[ether_en]) after asserting ecr[ether_en], the user can set up the buffer/frame descriptors and write to the tdar and rdar. refer to section 29.6.5, ?buffer descriptors ? for more details. 29.5.5 network interface options the fec supports both an mii interface for 10/100 m bps ethernet and a 7-wire serial interface for 10 mbps ethernet. the interface mode is selected by the rcr[mii_mode] bit. in mii mode (rcr[mii_mode] = 1), there are 18 signals define d by the ieee 802.3 standard and supported by the emac. these signals are shown in table 29-5 below. initialize etdsr initialize (empty) transmit descriptor ring initialize (empty) receive descriptor ring table 29-4. microcontroller initialization description initialize backoff random number seed activate receiver activate transmitter clear transmit fifo clear receive fifo initialize transmit ring pointer initialize receive ring pointer initialize fifo count registers table 29-5. mii mode signal description emac pin transmit clock fec_tx_clk transmit enable fec_tx_en transmit data fec_txd[3:0] table 29-3. fec user initialization (before ecr[ether_en]) (continued) description fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-7 the 7-wire serial mode interface (rcr[mii_mode] = 0) operates in what is generally referred to as the ?amd? mode. 7-wire mode connections to the external transceiver are shown in table 29-6 . 29.5.6 fec frame transmission the ethernet transmitter is designed to work with almost no intervention from software. once ecr[ether_en] is asserted and data appears in the tr ansmit fifo, the ethernet mac is able to transmit onto the network. when the transmit fifo fills to the watermark (defin ed by the tfwr), the mac transmit logic will assert fec_tx_en and start transmitting the preamble (pa) sequence, the start frame delimiter (sfd), and then the frame information from the fifo. however, the cont roller defers the transmission if the network is busy (fec_crs asserts). before transmitting, the cont roller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. if so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). see section 29.5.14.1, ?transmission errors ? for more details. transmit error fec_tx_er collision fec_col carrier sense fec_crs receive clock fec_rx_clk receive data valid fec_rx_dv receive data fec_rxd[3:0] receive error fec_rx_er management data clock fec_mdc management data input/output fec_mdio table 29-6. 7-wire mode configuration signal description emac pin transmit clock fec_tx_clk transmit enable fec_tx_en transmit data fec_txd[0] collision fec_col receive clock fec_rx_clk receive data valid fec_rx_dv receive data fec_rxd[0] table 29-5. mii mode (continued) signal description emac pin fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-8 freescale semiconductor if a collision occurs during transmission of the frame (half duplex mode), the ethernet controller follows the specified backoff procedures and attempts to re transmit the frame until the retry limit is reached. the transmit fifo stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved from system memory in case of a collision. this imp roves bus utilization and la tency in case immediate retransmission is necessary. when all the frame data has been transmitted, the fcs (frame check sequence or 32-bit cyclic redundancy check, crc) bytes ar e appended if the tc bit is set in the transmit frame control word. if the abc bit is set in the transmit frame control word, a bad crc will be appended to the frame data regardless of the tc bit value. following the transmission of the crc, the ethernet controller writes the frame status information to the mib block. short frames are automa tically padded by the transmit logic (if the tc bit in the transmit buffer descriptor for the end of frame buffer = 1). both buffer (txb) and frame (txf) interrupts may be generated as determined by the settings in the eimr. the transmit error interrupts are hberr, babt, late_col, col_retry_lim, and xfifo_un. if the transmit frame length exceeds max_fl bytes the babt interrupt will be asserted, however the entire frame will be transmitted (no truncation). to pause transmission, set the gts (graceful transmit stop) bit in the tcr register. when the tcr[gts] is set, the fec transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame either finishes or terminates with a collision. after the transmitter has stopped the gra (graceful stop complete) interrupt is asserted. if tcr[gts] is cleared, the fec resumes transmission with the next frame. the ethernet controller transmits bytes least significant bit first. 29.5.7 fec frame reception the fec receiver is designed to work with almost no intervention from the host and can perform address recognition, crc checking, short frame chec king, and maximum frame length checking. when the driver enables the fec receiver by as serting ecr[ether_en], it will immediately start processing receive frames. when fec_rx_dv asserts, the receiver will first check for a valid pa/sfd header. if the pa/sfd is valid, it will be stripped and the frame will be processed by the receiver. if a valid pa/sfd is not found, the frame will be ignored. in serial mode, the first 16 bit times of rx_d 0 following assertion of fec_rx_dv are ignored. following the first 16 bit times the data sequence is chec ked for alternating 1/0s. if a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. after bit time 21, the data sequence is monitored for a valid sfd (11). if a 00 is dete cted, the frame is rejected. when a 11 is detected, the pa/sfd sequence is complete. in mii mode, the receiver checks for at least one byte matching the sfd. zero or more pa bytes may occur, but if a 00 bit sequence is detected prior to the sfd byte, the frame is ignored. after the first 6 bytes of the frame have been rece ived, the fec performs address recognition on the frame. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-9 once a collision window (64 bytes) of data has been re ceived and if address re cognition has not rejected the frame, the receive fifo is signalled that the fra me is ?accepted? and may be passed on to the dma. if the frame is a runt (due to collision) or is reje cted by address recognition, th e receive fifo is notified to ?reject? the frame. thus, no collision fragments are presented to the user except late collisions, which indicate serious lan problems. during reception, the ethernet controller checks fo r various error conditions and once the entire frame is written into the fifo, a 32-bit frame status word is written into the fifo. this status word contains the m, bc, mc, lg, no, cr, ov and tr status bits, and the frame length. see section 29.5.14.2, ?reception errors ? for more details. receive buffer (rxb) and frame interrupts (rxf) may be generated if enabled by the eimr register. a receive error interrupt is babbling receiver error (bab r). receive frames are not truncated if they exceed the max frame length (max_fl); however, the babr in terrupt will occur and the lg bit in the receive buffer descriptor (rxbd) will be set. see section 29.6.5.2, ?ethernet receive buffer descriptor (rxbd) ? for more details. when the receive frame is complete, the fec sets the l- bit in the rxbd, writes the other frame status bits into the rxbd, and clears the e-bit. the ethernet c ontroller next generates a ma skable interrupt (rxf bit in eir, maskable by rxf bit in eimr), indicating that a frame has been received and is in memory. the ethernet controller then waits for a new frame. the ethernet controller receives serial data lsb first. 29.5.8 ethernet address recognition the fec filters the received frames based on destinat ion address (da) type ? individual (unicast), group (multicast), or broadcast (all-ones group address). the difference between an individual address and a group address is determined by the i/g bit in the destination address field. a flowchart for address recognition on received frames is illustrated in the figures below. address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. the flowchart shown in figure 29-2 illustrates the address re cognition decisions made by the receive block, while figure 29-3 illustrates the decisions made by the microcontroller. if the da is a broadcast address and broadcast reject (rcr[bc_rej]) is deasserted, then the frame will be accepted unconditionally, as shown in figure 29-2 . otherwise, if the da is not a broadcast address, then the microcontroller runs the address recognition subroutine, as shown in figure 29-3 . if the da is a group (multicast) address and flow contro l is disabled, then the microcontroller will perform a group hash table lookup using the 64-entry hash tabl e programmed in gaur and galr. if a hash match occurs, the receiver accepts the frame. if flow control is enabled, the microcontroller will do an exact address match check between the da and the designated pause da (01:80:c2:00: 00:01). if the receive block determines that the received frame is a valid pause frame, then the frame will be rejected. note the receiver will detect a pause frame with the da field set to either the designated pause da or the unicast physical address. if the da is the individual (unicast) address, th e microcontroller performs an individual exact match comparison between the da and 48-bit physical addre ss that the user programs in the palr and paur fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-10 freescale semiconductor registers. if an exact match occurs, the frame is acce pted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry ha sh table programmed in registers, iaur and ialr. in the case of an individual hash match, the frame is accepted. again, the receiver will accept or reject the frame based on pause frame detection, shown in figure 29-2 . if neither a hash match (group or individual), nor an exact match occur, then if promiscuous mode is enabled (rcr[prom] = 1), then the frame will be accepted and the miss bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. similarly, if the da is a broadcast address, broadcas t reject (rcr[bc_rej]) is asserted, and promiscuous mode is enabled, then the frame will be accepted and the miss bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. in general, when a frame is rejected, it is flushed from the fifo. figure 29-2. ethernet address recognition?receive block decisions accept/reject broadcast addr ? ? prom = 1 ? receive address true notes: bc_rej - field in rcr register (broadcast reject) false true false bc_rej = 1 ? frame hash match ? exact match ? pause frame false false false false true true true true receive frame receive frame receive frame receive frame reject frame reject frame prom - field in rcr register pause frame - valid pause frame received set bc bit in rcv bd set mc bit in rcv bd if multicast set m (miss) bit in rcv bd set mc bit in rcv bd if multicast set bc bit in rcv bd if broadcast flush from fifo flush from fifo recognition fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-11 figure 29-3. ethernet address recognition?microcode decisions 29.5.9 hash algorithm the hash table algorithm used in the group and individual hash filtering operates as follows. the 48-bit destination address is mapped into one of 64 bits, wh ich are represented by 64 bits stored in gaur, galr (group address hash match) or i aur, ialr (individual address hash match). this mapping is performed by passing the 48-bit address through the on-chip 32- bit crc generator and selecting the 6 most significant bits of the crc-encoded result to gene rate a number between 0 and 63. the msb of the crc result selects gaur (msb = 1) or galr (msb = 0). the least significant 5 bits of the hash result select the bit within the selected register. if the crc generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected. for example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. the effectiveness of the hash table declin es as the number of addresses increases. receive address i/g address ? exact match ? hash search group table match ? hash search individual table false match ? false false true true true notes: fce - field in rcr register (flow control enable) i/g - individual/group bit in destination address (least significant bit in first byte received in mac frame) individual group true false true false ? pause address fce ? recognition reject frame flush from fifo reject frame flush from fifo receive frame receive frame receive frame receive frame fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-12 freescale semiconductor the hash table registers must be initialized by the user. the crc32 polynomial to use in computing the hash is: a table of example destination addresses and corres ponding hash values is included below for reference. table 29-7. destination address to 6-bit hash 48-bit da 6-bit hash (in hex) hash decimal value 65:ff:ff:ff:ff:ff 0x0 0 55:ff:ff:ff:ff:ff 0x1 1 15:ff:ff:ff:ff:ff 0x2 2 35:ff:ff:ff:ff:ff 0x3 3 b5:ff:ff:ff:ff:ff 0x4 4 95:ff:ff:ff:ff:ff 0x5 5 d5:ff:ff:ff:ff:ff 0x6 6 f5:ff:ff:ff:ff:ff 0x7 7 db:ff:ff:ff:ff:ff 0x8 8 fb:ff:ff:ff:ff:ff 0x9 9 bb:ff:ff:ff:ff:ff 0xa 10 8b:ff:ff:ff:ff:ff 0xb 11 0b:ff:ff:ff:ff:ff 0xc 12 3b:ff:ff:ff:ff:ff 0xd 13 7b:ff:ff:ff:ff:ff 0xe 14 5b:ff:ff:ff:ff:ff 0xf 15 27:ff:ff:ff:ff:ff 0x10 16 07:ff:ff:ff:ff:ff 0x11 17 57:ff:ff:ff:ff:ff 0x12 18 77:ff:ff:ff:ff:ff 0x13 19 f7:ff:ff:ff:ff:ff 0x14 20 c7:ff:ff:ff:ff:ff 0x15 21 97:ff:ff:ff:ff:ff 0x16 22 a7:ff:ff:ff:ff:ff 0x17 23 99:ff:ff:ff:ff:ff 0x18 24 b9:ff:ff:ff:ff:ff 0x19 25 x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 +++++++ +++++++ fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-13 f9:ff:ff:ff:ff:ff 0x1a 26 c9:ff:ff:ff:ff:ff 0x1b 27 59:ff:ff:ff:ff:ff 0x1c 28 79:ff:ff:ff:ff:ff 0x1d 29 29:ff:ff:ff:ff:ff 0x1e 30 19:ff:ff:ff:ff:ff 0x1f 31 d1:ff:ff:ff:ff:ff 0x20 32 f1:ff:ff:ff:ff:ff 0x21 33 b1:ff:ff:ff:ff:ff 0x22 34 91:ff:ff:ff:ff:ff 0x23 35 11:ff:ff:ff:ff:ff 0x24 36 31:ff:ff:ff:ff:ff 0x25 37 71:ff:ff:ff:ff:ff 0x26 38 51:ff:ff:ff:ff:ff 0x27 39 7f:ff:ff:ff:ff:ff 0x28 40 4f:ff:ff:ff:ff:ff 0x29 41 1f:ff:ff:ff:ff:ff 0x2a 42 3f:ff:ff:ff:ff:ff 0x2b 43 bf:ff:ff:ff:ff:ff 0x2c 44 9f:ff:ff:ff:ff:ff 0x2d 45 df:ff:ff:ff:ff:ff 0x2e 46 ef:ff:ff:ff:ff:ff 0x2f 47 93:ff:ff:ff:ff:ff 0x30 48 b3:ff:ff:ff:ff:ff 0x31 49 f3:ff:ff:ff:ff:ff 0x32 50 d3:ff:ff:ff:ff:ff 0x33 51 53:ff:ff:ff:ff:ff 0x34 52 73:ff:ff:ff:ff:ff 0x35 53 23:ff:ff:ff:ff:ff 0x36 54 13:ff:ff:ff:ff:ff 0x37 55 3d:ff:ff:ff:ff:ff 0x38 56 0d:ff:ff:ff:ff:ff 0x39 57 table 29-7. destination address to 6-bit hash (continued) 48-bit da 6-bit hash (in hex) hash decimal value fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-14 freescale semiconductor 29.5.10 full duplex flow control full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. upon detection of a pause frame, mac data frame transmission stops for a given pause duration. to enable pause frame detection, the fec must opera te in full-duplex mode (tcr[fden] asserted) and flow control enable (rcr[fce]) must be asserted. the fec detects a pause frame when the fields of the incoming frame match the pause frame specifications, as shown in the table below. in addition, the receive status associated with the frame shoul d indicate that the frame is valid. pause frame detection is performed by the receiver and microcontroller modules. the microcontroller runs an address recognition subroutine to detect the spec ified pause frame destination address, while the receiver detects the type and opcode pause frame fi elds. on detection of a pause frame, tcr[gts] is asserted by the fec internally. when transmission has paused, the eir[gra] interr upt is asserted and the pause timer begins to increment. note that the pause timer makes use of the transmit back-off timer hardware, which is used for tracking the appropriate collision back-off timer in half-duplex mode. the pause timer increments once every slot time, until opd[pause_dur] slot times have expired. on opd[pause_dur] expiration, tcr[gts] is deasse rted allowing mac data frame transmission to resume. note that the receive flow control pause (t cr[rfc_pause]) status bit is asserted while the transmitter is paused due to reception of a pause frame. to transmit a pause frame, the fec must operate in fu ll-duplex mode and the user must assert flow control pause (tcr[tfc_pause]). on assertion of transmit flow control pause (tcr[tfc_pause]), the transmitter asserts tcr[gts] internally. when the transmission of data frames stops, the eir[gra] (graceful stop complete) interrupt asserts. following eir[gra] assertion, the pause frame is transmitted. on completion of pause frame transmission, flow control pause (tcr[tfc_pause]) and tcr[gts] are deasserted internally. the user must specify the desired pause duration in the opd register. 5d:ff:ff:ff:ff:ff 0x3a 58 7d:ff:ff:ff:ff:ff 0x3b 59 fd:ff:ff:ff:ff:ff 0x3c 60 dd:ff:ff:ff:ff:ff 0x3d 61 9d:ff:ff:ff:ff:ff 0x3e 62 bd:ff:ff:ff:ff:ff 0x3f 63 48-bit destination address 0x0180_c200_0001 or physical address 48-bit source address any 16-bit type 0x8808 16-bit opcode 0x0001 16-bit pause duration 0x0000 to 0xffff table 29-7. destination address to 6-bit hash (continued) 48-bit da 6-bit hash (in hex) hash decimal value fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-15 note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause (tcr[tfc_pause]) still may be as serted and will cause th e transmission of a single pause frame. in this case, the eir[gra] interrupt will not be asserted. 29.5.11 inter-packet gap (ipg) time the minimum inter-packet gap time for back-to-ba ck transmission is 96 bit times. after completing a transmission or after the back-off algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time ipg counter. frame tr ansmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. if carrier sense asserts during the last 36 bit times, it will be ignored and a collision will occur. the receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. if an inter-packet gap between receive frames is less than 28 bit times, the following frame may be discarded by the receiver. 29.5.12 collision handling if a collision occurs during frame tr ansmission, the ethernet controller will continue the transmission for at least 32 bit times, transmitting a jam pattern consisting of 32 ones. if the collision occurs during the preamble sequence, the jam pattern will be sent after the end of the preamble sequence. if a collision occurs within 512 bit times, the retry process is initiated. the tr ansmitter waits a random number of slot times. a slot time is 512 bit times. if a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a late collision (lc) error indication. 29.5.13 internal and external loopback both internal and external loopback are supported by the ethernet controller. in loopback mode, both of the fifos are used and the fec actually operates in a full-duplex fashion. both internal and external loopback are configured using combinations of the l oop and drt bits in the rcr register and the fden bit in the tcr register. for both internal and external loopback set fden = 1. for internal loopback set rcr[loop] = 1 and rc r[drt] = 0. fec_tx_en and fec_tx_er will not assert during internal loopback. during internal loopbac k, the transmit/receive data rate is higher than in normal operation because the internal system clock is used by the transmit and receive blocks instead of the clocks from the external transceiver. this will cau se an increase in the required system bus bandwidth for transmit and receive data being dma?d to/from ex ternal memory. it may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit fifo underrun and receive fifo overflow. for external loopback set rcr[loop] = 0, rcr[drt] = 0 and configure the external transceiver for loopback. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-16 freescale semiconductor 29.5.14 ethernet error-handling procedure the ethernet controller reports frame reception and transmission error conditions using the fec rxbds, the eir register, and the mib block counters. 29.5.14.1 transmission errors 29.5.14.1.1 transmitter underrun if this error occurs, the fec sends 32 bits that ensu re a crc error and stops transmitting. all remaining buffers for that frame are then flushed and closed. the un bit is set in the eir. the fec will then continue to the next transmit buffer descriptor and begin transmitting the next frame. the ?un? interrupt will be asserted if enabled in the eimr register. 29.5.14.1.2 retransmission attempts limit expired when this error occurs, the fec terminates transmi ssion. all remaining buffers for that frame are flushed and closed, and the rl bit is set in the eir. the fec will then continue to the next transmit buffer descriptor and begin transmitting the next frame. the ?rl? interrupt will be asserted if enabled in the eimr register. 29.5.14.1.3 late collision when a collision occurs after the slot time (512 b its starting at the preamble), the fec terminates transmission. all remaining buffers for that frame are fl ushed and closed, and the lc bit is set in the eir register. the fec will then continue to the next tr ansmit buffer descriptor and begin transmitting the next frame. the ?lc? interrupt will be asserted if enabled in the eimr register. 29.5.14.1.4 heartbeat some transceivers have a self-test feature called ?h eartbeat? or ?signal quality error.? to signify a good self-test, the transceiver indicates a collision to th e fec within 4 microseconds after completion of a frame transmitted by the ethernet controller. this indicati on of a collision does not imply a real collision error on the network, but is rather an indication that the tr ansceiver still seems to be functioning properly. this is called the heartbeat condition. if the hbc bit is set in the tcr register and the hear tbeat condition is not detected by the fec after a frame transmission, then a heartbeat error occurs. when this error occurs, the fec closes the buffer, sets the hb bit in the eir register, and generates the hberr interrupt if it is enabled. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-17 29.5.14.2 reception errors 29.5.14.2.1 overrun error if the receive block has data to put into the receive fi fo and the receive fifo is full, the fec sets the ov bit in the rxbd. all subsequent data in the frame w ill be discarded and subsequent frames may also be discarded until the receive fifo is serviced by the dma and space is made available. at this point the receive frame/status word is written into the fifo with the ov bit set. this frame must be discarded by the driver. 29.5.14.2.2 non-octet error (dribbling bits) the ethernet controller handles up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. dribbling bits are not used in the crc calculation. if there is a crc error, then the frame non-octet aligned (no) error is reported in the rxbd. if there is no crc error, then no error is reported. 29.5.14.2.3 crc error when a crc error occurs with no dribble bits, the fec closes the buffer and sets the cr bit in the rxbd. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 29.5.14.2.4 frame length violation when the receive frame length exceeds max_fl bytes the babr interrupt will be generated, and the lg bit in the end of frame rxbd will be set. the fr ame is not truncated unless the frame length exceeds 2047 bytes). 29.5.14.2.5 truncation when the receive frame length exceeds 2047 bytes the frame is truncated and the tr bit is set in the receive bd. 29.6 memory map and register definition this section gives an overview of the registers, followed by a description of the buffers. the fec is programmed by a combination of control/st atus registers (csrs) and buffer descriptors. the csrs are used for mode control and to extract global status information. the descriptors are used to pass data buffers and related buffer informat ion between the hardware and software. 29.6.1 high-level module memory map the fec implementation requires a 1-kbyte memory map space. this is divided into 2 sections of 512 bytes each. the first is used for control/status regist ers. the second contains event/statistic counters held in the mib block. table 29-8 defines the top level memory map. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-18 freescale semiconductor 29.6.2 detailed memory map (control/status registers) table 29-9 shows the fec register memory map with each re gister address, name, and a brief description. table 29-8. module memory map address function 0x1002_b + 0x000-1ff control/status registers 0x1002_b + 0x200-3ff mib block counters table 29-9. fec register memory map address register access reset value section/page 0x1002_b004 (eir) interrupt event register r/w 0x0000_0000 29.6.4.1/29-21 0x1002_b008 (eimr) interrupt mask register r/w 0x0000_0000 29.6.4.2/29-23 0x1002_b010 (rdar) receive descriptor active register r/w 0x0000_0000 29.6.4.3/29-23 0x1002_b014 (tdar) transmit descriptor active register r/w 0x0000_0000 29.6.4.4/29-24 0x1002_b024 (ecr) ethernet control register r/w 0xf000_0000 29.6.4.5/29-25 0x1002_b040 (mmfr) mii management frame register r/w undefined 29.6.4.6/29-25 0x1002_b044 (mscr) mii speed control register r/w 0x0000_0000 29.6.4.7/29-27 0x1002_b064 (mibc) mib control/status register r/w 0x0000_0000 29.6.4.8/29-28 0x1002_b084 (rcr) receive control register r/w 0x05ee_0001 29.6.4.9/29-29 0x1002_b0c4 (tcr) transmit control register r/w 0x0000_0000 29.6.4.10/29-30 0x1002_b0e4 (palr) physical address low register r/w undefined 29.6.4.11/29-30 0x1002_b0e8 (paur) physical address high register r/w see section 29.6.4.12/29-31 0x1002_b0ec (opd) opcode/pause duration r/w see section 29.6.4.13/29-31 0x1002_b118 (iaur) descriptor individual upper address register r/w undefined 29.6.4.14/29-32 0x1002_b11c (ialr) descriptor individual lower address register r/w undefined 29.6.4.15/29-32 fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-19 29.6.3 mib block counters memory map table 29-10 defines the mib counters memory map which defines the locations in the mib ram space where hardware maintained counters reside. thes e fall in the 0x200-0x3ff address offset range. the counters are divided into two groups. rmon counters are included which cover the ethern et statistics counters defined in rfc 1757. in addition to the counters defined in the ethernet sta tistics group, a counter is included to count truncated frames as the fec only supports frame lengths up to 2047 bytes. the rmon counters are implemented independently for transmit and receive to insure accu rate network statistics when operating in full duplex mode. ieee counters are included which support the mandatory and recommended counter packages defined in section 5 of ansi/ieee std. 802.3 (1998 edition). the ieee basic package objects are supported by the fec but do not require counters in the mib block. in addition, some of the recommended package objects which are supported do not require mib counters. count ers for transmit and receive full duplex flow control frames are included as well. 0x1002_b120 (gaur) descriptor group upper address register r/w undefined 29.6.4.16/29-33 0x1002_b124 (galr) descriptor group lower address register r/w undefined 29.6.4.17/29-33 0x1002_b144 (tfwr) transmit fifo watermark r/w 0x0000_0001 29.6.4.18/29-34 0x1002_b14c (frbr) fifo receive bound register r 0x0000_0600 29.6.4.19/29-34 0x1002_b150 (frsr) fifo receive fifo start register r 0x0000_0500 29.6.4.20/29-35 0x1002_b180 (erdsr) pointer to receive descriptor ring r/w undefined 29.6.4.21/29-35 0x1002_b184 (etdsr) pointer to transmit descriptor ring r/w undefined 29.6.4.22/29-36 0x1002_b188 (emrbr) maximum receive buffer size r/w undefined 29.6.4.23/29-36 table 29-10. mib counters memory map offset mnemonic description 0x200 rmon_t_drop count of frames not counted correctly 0x204 rmon_t_packets rmon tx packet count 0x208 rmon_t_bc_pkt rmon tx broadcast packets 0x20c rmon_t_mc_pkt rmon tx multicast packets table 29-9. fec register memory map address register access reset value section/page fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-20 freescale semiconductor 0x210 rmon_t_crc_align rmon tx packets w crc/align error 0x214 rmon_t_undersize rmon tx packets < 64 bytes, good crc 0x218 rmon_t_oversize rmon tx packets > max_fl bytes, good crc 0x21c rmon_t_frag rmon tx packets < 64 bytes, bad crc 0x220 rmon_t_jab rmon tx packets > max_fl bytes, bad crc 0x224 rmon_t_col rmon tx collision count 0x228 rmon_t_p64 rmon tx 64 byte packets 0x22c rmon_t_p65to127 rmon tx 65 to 127 byte packets 0x230 rmon_t_p128to255 rmon tx 128 to 255 byte packets 0x234 rmon_t_p256to511 rmon tx 256 to 511 byte packets 0x238 rmon_t_p512to1023 rmon tx 512 to 1023 byte packets 0x23c rmon_t_p1024to2047 rmon tx 1024 to 2047 byte packets 0x240 rmon_t_p_gte2048 rmon tx packets w > 2048 bytes 0x244 rmon_t_octets rmon tx octets 0x248 ieee_t_drop count of frames not counted correctly 0x24c ieee_t_frame_ok frames transmitted ok 0x250 ieee_t_1col frames transmitted with single collision 0x254 ieee_t_mcol frames transmitted with multiple collisions 0x258 ieee_t_def frames transmitted after deferral delay 0x25c ieee_t_lcol frames transmitted with late collision 0x260 ieee_t_excol frames transmitted with excessive collisions 0x264 ieee_t_macerr frames transmitted with tx fifo underrun 0x268 ieee_t_cserr frames transmitted with carrier sense error 0x26c ieee_t_sqe frames transmitted with sqe error 0x270 ieee_t_fdxfc flow control pause frames transmitted 0x274 ieee_t_octets_ok octet count for frames transmitted w/o error 0x284 rmon_r_packets rmon rx packet count 0x288 rmon_r_bc_pkt rmon rx broadcast packets 0x28c rmon_r_mc_pkt rmon rx multicast packets 0x290 rmon_r_crc_align rmon rx packets w crc/align error 0x294 rmon_r_undersize rmon rx packets < 64 bytes, good crc 0x298 rmon_r_oversize rmon rx pa ckets > max_fl bytes, good crc 0x29c rmon_r_frag rmon rx packets < 64 bytes, bad crc table 29-10. mib counters memory map (continued) offset mnemonic description fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-21 29.6.4 register descriptions the following sections describe each register in detail. 29.6.4.1 ethernet interrupt event register (eir) when an event occurs that sets a bit in the eir, an interrupt will be generated if the corresponding bit in the interrupt mask register (eimr) is also set. the bit in the eir is cleared if a one is written to that bit position; writing zero has no effect. this register is cleared upon hardware reset. these interrupts can be divided into operational inte rrupts, transceiver/network error interrupts, and internal error interrupts. interrupts which may occur in normal operation are gra, txf, txb, rxf, rxb, and mii. interrupts resulting from errors/problems de tected in the network or transceiver are hberr, babr, babt, lc and rl. interrupts resulting from internal errors are eberr and un. some of the error interrupts are independently count ed in the mib block counters. software may choose to mask off these interrupts since these errors will be visible to network management via the mib counters. ? hberr - ieee_t_sqe ? babr - rmon_r_oversize (good crc), rmon_r_jab (bad crc) ? babt - rmon_t_oversize (good crc), rmon_t_jab (bad crc) 0x2a0 rmon_r_jab rmon rx packets > max_fl bytes, bad crc 0x2a4 rmon_r_resvd_0 0x2a8 rmon_r_p64 rmon rx 64 byte packets 0x2ac rmon_r_p65to127 rmon rx 65 to 127 byte packets 0x2b0 rmon_r_p128to255 rmon rx 128 to 255 byte packets 0x2b4 rmon_r_p256to511 rmon rx 256 to 511 byte packets 0x2b8 rmon_r_p512to1023 rmon rx 512 to 1023 byte packets 0x2bc rmon_r_p1024to2047 rmon rx 1024 to 2047 byte packets 0x2c0 rmon_r_p_gte2048 rmon rx packets w > 2048 bytes 0x2c4 rmon_r_octets rmon rx octets 0x2c8 ieee_r_drop count of frames not counted correctly 0x2cc ieee_r_frame_ok frames received ok 0x2d0 ieee_r_crc frames received with crc error 0x2d4 ieee_r_align frames received with alignment error 0x2d8 ieee_r_macerr receive fifo overflow count 0x2dc ieee_r_fdxfc flow control pause frames received 0x2e0 ieee_r_octets_ok octet count for frames rcvd w/o error table 29-10. mib counters memory map (continued) offset mnemonic description fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-22 freescale semiconductor ? late_col - ieee_t_lcol ? col_retry_lim - ieee_t_excol ? xfifo_un - ieee_t_macerr 0x1002_b004 (eir) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rhb err babr babt gra txf txb rxf rxb mii eb err lc rl un 000 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 000000000 0 000000 w reset0000000000000000 figure 29-4. ethernet interrupt event register (eir) table 29-11. eir field descriptions field description 31 hberr heartbeat error. indicates tcr[hbc] is set and that the col input was not asserted within the heartbeat window following a transmission. 30 babr babbling receive error. indicates a frame was received with length in excess of rcr[max_fl] bytes. 29 babt babbling transmit error. indicates the transmitted frame length exceeds rcr[max_fl] bytes. usually this condition is caused by a frame that is too long is placed into the transmit data buffer(s). truncation does not occur. 28 gra graceful stop complete. indicates the graceful stop is complete. during graceful stop the transmitter is placed into a pause state after completion of the frame currently being transmitted. this bit is set by one of three conditions: 1) a graceful stop initiated by the setting of the tcr[gts] bit is now complete. 2) a graceful stop initiated by the setting of the tcr[tfc_pause] bit is now complete. 3) a graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. refer to section 29.5.10, ?full duplex flow control.? 27 txf transmit frame interrupt. indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated. 26 txb transmit buffer interrupt. indicates a transmit buffer descriptor has been updated. 25 rxf receive frame interrupt. indicates a frame has been received and the last corresponding buffer descriptor has been updated. 24 rxb receive buffer interrupt. indicates a receive buffer descriptor not the last in the frame has been updated. 23 mii mii interrupt. indicates the mii has completed the data transfer requested. 22 eberr ethernet bus error. indicates a system bus error occurred when a dma transaction is underway. when the eberr bit is set, ecr[ether_en] is cleared, halting frame processing by the fec. when this occurs, software needs to insure that the fifo controller and dma also soft reset. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-23 29.6.4.2 interrupt mask register (eimr) the eimr controls which interrupt events are allowed to generate actual interrupts. all implemented bits in this csr are read/write. this register is cleared upon a hardware reset. if the corresponding bits in both the eir and eimr are set, the interrupt will be signalled to the cpu. the interrupt signal will remain asserted until a 1 is written to the eir bit (write 1 to clear) or a 0 is written to the eimr bit. 29.6.4.3 receive descriptor active register (rdar) rdar is a command register, written by the user, that indicates that the receive descriptor ring has been updated (empty receive buffers have been produced by the driver with the empty bit set). 21 lc late collision. indicates a collision occurred beyond the collision window (slot time) in half duplex mode. the frame truncates with a bad crc and the remainder of the frame is discarded. 20 rl collision retry limit. indicates a collision occurs on each of 16 successive attempts to transmit the frame. the frame is discarded without being transmitted and transmission of the next frame commences. this error can only occur in half duplex mode. 19 un transmit fifo underrun. indicates the transmit fifo became empty before the complete frame was transmitted. a bad crc is appended to the frame fragment and the remainder of the frame is discarded. 18?0 reserved, must be cleared. 0x1002_b008 (eimr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r hb err babr babt gra txf txb rxf rxb mii eb err lc rl un 000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 000000000 0 000000 w reset0000000000000000 figure 29-5. eimr register table 29-12. eimr field descriptions field description 31?19 see figure 29-5 and table 29-11 interrupt mask. each bit corresponds to an interrupt source defined by the eir register. the corresponding eimr bit determines whether an interrupt condition can generate an interrupt. at every processor clock, the eir samples the signal generated by the interrupting source. the corresponding eir bit reflects the state of the interrupt signal even if the corresponding eimr bit is set. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 18?0 reserved, must be cleared. table 29-11. eir field descriptions (continued) field description fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-24 freescale semiconductor whenever the register is written, the rdar bit is set. this is independent of the data actually written by the user. when set, the fec will poll the receive descriptor ring and process receive frames (provided ecr[ether_en] is also set). once the fec polls a re ceive descriptor whose empty bit is not set, then the fec will clear the rdar bit and cease receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have be en placed into the receive descriptor ring. the rdar is cleared at reset and when ecr[ether_en] is cleared. 29.6.4.4 transmit descriptor active register (tdar) the tdar is a command register which should be wr itten by the user to indicate that the transmit descriptor ring has been updated (tra nsmit buffers have been produced by th e driver with the ready bit set in the buffer descriptor). whenever the register is written, the tdar bit is set. th is value is independent of the data actually written by the user. when set, the fec will poll the transmit descriptor ring and process transmit frames (provided ecr[ether_en] is also set). once the fec polls a transmit descriptor whose ready bit is not set, then the fec will clear the tdar bit and cease transmit desc riptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring. the tdar is cleared at reset, when ecr[ethe r_en] is cleared, or when ecr[reset] is set. 0x1002_b010 (rdar) access: user read/write 31302928272625 24 23222120191817161514131211109876543210 r0000000 rdar 00000 0 0 0000000000 0000000 w reset0000000 0 000000000000000000000000 figure 29-6. rdar register table 29-13. rdar field descriptions field description 31?25 reserved, must be cleared. 24 rdar set to 1 when this register is written, regardless of the value written. cleared by the fec device when no additional empty descriptors remain in the receive ring. also cleared when ecr[ether_en] is cleared. 23?0 reserved, must be cleared. 0x1002_b014 (tdar) access: user read/write 31302928272625 24 23222120191817161514131211109876543210 r0000000 tdar 00000 0 0 0000000000 0000000 w reset0000000 0 000000000000000000000000 figure 29-7. tdar register fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-25 29.6.4.5 ethernet control register (ecr) ecr is a read/write user register, though both fields in this register may be altered by hardware as well. the ecr is used to enable/disable the fec. 29.6.4.6 mii management frame register (mmfr) the mmfr is accessed by the user and does not rese t to a defined value. the mmfr is used to communicate with the attached mii compatible phy device(s), providing read/write access to their mii registers. performing a write to the mmfr will cause a management frame to be sourced unless the mscr has been programmed to 0. in the case of writing to mmfr when mscr = 0, if the mscr is then written to a non-zero value, an mii frame will be generated with the data previously written to the mmfr. this allows mmfr and mscr to be programmed in either order if mscr is currently zero. table 29-14. tdar field descriptions field description 31?25 reserved, must be cleared. 24 tdar set to 1 when this register is written, regardless of the value written. cleared by the fec device when no additional ready descriptors remain in the transmit ring. also cleared when ecr[ether_en] is cleared. 23?0 reserved, must be cleared. 0x1002_b024 (ecr) access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r1111000000000 0 0 0000000000 00000 ether _en reset w reset111100000000000000000000000000 0 0 figure 29-8. ecr register table 29-15. ecr field descriptions field description 31?2 reserved, must be cleared. 1 ether_en when this bit is set, fec is enabled, and reception and transmission are possible. when this bit is cleared, reception immediately stops and transmission stops after a bad crc is appended to any currently transmitted frame. the buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. when ether_en is cleared, the dma, buffer descriptor, and fifo control logic are reset, including the buffer descriptor and fifo pointers. hardware alters the ether_en bit under the following conditions: ecr[reset] is set by software, in which case ether_en is cleared an error condition causes the eir[eberr] bit to set, in which case ether_en is cleared 0 reset when this bit is set, the equivalent of a hardware reset is performed but it is local to the fec. ether_en is cleared and all other fec registers take their reset values. also, any transmission/reception currently in progress is abruptly aborted. this bit is automatically cleared by hardware during the reset sequence. the reset sequence takes approximately 8 internal bus clock cycles after reset is set. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-26 freescale semiconductor to perform a read or write operation on the mii mana gement interface, the mmfr must be written by the user. to generate a valid read or write management frame, the st field must be written with a 01 pattern, and the ta field must be written with a 10. if other patterns are written to these fields, a frame will be generated but will not comply with the ieee 802.3 mii definition. to generate an ieee 802.3-compliant mii management interface write frame (write to a phy register), the user must write {01 01 phyad regad 10 data} to the mmfr. writing this pattern will cause the control logic to shift out the data in the mmfr following a preamble genera ted by the control state machine. during this time the contents of the mmfr will be altered as the contents are serially shifted and will be unpredictable if read by the user. once the write management frame operation has completed, the mii interrupt will be generated. at this time the contents of the mmfr will match the original value written. to generate an mii management interface read fr ame (read a phy register) the user must write {01 10 phyad regad 10 xxxx} to the mmfr (the content of the data field is a don?t care). writing this pattern will cause the control logic to shift out the data in the mmfr following a preamble generated by the control state machine. during this time the contents of the mmfr will be altered as the contents are serially shifted, and will be unpredictable if read by the user. once the read management frame operation has completed, the mii interrupt will be generated. at this time the contents of the mmfr will match the 0x1002_b040 (mmfr) access: user read/write 313029282726252423222120191817161514131211109876543210 r st op pa ra ta data w reset???????????????????????????????? figure 29-9. mmfr register table 29-16. mmfr field descriptions field description 31?30 st start of frame delimiter. these bits must be programmed to 0b01 for a valid mii management frame. 29?28 op operation code. 00 write frame operation, but not mii compliant. 01 write frame operation for a valid mii management frame. 10 read frame operation for a valid mii management frame. 11 read frame operation, but not mii compliant. 27?23 pa phy address. this field specifies one of up to 32 attached phy devices. 22?18 ra register address. this field specifies one of up to 32 registers within the specified phy device. 17?16 ta turn around. this field must be programmed to 10 to generate a valid mii management frame. 15?0 data management frame data. this is the field for data to be written to or read from the phy register. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-27 original value written except for the data field whose contents have been replaced by the value read from the phy register. if the mmfr is written while frame generation is in pr ogress, the frame contents will be altered. software should use the mii interrupt to avoid writing to the mmfr while frame generation is in progress. 29.6.4.7 mii speed control register (mscr) the mscr provides control of the mii clock (fec_mdc pin) frequency, and allows a preamble drop on the mii management frame. the mii_speed field must be programmed with a valu e to provide an fec_mdc frequency of less than or equal to 2.5 mhz to be compliant with the i eee 802.3 mii specification. the mii_speed must be set to a non-zero value in order to source a read or wr ite management frame. after the management frame is complete the mscr may optionally be set to zero to turn off the fec_mdc. the fec_mdc generated will have a 50% duty cycle except when mii_speed is changed during operation (change will take effect following either a rising or falling edge of fec_mdc). if the internal bus clock is 25 mhz, programming this register to 0x0000_0005 results in an fec_mdc as stated the equation below. eqn. 29-1 a table showing optimum values for mii_speed as a f unction of internal bus clock frequency is provided below. 0x1002_b044 (mscr) access: user read/write 3130292827262524232221201918171615141312111098 7 6543210 r0000000000000 0 0 000000000 dis_ pre mii_speed 0 w reset000000000000000000000000 0 0000000 figure 29-10. mscr register table 29-17. mscr field descriptions field description 31?8 reserved, must be cleared. 7 dis_pre asserting this bit causes preamble (32 1?s) not to be prepended to the mii management frame. the mii standard allows the preamble to be dropped if the attached phy device(s) does not require it. 6?1 mii_speed mii_speed controls the frequency of the mii management interface clock (fec_mdc) relative to the internal bus clock. a value of 0 in this field turns off the fec_mdc and leaves it in low voltage state. any non-zero value results in the fec_mdc frequency of 1/(mii_speed 2) of the internal bus frequency. 0 reserved, must be cleared. 2 5 mhz 1 52 ------------ 2.5 mhz = fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-28 freescale semiconductor 29.6.4.8 mib control register (mibc) the mib control register is a read/write register used to provide control of and to observe the state of the mib block. this register is accessed by user software if there is a need to disable the mib block operation. for example, in order to clear all mib counters in ram the user should disable the mib block, then clear all the mib ram locations, then enable the mib block. the mib_disable bit is reset to 1. see table 29-10 for the locations of the mib counters. table 29-18. programming examples for mscr system clock frequency mii_speed (field in reg) fec_mdc frequency 25 mhz 0x5 2.5 mhz 33 mhz 0x7 2.36 mhz 40 mhz 0x8 2.5 mhz 50 mhz 0xa 2.5 mhz 66 mhz 0xd 2.54 mhz 0x1002_b064 (mibc) access: user read/write 31 30 29282726252423222120191817161514131211109876543210 r mib_ dis mib_ idle 00000000000 0 0 0000000000 0000000 w reset 1 1 000000000000000000000000000000 figure 29-11. mibc register table 29-19. mibc field descriptions field description 31 mib_dis a read/write control bit. if set, the mib logic halts and not update any mib counters. 30 mib_idle a read-only status bit. if set the mib block is not currently updating any mib counters. 29?0 reserved. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-29 29.6.4.9 receive control register (rcr) the rcr is programmed by the user. the rcr contro ls the operational mode of the receive block and should be written only when ecr[ether_en] = 0 (initialization time). 0x1002_b084 (rcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 00000 max_fl w reset00000101 1110 1 110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0000000 0 0 0 fce bc_ rej prom mii_ mode drt loop w reset00000000 0000 0 001 figure 29-12. rcr register table 29-20. rcr field descriptions field description 31?27 reserved, must be cleared. 26?16 max_fl maximum frame length. resets to decimal 1518. length is measured starting at da and includes the crc at the end of the frame. transmit frames longer than max_fl causes the babt interrupt to occur. receive frames longer than max_fl causes the babr interrupt to occur and sets the lg bit in the end of frame receive buffer descriptor. the recommended default value to be programmed by the user is 1518 or 1522 (if vlan tags are supported). 15?6 reserved, must be cleared. 5 fce flow control enable. if asserted, the receiver detects pause frames. upon pause frame detection, the transmitter will stop transmitting data frames for a given duration. 4 bc_rej broadcast frame reject. if asserted, frames with da (destination address) equals ff_ff_ff_ff_ff_ff are rejected unless the prom bit is set. if both bc_rej and prom equals 1, frames with broadcast da are accepted and the m (miss) is set in the receive buffer descriptor. 3 prom promiscuous mode. all frames are accepted regardless of address matching. 2 mii_mode media independent interface mode. selects the external interface mode for both transmit and receive blocks. 0 7-wire mode (used only for serial 10 mbps) 1 mii mode 1 drt disable receive on transmit. 0 receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 disable reception of frames while transmitting (normally used for half duplex mode). 0 loop internal loopback. if set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. the internal bus clock substitutes for the fec_txclk when loop is asserted. drt must be set to 0 when setting loop. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-30 freescale semiconductor 29.6.4.10 transmit control register (tcr) this register is read/write and is written by the user to configure the transmit block. this register is cleared at system reset. bits 2 and 1 should be modified only when ecr[ether_en] = 0. 29.6.4.11 physical address low register (palr) the palr is written by the user. this register cont ains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recogn ition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting pause frames. th is register is not reset and must be initialized by the user. 0x1002_b0c4 (tcr) access: user read/write 3130292827262524232221201918171615141312111098765 4 3 2 1 0 r 0000000000000 0 0 0000000000 00 rfc_ pau s e tfc_ pau s e fden hbc gts w reset000000000000000000000000000 0 0 0 0 0 figure 29-13. tcr register table 29-21. tcr field descriptions field description 31?5 reserved, must be cleared. 4 rfc_pause receive frame control pause. this read-only status bit is asserted when a full duplex flow control pause frame is received and the transmitter pauses for the duration defined in this pause frame. this bit automatically clears when the pause duration is complete. 3 tfc_pause transmit frame control pause. transmits a pause frame when asserted. when this bit is set, the mac stops transmission of data frames after the current transmission is complete. at this time, gra interrupt in the eir register is asserted. with transmission of data frames stopped, mac transmits a mac control pause frame. next, the mac clears the tfc_pause bit and resumes transmitting data frames. if the transmitter pauses due to user assertion of gts or reception of a pause frame, the mac may continue transmitting a mac control pause frame. 2 fden full duplex enable. if set, frames transmit independent of carrier sense and collision inputs. this bit should only be modified when ether_en is cleared. 1 hbc heartbeat control. if set, the heartbeat check performs following end of transmission and the hb bit in the status register is set if the collision input does not assert within the heartbeat window. this bit should only be modified when ether_en is cleared. 0 gts graceful transmit stop. when this bit is set, mac stops transmission after any frame currently transmitted is complete and gra interrupt in the eir register is asserted. if frame transmission is not currently underway, the gra interrupt will be asserted immediately. once transmission has completed, a restart can accomplish by clearing the gts bit. the next frame in the transmit fifo is then transmitted. if an early collision occurs during transmission when gts equals 1, transmission stops after the collision. the frame is transmitted again once gts is cleared. there may be old frames in the transmit fifo that transmit when gts is reasserted. to avoid this, clear ecr[ether_en] following the gra interrupt. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-31 29.6.4.12 physical address high register (paur) the paur is written by the user. this register cont ains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recogn ition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 4 and 5 of the 6-byte source address field when transmitting pause frames. bits 15:0 of paur contain a constant type field (0x8808) used for transmission of pause frames . this register is not reset and bits 31:16 must be initialized by the user. 29.6.4.13 opcode/pause duration register (opd) the opd register is read/write accessible. this register contains the 16-bit opcode, and 16-bit pause duration fields used in transmission of a pause fr ame. the opcode field is a constant value, 0x0001. when another node detects a pause frame, that node will pause transmission for the duration specified in the pause duration field. this register is not reset and must be initialized by the user. 0x1002_b0e4 (palr) access: user read/write 313029282726252423222120191817161514131211109876543210 r paddr1 w reset???????????????????????????????? figure 29-14. palr register table 29-22. palr field descriptions field description 31?0 paddr1 bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match and the source address field in pause frames. 0x1002_b0e8 (paur) access: user read/write 313029282726252423222120191817161514131211109876543210 r paddr2 type w reset???????????????? 1000100000001000 figure 29-15. paur register table 29-23. paur field descriptions field description 31?16 paddr2 bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in pause frames. 15?0 type type field in pause frames. these 16-bits are a constant value of 0x8808. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-32 freescale semiconductor 29.6.4.14 descriptor individual upper address register (iaur) the iaur is written by the user. this register contai ns the upper 32 bits of the 64-bit individual address hash table used in the address rec ognition process to check for possible match with the da field of receive frames with an individual da. this register is not reset and must be initialized by the user. 29.6.4.15 descriptor individual lower address register (ialr) the ialr is written by the user. this register contains the lower 32 bits of the 64-bit individual address hash table used in the address rec ognition process to check for possible match with the da field of receive frames with an individual da. this register is not reset and must be initialized by the user. 0x1002_b0ec (opd) access: user read/write 313029282726252423222120191817161514131211109876543210 ropcode pause_dur w reset0000000000000001? ??????????????? figure 29-16. opd register table 29-24. opd field descriptions field description 31?16 opcode opcode field used in pause frames. these bits are a constant, 0x0001. 15?0 pause_dur pause duration field used in pause frames. 0x1002_b118 (iaur) access: user read/write 313029282726252423222120191817161514131211109876543210 r iaddr1 w reset???????????????????????????????? figure 29-17. iaur register table 29-25. iaur field descriptions field description 31?0 iaddr1 the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. bit 31 of iaddr1 contains hash index bit 63. bit 0 of iaddr1 contains hash index bit 32. 0x1002_b11c (ialr) access: user read/write 313029282726252423222120191817161514131211109876543210 r iaddr2 w reset???????????????????????????????? figure 29-18. ialr register fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-33 29.6.4.16 descriptor group upper address register (gaur) the gaur is written by the user. this register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames wi th a multicast address. th is register must be initialized by the user. 29.6.4.17 descriptor group lower address register (galr) the galr is written by the user. this register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames wi th a multicast address. th is register must be initialized by the user. table 29-26. ialr field descriptions field description 31?0 iaddr2 the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. bit 31 of iaddr2 contains hash index bit 31. bit 0 of iaddr2 contains hash index bit 0. 0x1002_b120 (gaur) access: user read/write 313029282726252423222120191817161514131211109876543210 r gaddr1 w reset???????????????????????????????? figure 29-19. gaur register table 29-27. gaur field descriptions field description 31?0 gaddr1 the gaddr1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr1 contains hash index bit 63. bit 0 of gaddr1 contains hash index bit 32. 0x1002_b124 (galr) access: user read/write 313029282726252423222120191817161514131211109876543210 r gaddr2 w reset???????????????????????????????? figure 29-20. galr register table 29-28. galr field descriptions field description 31?0 gaddr2 the gaddr2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr2 contains hash index bit 31. bit 0 of gaddr2 contains hash index bit 0. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-34 freescale semiconductor 29.6.4.18 transmit fifo watermark register (tfwr) the tfwr is a 2-bit read/write register programmed by the user to control the amount of data required in the transmit fifo before transmission of a frame can begin. this allows the user to minimize transmit latency (tfwr = 0x) or allow for larger bus access la tency (tfwr = 11) due to contention for the system bus. setting the watermark to a high value will min imize the risk of transmit fifo underrun due to contention for the system bus. the byte counts associat ed with the tfwr field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data dma channel). 29.6.4.19 fifo receive bound register (frbr) the frbr is an 8-bit register that the user can read to determine the upper address bound of the fifo ram. drivers can use this value, along with the frsr to appropriately divide the available fifo ram between the transmit and receive data paths. 0x1002_b144 (tfwr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000000 0 0 0000000000 00000 tfwr w reset000000000000000000000000000000 0 0 figure 29-21. tfwr register table 29-29. tfwr field descriptions field description 31?2 reserved, must be cleared. 1?0 tfwr number of bytes written to transmit fifo before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written 0x1002_b14c (frbr) access: user read-only 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 0000001 r_bound 0 0 w reset000000000000000000000110000000 0 0 figure 29-22. frbr register table 29-30. frbr field descriptions field description 31?10 reserved, read as 0 (except bit 10, which is read as 1). 9?2 r_bound read-only. highest valid fifo ram address. 1?0 reserved, read as 0. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-35 29.6.4.20 fifo receive start register (frsr) the frsr is an 8-bit register programmed by the user to indicate the starting address of the receive fifo. frsr marks the boundary between the transmit and rece ive fifos. the transmit fifo uses addresses from the start of the fifo to the location four bytes before the address programmed into the frsr. the receive fifo uses addresses from frsr to frbr inclusive. the frsr is initialized by hardware at reset. frsr only needs to be written to change the default value. 29.6.4.21 receive buffer descriptor ring start register (erdsr) the erdsr is written by the user. it provides a pointer to the start of the circular receive buffer descriptor queue in external memory. this pointer must be 32- bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). this register is not reset and must be initialized by the user prior to operation. 0x1002_b150 (frsr) access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 0000001 r_fstart 00 w reset000000000000000000000101000000 0 0 figure 29-23. frsr register table 29-31. frsr field descriptions field description 31?11 reserved, must be cleared. 10 reserved, must be set. 9?2 r_fstart address of first receive fifo location. acts as delimiter between receive and transmit fifos. for proper operation, ensure that r_fstart is set to 0x48 or greater. 1?0 reserved, must be cleared. 0x1002_b180 (erdsr) access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r r_des_start 00 w reset?????????????????????????????? ? ? figure 29-24. erdsr register table 29-32. erdsr field descriptions field description 31?2 r_des_start pointer to start of receive buffer descriptor queue. 1?0 reserved, must be cleared. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-36 freescale semiconductor 29.6.4.22 transmit buffer descriptor ring start register (etdsr) the etdsr is written by the user. it provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. this pointer must be 32- bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). bits 1 and 0 should be written to 0 by the user. non-zero values in these two bit positions are ignored by the hardware. this register is not reset and must be initialized by the user prior to operation. 29.6.4.23 receive buffer size register (emrbr) the emrbr is a 9-bit register programmed by the us er. the emrbr dictates the maximum size of all receive buffers. note that because receive frames wi ll be truncated at 2k-1 bytes, only bits 10?4 are used. this value should take into consideration that the rece ive crc is always written into the last receive buffer. to allow one maximum size frame per buffer, em rbr must be set to rcr[max_fl] or larger. the emrbr must be evenly divisible by 16. to insure this, bits 3-0 are forced low. to minimize bus utilization (descriptor fetches) it is recommended that em rbr be greater than or equal to 256 bytes. the emrbr does not reset, and must be initialized by the user. 0x1002_b184 (etdsr) access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r x_des_start 00 w reset?????????????????????????????? ? ? figure 29-25. transmit buffer descriptor ring start register (etdsr) field description 31?2 x_des_start pointer to start of transmit buffer descriptor queue. 1?0 reserved, must be cleared. 0x1002_b188 (emrbr) access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 000000 r_buf_size 00 0 0 w reset?????????????????????????????? ? ? figure 29-26. emrbr register fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-37 29.6.5 buffer descriptors this section provides a description of the operation of the driver/dma via the buffer descriptors. it is followed by a detailed description of the receive and transmit descriptor fields. 29.6.5.1 driver/dma operation with buffer descriptors the data for the fec frames must reside in memory exte rnal to the fec. the data for a frame is placed in one or more buffers. associated with each buffer is a buffer descriptor (bd) which contains a starting address (pointer), data length, and status/control info rmation (which contains the current state for the buffer). to permit maximum user flexibility, the bds ar e also located in external memory and are read in by the fec dma engine. software ?produces? buffers by allocating/initializing me mory and initializing buffer descriptors. setting the rxbd[e] or txbd[r] bit ?produces? the buffer. so ftware writing to either the tdar or rdar tells the fec that a buffer has been placed in external memory for the transmit or receive data traffic, respectively. the hardware reads the bds and ?consumes ? the buffers after they have been produced. after the data dma is complete and the buffer descriptor st atus bits have been written by the dma engine, the rxbd[e] or txbd[r] bit will be cleared by hardware to signal the buffer has been ?consumed.? software may poll the bds to detect when the buffers have been consumed or may rely on the buffer/frame interrupts. these buffers may then be processed by the driver and returned to the free list. the ecr[ether_en] signal operates as a reset to the bd/dma logic. when ecr[ether_en] is deasserted the dma engine bd pointers are reset to point to the starting transmit and receive bds. the buffer descriptors are not initialized by hardware during reset. at least one transmit and receive buffer descriptor must be initialized by softwa re before the ecr[ether_en] bit is set. the buffer descriptors operate as tw o separate rings. erdsr defines th e starting address for receive bds and etdsr defines the starting address for transmit bds. the last buffer descriptor in each ring is defined by the wrap (w) bit. when set, w indicates that the next descriptor in the ring is at the location pointed to by erdsr and etdsr for the receive and transmit rings, respectively. note buffer descriptor rings must start on a 128-bit boundary. table 29-33. emrbr field descriptions field description 31?11 reserved, must be cleared. 10?4 r_buf_size receive buffer size in bytes. 0x00 0 bytes 0x01 16 bytes 0x02 32 bytes ... 0x7f 2032 bytes 3?0 reserved, must be cleared. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-38 freescale semiconductor 29.6.5.1.1 driver/dma operation with transmit bds typically a transmit frame will be divided between multiple buffers. an example is to have an application payload in one buffer, tcp header in a 2nd buffer, ip header in a 3rd buffer, ethernet/ieee 802.3 header in a 4th buffer. the ethernet mac does not prepend the ethernet header (destination address, source address, length/type field(s)), so this must be pr ovided by the driver in one of the transmit buffers. the ethernet mac can append the ethernet crc to the fr ame. whether the crc is appended by the mac or by the driver is determined by the tc bit in the transmit bd which must be set by the driver. the driver (txbd software producer) should set up tx bds in such a way that a complete transmit frame is given to the hardware at once. if a transmit frame c onsists of three buffers, the bds should be initialized with pointer, length and control (w, l, tc, abc) and then the txbd[r] bits should be set = 1 in reverse order (3rd, 2nd, 1st bd) to insure that the complete fr ame is ready in memory before the dma begins. if the txbds are set up in order, the dma controller could dma the first bd before the 2nd was made available, potentially caus ing a transmit fifo underrun. in the fec, the dma is notified by the driver that new transmit frame(s) are available by writing to the tdar register. when this register is written to (dat a value is not significant) the fec risc will tell the dma to read the next transmit bd in the ring. once started, the risc + dma will continue to read and interpret transmit bds in order and dma the associat ed buffers, until a transmit bd is encountered with the r bit = 0. at this point the fec will poll this bd one more time. if the r bit = 0 the second time, then the risc will stop the transmit descriptor read process until software sets up another transmit frame and writes to tdar. when the dma of each transmit buffer is complete, the dma writes back to the bd to clear the r bit, indicating that the hardware consumer is finished with the buffer. 29.6.5.1.2 driver/dma operation with receive bds unlike transmit, the length of the receive frame is unknown by the driver ahead of time. therefore the driver must set a variable to define the length of all receive buffers. in the fec, this variable is written to the emrbr register. the driver (rxbd software producer) should set up so me number of ?empty? buffers for the ethernet by initializing the address field and the e and w bits of the associated receive bds. the hardware (receive dma) will consume these buffers by filling them with data as frames are received and clearing the e bit and writing to the l (1 indicates last buffer in frame) b it, the frame status bits (i f l = 1) and the length field. if a receive frame spans multiple receive buffers, the l bi t is only set for the last buffer in the frame. for non-last buffers, the length field in the receive bd w ill be written by the dma (at the same time the e bit is cleared) with the default receive buffer length valu e. for end of frame buffers the receive bd will be written with l = 1 and information written to the status bits (m, bc, mc, lg, no, cr, ov, tr). some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. the frame status/length information is written into the receive fifo following the end of the frame (as a single 32-bit word) by the receive logic. the length field for the end of frame buffer will be written with the length of the entire frame, not just the length of the last buffer. for simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame, keeping in mind that a malfunction on the netw ork or out of specificat ion implementation could fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-39 result in giant frames. frames of 2k (2048) bytes or larger are truncated by the fec at 2047 bytes so software is guaranteed never to see a receive frame larger than 2047 bytes. similar to transmit, the fec will poll the receive descriptor ring after the driver sets up receive bds and writes to the rdar register. as frames are received the fec will fill receive buffers and update the associated bds, then read the next bd in the receiv e descriptor ring. if the fec reads a receive bd and finds the e bit = 0, it will poll this bd once more. if the bd = 0 a second time the fec will stop reading receive bds until the driver writes to rdar. 29.6.5.2 ethernet receive buffer descriptor (rxbd) in the rxbd, the user initializes the e and w bits in the first longword and the pointer in second longword. when the buffer has been dma?d, the ethernet controller will modify the e, l, m, bc, mc, lg, no, cr, ov, and tr bits and write the length of the used portion of the buffer in the first longword. the m, bc, mc, lg, no, cr, ov and tr bits in the first longwor d of the buffer descriptor are only modified by the ethernet controller when the l bit is set. 1514131211109876543210 offset + 0 e ro1 w ro2 l ? ? m bc mc lg no ? cr ov tr offset + 2 data length offset + 4 rx data buffer pointer - a[31:16] offset + 6 rx data buffer pointer - a[15:0] figure 29-27. receive buffer descriptor (rxbd) table 29-34. receive buffer descriptor field definitions word field description offset + 0 15 e empty. written by the fec (=0) and user (=1). 0 the data buffer associated with this bd is filled with received data, or data reception has aborted due to an error condition. the status and length fields have been updated as required. 1 the data buffer associated with this bd is empty, or reception is currently in progress. offset + 0 14 ro1 receive software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in erdsr. offset + 0 12 ro2 receive software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 11 l last in frame. written by the fec. 0 the buffer is not the last in a frame. 1 the buffer is the last in a frame. offset + 0 10?9 reserved, must be cleared. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-40 freescale semiconductor note whenever the software driver sets an e bit in one or more receive descriptors, the driver should follow that with a write to rdar. 29.6.5.3 ethernet transmit buffer descriptor (txbd) data is presented to the fec for transmission by arra nging it in buffers referenced by the channel?s txbds. the ethernet controller confirms transmission by clearing the ready bit (r bit) when dma of the buffer is offset + 0 8 m miss. written by the fec. this bit is set by the fec for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. therefore, while in promiscuous mode, the user can use the m-bit to quickly determine whether the frame was destined to this station. this bit is valid only if the l-bit is set and the prom bit is set. 0 the frame was received because of an address recognition hit. 1 the frame was received because of promiscuous mode. offset + 0 7 bc set if the da is broadcast (ff-ff-ff-ff-ff-ff). offset + 0 6 mc set if the da is multicast and not bc. offset + 0 5 lg rx frame length violation. written by the fec. a frame length greater than rcr[max_fl] was recognized. this bit is valid only if the l-bit is set. the receive data is not altered in any way unless the length exceeds 2032 bytes. offset + 0 4 no receive non-octet aligned frame. written by the fec. a frame that contained a number of bits not divisible by 8 was received, and the crc check that occurred at the preceding byte boundary generated an error. this bit is valid only if the l-bit is set. if this bit is set the cr bit will not be set. offset + 0 3 reserved, must be cleared. offset + 0 2 cr receive crc error. written by the fec. this frame contains a crc error and is an integral number of octets in length. this bit is valid only if the l-bit is set. offset + 0 1 ov overrun. written by the fec. a receive fifo overrun occurred during frame reception. if this bit is set, the other status bits, m, lg, no, cr, and cl lose their normal meaning and are zero. this bit is valid only if the l-bit is set. offset + 0 0 tr set if the receive frame is truncated (frame length > 2032 bytes). if the tr bit is set, frame must be discarded and the other error bits must be ignored as they may be incorrect. offset + 2 15?0 data length data length. written by the fec. data length is the number of octets written by the fec into this bd?s data buffer if l equals 0 (the value will be equal to emrbr), or the length of the frame including crc if l equals 1. it is written by the fec once as the bd is closed. 0ffset + 4 15?0 a[31:16] rx data buffer pointer, bits [31:16] 1 offset + 6 15?0 a[15:0] rx data buffer pointer, bits [15:0] 1 the receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. the buffer must reside in memory external to the fec. the ethernet controller never modifies this value. table 29-34. receive buffer descriptor field definitions (continued) word field description fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 29-41 complete. in the txbd the user initializes the r, w, l, and tc bits and the length (in bytes) in the first longword, and the buffer pointer in the second longword. the fec will set the r bit = 0 in the first longword of the bd when the buffer has been dma?d. status bits for the buffer/frame are not included in the transmit buffer descriptors. transmit frame status is indicated via individual interrupt bits (error conditi ons) and in statistic counters in the mib block. see section 29.6.3, ?mib block counters memory map ? for more details. 1514131211109876543210 offset+0rto1wto2ltcabc????????? offset + 2 data length offset + 4 tx data buffer pointer - a[31:16] offset + 6 tx data buffer pointer - a[15:0] figure 29-28. transmit buffer descriptor (txbd) table 29-35. transmit buffer descriptor field definitions word field description offset + 0 15 r ready. written by the fec and the user. 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buffer. the fec clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, prepared for transmission by the user, has not been transmitted or currently transmits. the user may write no fields of this bd once this bit is set. offset + 0 14 to1 transmit software ownership. this field is reserved for software use. this read/write bit will not be modified by hardware, nor will its value affect hardware. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in etdsr. offset + 0 12 to2 transmit software ownership. this field is reserved for use by software. this read/write bit will not be modified by hardware, nor will its value affect hardware. offset + 0 11 l last in frame. written by user. 0 the buffer is not the last in the transmit frame 1 the buffer is the last in the transmit frame offset + 0 10 tc transmit crc. written by user (only valid if l is set). 0 end transmission immediately after the last data byte 1 transmit the crc sequence after the last data byte offset + 0 9 abc append bad crc. written by user (only valid if l is set). 0no effect 1 transmit the crc sequence inverted after the last data byte (regardless of tc value) offset + 0 8?0 reserved, must be cleared. offset + 2 15?0 data length data length, written by user. data length is the number of octets the fec should transmit from this bd?s data buffer. it is never modified by the fec. bits [15:5] are used by the dma engine; bits[4:0] are ignored. fast ethernet controller (fec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 29-42 freescale semiconductor note once the software driver has set up th e buffers for a frame, it should set up the corresponding bds. the last step in setting up the bds for a transmit frame should be to set the r bit in the first bd for the frame. the driver should follow that with a write to td ar which will trigger the fec to poll the next bd in the ring. offset + 4 15?0 a[31:16] tx data buffer pointer, bits [31:16] 1 offset + 6 15?0 a[15:0] tx data buffer pointer, bits [15:0] 1 the transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. the buffer must reside in memory external to the fec. this value is never modified by the ethernet controller. table 29-35. transmit buffer descriptor field definitions (continued) word field description MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-1 chapter 30 high-speed usb on-t he-go (hs usb-otg) the usb module contains all of the functionality required to support three independent usb ports, compatible with the usb 2.0 specification. in additi on to the normal usb functionality, the module also provides support for direct connecti ons to on-board usb peripherals, and supports multiple interface types for serial transceivers. figure 30-1 shows a block diagram of the usb module. figure 30-1. usb block diagram ulpi/ serial mux otg core tmax bypass mux and tll control ulpi/ serial mux host1 core host2 core ulpi data and control serial phy data & control clk dir nxt stp data0/oen data1/txdp data2/txdm data3/rxdp data4/rxdm data5/rcv data6/speed data7/suspend oen txdp txdm rxdp rxdm rcv speed suspend ip2 ahb ip bus ahb usb control register pwr control pwr control pwr control ip bus usb mirror reg tll control clk dir nxt stp data0/oen data1/txdp data2/txdm data3/rxdp data4/rxdm data5/rcv data6/speed data7/suspend high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-2 freescale semiconductor 30.1 overview the usb module provides high performance usb on-the-go (otg) functionality, compliant with the usb 2.0 specification, the otg supplement and the ulpi 1.0 low pin count specification. the module consists of 3 independent usb cores, each controlling 1 usb port. in addition to the usb cores, the module provides for a transceiver-less link (tll) operation on host ports 1 and 2 and allows for routing the otg transceiver interface to host port 1 such that this transceiver can be used to communicate with a usb peripheral connected to host port 1. 30.2 features the usb module includes the following features: ? full speed/low speed host only core (host 1) ? transceiverless link logic (tll) for on board connection to a fs/ls usb peripheral ? bypass mode to route host port 1 signals to otg i/o port ? high speed/full speed/low speed host only core (host2) ? high speed ulpi 1.0 compliant interface ? full speed/low speed interface for serial transceiver ? tll function for direct connection to us b peripheral in fs/ls (serial) operation ? high speed otg core ? high speed ulpi 1.0 compliant interface ? software configurable for ulpi or serial transceiver interface ? high speed (with ulpi transceiver), full speed and low speed operation in host mode ? high speed (with ulpi transceiver), a nd full speed operation in peripheral mode ? hardware support for otg signaling, session reque st protocol and host negotiation protocol ? up to 8 bidirectional endpoints ? low power mode with local and remote wake-up capability ? serial phy interfaces configurable for bidirec tional/unidirectional and di fferential/single ended ? embedded dma controller 30.3 modes of operation the usb module has two main modes of operation; no rmal mode and bypass mode. furthermore, the usb interfaces can be configured for high speed operation (480 mbps) and/or full/low speed operation (12/1.5 mbps). this chapter details th e configuration options. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-3 30.3.1 operational modes 30.3.1.1 normal mode in normal mode, each usb core controls its corresponding port. each port can work in 1 or more modes ? host port 1: this port supports full/low speed and is used serial transceiver only. ? phy mode: in this mode, an external serial transceiver is connected to the port. this is used for off-board usb connections ? tll mode: in tll mode, internal logic is enabled to emulat e the functionality of 2 back-to-back connected transceivers. this mode is typically used for on-board usb connections to usb-capable peripherals ? host port 2 this port supports ulpi and serial transceivers. ? serial interface mode phy mode - for connections using transceivers tll mode - for direct on-board connections to usb peripherals ? ulpi interface ulpi is the low-pin count standard for connecting off-chip high-speed usb transceivers to a usb device. when the port is configured for ul pi mode, only a ulpi compatible transceiver can be used ? otg port: this port requires a transceiver and is intended for off-board usb connections. ? serial interface mode in serial mode, a serial otg transceiver must be connected. the port does not support dedicated signals for otg signaling. instead, a tr ansceiver with built-in otg registers must be used. typically, the transceiver registers are accessible over an i2c or spi interface ? ulpi mode it this mode, a ulpi transceiver is connected to the port pins to support high-speed off board usb connections. ulpi mode is activated by writing the relevant register 30.3.1.2 bypass mode bypass mode affects the operation of the otg port a nd host port 1. this mode is only available when a serial transceiver is used on the otg port, and th e peripheral device on port 1 is using a tll connection. bypass mode is activated by setting the bypass bit in the usbcontrol register. in this mode, the usb otg port connections are internally routed to the us b host 1 port, such that the transceiver on the otg port connects to a peripheral usb device on host port 1. the otg core and the host 1 core are high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-4 freescale semiconductor disconnected from their ports when bypass is active. th e status of the dm and dp inputs for the cores is programmable in the usb control register ( table 30-2 ). 30.3.1.3 low power mode each of the three usb cores has an associated power control module that is controlled by the usb core and clocked on a 32 khz clock. when a usb bus is idle, the transceiver can be placed in low power mode (suspend), after which the clocks to the usb core can be stopped. the 32 khz low power clock must remain active as it is needed for wakeup detection. either the local cpu or the remote usb host/peripheral can initiate a wake-up sequence to resume usb communication. 30.4 external signal description 30.4.1 overview see table 30-3 for the list of signals entering and existing this module to peripherals within the chip. 30.4.2 detailed signal descriptions detailed signal descriptions for each module lists in section 30.6, ?functional description .? 30.5 memory map and register definitions table 30-2 shows the usb module memory map. table 30-2. usb module memory map address controller use access base + 0x000 otg id (uog_id) r base + 0x004 otg hardware general (uog_hwgeneral) r base + 0x008 otg host hardware parameters (uog_hwhost) r base + 0x010 otg tx buffer hardware parameters (uog_hwtxbuf) r base +0x014 otg rx buffer hardware parameters (uog_hwrxbuf) r base +0x080 otg general purpose timer #0 load(gptimer0ld) rw base +0x084 otg general purpose timer #0 controller(gptimer0ctrl) rw base +0x088 otg general purpose timer #1 load(gptimer0ld) rw base +0x08c otg general purpose timer #1 controller(gptimer0ctrl) rw base +0x100 otg capability register length (uog_caplength) r base + 0x102 otg host interface version (uog_hciversion) r base +0x104 otg host control structural parameters (uog_hcsparams) r base +0x108 otg control capability parameters (uog_hccparams) r high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-5 base + 0x120 otg device interface version (uog_dciversion) r base + 0x124 otg device controller capability parameters (uog_dccparams) r base +0x140 otg usb command register (uog_usbcmd) rw base +0x144 otg usb status register (uog_usbsts) rw base +0x148 otg interrupt enable register (uog_usbintr) rw base + 0x14c otg usb frame index (uog_frindex) rw base +0x154 otg host controller frame list base address (uog_periodiclistbase) rw (32-bit only) base +0x158 otg host controller next asynch. address (uog_asynclistaddr) rw (32-bit only) base +0x160 otg host controller embedded tt asynch. buffer status (uog_burstsize) rw (32-bit only) base +0x164 otg tx fifo fill tuning (uog_txfilltuning) rw (32-bit only) base + 0x170 otg ulpi viewport (ulpiview) rw base +0x180 otg config flag (uog_cfgflag) r base +0x184 otg port status and control (uog_portsc1) rw base + 0x1a4 otg on-the-go status and control (uog_otgsc rw base +0x1a8 otg usb device mode (uog_usbmode) rw base + 0x1ac otg endpoint setup status (uog_endptsetupstat) rw base + 0x1b0 otg endpoint initialization (uog_endptprime) rw base + 0x1b4 otg endpoint de-initialize (uog_endptflush) rw base + 0x1b8 otg endpoint status (uog_endptstat) r base + 0x1bc otg endpoint complete (uog_endptcomplete)( rw base + 0x1c0 otg endpoint control0 (endptctrl0) rw base + 0x1c4 otg endpoint control1 (endptctrl1) rw base + 0x1c8 otg endpoint control2 (endptctrl2) rw base + 0x1cc otg endpoint control3 (endptctrl3) rw base + 0x1d0 otg endpoint control4 (endptctrl4) rw base + 0x1d4 otg endpoint control5 (endptctrl5) rw base + 0x1d8 otg endpoint control6 (endptctrl6) rw base + 0x1dc otg endpoint control07(endptctrl7) rw base + 0x200 host1 host 1 id (uh1_id) r base + 0x204 host1 hardware general (uh1_hwgeneral) r base + 0x208 host1 host hardware parameters (uh1_hwhost) r base + 0x210 host1 tx buffer hardware parameters (uh1_hwtxbuf) r base +0x214 host1 rx buffer hardware parameters (uh1_hwrxbuf) r table 30-2. usb module memory map (continued) address controller use access high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-6 freescale semiconductor base +0x280 host1 general purpose timer #0 load(gptimer0ld) rw base +0x284 host1 general purpose timer #0 controller(gptimer0ctrl) rw base +0x288 host1 general purpose timer #1 load(gptimer0ld) rw base +0x28c host1 general purpose timer #1 controller(gptimer0ctrl) rw base +0x300 host1 capability register length (uh1_caplength) r base + 0x302 host1 host interface version (uh1_hciversion) r base +0x304 host1 host control structural parameters (uh1_hcsparams) r base +0x308 host1 control capability parameters (uh1_hccparams) r base +0x340 host1 usb command register (uh1_usbcmd) rw base +0x344 host1 usb status register (uh1_usbsts) rw base +0x348 host1 interrupt enable register (uh1_usbintr) rw base + 0x34c host1 usb frame index (uh1_frindex) rw base +0x354 host1 host controller frame list base address (uh1_periodiclistbase) rw (32-bit only) base +0x358 host1 host controller next asynch. address (uh1_asynclistaddr) rw (32-bit only) base +0x360 host1 host controller embedded tt asynch. buffer status (uh1_burstsize) rw (32-bit only) base +0x364 host1 tx fifo fill tuning (uh1_txfilltuning) rw (32-bit only) base +0x380 host1 reserved r base +0x384 host1 port status and control (uh1_portsc1) rw base +0x3a8 host1 usb device mode (uh1_usbmode) rw base + 0x400 host2 id (uh2_id) r base + 0x404 host2 hardware general (uh2_hwgeneral) r base + 0x408 host2 host hardware parameters (uh2_hwhost) r base + 0x410 host2 tx buffer hardware parameters (uh2_hwtxbuf) r base +0x414 host2 rx buffer hardware parameters (uh2_hwrxbuf) r base +0x480 host2 general purpose timer #0 load(gptimer0ld) rw base +0x484 host2 general purpose timer #0 controller(gptimer0ctrl) rw base +0x488 host2 general purpose timer #1 load(gptimer0ld) rw base +0x48c host2 general purpose timer #1 controller(gptimer0ctrl) rw base +0x500 host2 capability register length (uh2_caplength) r base + 0x502 host2 host interface version (uh2_hciversion) r base +0x504 host2 host control structural parameters (uh2_hcsparams) r base +0x508 host2 control capability parameters (uh2_hccparams) r base +0x540 host2 usb command register (uh2_usbcmd) rw table 30-2. usb module memory map (continued) address controller use access high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-7 30.5.1 register descriptions the following sections describe the regi sters used to control the usb module. 30.5.1.1 usbcontrol?usb control register (usb_ctrl) the usb control register controls the integration speci fic features of the usb module. these features are not directly related to the usb functionality, but control special features, interfacing on the usb ports, as well as power control a nd wake-up functionality. figure 30-2. usb control register base +0x544 host2 usb status register (uh2_usbsts) rw base +0x548 host2 interrupt enable register (uh2_usbintr) rw base + 0x54c host2 usb frame index (uh2_frindex) rw base +0x554 host2 host controller frame list base address (uh2_periodiclistbase) rw (32-bit only) base +0x558 host2 host controller next asynch. address (uh2_asynclistaddr) rw (32-bit only) base +0x560 host2 host controller embedded tt asynch. buffer status (uh2_burstsize) rw (32-bit only) base +0x564 host2 tx fifo fill tuning (uh2_txfilltuning) rw (32-bit only) base + 0x570 host2 ulpi viewport (ulpiview) rw base +0x580 host2 reserved r base +0x584 host2 port status and control (uh2_portsc1) rw base +0x5a8 host2 usb device mode (uh2_usbmode) rw base + 0x600 usb control register (usb_ctrl) rw base + 0x604 usb otg mirror register (usb_otg_mirror) rw base + 0x600 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r owir osic ouie owie obpval opm h2wi r h2sic h2ui e h2wi e 0 0 h2p m w reset: ? p p 0 0 0 0 0 ? p p 0 0 ? ? 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r h1wi r h1sic 0 h1wi e h1bpval h1p m 0 0 h2dt h1dt 0 0 0 bpe w reset: ? p p ? 0 0 0 0 ? ? 0 0 ? 0 0 0 p = preset value taken from preset input signals table 30-2. usb module memory map (continued) address controller use access high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-8 freescale semiconductor table 30-3. usb control register field descriptions field description 31 owir otg wake-up interrupt request. this bit indicates that a wake-up interrupt request is received on the otg port. this bit is cleared by disabling the wake-up interrupt. 0 no wake-up detected 1 wake-up interrupt request received 30?29 osic otg serial interface configuration. controls the interface type of the otg port when used with a serial transceiver. this bit field allows for configuring the serial interface for single ended or differential operation combined with bidirectional or unidirectional operation. the reset value of osic depends on the state of the signals ?__add__? and ?__add__? during reset. 00 differential/unidirectional (6-wire) 01 differential/bidirectional (4-wire) 10 single ended/unidirectional (6-wire) 11 single ended/bidirectional (3-wire) 28 ouie otg ulpi interrupt enable. controls whether or not interrupts from the ulpi transceiver will trigger the wake-up logic. this bit is only meaningful when a ulpi transceiver is selected. 0 ulpi transceiver interrupts are ignored by the wakeup logic. 1 ulpi transceiver interrupts activate the wake-up logic 27 owie otg wake-up interrupt enable. this bit enables or disables the otg wake-up interrupt. disabling the interrupt also clears the interrupt request bit. wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode 0 interrupt disabled 1 interrupt enabled 26?25 obpval otg bypass value. this field contains the status of the rxdp and rxdm inputs to the otg core when bypass mode is enabled. bit 26 controls rxdp, bit 25 controls rxdm. 24 opm otg power mask. the power mask bit controls whether or not the external vbus power and overcurrent detection are active for the otg port. 0 the usbpwr pin will assert with the otg core?s vbus power enable and the assertion of the oc input will be reported to the otg core. 1 the usbpwr and oc pins are not used by the otg core. 23 h2wir host 2 wake-up interrupt request. indicates a pending wake-up request on host port 2. this bit is cleared by disabling the interrupt. the interrupt must be disabled for at least 2 clock cycles of the standby clock. 0 no wake-up interrupt received 1 wake-up interrupt received 22?21 h2sic host 2 serial interface configuration. controls the interface type of the host 2 port when used with a serial transceiver. this bit field allows for configuring the serial interface for single ended or differential operation combined with bidirectional or unidirectional operation. 00 differential/unidirectional (6-wire) 01 differential/bidirectional (4-wire) 10 single ended/unidirectional (6-wire) 11 single ended/bidirectional (3-wire) 20 h2uie host 2 ulpi interrupt enable. controls whether or not interrupts from the ulpi transceiver will trigger the wake-up logic. this bit is only meaningful when a ulpi transceiver is selected. 0 ulpi transceiver interrupts are ignored by the wakeup logic. 1 ulpi transceiver interrupts activate the wake-up logic high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-9 19 h2wie host 2 wake-up interrupt enable. this bit enables or disables the host 2 wake-up interrupt. disabling the interrupt also clears the interrupt request bit. wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode. 0 interrupt disabled 1 interrupt enabled 18?17 reserved. these bits are reserved and should read 0. 16 h2pm host 2 power mask. the power mask bit controls whether or not the external vbus power and overcurrent detection are active for the host 2 port. 0 the usbpwr pin will assert with the host 2 core?s vbus power enable and the assertion of the oc input will be reported to the host 2 core. 1 the usbpwr and oc pins are not used by the host 2 core. 15 h1wir host 1 wake-up interrupt request. indicates a pending wake-up request on host port 1. this bit is cleared by disabling the interrupt. the interrupt must be disabled for at least 2 clock cycles of the standby clock. 0 wake-up interrupt received 1 no wake-up interrupt received 14?13 h1sic host 1 serial interface configuration. controls the interface type of the host 1 port when used with a serial transceiver. this bit field allows for configuring the serial interface for single ended or differential operation combined with bidirectional or unidirectional operation. 00 differential/unidirectional (6-wire) 01 differential/bidirectional (4-wire) 10 single ended/unidirectional (6-wire) 11 single ended/bidirectional (3-wire) 12 reserved. this bit is reserved and should read 0. 11 h1wie host 1 wake-up interrupt enable. this bit enables or disables the host 1 wake-up interrupt. disabling the interrupt also clears the interrupt request bit. wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode 0 interrupt disabled 1 interrupt enabled 10?9 h1bpval host 1 bypass value. this field contains the status of the rxdp and rxdm inputs to the host1 core when bypass mode is enabled. bit 10 controls rxdp, bit 9 controls rxdm. 8 h1pm host 1 power mask. the power mask bit controls whether or not the external vbus power and overcurrent detection are active for the host 1 port. 0 the usbpwr pin will assert with the host 1core?s vbus power enable and the assertion of the oc input will be reported to the host 1 core. 1 the usbpwr and oc pins are not used by the host 1 core. 7?6 reserved. these bits are reserved and should read 0. 5 h2dt host 2 tll disable. this bit controls whether or not the transceiver-less link logic is enabled for the serial interface of host port 2. 0 tll is enabled 1 tll is disabled 4 h1dt host 1 tll disable. this bit controls the tll logic for host port 1 0 tll is enabled 1 tll is disabled table 30-3. usb control register field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-10 freescale semiconductor 30.5.1.2 otgmirror ? otg port mirror register the otg port is designed for operation with an external otg transceiver. when a ulpi transceiver is in use, all otg signaling is communicated over the ulpi data bus as described in the ulpi specification. however, when a serial transceiver is used, the inte rface for otg signaling is not standardized. most otg transceivers use a serial interface like i2c or spi to transfer the otg signaling back to the cpu and/or usb core. in this case, the usb core has no dire ct connection the otg signals in the transceiver. the otgmirror register provides a soft interface be tween the otg signals in the transceiver and the otg signal inputs to the usb core. the usb driver so ftware is responsible for reading the otg status registers in the transceiver over the serial interfa ce and set the bits accordingly in the otgmirror register (see figure 30-3 ), such that the usb controller know s the status of the transceiver. the usb driver should be designed such that the latency requirements as defined in the usb 2.0 otg supplement specification are met. figure 30-3. otg mirror register (otgmirror) sesend?b device session end this bit is set by the usb driver when the phy reports a session end condition. 1 = session end (0.2v < vbus < 0.8v) 0 = session active vbusvld?vbus valid the usb driver sets this bit when the transceiver reports vbus valid. 1 = vbus is valid (vbus > 4.4v) 0 = vbus invalid (vbus < 4.4v) bsesvld?b session valid b session valid should be set when the transceiver reports b-session valid. 1 = b session is valid (0.8v < vbus < 4.0v) 0 = b session is not valid (vbus < 0.8v) 3?1 reserved. these bits are reserved and should read 0. 0 bpe bypass enable. this bit enables/disables the usb bypass function. 0 bypass inactive?normal mode operation. 1 bypass active?usb signals from host port 1 are routed to the otg port. base + 0x604 7 6 5 4 3 2 1 0 r 0 0 0 sesend vbusval bsesvld asesvld iddig w reset: ? ? ? 0 0 0 0 0 = unimplemented or reserved table 30-3. usb control register field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-11 asesvld?a session valid this bit must be set when a valid ?a -session? level is detected on vbus. 1 = a session is valid (0.8v < vbus < 2.0v) 0 = session is not valid for a-device. ididg?otg id-pin status this bit indicates to the usb core whether it should operate as a-device or as b-device 1 = id pin is high?operate as b-device 0 = id pin is low?operate as a-device 30.5.1.3 usb core register for detailed registers description of otg controller, host 1 controller, and host 2 controller, refer to section 30.5.1, ?register descriptions .? the value of registers that depended on implementation can be found based on the core configuration para meter file (otg controller refer to section 30.6.3, ?usb otg controller ,? section 30.6.1, ?usb host controller 1 ,? and section 30.6.2, ?usb host controller 2 .? 30.6 functional description this sections describes the functionality and the t opology of the different building blocks of the usb module. 30.6.1 usb host controller 1 30.6.1.1 host controller 1 to host port 1 interface the host 1 core usb signals do not connect directly to the host1 i/o pins. instead, the signals pass through the bypass mux to allow for additiona l functionality on host port1. see section section 30.6.6, ?usb bypass mode ? for details. in addition to bypass muxing, this mux also provides interface type conversion for host core 1. this type conversion is independent of the mux state. table 30-3 details the available type settings. depending on the selected interface type, the usb port si gnals have the functionality as described in table table 30-4 . table 30-4. host port 1 pin functions single-ended mode differential mode signal unidir bidir unidir bidir oen oen oen = 0 oen = 1 oen oen = 0 oen = 1 txdp dat txdp txdm se0 txdm rxdp rxdp dato dati rxdp txdp rxdp high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-12 freescale semiconductor note if the rcv signal is not available on the external part (for example, when using a direct connection with tll mode), the rcv input must be tied to the rxvp input. 30.6.2 usb host controller 2 host controller 2 is configured for operation with a fs /ls serial transceiver or a parallel ulpi transceiver (hs/fs/ls). the selection between tr ansceiver type is software programmable. the module defaults to serial mode. 30.6.2.1 host port 2 signal connections and signal muxing table 30-5 details the i/o pad connections for the usb host port 2. the direction control is logic ?1? for output. host port 2 can support either a ulpi transceiver or a serial transceiver. depending on the selected type, signaling for one or the other is available at the top level. table 30-6 gives the relation between the top level signal and the usb core signal in both modes. rxdm rxdm se0o se0i rxdm txdm rxdm rcv rcv ? ? rcv ? rcv table 30-5. host port 2 signal connections i/o pad type input output direction control usb2_ulpi_clk i/o ipp_ind_uh2_clk usb2_ulpi_dir in ipp_ind_uh2_dir usb2_ulpi_stp out ipp_do_uh2_stp usb2_ulpi_nxt in ipp_ind_uh2_nxt usb2_ulpi_data0 i/o ipp_ind_uh2_data0 ipp_do_uh2_data0 ipp_obe_uh2_data0 usb2_ulpi_data1 i/o ipp_ind_uh2_data1 ipp_do_uh2_data1 ipp_obe_uh2_data1 usb2_ulpi_data2 i/o ipp_ind_uh2_data2 ipp_do_uh2_data2 ipp_obe_uh2_data2 usb2_ulpi_data3 i/o ipp_ind_uh2_data3 ipp_do_uh2_data3 ipp_obe_uh2_data3 usb2_ulpi_data4 i/o ipp_ind_uh2_data4 ipp_do_uh2_data4 ipp_obe_uh2_data4 usb2_ulpi_data5 i/o ipp_ind_uh2_data5 ipp_do_uh2_data5 ipp_obe_uh2_data5 usb2_ulpi_data6 i/o ipp_ind_uh2_data6 ipp_do_uh2_data6 ipp_obe_uh2_data6 usb2_ulpi_data7 i/o ipp_ind_uh2_data7 ipp_do_uh2_data7 ipp_obe_uh2_data7 table 30-4. host port 1 pin functions (continued) single-ended mode differential mode signal unidir bidir unidir bidir high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-13 30.6.3 usb otg controller the otg controller offers hs/fs/ls capabilities in host mode and hs/fs in device mode. table 30-6. ulpi/ serial muxing usb top input signals usb top output signals from i/o mux serial mode ulpi mode to i/o mux serial mode ulpi mode ipp_ind_uh2_data 0 ipp_ind_uh2_oe_n uuh2_data_in [0] ipp_do_uh2_dat a0 ipp_do_uh2_oe_n uuh2_data_out [0] ipp_ind_uh2_data 1 uuh2_data_in [1] ipp_do_uh2_dat a1 ipp_do_uh2_txdp_dat uuh2_data_out [1] ipp_ind_uh2_data 2 uuh2_data_in [2] ipp_do_uh2_dat a2 ipp_do_uh2_txdm_se0 uuh2_data_out [2] ipp_ind_uh2_data 3 ipp_ind_uh2_rxvp_txdp_dat uuh2_data_in [3] ipp_do_uh2_dat a3 ipp_do_uh2_rxvp_txdp_d at uuh2_data_out [3] ipp_ind_uh2_data 4 ipp_ind_uh2_rxvm_txdm_se0 uuh2_data_in [4] ipp_do_uh2_dat a4 ipp_do_uh2_rxvm_txdm_ se0 uuh2_data_out [4] ipp_ind_uh2_data 5 ipp_ind_uh2_xcvr_ser_rcv uuh2_data_in [5] ipp_do_uh2_dat a5 ipp_do_uh2_xcvr_ser_rcv uuh2_data_out [5] ipp_ind_uh2_data 6 uuh2_data_in [6] ipp_do_uh2_dat a6 ipp_do_uh2_speed uuh2_data_out [6] ipp_ind_uh2_data 7 uuh2_data_in [7] ipp_do_uh2_dat a7 ipp_do_uh2_suspend uuh2_data_out [7] usb port 2 direction control ipp_obe_uh2_d ata0 ipp_obe_uh2_oe_n uuh2_data_out _enable ipp_obe_uh2_d ata1 1'b0 uuh2_data_out _enable ipp_obe_uh2_d ata2 1'b0 uuh2_data_out _enable ipp_obe_uh2_d ata3 ipp_obe_uh2_rxvp_txdp_ dat uuh2_data_out _enable ipp_obe_uh2_d ata4 ipp_obe_uh2_rxvm_txdm _se0 uuh2_data_out _enable ipp_obe_uh2_d ata5 ipp_obe_uh2_xcvr_ser_r cv uuh2_data_out _enable ipp_obe_uh2_d ata6 1'b0 uuh2_data_out _enable ipp_obe_uh2_d ata7 1'b0 uuh2_data_out _enable high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-14 freescale semiconductor 30.6.3.1 host mode the controller supports direct connection of a fs/ls device (without external hub). although there is no separate transaction translator block in the system. the transact ion translator function normally associated with a usb 2.0 high speed hub has been imp lemented within the dma and protocol engine blocks to support connection to full and low speed devices. 30.6.3.2 peripheral (device) mode ? up to 8 bidirectional endpoints ? high/full speed operation ? supports hnp, srp. ? remote wakeup capable 30.6.3.3 special considerations the otg port functions as gateway between the host 1 port and the otg transceiver when in bypass mode. 30.6.3.4 otg port signal connections and signal muxing table 30-7 describes the signal connections from th e usb core to the otg port output pads. table 30-7. signal connections i/o pad type input output direction control usb_ulpi_clk i/o ipp_ind_otg_clk usb_ulpi_dir in ipp_ind_otg_dir usb_ulpi_stp out ipp_do_otg_stp usb_ulpi_nxt in ipp_ind_otg_nxt usb_ulpi_data0 i/o ipp_ind_otg_data0 ipp_do_otg_data0 ipp_obe_otg_data0 usb_ulpi_data1 i/o ipp_ind_otg_data1 ipp_do_otg_data1 ipp_obe_otg_data1 usb_ulpi_data2 i/o ipp_ind_otg_data2 ipp_do_otg_data2 ipp_obe_otg_data2 usb_ulpi_data3 i/o ipp_ind_otg_data3 ipp_do_otg_data3 ipp_obe_otg_data3 usb_ulpi_data4 i/o ipp_ind_otg_data4 ipp_do_otg_data4 ipp_obe_otg_data4 usb_ulpi_data5 i/o ipp_ind_otg_data5 ipp_do_otg_data5 ipp_obe_otg_data5 usb_ulpi_data6 i/o ipp_ind_otg_data6 ipp_do_otg_data6 ipp_obe_otg_data6 usb_ulpi_data7 i/o ipp_ind_otg_data7 ipp_do_otg_data7 ipp_obe_otg_data7 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-15 30.6.4 usb power control module the usb module supports suspend and wakeup functionali ty, but the circuit is considered application specific and therefore not part of the ip. an external ci rcuit has been designed to place external transceivers in suspend mode, and wake them up either on a loca l request (cpu initiated) or on remote request by table 30-8. otg ulpi/serial muxing usb top input signals usb top output signals from i/o mux serial mode ulpi mode to i/o mux serial mode ulpi mode ipp_ind_otg_data 0 uotg_data_in [0] ipp_do_otg_data0 ipp_do_otg_oe_n uotg_data_out [0] ipp_ind_otg_data 1 uotg_data_in [1] ipp_do_otg_data1 ipp_do_otg_txdp_dat uotg_data_out [1] ipp_ind_otg_data 2 uotg_data_in [2] ipp_do_otg_data2 ipp_do_otg_txdm_se0 uotg_data_out [2] ipp_ind_otg_data 3 ipp_ind_otg_xcvr_ser_vp uotg_data_in [3] ipp_do_otg_data3 ipp_do_otg_xcvr_ser_ vp uotg_data_out [3] ipp_ind_otg_data 4 ipp_ind_otg_xcvr_ser_vm uotg_data_in [4] ipp_do_otg_data4 ipp_do_otg_xcvr_ser_ vm uotg_data_out [4] ipp_ind_otg_data 5 ipp_ind_otg_xcvr_ser_rcv uotg_data_in [5] ipp_do_otg_data5 uotg_data_out [5] ipp_ind_otg_data 6 uotg_data_in [6] ipp_do_otg_data6 ipp_do_otg_speed uotg_data_out [6] ipp_ind_otg_data 7 uotg_data_in [7] ipp_do_otg_data7 ipp_do_otg_suspend uotg_data_out [7] otg port direction control ipp_obe_otg_data0 1?b1 uotg_data_out _enable ipp_obe_otg_data1 1'b0 uotg_data_out _enable ipp_obe_otg_data2 1'b0 uotg_data_out _enable ipp_obe_otg_data3 ipp_obe_otg_xcvr_ser _vp uotg_data_out _enable ipp_obe_otg_data4 ipp_obe_otg_xcvr_ser _vm uotg_data_out _enable ipp_obe_otg_data5 1'b0 uotg_data_out _enable ipp_obe_otg_data6 1'b0 uotg_data_out _enable ipp_obe_otg_data7 1'b0 uotg_data_out _enable high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-16 freescale semiconductor detecting activity on the usb line. the wake-up logic can optionally wake the cpu when it is in sleep mode at the time of the request. the power contro l mechanism is described in the vusb-hs-sph and vusb-hs-otg reference manuals. for details on the power control module, refer to the power module creation guide. 30.6.4.1 entering suspend mode suspend mode is always entered under control of dr iver software by setting the appropriate bit int portsc register. once the controller is suspe nded, the clocks to the usb block can be stopped. 30.6.4.2 wake-up events the power control module monitors the usb bus when the usb core is in the suspend state. depending on whether the core is on host or device mode, a number of wakeup conditions are detected. upon detection of a wakeup condition, an interrupt (asynchronous) is gene rated on the cpu complex. this interrupt will also re-activate the clocks if these were stopped during the suspend. 30.6.4.2.1 host mode events the host controller wakes-up on the following events: remote wakeup request a peripheral can request the host to re-activate th e bus by driving wake-up signaling on the dm/dp lines. the power control module will detect a j-k trans ition on the dm/dp lines and signal the wakeup request to the core. wake on over-current if wake on overcurrent is enabled in the portsc regi sters, the power control module will signal a wakeup condition to the usb core. wake on disconnect the power control module detects disconnect events by monitoring the dp/dm lines. when a disconnect event is detected (dm = dp = 0) and the wake on disc onnect is enabled in the portsc register, the core will be notified. wake on connect similar to the wake on disconnect, the power contro l module detects a connect event (dm or dp high) and signals this to the usb core by setting the pwrc tl_wakeup signal if enabled in the portsc register. 30.6.4.2.2 device mode events when the otg controller is configured for periphe ral operation, the power control module will detected following events: high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-17 detection of bus activity any non-idle condition on the usb bus will activate the wakeup output of the power control module to notify the usb core of the wakeup event. 30.6.5 tll mode the transceiver less link logic circuit allows two mi cro-controllers to use usb for an inter-processor communication link (icl) without using conventiona l usb transceivers. the tll muxes support serial type interfacing only and are available on host port 1 and host port 2. 30.6.5.1 tll functional description the tll logic is a logic representati on of 2 serial transceivers connected by a usb cable. the usb bus dm/dp states are modeled internally in the tll functi on, such that the usb i/o port acts as if it were a transceiver. in a regular usb implementation with serial phy?s, the speed selection on the usb bus is done by means of a pull-up resistor on the peripheral side either on th e dm (low speed) or the dp (full speed) line. this pull-up pulls one of the usb lines high when the bus is idle. this option cannot be modeled in logic as the serial usb interface does not provide for such a signal. the tll mux is therefore configured for full speed only operation. the idle condition of the bus is determined by the oe n signals and suspend signals on both sides of the mux. when both oen signals are high, or when one or both suspend signals are high, the idle condition is assumed. the tll block then drives txdp high and txdm low on both sides of the block. figure 30-4. tll mux functional diagram dm/dp bus state model i/o port interface usb core interface model speed txenb rxdm/se0i rxdm/dati txdm/se0 txdp/dat rcv speed txenb dat se0 rxdm rxdp rcv suspend suspend tll mux external usb peripheral usb host core high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-18 freescale semiconductor 30.6.5.2 host port 1 on host port1, the tll function is inte grated with the bypass function (see section 30.6.6, ?usb bypass mode ?) and the transceiver type conversion logic. tll mode is the default mode for this port. it can be disabled by setting bit 4 in the usbcontrol register. 30.6.5.3 host port 2 the tll module on host port 2 contains the tll logic a nd the serial transceiver type conversion logic. the interface type conversion is available in both tll and non tll modes. tll operation is the default mode. it can be turned of f for operation with an external transceiver by setting bit 5 in the usbcontrol register. the usbcontrol register. table 30-9. port 1 tll and phy mode pin connections tll mode phy mode pin i/o external device pin i/o external phy pin speed i speed o speed txenb i txenb o txenb rxvm i txdm i rxvm rxvp i txdp i rxvp txdm o rxdm o txdm txdp o rxdp o txdp rcv o rcv i rcv suspend i suspend o suspendm table 30-10. port 2 tll and phy mode pin connections tll mode phy mode pin i/o external device pin i/o external phy pin speed i speed o speed txenb i txenb o txenb rxvm i txdm i rxvm rxvp/ i txdp o rxvp txdm o rxdm o txdm txdp o rxdp o txdp rcv o rcv i rcv suspend i suspend o suspendm high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-19 30.6.6 usb bypass mode the usb bypass mode is a special mode that allows for the transceiver on the otg port to be used as transceiver for a usb peripheral device connected to hos t port 1. this mode is only available for full/low speed serial transceivers. the bypass module is combination of: ? the bypass function (host port1 - otg port pass through) ? tll function for host port 1 ? serial transceiver interface conversion 30.6.6.1 bypass mode operation bypass mode is enabled by writing a ?1? to bit 0 (bpe) in figure 30-2 . figure 30-5 shows the usb bypass mux functional diagram. figure 30-5. usb bypass mux functional diagram in bypass mode, the serial interface signals from host po rt 1 are routed to the serial interface pins of the otg port such that an external usb peripheral devi ce can use the otg transceiver to connect to an external usb host. as this function only works with usb peripherals directly connected to host port 1, the port is automatically set for tll mode. transceiver interface type conversion is available in bypass mode such that the interface type of the otg transcei ver can be different from the host 1 interface type. the usb host1 core is disconnected from the port and the inputs rxdp, rcv and rxdm from the core are driven by bits 9 and 10 (h1bpval) in the figure 30-2 .the otg core is also disconnected from its port and inputs rxdp, rcv and rxdm are driven by bits 25 and 26 (obpval) from the figure 30-2 . usb bypass mux host 1 otg to r t o l a on board usb peripheral transceiver normal mode bypass mode high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-20 freescale semiconductor 30.6.6.2 otg and host 1 pin functions table 30-11 list the pin functions of the host 1 port when bypass mode is enabled and the associated otg pin. the pin functions of the otg port are not affected by bypass mode. 30.6.7 ulpi/serial mux both host2 and otg cores can be configured by software for ulpi or serial phy operation. the ulpi/serial mux selects between ulpi interface si gnals and serial phy interface signals. the mux is controlled by the phy select signals from the usb core and is switched when the software selects the interface mode. the default configuration for the mux is serial mode. switching to ulpi mode is done by writing the parallel transceiver select (pts) bits in the portsc register with 0b10. 30.6.8 interrupts 30.6.8.1 usb core interrupts each usb core uses one dedicated vector in the interr upt table. the vector numbers associated with each of the cores can be found in the interrupt section. with the exception of the wake-up interrupts, all of th e interrupt sources are cont rolled in the usb cores. refer to the usb core documentation for details. 30.6.8.2 usb wake-up interrupts each usb core has an associated wake-up interrupt . the wake-up interrupts are generated outside the usb cores? but use the same vector as the corres ponding cores? interrupt. these interrupt are generated by the power control modules which run on the 32khz standby clock.the wake-u p interrupt is designed to work even when the usb and cpu clocks are di sabled, such that a wake-up condition on the usb bus table 30-11. host1 bypass mode pin functions unidirectional bidirectional otg port pin i/o single- ended i/o differential i/o single- ended i/o differential i/o pin rxdm i rxdm i rxdm i/o seoi/se0o i/o rxdm/txdm o txdm rxdp i rxdp i rxdp i/o dati/dato i/o rxdp/txdp o txdp rcv o rcv o rcv ? o rcv i rcv txdm o se0 o txdm ? ? i rxdm txdp o dat o txdp ? ? rxdp oeb i oen i oeb i oen i oen oeb fs i speed i fs i speed i speed speed suspend i suspend i suspend i suspend i suspend suspend high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-21 can re-activate the cpu clocks. therefore, this in terrupt request propagates through combinatorial logic to the cpu?s interrupt module. because the wake-up interrupt is generated and clea red on a 32 khz clock, this interrupt request will respond very slowly to clear actions. for this reason, the software must disable the wake-up interrupt to clear the request flag. disabling the interrupt will mask the request instantaneously as this is clocked by the cpu clock. the software should than wait for at le ast 3 32 khz clock cycles before re-enabling this interrupt to allow sufficient time for the request flag to clear. as this interrupt is only used during low-power modes of the usb, it is sufficient to enable the wake-up interrupt just prior to enter usb suspend mode. 30.7 initialization/app lication information this section described the detaile d application knowledge for host1, host2 and otg ports. it can be generally divided in two parts, one is for host and th e other is for device. host part is applied to three ports, device part is only applied to otg port. in fo llowing register description, device related content is just for otg, and host related content is for all three ports. 30.7.1 software model the device api provides a framework of routin es to control the usb-hs otg high-speed usb on-the-go peripheral in usb device applications. it includes an application to respond to the device framework commands issued by a usb host. the usb-hs otg high-speed usb on-the-go device api is designed to significantly simplify the software tasks required to develop a usb device applic ation. the api presents a high-level data transfer interface to the user?s application code. all the regist er, interrupt and dma interactions with the usb-hs otg high-speed usb on-the-go core are managed by the api. the api also includes routines that handle all the usb device framework commands which are required for all usb devices. the host stack provides a layered software architect ure to control all aspects of a usb bus system. the host controller device (hcd) interface controls the functions of an embedded ehci host controller. the usb driver layer provides all the usb driver functions to enumerat e, manage and schedule a usb bus system, while the upper layers of the stack support st andard usb device class interfaces to the device drives running on your embedded system. for details on the usb-hs otg high-speed usb on-the-go software stack refer the documentation provided with the software products. ? ansi-c otg software stack provides host a nd device application support. usb software included with the usb-hs otg high-speed usb on-t he-go core is tested with the hardware. ? otg application program interface (api) handles otg protocols. connect and disconnect events are handled as well as the otg host negotiati on protocol (hnp) and se ssion request protocol (srp) state machines. the otg code calls th e host or device api functions based on the connection state of the otg state machines. ? host api to speed up host software development. simple api calls allow direct interaction with usb pipes. additional layers support bus enumer ation, bus management and a growing set of supported usb classes. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-22 freescale semiconductor ? device api to speed up peripheral development. us b peripheral characteristics such as endpoints, configurations, interfaces, and alternate settings are controlled by supplied ansi-c firmware. device frame work command set reduces software development time. simple api interface allows quick coding of usb device applications. 30.7.1.1 device data structure the function of the device operation is to transfer a request in the memory image to and from the universal serial bus. using a set of linked list transfer descript ors, pointed to by a queue head, the device controller will perform the data transfers. figure 30-6. end point queue head organization the usb-hs otg high-speed usb on-the-go devi ce api incorporates and abstracts for the application developer all of the informati on contained in the device operational model. 30.7.1.2 host data structure the host data structures are used to communicate cont rol, status, and data between software and the host controller. the periodic frame list is an array of pointers for the periodic schedule. a sliding window on the periodic frame list is used. the asynchronous transf er list is where all the control and bulk transfers are managed. the usb-hs otg high-speed usb on-the -go host api incorporates and abstracts for the application developer all of the inform ation contained in the host operational model. 30.7.2 register interface slave accesses from the controlling processor enables access to the configuration, control, and status registers. one function of the syst em address map is the registers ba se address, which must begin on a dword (32-bit) boundary. register offset definitions are listed in the table below. configuration, control and status regi sters are divided into three categor ies, identification, capability, and operational registers. ? identification registers are used to declare the slave interface presence along with the complete set of the hardware configuration parameters. up to 32 elements endpoint qh 0 ? in endpointlistaddr endpoint qh 1 ? out endpoint transfer descriptor endpoint queue heads transfer buffer pointer transfer buffer transfer buffer transfer buffer transfer buffer transfer buffer pointer transfer buffer pointer transfer buffer pointer endpoint qh 0 ? out high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-23 ? static, read only capability registers define the software limits, restrictions, and capabilities of the host/device controller. ? operational registers are comprise d of dynamic control or status registers that may be read only, read/write, or read/write to clear. the followi ng sections define the use of these registers. ehci registers are listed alongside device registers to show the complementary nature of host and device control. 30.7.2.1 configuration, control and status register set note: host mode ehci compatibility begins at offset 0x100. if it is necessary to begin the ehci register set at offset 0x000, the identification registers are disabled from the address map by connecting the upper most address bit of the slave interface to a logic level ?1? and adjusting the offsets below accordingly. table 30-12. interface register sets offset register set explanation 000h to 0fch identification registers identification registers are used to declare the slave interface presence and include a table of the hardware configuration parameters. 100h to 124h capability registers capability registers specify the limits, restrictions, and capabilities of a host/device controller implementation. these values are used as parameters to the host/device controller driver. 140h to 1fch operational registers operational registers are used by the system software to control and monitor the operational state of the host/device controller. table 30-13. configuration, control, and status register set offset size (bytes) mnemonic register name dev otg sph mph 000h 4 id identification register ??? 004h 4 hwgeneral general hardware parameters ??? 008h 4 hwhost host hardware parameters ?? 00ch 4 hwdevice device hardware parameters ? 010h 4 hwtxbuf tx buffer hardware parameters ??? high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-24 freescale semiconductor 014h 4 hwrxbuf rx buffer hardware parameters ??? 018h 4 hwtttxbuf tt-tx buffer hardware parameters 01ch 4 hwttrxbuf tt-rx buffer hardware parameters 020h-0fch 232 reserved n/a 080h 4 gptimer0ld general purpose timer #0 load register 084h 4 gptimer0ctrl general purpose timer #0 control register 088h 4 gptimer1ld general purpose timer #1 load register 08ch 4 gptimer1ctrl general purpose timer #1 control register 100h 1 caplength capability register length ??? 101h 1 reserved n/a 102h 2 hciversion host interface version number ?? 104h 4 hcsparams host ctrl. structural parameters ?? 108h 4 hccparams host ctrl. capability parameters ?? 10ch?11fh 20 reserved n/a 120h 2 dciversion dev. interface version number ? 122h 2 reserved n/a 124h 4 dccparams device ctrl. capability parameters ? 128h?13ch 24 reserved n/a table 30-13. configuration, control, and status register set (continued) offset size (bytes) mnemonic register name dev otg sph mph high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-25 140h 4 usbcmd usb command 144h 4 usbsts usb status 148h 4 usbintr usb interrupt enable ??? 14ch 4 frindex usb frame index 150h 4 reserved 4g segment selector 154h 4 periodiclistbase frame list base address ?? device addr usb device address ? 158h 4 asynclistaddr next asynchronous list address ?? endpointlist addr address at endpoint list in memory ? 15ch 4 asyncttsts asynchronous buffer status for embedded tt. 160h 4 burstsize programmable burst size ??? 164h 4 txfilltuning host transmit pre-buffer packet tuning ?? 168h 4 txttfilltuning host tt transmit pre-buffer packet tuning 16ch 4 n/a reserved 170-17ch 16 n/a reserved 180h 4 configflag configured flag register ?? 184h 4 portsc1 port status/control 1 ??? 188h 4 portsc2 port status/control 2 ? 4 portscx port status/control x 1a0h 4 portsc8 port status/control 8 table 30-13. configuration, control, and status register set (continued) offset size (bytes) mnemonic register name dev otg sph mph high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-26 freescale semiconductor 1a4h 4 otgsc on-the-go (otg) status and control 1a8h 4 usbmode usb device mode ??? 1ach 4 enpdtsetupstat endpoint setup status ? 1b0h 4 endptprime endpoint initialization ? 1b4h 4 endptflush endpoint de-initialize ? 1b8h 4 endptstatus endpoint status 1bch 4 endptcomplete endpoint complete ? 1c0h 4 endptctrl0 endpoint control 0 ? 1c4h 4 endptctrl1 endpoint control 1 ? ? 4 endptctrlx endpoint control x ? 1fch 4 endptctrl15 endpoint control 15 ? note italic text indicates a deviation from ehci for device table 30-13. configuration, control, and status register set (continued) offset size (bytes) mnemonic register name dev otg sph mph high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-27 30.8 summary of register layouts table 30-14. hs-usb register summary name 313029282726252423222120191817161514131211109876543210 000h id reserved revision nid id 004h hwgeneral reserved s m phym phy w b w t clkc r t 008h hwhost ttper ttasy reserved nport h c 00ch hwdevice reserved devp d c 010h hwtxbuf txlc reserved txchanadd txadd txburst 014h hwrxbuf reserved rxadd rxburst 020h reserved reserved ? reserved reserved 0fch reserved reserved 100h caplength caplength 101h reserved reserved 102h hciversion hciversion 104h hcsparams reserved n_tt n_ptt reserved pi n_cc n_pcc reserved p p c n_ports 108h hccparams reserved eec{[7:0] ist[7:4] r r p f l a d c 10ch reserved reserved ? reserved reserved 11fh reserved reserved 120h dciversion dciversion 122h reserved reserved high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-28 freescale semiconductor 124h dccparams reserved h c d c r rden 128h reserved reserved ? reserved reserved 13ch reserved reserved 140h usbcmd reserved itc fs 2 r su tw at d t w as pe r a s p 1 a s p 0 l r i a a a s e p s e f s 1 f s 0 r s t r s 144h usbsts reserved as ps r cl h c h reserved s li s r i u r i a a i s e i f r i p c i u e i u i 148h usbintr reserved s l e s r e u r e a a e s e e f r e p c e u e e u e 14ch frindex reserved frindex[13:0] 150h reserved reserved 154h periodiclistba se perbase[31:12] reserved device addr usbadr[31:25] reserved 158h asynclistaddr asybase[31:5] reserved endpointlist addr epbase[31:11] reserved 15ch asyncttsts reserved t t a c t t a s 160h burstsize reserved txpburst rxpburst 164h txfilltuning reserved txfifothres r txschhealth txschoh 168h txttfilltuning reserved txttschhealth r txttschoh 16ch reserved reserved 170 ulpi viewport ulpi viewport [optional] table 30-14. hs-usb register summary (continued) name 313029282726252423222120191817161514131211109876543210 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-29 174 reserved reserved ? reserved reserved 17ch reserved reserved 180h configflag set to zero 1 184h portsc1 pts st s pt w pspd r pf sc ph c d w k o c w kd s w kc n ptc pic p o pp ls h s p p r s u s p f p r o c c o c a p e c p e c s c c c s 188h portsc2 pts st s pt w pspd r pf sc ph c d w k o c w kd s w kc n ptc pic p o pp ls h s p p r s u s p f p r o c c o c a p e c p e c s c c c s ? portscx pts st s pt w pspd r pf sc ph c d w k o c w kd s w kc n ptc pic p o pp ls h s p p r s u s p f p r o c c o c a p e c p e c s c c c s 1a0h portsc8 pts st s pt w pspd r pf sc ph c d w k o c w kd s w kc n ptc pic p o pp ls h s p p r s u s p f p r o c c o c a p e c p e c s c c c s 1a4h otgsc r dp ie 1 ms e bs ei e bs vi e as vi e av vi e id ie r dp is 1 ms s bs ei s bs vi s as vi s av vi s id is r dp s 1 ms t bs e bs v as v a v v i d reserved d p o t r v c v d 1a8h usbmode reserved sdi s s l o m e s cm 1ach enpdtsetupst at reserved endptsetupstat 1b0h endptprime petb[15:0] perb[15:0] 1b4h endptflush fetb[15:0] ferb[15:0] 1b8h endptstatus etbr[15:0] erbr[15:0] 1bch endptcomplet e etce[15:0] erce[15:0] 1c0h endptctrl0 reserved tx e reserved txt r tx s reserved r x e reserved rxt r r x s 1c4h endptctrl1 reserved tx e tx r tx i rtxt tx d tx s reserved r x e r x r r x i rrxt r x d r x s table 30-14. hs-usb register summary (continued) name 313029282726252423222120191817161514131211109876543210 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-30 freescale semiconductor 30.8.1 identification registers identification registers are used to declare the slave in terface presence and include a table of the hardware configuration parameters. 30.8.1.1 id address:base + 000h default value:implementation dependent attribute:read only size:32 bits the identification register (id) provides a simple way to determine if the usb-hs otg high-speed usb on-the-go usb 2.0 core is provided in the syst em. the id register identifies the usb-hs otg high-speed usb on-the-go usb 2.0 core and its revision. figure 30-7. id - identification register the register fields are desc ribed in the following table. 30.8.1.2 hwgeneral address:base + 004h ? endptctrlx reserved tx e tx r tx i rtxt tx d tx s reserved r x e r x r r x i rrxt r x d r x s 1fch endptctrl15 reserved tx e tx r tx i rtxt tx d tx s reserved r x e r x r r x i rrxt r x d r x s 313029282726252423222120191817161514131211109876543210 reserved revision 1 1 nid 0 0 id field description id[5:0] configuration number. this number is set to 0x05 and indicates that the peripheral is the usb-hs otg high-speed usb on-the-go usb 2.0 core. nid[5:0] ones complement version of id[5:0]. revision[7:0] revision number of the core reserved these bits are reserved and should be set to zero table 30-14. hs-usb register summary (continued) name 313029282726252423222120191817161514131211109876543210 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-31 default value:implementation dependent attribute:read only size:32 bits general hardware parameters as defined in system level issues and core configuration. figure 30-8. hwgeneral?general hardware parameters the register fields are desc ribed in the following table. 30.8.1.2.1 hwhost address:base + 008h default value:implementation dependent attribute:read only size:32 bits host hardware parameters as defined in sy stem level issues and core configuration. figure 30-9. hwhost?host hardware parameters the register fields are desc ribed in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved s m phym phy w bw t cl kc r t table 30-15. hwgeneral field description reserved reserved. these bits are reserved and should be set to zero. sm vusb_hs_phy_serial phym vusb_hs_phy_type phyw vusb_hs_phy16_8 bwt reserved for internal testing. clkc vusb_hs_clock_configuration rt vusb_hs_reset_type 31 30 29 28 27 2625242322212019181716151413121110987654321 0 ttper ttasy reserved npor t h c high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-32 freescale semiconductor 30.8.1.2.2 hwdevice address:base + 00ch default value:implementation dependent attribute:read only size:32 bits device hardware parameters as defined in system level issues and core configuration. figure 30-10. hwdevice?device hardware parameters the register fields are desc ribed in the following table. 30.8.1.2.3 hwtxbuf address:base + 010h default value:implementation dependent attribute:read only size:32 bits tx buffer hardware parameters as defined in system level issues a nd core configuration. table 30-16. hwhost field descriptions field description ttper vusb_hs_tt_periodic_contexts ttasy vusb_hs_tt_async_contexts reserved reserved. these bits are reserved and should be set to zero. nport vusb_hs_num_port-1 hc vusb_hs_host 31302928272625242322212019181716151413121110 9 8 7 6 54321 0 reserved devep d c field description reserved reserved. these bits are reserved and should be set to zero. devep vusb_hs_dev_ep dc device capable; [vusb_hs_dev /= 0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-33 figure 30-11. hwtxbuf?tx buffer hardware parameters the register fields are desc ribed in the following table. 30.8.1.2.4 hwrxbuf address:base + 014h default value:implementation dependent attribute:read only size:32 bits rx buffer hardware parameters as defined in system level issues and core configuration. figure 30-12. wrxbuf?rx buffer hardware parameters the register fields are desc ribed in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txlcr reserved txchanadd txadd tcburst field description txlc vusb_hs_tx_local_context_registers reserved reserved. these bits are reserved and should be set to zero. txchanadd vusb_hs_tx_chan_add txadd vusb_hs_tx_add tcburst vusb_hs_tx_burst 313029282726252423222120191817161514131211109876543210 reserved rxadd rxburst field description reserved reserved. these bits are reserved and should be set to zero. rxadd vusb_hs_rx_add rxburst vusb_hs_rx_burst high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-34 freescale semiconductor 30.8.1.3 device/host capability registers device/host capability registers specify the software limits, restrictions, and capabilities of the host/device controller implementation. 30.8.1.3.1 caplength?ehci compliant address:base + 100h default value:40h attribute:read only size:8 bits this register is used to indicate which offset to a dd to the register base address at the beginning of the operational register. figure 30-13. caplength?capability register length 30.8.1.3.2 hciversion?ehci compliant address:base + 102h default value:0100h attribute:read only size:16 bits this is a two-byte register containing a bcd encodi ng of the ehci revision number supported by this host controller. the most significant byte of this register represents a major revision and the least significant byte is the minor revision. figure 30-14. hciversion?host interface version number 30.8.1.3.3 hcsparams?ehci compliant with extensions address:base + 104h default value:implementation dependent attribute:read only size:32 bits 76543210 caplength[7:0] 1514131211109876543210 hciversion[15:0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-35 port steering logic capabilities are described in this register. figure 30-15. hcsparams?host control structural parameters the register fields are desc ribed in the following table. 3130292827262524232221201918171615141312111098765 4 3210 reserved n_tt n_ptt reserved pi n_cc n_pcc reserv ed p p c n_port s table 30-17. hcsparams field descriptions field description reserved reserved. these bits are reserved and should be set to zero. pi port indicators (p indicator). this bit indicates whether the ports support port indicator control. when set to one, the port status and control registers include a read/writeable field for controlling the state of the port indicator. this field will always be ?1?. n_tt[3:0] number of transaction translators (n_tt). this field indicates the number of embedded transaction translators associated with the usb2.0 host controller. for multi-port host this field will always equal ?0001?. for all other implementations, n_tt = ?0000?. this in a non-ehci field to support embedded tt. n_ptt[3:0] number of ports per transaction translator (n_ptt). this field indicates the number of ports assigned to each transaction translator within the usb2.0 host controller. for multi-port host this field will always equal n_ports. for all other implementations, n_ptt = ?0000?. this in a non-ehci field to support embedded tt. n_cc[3:0] number of companion controller (n_cc). this field indicates the number of companion controllers associated with this usb2.0 host controller. a zero in this field indicates there are no internal companion controllers. port-ownership hand-off is not supported. a value larger than zero in this field indicates there are companion usb1.1 host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. in this implementation this field will always be ?0?. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-36 freescale semiconductor 30.8.1.3.4 hccparams?ehci compliant address:base + 108h default value:0006h attribute:read only size:32 bits this register identifies multiple mode control (t ime-base bit functionality) addressing capability. figure 30-16. hccparams?host control capability parameters n_pcc[3:0] number of ports per companion controller. this field indicates the number of ports supported per internal companion controller. it is used to indicate the port routing configuration to the system software. for example, if n_ports has a value of 6 and n_cc has a value of 2 then n_pcc could have a value of 3. the convention is that the first n_pcc ports are assumed to be routed to companion controller 1, the next n_pcc ports to companion controller 2, etc. in the previous example, the n_pcc could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. the number in this field must be consistent with n_ports and n_cc. in this implementation this field will always be ?0?. ppc port power control. this field indicates whether the host controller implementation includes port power control. a one indicates the ports have port power switches. a zero indicates the ports do not have port power switches. the value of this field affects the functionality of the port power field in each port status and control register. this field will always be ?0? for a device only implementation. n_ports[3:0] number of downstream ports. this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register. valid values are in the range of 1h to fh. a zero in this field is undefined. the number of ports for a host implementation is parameterizable from 1 to 8. this field will always be 1 for device only implementation. 3130 29 282726 252423 2221 20 19 18 17 16 15 14 13 12 11109876543 2 1 0 reserved eecp[7:0] ist[7:4] r a s p p f l a d c table 30-17. hcsparams field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-37 the register fields are desc ribed in the following table. dciversion (non-ehci) address:base + 120h default value:implementation dependent attribute:read only size:16 bits table 30-18. hccparams field descriptions field description reserved reserved. these bits are reserved and should be set to zero. eecp[7:0] ehci extended capabilities pointer. default = 0. this optional field indicates the existence of a capabilities list. a value of 00h indicates no extended capabilities are implemented. a non-zero value in this register indicates the offset in pci configuration space of the first ehci extended capability. the pointer value must be 40h or greater if implemented to maintain the consistency of the pci header defined for this class of device. for this implementation this field is always ?0?. ist[7:4] isochronous scheduling threshold. default = implementation dependent. this field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. when bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. when bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. this field will always be ?0?. r reserved. these bits are reserved and should be set to zero. asp asynchronous schedule park capability. default = 1. if this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the asynchronous schedule. the feature can be disabled or enabled and set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the usbcmd register. this field will always be ?1? pfl programmable frame list flag. if this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller. the usbcmd register frame list size field is a read-only register and must be set to zero. if set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the usbcmd register frame list size field. the frame list must always be aligned on a 4k-page boundary. this requirement ensures that the frame list is always physically contiguous. this field will always be ?1?. adc 64-bit addressing capability. this field will always be ?0?. no 64-bit addressing capability is supported. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-38 freescale semiconductor the device controller interface conforms to the tw o-byte bcd encoding of the interface version number contained in this register. figure 30-17. dciversion?device interface version number 30.8.1.3.5 dccparams (non-ehci) address:base + 124h default value:implementation dependant attribute:read only size:32 bits these fields describe the overall host/device capability of the controller. figure 30-18. dccparams?device control capability parameters the register fields are desc ribed in the following table. 30.8.1.4 device/host timer registers (non-ehci) the host/device controller drivers can measure time related activities using these timer registers. these registers are not part of the standard ehci controller. 1514131211109876543210 dciversion[15:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved h d r rden[4:0] table 30-19. dccparams field descriptions field description reserved reserved. these bits are reserved and should be set to zero. hc host capable. when this bit is 1, this controller is capable of operating as an ehci compatible usb 2.0 host controller. dc device capable. when this bit is 1, this controller is capable of operating as a usb 2.0 device. r reserved. these bits are reserved and should be set to zero. den[4:0] device endpoint number. this field indicates the number of endpoints built into the device controller. if this controller is not device capable, then this field will be zero. valid values are 0?16. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-39 30.8.1.4.1 gptimer0ld (non-ehci) address: base + 80h default value: 00000000h attribute: read/write size: 32 bits this register contains the timer duration or load value. see the gptimer0ctrl (non-ehci) for a description of the timer functions. figure 30-19. gptimer0ld-general purpose timer #0 load register the register fields are desc ribed in the following table. 30.8.1.4.2 gptimer0ctrl (non-ehci) address: base + 84h default value: 00000000h attribute: read only, write only, read/write size: 32 bits this register contains the control for the timer and a data field can be queried to determine the running count value. this timer has granularity on 1 us a nd can be programmed to a little over 16 seconds. there are two modes supported by this timer, the first is a one shot and the second is a looped count which is described in the register table below. when the timer counter value transitions to zero, an interrupt can be generated though the use of the timer interr upts in the usbsts and usbintr registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved gptld table 30-20. gptimer0ld field descriptions field description reserved reserved. these bits are reserved and should be set to zero. h\gptld general purpose timer load value. this field is the value to be loaded into the gptcnt countdown timer on a reset action. this value represents the time in microseconds minus 1 for the timer duration. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-40 freescale semiconductor figure 30-20. gptimer0ld-general purpose timer #0 controller the register fields are desc ribed in the following table. 30.8.1.4.3 gptimer1ld (non-ehci) address: base + 88h default value: 00000000h high-speed usb controller core reference attribute: read/write size: 32 bits same as gptimer0ld. 30.8.1.4.4 gptimer1ctrl (non-ehci) address: base + 8ch default value: 00000000h attribute: read only, write only, read/write size: 32 bits same as gptimer0ctrl. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gptr gptr reserved gpt gptcnt table 30-21. gptimer0ld field descriptions field description gptrun general purpose timer run (0)-timer stop; (1)-timer run. this bit enable the gpt to run. setting or clearing this bit will not have an effect on the gptcnt except. gptrst general purpose timer reset (0)-no action; (1)-load counter value. this bit will reload the gptcnt with the value in gptld. reserved reserved. these bits are reserved and should be set to zero. gptmod general purpose timer mode. (0)-one shot; (1)-repeat.in one-shot mode the timer will count to zero, generate an interrupt and stop until the timer is reset by software. in repeat mode the timer will count to zero, generate an interrupt and automatically reload the counter to begin again. gptcnt general purpose timer counter. this field is the value of running timer. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-41 30.8.1.5 device/host operational registers operational registers are comprise d of dynamic control or status registers that may be read only, read/write, or read/write to clear. the followi ng sections define the use of these registers. 30.8.1.5.1 usbcmd address:base + 140h default value:00080b00h (host mode) 00080000h (device mode) attribute:read only, read/write , write only (field dependent) size:32 bits the serial bus host/device controller executes the command indicated in this register. figure 30-21. usbcmd?usb command register the register fields are desc ribed in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved itc[7:0] fs 2 r sut w at d tw as pe r as p1 as p0 l r i a a as e ps e fs 1 fs 0 rs t r s table 30-22. usbcmd?usb command register field descriptions field description r, reserved reserved. these bits are reserved and should be set to zero. itc[7:0] interrupt threshold control. read/write. default 08h. the system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. itc contains the maximum interrupt interval measured in micro-frames. valid values are shown below. value maximum interrupt interval 00h immediate (no threshold) 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames 10h 16 micro-frames 20h 32 micro-frames 40h 64 micro-frames sutw setup tripwire. read/write [device mode only].this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a qh by the dcd without being corrupted. if the setup lockout mode is off (see usbmode) then there exists a hazard when new setup data arrives while the dcd is copying the setup data payload from the qh for a previous setup packet. this bit is set and cleared by software and will be cleared by hardware when a hazard exists. for more information on the use of this bit, see the device operational model section of the usb-hs otg high-speed usb on-the-go dev reference manual. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-42 freescale semiconductor atdtw add dtd tripwire. read/write[device mode only]. this bit is used as a semaphore to ensure the to proper addition of a new dtd to an active (primed) endpoint?s linked list. this bit is set and cleared by software. this bit shall also be cleared by hardware when is state machine is hazard region for which adding a dtd to a primed endpoint may go unrecognized. for more information on the use of this bit, see the device operational model section of the usb-hs otg high-speed usb on-the-go dev reference manual. aspe asynchronous schedule park mode enable (optional). read/write. if the asynchronous park capability bit in the hccparams register is a one, then this bit defaults to a 1h and is r/w. otherwise the bit must be a zero and is read-only. software uses this bit to enable or disable park mode. when this bit is one, park mode is enabled. when this bit is a zero, park mode is disabled. this field is set to ?1? in this implementation. asp[1:0] asynchronous schedule park mode count (optional). read/write. if the asynchronous park capability bit in the hccparams register is a one, then this field defaults to 3h and is r/w. otherwise it defaults to zero and is ro. it contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the asynchronous schedule before continuing traversal of the asynchronous schedule. see section 4.10.3.2 for full operational details. valid values are 1h to 3h. software must not write a zero to this bit when park mode enable is a one as this will result in undefined behavior. this field is set to 3h in this implementation. lr light host/device controller reset (optional). read only. not implemented. this field will always be ?0?. iaa interrupt on async advance doorbell. read/write. this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. software must write a 1 to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule states, it sets the interrupt on async advance status bit in the usbsts register. if the interrupt on sync advance enable bit in the usbintr register is one, then the host controller will assert an interrupt at the next interrupt threshold. the host controller sets this bit to zero after it has set the interrupt on sync advance status bit in the usbsts register to one. software should not write a one to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. this bit is only used in host mode. writing a one to this bit when device mode is selected will have undefined results. ase asynchronous schedule enable. read/write. default 0b. this bit controls whether the host controller skips processing the asynchronous schedule. valuesmeaning 0 do not process the asynchronous schedule. 1 use the asynclistaddr register to access theasynchronous schedule. only the host controller uses this bit. pse periodic schedule enable. read/write. default 0b. this bit controls whether the host controller skips processing the periodic schedule. values meaning 0 do not process the periodic schedule 1 use the periodiclistbase register to access the periodicschedule. only the host controller uses this bit. table 30-22. usbcmd?usb command register field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-43 30.8.1.5.2 usbsts address:base + 144h default value:00001000h (host mode) 00000000h (device mode) fs[2:0] frame list size. (read/write or read only). default 000b. this field is read/write only if programmable frame list flag in the hccparams registers is set to one. this field specifies the size of the frame list that controls which bits in the frame index register should be used for the frame list current index. note that this field is made up from usbcmd bits 15, 3 and 2. values meaning 000 1024 elements (4096 bytes) default value 001 512 elements (2048 bytes) 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) only the host controller uses this field. rst controller reset (reset) ? read/write. software uses this bit to reset the controller. this bit is set to zero by the host/device controller when the reset process is complete. software cannot terminate the reset process early by writing a zero to this register. host controller: when software writes a one to this bit, the host controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. software should not set this bit to a one when the hchalted bit in the usbsts register is a zero. attempting to reset an actively running host controller will result in undefined behavior. device controller: when software writes a one to this bit, the device controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. in order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the usbcmd run/stop bit should be set to 0. rs run/stop (rs)?read/write. default 0b. 1=run. 0=stop. host controller: when set to a 1, the host controller proceeds with the execution of the schedule. the host controller continues execution as long as this bit is set to a one. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a one to this field unless the host controller is in the halted state (that is, hchalted in the usbsts register is a one). device controller: writing a one to this bit will cause the device controller to enable a pull-up on d+ and initiate an attach event. this control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. software should use this bit to prevent an attach event before the device controller has been properly initialized. writing a 0 to this will cause a detach event. table 30-22. usbcmd?usb command register field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-44 freescale semiconductor attribute:read only, read/write, r ead/write-clear (field dependant) size:32 bits this register indicates various states of the ho st/device controller and a ny pending interrupts. this register does not indicate st atus resulting from a transaction on the seri al bus. software clears certain bits in this register by writing a 1 to them. figure 30-22. usbsts?usb status the register fields are desc ribed in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ti 1 ti 0 reserved a s p s r c l h c h r ul pii r s l i s r i u r i a a i s e i f r i p c i u e i u i table 30-23. usbsts field descriptions field description reserved reserved. these bits are reserved and should be set to zero. ti1 general purpose timer interrupt 1(gptint1)--r/wc. this bit is set when the counter in the gptimer1ctrl register transitions to zero, writing a one to this bit will clear it. ti0 general purpose timer interrupt 0(gptint0)--r/wc. this bit is set when the counter in the gptimer0ctrl register transitions to zero, writing a one to this bit will clear it. reserved reserved. these bits are reserved and should be set to zero. as asynchronous schedule status ? read only. 0=default. this bit reports the current real status of the asynchronous schedule. when set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit in the usbcmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). only used by the host controller. ps periodic schedule status ? read only. 0=default. this bit reports the current real status of the periodic schedule. when set to zero the periodic schedule is disabled, and if set to one the status is enabled. the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit in the usbcmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). only used by the host controller. rcl reclamation ? read only. 0=default. this is a read-only status bit used to detect an empty asynchronous schedule. only used by the host controller. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-45 hch hchaited ? read only. 1=default. this bit is a zero whenever the run/stop bit is a one. the host controller sets this bit to one after it has stopped executing because of the run/stop bit being set to 0, either by software or by the host controller hardware (for example, internal error). only used by the host controller. r reserved. these bits are reserved and should be set to zero. ulpii ulpi interrupt?r/wc. 0=default. when the ulpi viewport is present in the design, an event completion will set this interrupt. used by both host and device controller. only present in designs where configuration constant vusb_hs_phy_ulpi = 1. r reserved. these bits are reserved and should be set to zero. sli dcsuspend?r/wc. 0=default. when a device controller enters a suspend state from an active state, this bit will be set to a one. the device controller clears the bit upon exiting from a suspend state. only used by the device controller. sri sof received?r/wc. 0=default. when the device controller detects a start of (micro) frame, this bit will be set to a one. when a sof is extremely late, the device controller will automatically set this bit to indicate that an sof was expected. therefore, this bit will be set roughly every 1ms in device fs mode and every 125ms in hs mode and will be synchronized to the actual sof that is received. since the device controller is initialized to fs before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. in host mode, this bit will be set every 125us and can be used by host controller driver as a time base. software writes a 1 to this bit to clear it. this is a non-ehci status bit. uri usb reset received?r/wc. 0=default. when the device controller detects a usb reset and enters the default state, this bit will be set to a one. software can write a 1 to this bit to clear the usb reset received status bit. only used by the device controller. aai interrupt on async advance ? r/wc. 0=default. system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the interrupt on async advance doorbell bit in the usbcmd register. this status bit indicates the assertion of that interrupt source. only used by the host controller. sei system error? r/wc. this bit is not used in this implementation and will always be set to ?0?. fri frame list rollover ? r/wc. the host controller sets this bit to a one when the frame list index rolls over from its maximum value to zero. the exact value at which the rollover occurs depends on the frame list size. for example. if the frame list size (as programmed in the frame list size field of the usbcmd register) is 1024, the frame index register rolls over every time frindex [1 3] toggles. similarly, if the size is 512, the host controller sets this bit to a one every time fhindex [12] toggles. only used by the host controller. table 30-23. usbsts field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-46 freescale semiconductor 30.8.1.5.3 usbintr address:base + 148h default value:00000000h attribute:read/write size:32 bits the interrupts to software are enabled with this register. an interrupt is generated when a bit is set and the corresponding interrupt is active. the usb status regist er (usbsts) still shows interrupt sources even if they are disabled by the usbintr register, allo wing polling of interrupt events by the software. figure 30-23. usbintr?usb interrupt enable pci port change detect ? r/wc. the host controller sets this bit to a one when on any port a connect status occurs, a port enable/disable change occurs, or the force port resume bit is set as the result of a j-k transition on the suspended port. the device controller sets this bit to a one when the port controller enters the full or high-speed operational state. when the port controller exits the full or high-speed operation states due to reset or suspend events, the notification mechanisms are the usb reset received bit and the dcsuspend bits respectively. this bit is not ehci compatible. uei usb error interrupt (usberrint) ? r/wc. when completion of a usb transaction results in an error condition, this bit is set by the host/device controller. this bit is set along with the usbint bit, if the td on which the error interrupt occurred also had its interrupt on complete (ioc) bit set see section (reference host operation model: transfer/transaction based interrupt?that is, 4.15.1 in ehci enhanced host controller interface specification for universal serial bus, revision 0.95, november 2000, intel corporation. http://www.intel.com) for a complete list of host error interrupt conditions. see section device error matrix in the usb-hs otg high-speed usb on-the-go dev reference manual. the device controller detects resume signaling only. ui usb interrupt (usbint)?r/wc. this bit is set by the host/device controller when the cause of an interrupt is a completion of a usb transaction where the transfer descriptor (td) has an interrupt on complete (ioc) bit set. this bit is also set by the host/device controller when a short packet is detected. a short packet is when the actual number of bytes received was less than the expected number of bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ti e 1 ti e 0 reserved ulp ie r s l e s r e u r e a a e s e e f r e p c e u e e u e table 30-23. usbsts field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-47 the register fields are desc ribed in the following table. table 30-24. usbintr field descriptions field interrupt source description reserved reserved these bits are reserved and should be set to zero. tie1 gpt interrupt enable1 when this bit is one and the gptint1 in usbsts register is a one the controller will issue an interrupt. the interrupt is acknowledge by software clear the gptint1 bit. tie0 gpt interrupt enable0 when this bit is one and the gptint0 in usbsts register is a one the controller will issue an interrupt. the interrupt is acknowledge by software clear the gptint0 bit. reserved reserved. these bits are reserved and should be set to zero. ulpie ulpi enable when this bit is a one, and the ulpi interrupt bit in the usbsts register transitions, the controller will issue and interrupt. the interrupt is acknowledged by software writing a one to the ulpi interrupt bit. used by both host and device controller. only present in designs where configuration constant vusb_hs_phy_ulpi = 1. reserved reserved. these bits are reserved and should be set to zero. sle sleep enable when this bit is a one, and the dcsuspend bit in the usbsts register transitions, the device controller will issue an interrupt. the interrupt is acknowledged by software writing a one to the dcsuspend bit. only used by the device controller. sre sof received enable when this bit is a one, and the sof received bit in the usbsts register is a one, the device controller will issue an interrupt. the interrupt is acknowledged by software clearing the sof received bit. ure usb reset enable when this bit is a one, and the usb reset received bit in the usbsts register is a one, the device controller will issue an interrupt. the interrupt is acknowledged by software clearing the usb reset received bit. only used by the device controller. aae interrupt on async advance enable when this bit is a one, and the interrupt on async advance bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. only used by the host controller. see system error enable when this bit is a one, and the system error bit in the usbsts register is a one, the host/device controller will issue an interrupt. the interrupt is acknowledged by software clearing the system error bit. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-48 freescale semiconductor 30.8.1.5.4 frindex address:base + 14ch default value:undefined (free running counter) attribute:read/write in host mode, read in device mode size:32 bits this register is used by the host controller to index the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits [n: 3] are used to select a particular entry in the periodic frame list during periodic schedule execution. the numbe r of bits used for the index depends on the size of the frame list as set by system software in the frame list size field in the usbcmd register. this register must be written as a dword. byte wr ites produce-undefined results. this register cannot be written unless the host controller is in the 'halted' state as indicated by the hchalted bit. a write to this register while the run/stop hit is set to a one produces undefined results. writes to this register also affect the sof value. in device mode this register is read only and, the device controller updates the frindex [13:3] register from the frame number indicated by the sof marker . whenever a sof is received by the usb bus, frindex [13:3] will be checked against the sof mark er. if frindex [13:3] is different from the sof marker, frindex [13:3] will be set to the sof value and frindex [2:0] will be set to zero (that is, sof for 1 ms frame). if frindex [13:3] is equal to the sof value, frindex [2:0] will be increment (that is, sof for 125 us micro-frame.) fre frame list rollover enable when this bit is a one, and the frame list rollover bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. only used by the host controller. pce port change detect enable when this bit is a one, and the port change detect bit in the usbsts register is a one, the host/device controller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. uee usb error interrupt enable when this bit is a one, and the usberrint bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the usberrint bit in the usbsts register. ue usb interrupt enable when this bit is a one, and the usbint bit in the usbsts register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the usbint bit. table 30-24. usbintr field descriptions (continued) field interrupt source description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-49 figure 30-24. frindex?usb frame index the register fields are desc ribed in the following table. 30.8.1.5.5 ctrldssegment address:base + 150h default value:00000000h attribute:read only size:32 bits this register is not used in this implementation. 30.8.1.5.6 periodiclistbase; deviceaddr address:base + 154h default value:00000000h attribute:read/write (writes must be dword writes) size:32 bits 31 30 2928 27 26 25 24 23 22 2120 19 18 17 16 15 14 13 12 11 10 9876543210 reserved frindex[13:0] table 30-25. frindex register field descriptions field description reserved reserved. these bits are reserved and should be set to zero. frindex frame index. the value, in this register, increments at the end of each time frame (for example, micro-frame). bits [n: 3] are used for the frame list current index. this means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. the following illustrates values of n based on the value of the frame list size field in the usbcmd register, when used in host mode. usbcmd[frame list size] number elements n 000b (1024)12 001b (512)11 010b (256)10 011b (128)9 100b (64)8 101b (32)7 110b (16)6 111b (8) 5 in device mode the value is the current frame number of the last frame transmitted. it is not used as an index. in either mode bits 2:0 indicate the current microframe. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-50 freescale semiconductor this register is shared between the host controller and the device controller operation. host controller ( periodiclistbase) this 32-bit register contains the beginning address of the periodic frame list in the system memory. hcd loads this register prior to starting the schedule ex ecution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. figure 30-25. periodiclistbase - host controller frame list base address the register fields are desc ribed in the following table. device controller (usb deviceaddr) the upper seven bits of this register represent the devi ce address. after any controll er reset or a usb reset, the device address is set to the default address (0). the default address will match all incoming addresses. software shall reprogram the address after receiving a set_address descriptor. figure 30-26. deviceaddr - device controller usb device address the register fields are desc ribed in the following table. 31 3029 28 27 2625 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 perbase[31:12] reserved table 30-26. periodiclistbase register field descriptions field description baseadr base address (low). these bits correspond to memory address signals [31:12], respectively. only used by the host controller. reserved reserved. must be written as zeros. during runtime, the values of these bits are undefined. 313029282726252423222120191817161514131211109876543210 usbadr[31:25] reserved table 30-27. deviceaddr field descriptions field description usbadr device address. these bits correspond to the usb device address reserved reserved. must be written as zeros. during runtime, the values of these bits are undefined. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-51 30.8.1.5.7 asynclistaddr; endpointlistaddr address:base + 158h default value:00000000h attribute:read/write (writes must be dword writes) size:32 bits this register is shared between the host controller and the device controller operation. host controller (asynclistaddr) this 32-bit register contains the address of the next asynchronous queue head to be executed by the host. bits [4:0] of this register cannot be modified by the system software and will always return a zero when read. figure 30-27. asynclistaddr - host controller next asynch. address the register fields are desc ribed in the following table. device controller (endpointlistaddr) in device mode, this register contains the address of the top of the endpoint list in system memory. bits [10:0] of this register cannot be modified by the syst em software and will always return a zero when read. the memory structure referenced by this phys ical memory pointer is assumed 64-byte. figure 30-28. endpointlistaddr - device controller endpoint list address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 asybase[31:5] reserved table 30-28. asynclistaddr field descriptions field description asybase[31:5] link pointer low (lpl). these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (oh). only used by the host controller. reserved reserved. these bits are reserved and their value has no effect on operation. 313029282726252423222120191817161514131211109876543210 epbase[31:11] reserved high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-52 freescale semiconductor the register fields are desc ribed in the following table. 30.8.1.5.8 burstsize address:base + 160h default value:implementation dependent attribute:read/write (writes must be dword writes) size:32 bits this register is used to control dynamically change the burst size used during data movement on the initiator (master) interface. figure 30-29. burstsize - host controller embedded tt async. buffer status the register fields are desc ribed in the following table. 30.8.1.5.9 txfilltuning address:base + 164h default value:00020000h table 30-29. endpointlistaddr field descriptions field description epbase[31:11] endpoint list pointer(low). these bits correspond to memory address signals [31:11], respectively. this field will reference a list of up to 32 queue head (oh) (for example, one queue head per endpoint and direction). reserved reserved. these bits are reserved and their value has no effect on operation. 313029282726252423222120191817161514131211109876543210 reserved txpburst rxpburst table 30-30. burstsize field descriptions field description reserved reserved. these bits are reserved and their value has no effect on operation. txpburst programmable tx burst length. (read/write) default is the constant vusb_hs_tx_burst. this register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the usb bus. rxpburst programmable rx burst length. (read/write) default is the constant vusb_hs_rx_burst. this register represents the maximum length of a the burst in 32-bit words while moving data from the usb bus to system memory. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-53 attribute:read/write (writes must be dword writes) size:32 bits figure 30-30. txfilltuning the fields in this register control performance tuning associated with how the host controller posts data to the tx latency fifo before moving the data onto the usb bus. the specific areas of performance include the how much data to post into the fifo and an estimate for how long that operation should take in the target system. definitions: t 0 = standard packet overhead t 1 = time to send data payload t ff = time to fetch packet into tx fifo up to specified level. t s = total packet flight time (send-only) packet t s = t 0 + t 1 t p = total packet time (fetch and send) packet t p = t ff + t 0 + t 1 upon discovery of a transmit (out/setup) packet in th e data structures, host controller checks to ensure t p remains before the end of the [micro]frame. if so it proceeds to pre-fill the tx fifo. if at anytime during the pre-fill operation the time remaining the [micro]frame is < t s then the packet attempt ceases and the packet is tried at a later time. although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a ?back-off? event. when a back-off event is detected, the partia l packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next sof. too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). back-offs can be minimized with use of the tschhealth ( t ff ) described below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved txfifothres reserved txschealth txschoh high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-54 freescale semiconductor the register fields are desc ribed in the following table. 30.8.1.5.10 ulpi viewport (optional) address:base + 170h default value:00000000h attribute:read/write size:32 bits the register provides indirect access to the ulpi p hy register set. although the core performs access to the ulpi phy register set, there may be extraordinary circumstances where software may need direct access. ? caution: writes to the ulpi through the viewport can substantially harm standard usb operations. currently no usage model table 30-31. txfilltuning field descriptions field description reserved reserved. these bits are reserved and their value has no effect on operation. txfifothres fifo burst threshold. (read/write) [default = 2] this register controls the number of data bursts that are posted to the tx latency fifo in host mode before the packet begins on to the bus. the minimum value is 2 and this value should be a low as possible to maximize usb performance. a higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the fifo may underrun because the data transferred from the latency fifo to usb occurs before it can be replenished from system memory. this value is ignored if the stream disable bit in usbmode register is set. txschhealth scheduler health counter. (read/write to clear) [default = 0] this register increments when the host controller fails to fill the tx latency fifo to the level programmed by txfifothres before running out of time to send the packet before the next start-of-frame. this health counter measures the number of times this occurs to provide feedback to selecting a proper txschoh. writing to this register will clear the counter and this counter will max. at 31. reserved reserved. these bits are reserved and their value has no effect on operation. txschoh scheduler overhead. (read/write) [default = 0] this register adds an additional fixed offset to the schedule time estimator described above as tff. as an approximation, the value chosen for this register should limit the number of back-off events captured in the txschhealth to less than 10 per second in a highly utilized bus. choosing a value that is too high for this register is not desired as it can needlessly reduce usb utilization. the time unit represented in this register is 1.267us when a device is connected in high-speed mode for otg and sph. the time unit represented in this register is 6.333us when a device is connected in low/full speed mode for otg and sph. the time unit represented in this register is always 1.267 the mph product. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-55 has been defined where software should need to execute writes directly to the ulpi. ? note: executing read operations though the ulpi viewport should have no harmful side effects to standard usb operations. ? note: the ulpi viewport is only synthesized in the design if the ulpi option has been purchased and installed and the constant vusb_hs_phy_ulpi is set to 1 . if the ulpi interface is not enabled, this register will always read zeros. there are two operations that can be performed wi th the ulpi viewport, wakeup and read /write operations. the wakeup operation is used to put th e ulpi interface into normal operation mode and re-enable the clock if necessary. a wakeup operation is required before accessing the registers when the ulpi interface is operating in low power mode, serial mode, or carkit mode. the ulpi state can be determined by reading the sync. state bit (ulpiss). if this bit is a one, then ulpi interface is running in normal operation mode and can accept re ad/write operations. if the ulpiss indicates a ?0? then read/write operations will not be able execute. undefined behavi or will result if ulpiss = 0 and a read or write operation is performed. to execute a wakeup operati on, write all 32-bits of the ulpi viewport where ulpiport is constructed a ppropriately and the ulpiwu bit is a ?1? and ulpirun bit is a ?0?. poll the ulpi viewport until ulpiwu is zero for the operation to complete. to execute a read or write operation, write all 32-bits of the ulpi viewport where ulpidatwr, ulpiaddr, ulpiport, ulpirw are constructed appropr iately and the ulpirun bit is a ?1?. poll the ulpi viewport until ulpirun is zero for the operation to complete. once ulpirun is zero, the ulpidatrd will be valid if the operation was a read. the polling method above could also be replaced and inte rrupt driven using the ulpi interrupt defined in the usbsts and usbintr registers. when a wake up or read/write operation complete, the ulpi interrupt will be set. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-56 freescale semiconductor figure 30-31. ulpi viewport 30.8.1.5.11 configflag address:base + 180h default value:00000001h attribute:read only size:32 bits 31 30 29 2 8 27 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ulpi ulpir ulpir r ulpi ulpipo ulpiaddr ulpidatrd ulpidatwr table 30-32. ulpi viewport field descriptions field description ulpiwu ulpi wakeup?read/write. writing the ?1? to this bit will begin the wakeup operation. the bit will automatically transition to 0 after the wakeup is complete. once this bit is set, the driver can not set it back to ?0?. note: the driver must never execute a wakeup and a read/write operation at the same time. ulpirun ulpi read/write run?read/write. writing the ?1? to this bit will begin the read/write operation. the bit will automatically transition to 0 after the read/write is complete. once this bit is set, the driver can not set it back to ?0?. note: the driver must never execute a wakeup and a read/write operation at the same time. ulpirw ulpi read/write control?read/write. (0)?read; (1)?write. this bit selects between running a read or write operation. reserved reserved. this bit is reserved and its value has no effect on operation. ulpiss ulpi sync state?read only. (1)?normal sync. state. (0) in another state (that is, carkit, serial, low power) this bit represents the state of the ulpi interface. before reading this bit, the ulpiport field should be set accordingly if used with the multi-port host. otherwise, this field should always remain 0. ulpiport ulpi port number?read/write. for the wakeup or read/write operation to be executed, this value selects the port number the ulpi phy is attached to in the multi-port host. the range is 0 to 7. this field should always be written as a 0 for the non-multi port products. ulpiaddr ulpi data address?read/write. when a read or write operation is commanded, the address of the operation is written to this field. ulpidatrd ulpi data read?read only. after a read operation completes, the result is placed in this field. ulpidatwr ulpi data write?read/write. when a write operation is commanded, the data to be sent is written to this field. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-57 this register is not used in this implementation. a read from this register returns a constant of a 00000001h to indicate that all port routines default to this host controller. 30.8.1.5.12 portscx address:base + 184h + (4*(port number ?1)) where port number =1,2,3,?8 default value: iiii0000000000000000xx0000000000b (host mode) iiii0000000000000001xx0000000100b (device mode) i = implementation dependent x = unknown attribute:ro, read/write, r/wc (field dependent) size:32 bits host controller a host controller must implement one to eight port re gisters. the number of por t registers implemented by a particular instantiation of a host controller is doc umented in the hcsparams register. software uses this information as an input parameter to determine how many ports need service. this register is only reset when power is initially app lied or in response to a controller reset. the initial conditions of a port are: no device connected port disabled if the port has port power control, this state remains until software applies power to the port by setting port power to one. device controller a device controller must implement only port regist er one and it does not support power control. port control in device mode is only used for status port rese t, suspend, and current connect status. it is also used to initiate test mode or force signaling and allows so ftware to put the phy into low power suspend mode and disable the phy clock. figure 30-32. portscx - port status control[1:8] 313029282726252423222120191817161514131211109876543210 pts s t s p t w psp d r p f s c p h c d w k o c w k d s w k c n ptc[3:0] pic p o p p ls h s p p r s u s p f p r o c c o c a p e c p e c s c c c s high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-58 freescale semiconductor the register fields are desc ribed in the following table. table 30-33. portscx field descriptions field description pts parallel transceiver select?read/write. this register bit pair is used in conjunction with the configuration constant vusb_hs_phy_type to control which parallel transceiver interface is selected. if vusb_hs_phy_type is set for 0,1,2, or 3 then this bit is read only. if vusb_hs_phy_type is 3,4,5, or 6 then this bit is read/write. this field is reset to: ?00? if vusb_hs_phy_type = 0,4?utmi/utmi+ ?01? if vusb_hs_phy_type = 1,5?reserved ?10? if vusb_hs_phy_type = 2,6?ulpi ?11? if vusb_hs_phy_type = 3,7?serial/1.1 phy (fs only) this bit is not defined in the ehci specification. sts serial transceiver select?read/write. this register bit is used in conjunction with the configuration constant vusb_hs_phy_serial to control whether the parallel or serial transceiver interface is selected for fs and ls operation. the serial interface engine can be used in combination with the utmi+ or ulpi physical interface to provide fs/ls signaling instead of the parallel interface. if vusb_hs_phy_serial is set for 0 or 1 then this bit is read only. if vusb_hs_phy_serial is 3 or 4 then this bit is read/write. this bit has no effect unless parallel transceiver select is set to utmi+ or ulpi. the serial/1.1 physical interface will use the serial interface engine for fs/ls signaling regardless of this bit value. note: this bit is reserved for future operation and is a placeholder adding dynamic use of the serial engine in accord with umti+ and ulpi characterization logic. this bit is not defined in the ehci specification. ptw parallel transceiver width?read/write. this register bit is used in conjunction with the configuration constant vusb_hs_phy8_16 to control whether the data bus width of the utmi transceiver interface. if vusb_hs_phy8_16 is set for 0 or 1 then this bit is read only. if vusb_hs_phy8_16 is 2 or 3 then this bit is read/write. this bit is reset to 1 if vusb_hs_phy8_16 selects a default utmi interface width of 16-bits else it is reset to 0. writing this bit to 0 selects the 8-bit [60mhz] utmi interface. writing this bit to 1 selects the 16-bit [30mhz] utmi interface. this bit has no effect if the serial interfaces are selected. this bit is not defined in the ehci specification. pspd port speed?read only. this register field indicates the speed at which the port is operating. for hs mode operation in the host controller and hs/fs operation in the device controller the port routing steers data to the protocol engine. for fs and ls mode operation in the host controller, the port routing steers data to the protocol engine w/ embedded transaction translator. 00?full speed 01?low speed 10?high speed this bit is not defined in the ehci specification. pfsc port force full speed connect?read/write. default = 0b. writing this bit to a 1b will force the port to only connect at full speed. it disables the chirp sequence that allows the port to identify itself as high speed. this is useful for testing fs configurations with a hs host, hub or device. this bit is not defined in the ehci specification. this bit is for debugging purposes. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-59 phcd phy low power suspend - clock disable (plpscd)?read/write. default = 0b. writing this bit to a 1b will disable the phy clock. writing a 0b enables it. reading this bit will indicate the status of the phy clock. note: the phy clock cannot be disabled if it is being used as the system clock. in device mode, the phy can be put into low power suspend?clock disable when the device is not running (usbcmd run/stop=0b) or the host has signaled suspend (portsc suspend=1b). low power suspend will be cleared automatically when the host has signaled resume if using a circuit similar to that in. before forcing a resume from the device, the device controller driver must clear this bit. in host mode, the phy can be put into low power suspend?clock disable when the downstream device has been put into suspend mode or when no downstream device is connected. low power suspend is completely under the control of software. see for more discussion on clock disable and power down issues. this bit is not defined in the ehci specification. wkoc wake on over-current enable (wkoc_e) ? read/write. default = 0b. writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. this field is zero if port power(pp) is zero. this bit is output from the controller as signal pwrctl_wake_ovrcurr_en (otg/host core only) for use by an external power control circuit. wkdc wake on disconnect enable (wkdscnnt_e) ? read/write. default=0b. writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. this field is zero if port power(pp) is zero or in device mode. this bit is output from the controller as signal pwrctl_wake_dscnnt_en (otg/host core only) for use by an external power control circuit. wkcn wake on connect enable (wkcnnt_e) ? read/write. default=0b. writing this bit to a one enables the port to be sensitive to device connects as wake-up events. this field is zero if port power(pp) is zero or in device mode. this bit is output from the controller as signal pwrctl_wake_dscnnt_en (otg/host core only) for use by an external power control circuit. ptc[3:0] port test control ? read/write. default = 0000b. any other value than zero indicates that the port is operating in test mode. value specific test 0000b test_mode_disable 0001b j_ state 0010b k_state 0011b se0 (host)/nak (device) 0100b packet 0101b force_enable_hs 0110b force_enable_fs 0111b force_enable_ls 1000b to 1111breserved refer to the usb specification revision 2.0 universal serial bus specification, revision 2.0, april 2000, compaq, hewlett-packard, intel, lucent, microsoft, nec, philips. http://www.usb.org for details on each test mode. the force_enable_fs and force enable_ls are extensions to the test mode support specified in the ehci specification. writing the ptc field to any of the force_enable_{hs/fs/ls} values will force the port into the connected and enabled state at the selected speed. writing the ptc field back to test_mode_disable will allow the port state machines to progress normally from that point. note: low-speed operations are not supported as a peripheral device. table 30-33. portscx field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-60 freescale semiconductor pic[1:0] port indicator control ? read/write. default = ob. writing to this field has no effect if the p_indicator bit in the hcsparams register is a zero. if p_indicator bit is a one, then the bit is: bit valuemeaning 00b port indicators are off 01b amber 10b green 11b undefined refer to the usb specification revision 2.0 universal serial bus specification, revision 2.0, april 2000, compaq, hewlett-packard, intel, lucent, microsoft, nec, philips. http://www.usb.org for a description on how these bits are to be used. this field is output from the controller as signals port_ind_ctl_1 and port_ind_ctl_0 for use by an external led driving circuit. po port owner?read/write. default = 0. this bit unconditionally goes to a 0 when the configured bit in the configflag register makes a 0 to 1 transition. this bit unconditionally goes to 1 whenever the configured bit is zero system software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). software writes a one to this bit when the attached device is not a high-speed device. a one in this bit means that an internal companion controller owns and controls the port. port owner handoff is not implemented in this design, therefore this bit will always be 0. pp port power (pp)?read/write or read only. the function of this bit depends on the value of the port power switching (ppc) field in the hcsparams register. the behavior is as follows: ppc pp operation 0b 0b read only? a device controller with no otg capability does not have port power control switches. 1b 1b/0b?rw. host/otg controller requires port power control switches. this bit represents the current setting of the switch (0=off, 1=on). when power is not available on a port (that is, pp equals a 0), the port is non-functional and will not report attaches, detaches, etc. when an over-current condition is detected on a powered port and ppc is a one, the pp bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). this feature is implemented in the host/otg controller (ppc = 1). in a device only implementation port power control is not necessary, thus ppc and pp = 0. ls[1:0] line status?read only. these bits reflect the current logical levels of the d+ (bit 11) and d- (bit 10) signal lines. the encoding of the bits are: bits [11:10]meaning 00b se0 10b j-state 01b k-state 11b undefined in host mode, the use of linestate by the host controller driver is not necessary (unlike ehci), because the port controller state machine and the port routing manage the connection of ls and fs. in device mode, the use of linestate by the device controller driver is not necessary. hsp high-speed port ? read only. default = 0b. when the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. note: hsp is redundant with pspd(27:26) but will remain in the design for compatibility. this bit is not defined in the ehci specification. table 30-33. portscx field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-61 pr port reset this field is zero if port power(pp) is zero. in host mode: read/write. 1=port is in reset. 0=port is not in reset. default 0. when software writes a one to this bit the bus-reset sequence as defined in the usb specification revision 2.0 is started. this bit will automatically change to zero after the reset sequence is complete. this behavior is different from ehci where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. in device mode: this bit is a read only status bit. device reset from the usb bus is also indicated in the usbsts register. susp suspend in host mode: read/write. 1=port in suspend state. 0=port not in suspend state. default=0. port enabled bit and suspend bit of this register define the port states as follows: bits [port enabled, suspend]port state 0x disable 10 enable 11 suspend when in suspend state, downstream propagation of data is blocked on this port, except for port reset. the blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. the host controller will unconditionally set this bit to zero when software sets the force port resume bit to zero. the host controller ignores a write of zero to this bit. if host software sets this bit to a one when the port is not enabled (that is, port enabled bit is a zero) the results are undefined. this field is zero if port power(pp) is zero in host mode. in device mode: read only. 1=port in suspend state. 0=port not in suspend state. default=0. in device mode this bit is a read only status bit. fpr force port resume ?read/write. 1= resume detected/driven on port. 0=no resume (k-state) detected/driven on port. default = 0. in host mode: software sets this bit to one to drive resume signaling. the host controller sets this bit to one if a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a one because a j-to-k transition is detected, the port change detect bit in the usbsts register is also set to one. this bit will automatically change to zero after the resume sequence is complete. this behavior is different from ehci where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. note that when the host controller owns the port, the resume sequence follows the defined sequence documented in the usb specification revision 2.0. the resume signaling (full-speed ?k?) is driven on the port as long as this bit remains a one. this bit will remain a one until the port has switched to the high-speed idle. writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to hs or fs idle. this field is zero if port power(pp) is zero in host mode. this bit is not-ehci compatible. in device mode: after the device has been in suspend state for 5ms or more, software must set this bit to one to drive resume signaling before clearing. the device controller will set this bit to one if a j-to-k transition is detected while the port is in the suspend state. the bit will be cleared when the device returns to normal operation. also, when this bit transitions to a one because a j-to-k transition detected, the port change detect bit in the usbsts register is also set to one. table 30-33. portscx field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-62 freescale semiconductor occ over-current change?r/wc. default=0. 1=this bit gets set to one when there is a change to over-current active. software clears this bit by writing a one to this bit position. for host/otg implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. for device-only implementations this bit shall always be 0. oca over-current active?read only. default 0. 1=this port currently has an over-current condition. 0=this port does not have an over-current condition. this bit will automatically transition from one to zero when the over current condition is removed. for host/otg implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. for device-only implementations this bit shall always be 0. pec port enable/disable change?r/wc. 1=port enabled/disabled status has changed. 0=no change. default = 0. in host mode: for the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the eof2 point. software clears this by writing a one to it. this field is zero if port power(pp) is zero. in device mode: the device port is always enabled. (this bit will be zero) pe port enabled/disabled?read/write. 1=enable. 0=disable. default 0. in host mode: ports can only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a one to this field. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. note that the bit status does not change until the port state actually changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. when the port is disabled, (0b) downstream propagation of data is blocked except for reset. this field is zero if port power(pp) is zero in host mode. in device mode: the device port is always enabled. (this bit will be one) csc connect status change?r/wc. 1 =change in current connect status. 0=no change. default 0. in host mode: indicates a change has occurred in the port?s current connect status. the host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (that is, the bit will remain set). software clears this bit by writing a one to it. this field is zero if port power(pp) is zero in host mode. in device mode: this bit is undefined in device controller mode. ccs current connect status?read only. in host mode: 1=device is present on port. 0=no device is present. default = 0. this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. this field is zero if port power(pp) is zero in host mode. in device mode: 1=attached. 0=not attached. default=0. a one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the high speed port bit in this register. a zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the run bit in the usbcmd register. it does not state the device being disconnected or suspended. table 30-33. portscx field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-63 30.8.1.5.13 otgsc address:base + 1a4h default value:00000020h attribute:ro, read/write, r/wc (field dependent) size:32 bits host controller a host controller implements one on-the-go (otg) status and control register corresponding to port 0 of the host controller. the otgsc register has four sections otg interrupt enables (read/write) otg interrupt status (read/write to clear) otg status inputs (read only) otg controls(read/write) the status inputs are debounced using a 1msec time consta nt. values on the status inputs that do not persist for more than 1msec will not cause an update of the status input register, or cause an otg interrupt. see also usbmode register. figure 30-33. otgsc?otg status control the register fields are desc ribed in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r d p i e 1 m s e b s ei e b s vi e a s vi e a v vi e id ie r d pi s 1 m s s b s ei s b s vi s a s vi s a v vi s i d is r d p s 1 m s t b s e b s v a s v a v v i d r i d p u d p o t r v c v d table 30-34. otgsc field descriptions field description dpie data pulse interrupt enable 1mse 1 millisecond timer interrupt enable?read/write bseie b session end interrupt enable?read/write. setting this bit enables the b session end interrupt. bsvie b session valid interrupt enable?read/write. setting this bit enables the b session valid interrupt. asvie a session valid interrupt enable?read/write. setting this bit enables the a session valid interrupt. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-64 freescale semiconductor avvie a vbus valid interrupt enable?read/write. setting this bit enables the a vbus valid interrupt. idie usb id interrupt enable?read/write. setting this bit enables the usb id interrupt. dpis data pulse interrupt status?read/write to clear. this bit is set when data bus pulsing occurs on dp or dm. data bus pulsing is only detected when usbmode.cm = host (11) and portsc(0).portpower = off (0). software must write a one to clear this bit. 1mss 1 millisecond timer interrupt status?read/write to clear. this bit is set once every millisecond. software must write a one to clear this bit. bseis b session end interrupt status?read/write to clear. this bit is set when vbus has fallen below the b session end threshold. software must write a one to clear this bit bsvis b session valid interrupt status?read/write to clear. this bit is set when vbus has either risen above or fallen below the b session valid threshold (0.8 vdc). software must write a one to clear this bit. asvis a session valid interrupt status?read/write to clear. this bit is set when vbus has either risen above or fallen below the a session valid threshold (0.8 vdc). software must write a one to clear this bit. avvis a vbus valid interrupt status?read/write to clear. this bit is set when vbus has either risen above or fallen below the vbus valid threshold (4.4 vdc) on an a device. software must write a one to clear this bit. idis usb id interrupt status?read/write. this bit is set when a change on the id input has been detected. software must write a one to clear this bit. dps data bus pulsing status?read only. a ?1? indicates data bus pulsing is being detected on the port. 1mst 1 millisecond timer toggle - read only. this bit toggles once per millisecond. bse b session end?read only. indicates vbus is below the b session end threshold. bsv b session valid?read only. indicates vbus is above the b session valid threshold. asv a session valid?read only. indicates vbus is above the a session valid threshold. avv a vbus valid?read only. indicates vbus is above the a vbus valid threshold. id usb id?read only. 0 = a device, 1 = b device table 30-34. otgsc field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-65 30.8.1.5.14 usbmode address:base + 1a8h default value:00000000h (otg implementation?mode not selected) 00000003h (host mode) 00000002h (device mode)) attribute:r/wo, read only size:32 bits figure 30-34. usbmode -usb device mode idpu id pullup?read/write this bit provide control over the id pull-up resister; 0 = off, 1 = on [default]. when this bit is 0, the id input will not be sampled. dp data pulsing?read/write. setting this bit causes the pullup on dp to be asserted for data pulsing during srp. ot otg termination?read/write. this bit must be set when the otg device is in device mode, this controls the pulldown on dm. vc vbus charge?read/write. setting this bit causes the vbus line to be charged. this is used for vbus pulsing during srp. vd vbus_discharge?read/write. setting this bit causes vbus to discharge through a resistor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved s sl e cm table 30-34. otgsc field descriptions (continued) field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-66 freescale semiconductor the register fields are desc ribed in the following table. 30.8.1.5.15 endptsetupstat address:base + 1ach default value:00000000h attribute:r/wc field description reserved reserved. these bits are reserved and should be set to zero. sdis stream disable mode. (0?inactive [default]; 1?active) device mode: setting to a ?1? disables double priming on both rx and tx for low bandwidth systems. this mode ensures that when the rx and tx buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. note: in high speed mode, all packets received will be responded to with a nyet handshake when stream disable is active. host mode: setting to a ?1? ensures that overruns/underruns of the latency fifo are eliminated for low bandwidth systems where the rx and tx buffers are sufficient to contain the entire packet. enabling stream disable also has the effect of ensuring the tx latency is filled to capacity before the packet is launched onto the usb. note: time duration to pre-fill the fifo becomes significant when stream disable is active. see txfilltuning and txttfilltuning [mph only] to characterize the adjustments needed for the scheduler when using this feature. note: the use of this feature substantially limits of the overall usb performance that can be achieved. slom setup lockout mode. in device mode, this bit controls behavior of the setup lock mechanism. see control endpoint operation model. 0?setup lockouts on (default); 1?setup lockouts off (dcd requires use of setup data buffer tripwire in usbcmd) es endian select?read/write. this bit can change the byte alignment of the transfer buffers to match the host microprocessor. the bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. bit meaning 0 little endian [default] 1big endian cm[1:0] controller mode?r/wo. controller mode is defaulted to the proper mode for host only and device only implementations. for those designs that contain both host and device capability, the controller will default to an idle state and will need to be initialized to the desired operating mode after reset. for combination host/device controllers, this register can only be written once after reset. if it is necessary to switch modes, software must reset the controller by writing to the reset bit in the usbcmd register before reprogramming this register. bit meaning 00 idle [default for combination host/device] 01 reserved 10 device controller [default for device only controller] 11 host controller [default for host only controller] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-67 size:32 bits figure 30-35. endptsetupstat?endpoint setup status the register fields are desc ribed in the following table. 30.8.1.5.16 endptprime address:base + 1b0h default value:00000000h attribute:r/ws size:32 bits figure 30-36. endptprime ?endpoint initialization this register is only used in device mode. the regi ster fields are described in the following table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 reserved endptsetupstat[15:0] field description reserved reserved. these bits are reserved and should be set to zero. endptsetupstat [15:0] setup endpoint status. for every setup transaction that is received, a corresponding bit in this register is set to one. software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from queue head. the response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock our mechanism is engaged. see managing endpoints in the device operational model. this register is only used in device mode. 313029282726252423222120191817161514131211109876543210 petb[15:0] perb[15:0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-68 freescale semiconductor 30.8.1.5.17 endptflush address:base + 1b4h default value:00000000h attribute:r/ws size:32 bits figure 30-37. endptflush?endpoint de-initialize this register is only used in device mode. the regi ster fields are described in the following table. field description petb [15:0] prime endpoint transmit buffer?r/ws. for each endpoint a corresponding bit is used to request that a buffer prepared for a transmit operation in order to respond to a usb in/interrupt transaction. software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. note: these bits will be momentarily set by hardware during hardware re-priming operations when a dtd is retired, and the dqh is updated. petb[15] ? endpoint #15 petb[1] ? endpoint #1 petb[0] ? endpoint #0 perb [15:0] prime endpoint receive buffer?r/ws. for each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a usb host initiates a usb out transaction. software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. note: these bits will be momentarily set by hardware during hardware re-priming operations when a dtd is retired, and the dqh is updated. bit 15 ? endpoint #15 bit 1 ? endpoint #1 bit 0 ? endpoint #0 313029282726252423222120191817161514131211109876543210 fetb[15:0] ferb[15:0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-69 30.8.1.5.18 endptstat address:base + 1b8h default value:00000000h attribute:read only size:32 bits figure 30-38. endptstat?endpoint status this register is only used in device mode. the regi ster fields are described in the following table. field description fetb [15:0] flush endpoint transmit buffer?r/ws. writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. if a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. hardware will clear this register after the endpoint flush operation is successful. fetb[15] ? endpoint #15 fetb[1] ? endpoint #1 fetb[0] ? endpoint #0 ferb [15:0] flush endpoint receive buffer?r/ws. writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. if a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. hardware will clear this register after the endpoint flush operation is successful. bit 15 ? endpoint #15 bit 1 ? endpoint #1 bit 0 ? endpoint #0 313029282726252423222120191817161514131211109876543210 etbr[15:0] erbr[15:0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-70 freescale semiconductor 30.8.1.5.19 endptcomplete address:base + 1bch default value:00000000h attribute:r/wc size:32 bits figure 30-39. endptcomplete?endpoint compete this register is only used in device mode. the regi ster fields are described in the following table. field description etbr [15:0] endpoint transmit buffer ready?read only. one bit for each endpoint indicates status of the respective endpoint buffer. this bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the endptprime register. there will always be a delay between setting a bit in the endptprime register and endpoint indicating ready. this delay time varies based upon the current usb traffic and the number of bits set in the endptprime register. buffer ready is cleared by usb reset, by the usb dma system, or through the endptflush register. note: these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dtd is retired, and the dqh is updated. etbr[15]? endpoint #15 etbr[1]? endpoint #1 etbr[0]? endpoint #0 erbr [15:0] endpoint receive buffer ready?read only. one bit for each endpoint indicates status of the respective endpoint buffer. this bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the endptprime register. there will always be a delay between setting a bit in the endptprime register and endpoint indicating ready. this delay time varies based upon the current usb traffic and the number of bits set in the endptprime register. buffer ready is cleared by usb reset, by the usb dma system, or through the endptflush register. note: these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dtd is retired, and the dqh is updated. erbr[15]? endpoint #15 erbr[1]? endpoint #1 erbr[0]? endpoint #0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 etce[15:0] erce[15:0] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-71 30.8.1.5.20 endptctrl0 address:base + 1c0h default value:0080008h attribute:read only, read/wr ite, r/wc (field dependent) size:32 bits every device will implement endpoint0 as a control endpoint. figure 30-40. endptctrl0?endpoint control 0 the register fields are desc ribed in the following table. field description etce [15:0] endpoint transmit complete event?r/wc. each bit indicates a transmit event (in/interrupt) occurred and software should read the corresponding endpoint queue to determine the endpoint status. if the corresponding ioc bit is set in the transfer descriptor, then this bit will be set simultaneously with the usbint . writing a one will clear the corresponding bit in this register. etce[15]? endpoint #15 etce[1]? endpoint #1 etce[0]? endpoint #0 erce [15:0] endpoint receive complete event?rw/c. each bit indicates a received event (out/setup) occurred and software should read the corresponding endpoint queue to determine the transfer status. if the corresponding ioc bit is set in the transfer descriptor, then this bit will be set simultaneously with the usbint . writing a one will clear the corresponding bit in this register. erce[15]? endpoint #15 erce[1]? endpoint #1 erce[0]? endpoint #0 313029282726252423222120191817161514131211109876543210 reserved t x e reserved txt r t x s reserved r x e reserv ed rx t r r x s field description reserved reserved. these bits are reserved and should be set to zero. txe tx endpoint enable 1?enabled endpoint0 is always enabled. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-72 freescale semiconductor 30.8.1.5.21 endptctrl1?endptctrl15 address:base + 1c0h+(4*(endpoint number)) default value:00000000h attribute:read/write size:32 bits there is an endptctrlx register for each endpoint in a device. figure 30-41. endptctrl1?endptctrl15?endpoint control 1 to 15 txt[1:0] tx endpoint type?read/write 00?control endpoint0 is fixed as a control end point. r reserved. bit reserved and should be set to zero. txs tx endpoint stall?read/write 0?end point ok [default] 1?end point stalled software can write a one to this bit to force the endpoint to return a stall handshake to the host. it will continue returning stall until the bit is cleared by software or it will automatically be cleared upon receipt of a new setup request. rxe rx endpoint enable 1?enabled endpoint0 is always enabled. rxt[1:0] rx endpoint type?read/write 00?control endpoint0 is fixed as a control end point. rxs rx endpoint stall?read/write 0?end point ok. [default] 1?end point stalled software can write a one to this bit to force the endpoint to return a stall handshake to the host. it will continue returning stall until the bit is cleared by software or it will automatically be cleared upon receipt of a new setup request. 313029282726252423222120191817161514131211109876543210 reserved t x e t x r t x i rtxt t x d t x s reserved r x e r x r r x i r rx t r x d r x s field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-73 caution : if one endpoint direction is en abled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (ie. bulk-type). leaving an unconfigured endpoint cont rol will cause undefined behavior for the data pid tracking on the active endpoint/direction. the register fields are desc ribed in the following table. field description reserved reserved. these bits are reserved and should be set to zero. txe tx endpoint enable 0?disabled [default] 1?enabled an endpoint should be enabled only after it has been configured. txr tx data toggle reset (ws) write 1?reset pid sequence whenever a configuration event is received for this endpoint, software must write a one to this bit in order to synchronize the data pid?s between the host and device. txi tx data toggle inhibit 0?pid sequencing enabled. [default] 1?pid sequencing disabled. this bit is only used for test and should always be written as zero. writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always transmit data0 for a data packet. r reserved. bit reserved and should be set to zero. txt[1:0] tx endpoint type?read/write 00?control 01?isochronous 10?bulk 11?interrupt txd tx endpoint data source?read/write 0?dual port memory buffer/dma engine [default] should always be written as 0. txs tx endpoint stall?read/write 0?end point ok 1?end point stalled this bit will be set automatically upon receipt of a setup request if this endpoint is not configured as a control endpoint. it will be cleared automatically upon receipt of a setup request if this endpoint is configured as a control endpoint. software can write a one to this bit to force the endpoint to return a stall handshake to the host. it will continue to returning stall until this bit is either cleared by software or automatically cleared as above. rxe rx endpoint enable 0?disabled [default] 1?enabled an endpoint should be enabled only after it has been configured. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-74 freescale semiconductor 30.8.1.6 otg operations 30.8.1.6.1 register bits in the previous section, the register interface has behaviors described for de vice mode and behaviors described for host mode. however, during otg operations it is necessary to perform tasks independent of the controller mode. note also from endptctrl1?endptctrl15?endpoint control 1 to 1542 that the only way to transition the controller mode out of host or device mode is with the controller reset bit. therefore, it is also necessary for the otg tasks to be performed inde pendent of a controller rese t as well as independent of the controller mode. rxr rx data toggle reset (ws) write 1?reset pid sequence whenever a configuration event is received for this endpoint, software must write a one to this bit in order to synchronize the data pid?s between the host and device. rxi rx data toggle inhibit 0 disabled [default] 1 enabled this bit is only used for test and should always be written as zero. writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packet regardless of their data pid. rxt[1:0] rx endpoint type?read/write 00 control 01 isochronous 10 bulk 11 reserved rxd rx endpoint data sink?read/write?tbd 0?dual port memory buffer/dma engine [default] should always be written as zero. rxs rx endpoint stall?read/write 0 end point ok. [default] 1 end point stalled this bit will be set automatically upon receipt of a setup request if this endpoint is not configured as a control endpoint. it will be cleared automatically upon receipt a setup request if this endpoint is configured as a control endpoint, software can write a one to this bit to force the endpoint to return a stall handshake to the host. it will continue to returning stall until this bit is either cleared by software or automatically cleared as above, field description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-75 figure 30-42. controller mode to this end, the listed below are the register bits that are used for otg operations, which are independent of the controller mode and are also not affected by a write to the reset bit in the usbcmd register: all identification registers all device/host capability registers otgsc: all bits portsc: physical interface select physical interface serial select physical interface data width physical interface low power physical interface wake signals port indicators port power 30.8.1.6.2 hardware assist the hardware assist provides auto mated response and sequencing that may not be possible to software with significant interrupt latency response times. the use of this additional circuitr y is optional and can be used to assist the 3 sequences below. auto-reset when the haar is set to one, the host will automatically start a reset after a connect event. this shortcuts the normal process where software is notified of the c onnect event and starts the reset. software will still receive notification of the connect event but should not write the reset bit when the haar is set. software will be notified again after the reset is complete via the enable change bit in the portsc register which cause a port change interrupt. this assist will ensure the otg parameter tb_acon_bse0_max = 1ms is met. idle (00) device (10) host (11) write ?10? to usbmode write ?11? to usbmode hardware reset or usbcmd.reset = 1 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-76 freescale semiconductor data-pulse writing a one to hadp will start a data pulse of approximately 7ms in duration and then automatically cease the data pulsing. during the data pulse, the dp will be set and then cleared. this automation relieves software from accurately controlli ng the data-pulse duration. during th e data pulse, the hcd can poll to see that the hadp and dp bit have returned low to recognize the completion or simply launch the data pulse and wait to see if a vbus valid interrupt occurs when the a-side supplies bus power. this assist will ensure data pulsing meets the otg requirement of > 5ms and < 10ms. b-disconnect to a-connect during hnp, the b-disconnect occurs from the otg a_ suspend state and within 3 ms, the device must enable the pullup on the dp leg in the a-peripheral st ate. when haba is set, the host controller port is in suspend mode, and the device disconnect s, then this hardware assist begins. 1. reset the otg core. 2. write the otg core into device mode. 3. write the device run bit to a 1 and enable necessary interrupts including: ? usb reset enable (ure); enables interrupt on usb bus reset to device ? sleep enable (sle); enables interrupt on device suspend ? port change detect enable (pce); enables interrupt on device connect when software has enabled this hardware assist, it must not interfere during the transition and should not write any register in the core until it gets an interr upt from the device controller signifying that a reset interrupt has occurred or at least first verify that the core has entered device mode. hcd/dcd must not activate the core soft reset at any time since this action is performed by hardware. during the transition, the software may see an interrupt from the disconnect and/or other spurious interrupts (i.e. sof/etc.) that may or may not cascade and my be cleared by the soft reset depending on the software response time. after the core has entered device mode by the ha rdware assist, the dcd must ensure that the endptlistaddr is programmed properly before the hos t sends a setup packet. since the end of the reset duration, which may be initiated quickly (a few microseconds) after connect, will require at a minimum 50 ms, this is the time for which the dcd must be ready to accept setup packets after having received notification that the reset has been detected or simply that the otg is in device mode which ever occurs first. in the case where the a-peripheral fails to see a reset after the controller enters device mode and engages the dp-pullup, the device controller interrupt the dcd signifying that a suspend has occurred. this assist will ensure the parameter ta_bdis_acon_max = 3ms is met. 30.8.2 host data structures this section defines the interface da ta structures used to communicate control, status, and data between hcd (software) and the enhanced host controller (h ardware). the data structure definitions in this chapter support a 32-bit memory buffer address space. the interface consists of a periodic schedule, high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-77 periodic frame list, asynchronous sc hedule, isochronous transaction de scriptors, split-transaction isochronous transfer descriptors, queue head s, and queue element transfer descriptors. the periodic frame list is the root of all periodic (i sochronous and interrupt transfer type) support for the host controller interface. the asynchronous list is the root for all the bulk and control transfer type support. isochronous data streams are managed using is ochronous transaction descriptors. isochronous split-transaction data streams are managed with split-transaction isoc hronous transfer descriptors. all interrupt, control, and bulk data streams are ma naged via queue heads and queue element transfer descriptors. these data structures are optimized to re duce the total memory foot print of the schedule and to reduce (on average) the number of memory accesses needed to execute a usb transaction. note that software must ensure that no interface data structure reachable by the ehci host controller spans a 4k-page boundary. the data structures defined in this section are (fro m the host controller?s perspective) a mix of read-only and read/writeable fields. the host controller must pr eserve the read-only fields on all data structure writes. 30.8.2.1 periodic frame list this schedule is for all periodic transfers (isochronous and interrupt). the periodic schedule is referenced from the operational registers space using the periodiclistbase address register and the frindex register. the periodic schedule is based on an a rray of pointers called the periodic frame list. the periodiclistbase address register is combined with the frindex register to produce a memory pointer into the frame list. the periodic frame list implements a sliding window of work over time. figure 30-43. periodic schedule organization 1 split transaction interrupt, bulk and control are also managed using queue heads and queue element transfer descriptors. the periodic frame list is a 4k-page aligned array of frame list link pointers. the length of the frame list may be programmable. the programmab ility of the periodic frame list is exported to system software via the hccparams register. if non-programmable, th e length is 1024 elements. if programmable, the length can be selected by system software as one of 256, 512, or 1024 elements. an implementation must high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-78 freescale semiconductor support all three sizes. programming the size (that is , the number of elements) is accomplished by system software writing the appropriate value into frame list size field in the usbcmd register. frame list link pointers dire ct the host controller to the first work item in the frame?s periodic schedule for the current micro-frame. the link pointers are a ligned on dword boundaries within the frame list. figure 30-44. format of frame list element pointer frame list link pointers always reference memory ob jects that are 32-byte aligned. the referenced object may be an isochronous transfer descriptor for high-sp eed devices, a split-transac tion isochronous transfer descriptor (for full-speed isoc hronous endpoints), or a queue head (used to support high-, full- and low-speed interrupt). system software should not place non-periodic schedule items into the periodic schedule. the least significant bits in a frame list point er are used to key the host controller as to the type of object the pointer is referencing. the least significant bit is the t-bit (bit 0). when this bit is set to a one, the host controller will never use the value of the frame list pointer as a physical memory pointer. the typ field is used to indicate the exact type of data structure being referenced by this pointer. the value encodings are: table 30-35. typ field value definitions 30.8.2.2 asynchronous list queue head pointer the asynchronous transfer list (based at the async listaddr register) is where all the control and bulk transfers are managed. host controllers use this list only when it reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 frame list link pointer 0 typ 03-0 value meaning 00b isochronous transfer descriptor 01b queue head 10b split transaction isochronous transfer descriptor. 11b frame span traversal node. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-79 figure 30-45. asynchronous schedule organization the asynchronous list is a simple circular list of queue heads. the asynclistaddr register is simply pointer to the next queue head. this implements a pure round-robi n service for all queue heads linked into the asynchronous list. 30.8.2.3 isochronous (high-speed) transfer descriptor (itd) the format of an isochronous transf er descriptor is illustrated in table 30-36 . this structure is used only for high-speed isochronous endpoints. all other transf er types should use queue structures. isochronous tds must be aligned on a 32-byte boundary. table 30-36. isochronous transfer descriptor 31302928272625242322212019181716 15 141312 11 10987654321 0 next link pointer 0 typ t 03-0 status transaction 0 length io pg* transaction 0 offset* 07-0 status transaction 1 length io pg* transaction 1 offset* 0b-0 status transaction 2 length io pg* transaction 2 offset* 0f-0 status transaction 3 length io pg* transaction 3 offset* 13-1 status transaction 4 length io pg* transaction 4 offset* 17-1 status transaction 5 length io pg* transaction 5 offset* 1b-1 status transaction 6 length io pg* transaction 6 offset* 1f-1 status transaction 7 length io pg* transaction 7 offset* 23-2 buffer pointer (page 0) endpt r device address 27-2 buffer pointer (page 1) i/ maximum packet size 2b-2 buffer pointer (page 2) reserved mult 2f-2 buffer pointer (page 3) reserved 33-3 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-80 freescale semiconductor note: *note: these fields may be modified by the host controller if the i/o field indicates an out. 30.8.2.3.1 next link pointer the first dword of an itd is a pointer to the next schedule data structure. table 30-37. next schedule element pointer 30.8.2.3.2 itd transaction status and control list dwords 1 through 8 are eight slots of transaction cont rol and status. each trans action description includes: ? status results field ? transaction length (bytes to send for out transa ctions and bytes received for in transactions). ? buffer offset. the pg and transaction x offset fields are used with th e buffer pointer list to construct the starting buffer address for the transaction. the host controller uses the information in each tr ansaction description plus the endpoint information contained in the first three dwords of the buffer pa ge pointer list, to execute a transaction on the usb. buffer pointer (page 4) reserved 37-3 buffer pointer (page 5) reserved 3b-3 buffer pointer (page 6) reserved 3f-3 host controller read/write host controller read only. bit description 31:5 link pointer (lp). these bits correspond to memory address signals [31:5], respectively. this field points to another isochronous transaction descriptor (itd/sitd) or queue head (qh). 4:3 reserved. these bits are reserved and their value has no effect on operation. software should initialize this field to zero. 2:1 qh/(s)itd select (typ). this field indicates to the host controller whether the item referenced is an itd, sitd or a qh. this allows the host controller to perform the proper type of processing on the item after it is fetched. value encodings are: valuemeaning 00b itd (isochronous transfer descriptor) 01b qh (queue head) 10b sitd (split transaction isochronous transfer descriptor 11b fstn (frame span traversal node) 0 terminate (t). 1= link pointer field is not valid. 0= link pointer field is valid. table 30-36. isochronous transfer descriptor (continued) 31302928272625242322212019181716 15 141312 11 10987654321 0 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-81 table 30-38. itd transaction status and control 30.8.2.3.3 itd buffer page pointer list (plus) dwords 9-15 of an isochronous transac tion descriptor are nominally page pointers (4k aligned) to the data buffer for this transfer descriptor. this data structur e requires the associated data buffer to be contiguous (relative to virtual memory), but allows the physic al memory pages to be non-contiguous. seven page bit description 31:28 status. this field records the status of the transaction executed by the host controller for this slot. this field is a bit vector with the following encoding: bit definition 31 active. set to one by software to enable the execution of an isochronous transaction by the host controller. when the transaction associated with this descriptor is completed, the host controller sets this bit to zero indicating that a transaction for this element should not be executed when it is next encountered in the schedule. 30 data buffer error. set to a one by the host controller during status update to indicate that the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). if an overrun condition occurs, no action is necessary. 29 babble detected. set to one by the host controller during status update when? babble? is detected during the transaction generated by this descriptor. 28 transaction error (xacterr). set to one by the host controller during status update in the case where the host did not receive a valid response from the device (timeout, crc, bad pid, etc.). this bit may only be set for isochronous in transactions. 27:16 transaction x length. for an out, this field is the number of data bytes the host controller will send during the transaction. the host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer. for an in, the initial value of the endpoint to deliver. during the status update, the host controller writes back the field is the number of bytes the host expects the number of bytes successfully received. the value in this register is the actual byte count (for example, 0 ? zero length data, 1 ? one byte, 2 ? two bytes, etc.). the maximum value this field may contain is 0xc00 (3072). 15 interrupt on complete (ioc). if this bit is set to one, it specifies that when this transaction completes, the host controller should issue an interrupt at the next interrupt threshold. 14:12 page select (pg). these bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. the valid range of values for this field is 0 to 6. 11:0 transaction x offset. this field is a value that is an offset, expressed in bytes, from the beginning of a buffer. this field is concatenated onto the buffer page pointer indicated in the adjacent pg field to produce the starting buffer address for this transaction. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-82 freescale semiconductor pointers are provided to support the expression of ei ght isochronous transfers. the seven pointers allow for 3 (transactions) * 1024 (maximum packet size) * 8 (transaction records) (24576 bytes) to be moved with this data structure, regardless of the alignment offset of the first page. since each pointer is a 4k aligned page pointer, the le ast significant 12 bits in several of the page pointers are used for other purposes. table 30-39. it buffer pointer page 0 (plus) table 30-40. itd buffer pointer page 1 (plus) table 30-41. itd buffer pointer page 2 (plus) bit description 31:12 buffer pointer (page 0). this is a 4k aligned pointer to physical memory. corresponds to memory address bits [31:12]. 11:8 endpoint number (endpt). this 4-bit field selects the particular endpoint number on the device serving as the data source or sink. 7 reserved. bit reserved for future use and should be initialized by software to zero. 6:0 device address. this field selects the specific device serving as the data source or sink. bit description 31:12 buffer pointer (page 1). this is a 4k aligned pointer to physical memory. corresponds to memory address bits [31:12]. 11 direction (i/o). 0 = out; 1 = in. this field encodes whether the high-speed transaction should use an in or out pid. 10:0 maximum packet size. this directly corresponds to the maximum packet size of the associated endpoint ( wmaxpacketsize ). this field is used for high-bandwidth endpoints where more than one transaction is issued per transaction description (for example, per micro-frame). this field is used with the multi field to support high-bandwidth pipes. this field is also used for all in transfers to detect packet babble. software should not set a value larger than 1024 (400h). any value larger yields undefined results. bit description 31:12 buffer pointer. this is a 4k aligned pointer to physical memory. corresponds to memory address bits [31:12]. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-83 table 30-42. itd buffer pointer page 3-6 30.8.2.4 split transaction isochronous transfer descriptor (sitd) all full-speed isochronous transfers through the internal transaction translator are managed using the sitd data structure. this data structure satisfies the operational requirements for managing the split transaction protocol. 11:2 reserved. this bit reserved for future use and should be set to zero. 1:0 multi. this field is used to indicate to the host controller the number of transactions that should be executed per transaction description (for example, per micro-frame). the valid values are: valuemeaning 00breserved. a zero in this field yields undefined results. 01bone transaction to be issued for this endpoint per micro- frame 10btwo transactions to be issued for this endpoint per micro- frame 11bthree transactions to be issued for this endpoint per micro-frame bit description 31:12 buffer pointer. this is a 4k aligned pointer to physical memory. corresponds to memory address bits [31:12]. 11:0 reserved. these bits reserved for future use and should be set to zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 next link pointer 0 typ t 03-0 i/o port number r hub addr r endpt r device address 07-0 reserved frame c-mask frame s-mask 0b-0 ioc p reserved total bytes to transfer frame c-prog-mask status 0f-0 buffer pointer (page 0) current offset 13-1 buffer pointer (page 1) reserved tp t- c o u 1 7 - 1 back pointer 0 t 1b-1 bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-84 freescale semiconductor figure 30-46. split-transaction isochronous transaction descriptor (sitd) 30.8.2.4.1 next link pointer dword0 of a sitd is a pointer to the next schedule data structure. table 30-43. next link pointer 30.8.2.4.2 sitd endpoint capabilities/characteristics dwords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent companion controller, and micro-frame scheduling control. table 30-44. endpoint and transaction translator characteristics host controller read/write host controller read only. bit description 31:5 next link pointer (lp). this field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. 4:3 reserved. these bits must be written as zeros. 2:1 qh/(s)itd select (typ). this field indicates to the host controller whether the item referenced is an itd/sitd or a qh. this allows the host controller to perform the proper type of processing on the item after it is fetched. value encodings are: valuemeaning 00bitd (isochronous transfer descriptor) 01bqh (queue head) 10bsitd (split transaction isochronous transfer descriptor 11bfstn (frame span traversal node) 0 terminate (t). 1=link pointer field is not valid. 0=link pointer is valid. bit description 31 direction (i/o).0 = out; 1 = in. this field encodes whether the full-speed transaction should be an in or out. 30:24 port number. this field is the port number of the recipient transaction translator. 23 reserved. bit reserved and should be set to zero. 22:16 hub address. this field holds the device address of the companion controllers? hub. 15:12 reserved. field reserved and should be set to zero. 11:8 endpoint number (endpt). this 4-bit field selects the particular endpoint number on the device serving as the data source or sink. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-85 table 30-45. micro-frame schedule control 30.8.2.4.3 sitd transfer state dwords 3-6 are used to manage the state of the transfer. table 30-46. sitd transfer status and control 7 reserved. bit is reserved for future use. it should be set to zero. 6:0 device address. this field selects the specific device serving as the data source or sink. bit description 31:16 reserved. this field reserved for future use. it should be set to zero. 15:8 split completion mask ( frame c-mask). this field (along with the active and splitx- state fields in the status byte) is used to determine during which micro-frames the host controller should execute complete-split transactions. when the criteria for using this field is met, an all zeros value has undefined behavior. the host controller uses the value of the three low-order bits of the frindex register to index into this bit fi eld. if the frindex register value indexes to a position where the frame c-mask field is a one, then this sitd is a candidate for transaction execution. there may be more than one bit in this mask set. 7:0 split start mask ( frame s-mask). this field (along with the active and splitx-state fields in the status byte) is used to determine during which micro-frames the host controller should execute start-split transactions. the host controller uses the value of the three low-order bits of the frindex register to index into this bit field. if the frindex register value indexes to a position where the frame s-mask field is a one, then this sitd is a candidate for transaction execution. an all zeros value in this field, in combination with existing periodic frame list has undefined results. bit description 31 interrupt on complete (ioc). 0 = do not interrupt when transaction is complete. 1 = do interrupt when transaction is complete. when the host controller determines that the split transaction has completed it will assert a hardware interrupt at the next interrupt threshold. 30 page select (p). used to indicate which data page pointer should be concatenated with the currentoffset field to construct a data buffer pointer (0 selects page 0 pointer and 1 selects page 1 ). the host controller is not required to write this field back when the sitd is retired ( active bit transitioned from a one to a zero). 29:26 reserved. this field reserved for future use and should be set to zero. 25:16 total bytes to transfer. this field is initialized by software to the total number of bytes expected in this transfer. maximum value is 1023 (3ffh) bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-86 freescale semiconductor 30.8.2.4.4 sitd buffer pointer list (plus) dwords 4 and 5 are the data buffer page pointers for th e transfer. this structure supports one physical page cross. the most significant 20 bits of each dword in this section are the 4k (page) aligned buffer pointers. the least significant 12 bits of each dwor d are used as additional transfer state. 15:8 frame complete-split progress mask (c-prog-mask). this field is used by the host controller to record which split-completes has been executed. 7:0 status. this field records the status of the transaction executed by the host controller for this slot. this field is a bit vector with the following encoding: bit definition 7 active. set to one by software to enable the execution of an isochronous split transaction by the host controller. 6 err. set to a one by the host controller when an err response is received from the companion controller. 5 data buffer error. set to a one by the host controller during status update to indicate that the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). in the case of an under run, the host controller will transmit an incorrect crc (thus invalidating the data at the endpoint). if an overrun condition occurs, no action is necessary. 4 babble detected. set to a one by the host controller during status update when? babble? is detected during the transaction generated by this descriptor. 3 transaction error (xacterr). set to a one by the host controller during status update in the case where the host did not receive a valid response from the device (timeout, crc, bad pid, etc.). this bit will only be set for in transactions. 2 missed micro-frame. the host controller detected that a host-induced hold- off caused the host controller to miss a required complete-split transaction. 1 split transaction state (splitxstate). the bit encodings are: valuemeaning 00bdo start split. this value directs the host controller to issue a start split transaction to the endpoint when a match is encountered in the s-mask. 01bdo complete split. this value directs the host controller to issue a complete split transaction to the endpoint when a match is encountered in the c-mask. 0 reserved. bit reserved for future use and should be set to zero. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-87 table 30-47. buffer page pointer list (plus) 30.8.2.4.5 sitd back link pointer dword 6 of a sitd is simply another schedule link point er. this pointer is always zero, or references a sitd. this pointer cannot reference any other schedule data structure. table 30-48. sitd back link pointer bit description 31:12 buffer pointer list. bits [31:12] of dwords 4 and 5 are 4k paged aligned, physical memory addresses. these bits correspond to physical address bits [31:12] respectively. the lower 12 bits in each pointer are defined and used as specified below. the field p specifies the current active pointer 11:0 page 0: current offset. the 12 least significant bits of the page 0 pointer is the current byte offset for the current page pointer (as selected with the page indicator bit ( p field)). the host controller is not required to write this field back when the sitd is retired ( active bit transitioned from a one to a zero). the least significant bits of page 1 pointer is split into three sub-fields page 1: bits description 11:5 reserved. 4:3 transaction position (tp). this field is used with t-count to determine whether to send all , first , middle , or last with each outbound transaction payload. system software must initialize this field with the appropriate starting value. the host controller must correctly manage this state during the lifetime of the transfer. the bit encodings are: value meaning 00b all. the entire full-speed transaction data payload is in this transaction (that is, less than or equal to 188 bytes). 01b begin. this is the first data payload for a full-speed that is greater than 188 bytes.transaction 10b mid. this is the middle payload for a full-speed out transaction that is larger than 188 bytes. 11b end. this is the last payload for a full-speed out transaction that was larger than 188 bytes. 2:0 transaction count (t-count). software initializes this field with the number of out start-splits this transfer requires. any value larger than 6 is undefined. bit description 31:5 sitd back pointer. this field is a physical memory pointer to a sitd. 4:1 reserved. this field is reserved for future use. it should be set to zero. 0 terminate (t). 1 = sitd back pointer field is not valid. 0 = sitd back pointer field is valid. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-88 freescale semiconductor 30.8.2.5 queue element transfer descriptor (qtd) this data structure is only used with a queue head. this data structure is used for one or more usb transactions. this data structure is used to tran sfer up to 20480 (5*4096) bytes. the structure contains two structure pointers used for queue advancement, a dword of transfer state, and a five-element array of data buffer pointers. this structure is 32 bytes (or one 32-byte cache line). this data structure must be physically contiguous. the buffer associated with this transfer must be virtually contiguous. the buffer may start on any byte boundary. a separate buffer pointer list element must be used for each physical page in the buffer, regardless of whether the buffer is physically contiguous. host controller updates (host controller writes) to st and-alone qtds only occur during transfer retirement. references in the following bit field definitions of updates to the qtd are to the qtd portion of a queue head. figure 30-47. queue element transfer descriptor block diagram queue element transfer descriptors must be aligned on 32-byte boundaries. 30.8.2.5.1 next qtd pointer the first dword of an element transfer descriptor is a pointer to another transfer element descriptor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 next qtd pointer 0 t 03-0 alternate next qtd pointer 0 t 07-0 dt total bytes to transfer io c_page cerr pi status 0b-0 buffer pointer (page 0) current offset 0f-0 buffer pointer (page 0) reserved 13-1 buffer pointer (page 0) reserved 17-1 buffer pointer (page 0) reserved 1b-1 buffer pointer (page 0) reserved 1f-1 host controller read/write host controller read only. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-89 table 30-49. d next element transfer pointer (dword 0) 30.8.2.5.2 alternate next qtd pointer the second dword of a queue element transfer descript or is used to support hardware-only advance of the data stream to the next client buffer on short packet. to be more explicit the host controller will always use this pointer when the current qtd is retired due to short packet. table 30-50. td alternate next element transfer pointer (dword 1) 30.8.2.5.3 qtd token the third dword of a queue element transfer descri ptor contains most of the information the host controller requires to execute a usb transaction (the remaining endpoint-addressing information is specified in the queue head). bit description 31:5 next transfer element pointer. this field contains the physical memory address of the next qtd to be processed. the field corresponds to memory address signals[31:5], respectively. 4:1 reserved. these bits are reserved and their value has no effect on operation. 0 terminate (t). 1= pointer is invalid. 0=pointer is valid (points to a valid transfer element descriptor). this bit indicates to the host controller that there are no more valid entries in the queue. bit description 31:5 alternate next transfer element pointer. this field contains the physical memory address of the next qtd to be processed in the event that the current qtd execution encounters a short packet (for an in transaction). the field corresponds to memory address signals [31:5], respectively. 4:1 reserved. these bits are reserved and their value has no effect on operation. 0 terminate (t). 1= pointer is invalid. 0=pointer is valid (points to a valid transfer element descriptor). this bit indicates to the host controller that there are no more valid entries in the queue. note the field descriptions forward reference fields defined in the queue head. where necessary, these forward references are preceded with a qh notation. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-90 freescale semiconductor table 30-51. qtd token (dword 2) bit description 31 data toggle. this is the data toggle sequence bit. the use of this bit depends on the setting of the data toggle control bit in the queue head. 30:16 total bytes to transfer. this field specifies the total number of bytes to be moved with this transfer descriptor. this field is decremented by the number of bytes actually moved during the transaction, only on the successful completion of the transaction. the maximum value software may store in this field is 5 * 4k (5000h). this is the maximum number of bytes 5 page pointers can access. if the value of this field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host controller executes a zero-length transaction and retires the transfer descriptor. it is not a requirement for out transfers that total bytes to transfer be an even multiple of qhd.maximum packet length. if software builds such a transfer descriptor for an out transfer, the last transaction will always be less than qhd.maximum packet length. although it is possible to create a transfer up to 20k this assumes the 1 st offset into the first page is 0. when the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16k**. therefore, the maximum recommended transfer is 16k(4000h). 15 interrupt on complete (ioc). if this bit is set to a one, it specifies that when this qtd is completed, the host controller should issue an interrupt at the next interrupt threshold. 14:12 current page (c_page). this field is used as an index into the qtd buffer pointer list. valid values are in the range 0h to 4h. the host controller is not required to write this field back when the qtd is retired. 11:10 error counter (cerr). this field is a 2-bit down counter that keeps track of the number of consecutive errors detected while executing this qtd. if this field is programmed with a non-zero value during set-up, the host controller decrements the count and writes it back to the qtd if the transaction fails. if the counter counts from one to zero, the host controller marks the qtd inactive, sets the halted bit to a one, and error status bit for the error that caused cerr to decrement to zero. an interrupt will be generated if the usb error interrupt enable bit in the usbintr register is set to a one. if hcd programs this field to zero during set-up, the host controller will not count errors for this qtd and there will be no limit on the retries of this qtd. note that write-backs of intermediate execution state are to the queue head overlay area, not the qtd. error decrement counter transaction error yes data buffer error no 3 stalled no 1 babble detected no 1 no error no 2 error decrement counter error decrement counter 1 detection of babble or stall automatically halts the queue head. thus, count is not decremented high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-91 2 if the eps field indicates a hs device or the queue head is in the asynchronous schedule (and pidcode indicates an in or out) and a bus transaction completes and the host controller does not detect a transaction error, then the host controller should reset cerr to extend the total number of errors for this transaction. for example, cerr should be reset with maximum value (3) on each successful completion of a transaction. the host controller must never reset this field if the value at the start of the transaction is 00b. see section split transaction execution state machine for interrupt for cerr adjustment rules when the eps field indicates a fs or ls device and the queue head is in the periodic schedule. see section asynchronous - do complete split for cerr adjustment rules when the eps field indicates a fs or ls device, the queue head is in the asynchronous schedule and the pidcode indicates a setup. 3 data buffer errors are host problems. they don't count against the device's retries. note: software must not program cerr to a value of zero when the eps field is programmed with a value indicating a full- or low-speed device. this combination could result in undefined behavior. 9:8 pid code. this field is an encoding of the token, which should be used for transactions associated with this transfer descriptor. encodings are: 00b out token generates token (e1h) 01b in token generates token (69h) 10b setup token generates token (2dh) (undefined if endpoint is an interrupt the queue head is non-zero.) transfer type, for example, frame s-mask field in 11b reserved 7:0 status. this field is used by the host controller to communicate individual command execution states back to hcd. this field contains the status of the last transaction performed on this qtd. the bit encodings are: bit status field description 7 active. set to one by software to enable the execution of transactions by the host controller. 6 halted. set to a one by the host controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qtd. this can be caused by babble, the error counter counting down to zero, or reception of the stall handshake from the device during a transaction. any time that a transaction results in the halted bit being set to a one, the active bit is also set to zero. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-92 freescale semiconductor 5 data buffer error. set to a one by the host controller during status update to indicate that the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). if an overrun condition occurs, the host controller will force a timeout condition on the usb, invalidating the transaction at the source. if the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 4 babble detected. set to a one by the host controller during status update when? babble? is detected during the transaction. in addition to setting this bit, the host controller also sets the halted bit to a one. since ?babble? is considered a fatal error for the transfer, setting the halted bit to a one insures that no more transactions occur because of this descriptor. 3 transaction error (xacterr). set to a one by the host controller during status update in the case where the host did not receive a valid response from the device (timeout, crc, bad pid, etc.). if the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 2 missed micro-frame. this bit is ignored unless the qh.eps field indicates a full- or low-speed endpoint and the queue head is in the periodic list. this bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. if the host controller sets this bit to a one, then it remains a one for the duration of the transfer. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-93 30.8.2.5.4 qtd buffer page pointer list the last five dwords of a queue element transfer descriptor is an array of physical memory address pointers. these pointers reference the individual pages of a data buffer. system software initializes current offset field to the starting offset into the current page, where current page is selected via the value in the c_page field. 1 split transaction state (splitxstate). this bit is ignored by the host controller unless the qh.eps field indicates a full- or low-speed endpoint. when a full- or low-speed device, the host controller uses this bit to track the state of the split- transaction. the functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. the bit encodings are: valuemeaning 0b do start split. this value directs the host controller to issue a start split transaction to the endpoint. 1b do complete split. this value directs the host controller to issue a complete split transaction to the endpoint. 0 ping state (p)/err. if the qh.eps field indicates a high-speed device and the pid_code indicates an out endpoint, then this is the state bit for the ping protocol. the bit encodings are: valuemeaning 0b do out. this value directs the host controller to issue an out pid to the endpoint. 1b do ping. this value directs the host controller to issue a ping pid to the endpoint. if the qh.eps field does not indicate a high-speed device, then this field is used as an error indicator bit. it is set to a one by the host controller whenever a periodic split-transaction receives an err handshake. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-94 freescale semiconductor table 30-52. qtd buffer pointer(s) (dwords 3-7) 30.8.2.6 queue head transfer overlaytransfer results bit description 31:12 buffer pointer list. each element in the list is a 4k page aligned physical memory address. the lower 12 bits in each pointer are reserved (except for the first one), as each memory pointer must reference the start of a 4k page. the field c_page specifies the current active pointer. when the transfer element descriptor is fetched, the starting buffer address is selected using c_page (similar to an array index to select an array element). if a transaction spans a 4k buffer boundary, the host controller must detect the page-span boundary in the data stream, increment c_page and advance to the next buffer pointer in the list, and conclude the transaction via the new buffer pointer. 11:0 current offset (reserved). this field is reserved in all pointers except the first one (for example, page 0). the host controller should ignore all reserved bits. for the page 0 current offset interpretation, this field is the byte offset into the current page (as selected by c_page). the host controller is not required to write this field back when the qtd is retired. software should ensure the reserved fields are initialized to zeros. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543 2 1 0 queue head horizontal link pointer 0 typ t 03-0 rl c maximum packet length h dt ep endpt i device address 07-0 mult port number* hub addr* frame c-mask* frame s-mask* 0b-0 current qtd pointer 00f-0 next qtd pointer 0 t 13-1 alternate next qtd pointer nak t 17-1 dt total bytes to transfer io c_page cerr pi status 1b-1 buffer pointer (page 0) current offset 1f-1 buffer pointer (page 1) reserved c-prog-mask* 23-2 buffer pointer (page 2) s-bytes* frameta 27-2 buffer pointer (page 3) reserved 2b-2 buffer pointer (page 4) reserved 2f-2 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-95 static endpoint state *these fields are used exclusively to support split transactions to usb 2.0 hubs figure 30-48. queue head structure layout queue head horizontal link pointer the first dword of a queue head cont ains a link pointer to the next data object to be processed after any required processing in this queue has been comple ted, as well as the control bits defined below. this pointer may reference a queue head or one of the isochronous transfer descriptors. it must not reference a queue element transfer descriptor. table 30-53. queue head dword 0 30.8.2.6.1 endpoint capab ilities/characteristics the second and third dwords of a queue head specifies static information about the endpoint. this information does not change over the lifetime of the endpoint. there are three types of information in this region: ? endpoint characteristics. these are the usb endpoint characteristics including addressing, maximum packet size, and endpoint speed. host controller read/write host controller read only. bit description 31:5 queue head horizontal link pointer (qhlp). this field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:5], respectively. 4:3 reserved. these bits must be written as zeros. 2:1 qh/(s)itd select (typ). this field indicates to the hardware whether the item referenced by the link pointer is an itd, sitd or a qh. this allows the host controller to perform the proper type of processing on the item after it is fetched. value encodings are: valuemeaning 00b itd (isochronous transfer descriptor) 01b qh (queue head) 10b sitd (split transaction isochronous transfer descriptor) 11b fstn (frame span traversal node) 0 terminate (t). 1=last qh (pointer is invalid). 0=pointer is valid. if the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that this is the end of the periodic list. this bit is ignored by the host controller when the queue head is in the asynchronous schedule. software must ensure that queue heads reachable by the host controller always have valid horizontal link pointers. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-96 freescale semiconductor ? endpoint capabilities. these are adjustable para meters of the endpoint. they effect how the endpoint data stream is ma naged by the host controller. ? split transaction characteristics. this data structure is used to manage full- and low-speed data streams for bulk, control, and interrupt via split transactions to usb2.0 hub transaction translator. there are additional fields used fo r addressing the hub and scheduling the protocol transactions (for periodic). the host controller must not modify the bits in this region. table 30-54. endpoint characteristics: queue head dword 1 bit description 31:28 nak count reload (rl). this field contains a value, which is used by the host controller to reload the nak counter field. 27 control endpoint flag (c). if the qh.eps field indicates the endpoint is not a high-speed device, and the endpoint is a control endpoint, then software must set this bit to a one. otherwise, it should always set this bit to a zero. 26:16 maximum packet length. this directly corresponds to the maximum packet size of the associated endpoint ( wmaxpacketsize ). the maximum value this field may contain is 0x400 (1024). 15 head of reclamation list flag (h). this bit is set by system software to mark a queue head as being the head of the reclamation list. 14 data toggle control (dtc). this bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b ignore dt bit from incoming qtd. host controller preserves dt bit in the queue head. 1b initial data toggle comes from incoming qtd dt bit. host controller replaces dt bit in the queue head from the dt bit in the qtd. 13:12 endpoint speed (eps). this is the speed of the associated endpoint. bit combinations are: value meaning 00b full-speed (12mbs) 01b low-speed (1.5mbs) 10b high-speed (480 mb/s) 11b reserved this field must not be modified by the host controller. 11:8 endpoint number (endpt). this 4-bit field selects the particular endpoint number on the device serving as the data source or sink. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-97 table 30-55. endpoint capabilities: queue head dword 2 7 inactivate on next transaction (i). this bit is used by system software to request that the host controller set the active bit to zero. see section rebalancing the periodic schedule for full operational details. this field is only valid when the queue head is in the periodic schedule and the eps field indicates a full or low-speed endpoint. setting this bit to a one when the queue head is in the asynchronous schedule or the eps field indicates a high-speed device yields undefined results. 6:0 device address. this field selects the specific device serving as the data source or sink. bit description 31:30 high-bandwidth pipe multiplier (mult). this field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. the host controller makes the simplifying assumption that software properly initializes this field (regardless of location of queue head in the schedules or other run time parameters). the valid values are: valuemeaning 00b reserved. a zero in this field yields undefined results. 01b one transaction to be issued for this endpoint per micro-frame 10b two transactions to be issued for this endpoint per micro-frame 11b three transactions to be issued for this endpoint per micro-frame 29:23 port number. this field is ignored by the host controller unless the eps field indicates a full- or low-speed device. the value is the port number identifier on the usb 2.0 hub (for hub at device address hub addr below), below which the full- or low-speed device associated with this endpoint is attached. this information is used in the split-transaction protocol. 22:16 hub addr. this field is ignored by the host controller unless the eps field indicates a full-or low-speed device. the value is the usb device address of the usb 2.0 hub below which the full- or low-speed device associated with this endpoint is attached. this field is used in the split-transaction protocol. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-98 freescale semiconductor 30.8.2.6.2 transfer overlay the nine dwords in this area represent a transaction working space for the host controller. the general operational model is that the host controller can detect whether the overlay area c ontains a description of an active transfer. if it does not contain an active transfer, then it follows the queue head horizontal link pointer to the next queue head. the host controller will never follow the next transfer queue element or alternate queue element pointers unless it is actively attempting to advance the queue. for the duration of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. when the transfer is complete, the results are written back to the original queue element. the dword3 of a queue head contains a pointer to th e source qtd currently associated with the overlay. the host controller uses this pointer to write back the overlay area into the source qtd after the transfer is complete. table 30-56. current qtd link pointer 15:8 split completion mask ( frame c-mask). this field is ignored by the host controller unless the eps field indicates this device is a low- or full-speed device and this queue head is in the periodic list. this field (along with the active and splitx-state fields) is used to determine during which micro-frames the host controller should execute a complete-split transaction. when the criteria for using this field are met, a zero value in this field has undefined behavior. this field is used by the host controller to match against the three low-order bits of the frindex register. if the frindex register bits decode to a position where the frame c- mask field is a one, then this queue head is a candidate for transaction execution. there may be more than one bit in this mask set. 7:0 interrupt schedule mask ( frame s-mask). this field is used for all endpoint speeds. software should set this field to a zero when the queue head is on the asynchronous schedule. a non-zero value in this field indicates an interrupt endpoint. the host controller uses the value of the three low-order bits of the frindex register as an index into a bit position in this bit vector. if the frame s-mask field has a one at the indexed bit position then this queue head is a candidate for transaction execution. if the eps field indicates the endpoint is a high-speed endpoint, then the transaction executed is determined by the pid_code field contained in the execution area. this field is also used to support split transaction types: interrupt (in/out). this condition is true when this field is non-zero and the eps field indicates this is either a full- or low-speed device. a zero value in this field, in combination with existing in the periodic frame list has undefined results. bit description 31:5 current element transaction descriptor link pointer. this field contains the address of the current transaction being processed in this queue and corresponds to memory address signals [31:5], respectively. 4:0 reserved (r). these bits are ignored by the host controller when using the value as an address to write data. the actual value may vary depending on the usage. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-99 the dwords 4-11 of a queue head are the transaction overlay area. this area has the same base structure as a queue element transfer descriptor. the queue head utilizes the reserved fields of the page pointers to implement tracking the state of split transactions. this area is characterized as an overlay because when the queue is advanced to the next queue element, the source queue element is merged onto this area. this area serves an execution cache for the transfer. table 30-57. host-controller rules for bits in overlay (dwords 5, 6, 8 and 9) 30.8.2.7 periodic frame span traversal node (fstn) this data structure is to be used only for mana ging full- and low-speed transactions that span a host-frame boundary. see section host controller op erational model for fstns for full operational details. software must not use an fstn in the asynchronous schedule. an fstn in the asynchronous schedule results in undefined behavi or. software must not use the fstn feature with a host controller whose hciversion register indi cates a revision implementation below 0096h. fstns are not defined for implementations before 0.96 and th eir use will yield undefined results. dword bit description 5 4:1 nak counter (nakcnt) rw. this field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a nak or nyet response. this counter is reloaded from rl before a transaction is executed during the first pass of the reclamation list (relative to an asynchronous list restart condition). it is also loaded from rl during an overlay. 6 31 data toggle. the data toggle control controls whether the host controller preserves this bit when an overlay operation is performed. 6 15 interrupt on complete (ioc). the ioc control bit is always inherited from the source qtd when the overlay operation is performed. 6 11:10 error counter (c_err). this two-bit field is copied from the qtd during the overlay and written back during queue advancement. 6 0 ping state (p)/err. if the eps field indicates a high-speed endpoint, then this field should be preserved during the overlay operation. 8 7:0 split-transaction complete-split progress (c-prog-mask). this field is initialized to zero during any overlay. this field is used to track the progress of an interrupt split-transaction. 9 4:0 split-transaction frame tag (frame tag). this field is initialized to zero during any overlay. this field is used to track the progress of an interrupt split-transaction. 9 11:5 s-bytes. software must ensure that the s-bytes field in a qtd is zero before activating the qtd . this field is used to keep track of the number of bytes sent or received during an in or out split transaction. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-100 freescale semiconductor figure 30-49. frame span traversal node structure layout 30.8.2.7.1 fstn normal path pointer the first dword of an fstn contains a link pointer to the next schedule object. this object can be of any valid periodic schedule data type. 30.8.2.7.2 fstn back path link pointer the second dword of an ftsn node contains a link pointer to a queue head. if the t-bit in this pointer is a zero, then this fstn is a save-place indicator. its typ field must be set by software to indicate the target data structure is a queue head. if the t-bit in this pointer is set to a one, then this fstn is the restore indicator. when the t-bit is a one, the host controller ignores the typ field. 3130 29 2827 26 25 24 23 22 2120 19 1817 16 15 14 13 12 11 109876543210 normal path link pointer 0 typ t 03-0 back path link pointer 0 typ t 07-0 host controller read/write host controller read only. bit description 31:5 normal path link pointer (nplp). this field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. 4:3 reserved. these bits must be written as 0s . 2:1 qh/(s)itd/fstn select (typ). this field indicates to the host controller whether the item referenced is a itd/sitd, a qh or an fstn. this allows the host controller to perform the proper type of processing on the item after it is fetched. value encodings are: valuemeaning 00bitd (isochronous transfer descriptor) 01bqh (queue head) 10bsitd (split transaction isochronous transfer descriptor) 11bfstn (frame span traversal node) 0 terminate (t). 1=link pointer field is not valid. 0=link pointer is valid. bit description 31:5 back path link pointer (bplp). this field contains the address of a queue head. this field corresponds to memory address signals [31:5], respectively. 4:3 reserved. these bits must be written as 0s. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-101 30.8.3 host operational model the general operational model is for the enhanced interface host controller hardware and enhanced interface host controller driver (generally referred to as system software). each significant operational feature of the ehci host controller is discussed in a separate section. each sec tion presents the operational model requirements for the host controller hardware. where appropriate, recommended system software operational models for features are also presented. 30.8.3.1 host controller initialization when the system boots, the host controller is enumer ated, assigned a base addre ss for the register space and bios sets the fladj register to a system-specific value. after initial power-on or hcreset (hardware or via hcreset bit in the usbcmd register), all of the operational registers will be at their default values, as illustrated in table 30-58 . after a hardware reset, only the opera tional registers not contained in the auxiliary power well will be at their default values. table 30-58. default values of operational register space 2:1 typ. software must ensure this field is set to indicate the target data structure is a queue head. any other value in this field yields undefined results. 0 terminate (t). 1=link pointer field is not valid (that is, the host controller must not use bits [31:5] (in combination with the ctrldssegment register if applicable) as a valid memory address). this value also indicates that this fstn is a restore indicator. 0=link pointer is valid (that is, the host controller may use bits [31:5] (in combination with the ctrldssegment register if applicable) as a valid memory address). this value also indicates that this fstn is a save-place indicator. operational register default value (after reset) usbcmd 00080000h (00080b00h if asynchronous schedule park capability is a one ) usbsts 00001000h usbintr 00000000h frindex 00000000h ctrldssegment 00000000h periodiclistbase undefined asynclistaddr undefined configflag 00000000h portsc 00002000h (w/ ppc set to one); 00003000h (w/ ppc set to a zero) bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-102 freescale semiconductor in order to initialize the host controller, software should perform the following steps ? program the ctrldssegment register with 4-giga byte segment where all of the interface data structures are allocated. ? write the appropriate value to the usbintr re gister to enable the appropriate interrupts. ? write the base address of the periodic frame list to the periodiclist base register. if there are no work items in the periodic schedule, all el ements of the periodic frame list should have their t-bits set to a one. ? write the usbcmd register to set the desired interrupt threshold, frame list size (if applicable) and turn the host controller on via setting the run/stop bit. ? write a 1 to configflag register to route all ports to the ehci controller (see section any time the usbcmd register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. ). at this point, the host controller is up and running and the port registers will begin reporting device connects, etc. system software can enumerate a port through the reset process (where the port is in the enabled state). at this point, the port is active with sofs occurring down the enabled port enabled high-speed ports, but the schedules have not yet been en abled. the ehci host controller will not transmit sofs to enabled full- or low-speed ports. in orde r to communicate with devices via the asynchronous schedule, system software must write the asyndlista ddr register with the a ddress of a control or bulk queue head. software must then enable the asynchronous schedule by writing a one to the asynchronous schedule enable bit in the usbcmd register. in orde r to communicate with devices via the periodic schedule, system software must enable the periodic schedule by writing a one to the periodic schedule enable bit in the usbcmd register. note that the schedules can be turned on before the first port is reset (and enabled). any time the usbcmd register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. 30.8.3.2 port routing and control a usb 2.0 host controller is comprised of one high- speed host controller, which implements the ehci programming interface and 0 to n usb 1.1 companion host controllers. companion host controllers (chcs) may be implementations of either univer sal or open host controller specifications. this configuration is used to deliver the required full us b 2.0-defined port capability; for example, low-, full-, and high-speed capability for every port. figure 30-50 illustrates a simple bl ock diagram of the port routing logic and its relationship to the high-speed and companion host controllers within a usb 2.0 host controller. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-103 figure 30-50. example usb 2.0 host controller port routing block diagram there exists one transceiver per physical port and each host controller module has its own port status and control registers. the ehci controller has port status and control registers for every port. each companion host controller has only the port control and status regi sters it is required to operate. each transceiver can be controlled by either the ehci host controller or one companion host controller. routing logic lies between the transceiver and the port status and control registers. 1 the port routing logic is controlled from signals orig inating in the ehci host controller. the ehci host controller has a global routing policy control field and per-port ownership control fields. the configured flag ( cf ) bit (defined in section burstsize) is the globa l routing policy control. at power-on or reset, the default routing policy is to the companion controlle rs (if they exist). if the system does not include a driver for the ehci host controller and the host controller includes companion controllers, then the ports will still work in full- and low-speed mode (assuming the system includes a driver for the companion controllers). in general, when the ehci owns the ports, the companion host controllers' port registers do not see a connect indication from the transceiver. s imilarly, when a companion host controller owns a port, the ehci controller's port registers do not see a connec t indication from the transceiver. the details on the rules for the port routing logic are described in the following sections. the usb 2.0 host controller must be implemented as a multi-function pci device if th e implementation includes companion controllers. the companion host controllers? function num bers must be less than the eh ci host controller function number. the ehci host controller must be a larger function number with respect to the companion host controllers associated with this ehci host controller. if a pci device implementation contains only an ehci controller (that is, no companion controllers or other pci functions), then the ehci host controller must be function zero, in accordance with the pci specification. the n_cc field in the structural parameter register ( hcsparams ) indicates whether the controller imp lementation includes companion host controllers. when n_cc has a non-zero value there exists companion host controllers. if n_cc has a value of zero, then the host controller implementation does not include comp anion host controllers. if the host controller root ports are exposed to attachment of full- or low-speed devices, the ports will always fail the high-speed chirp during reset and the ports will not be enabled. system software can notify the user of the illegal condition. this type of imp lementation requires a usb 2.0 hub be connected to a root port to provide full and low-speed device connectivity. 1.the routing logic should not be implemented in the 480 mhz clock domain of the transceiver. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-104 freescale semiconductor system software uses information in the host controller capability registers to determine how the ports are routed to the companion host controllers. see sec tion hcsparams?ehci compliant with extensions. 1 30.8.3.2.1 port routing control via ehci configured ( cf ) bit each port in the usb 2.0 host controller can be routed either to a single companion host controller or to the ehci host controller. the port routing logic is c ontrolled by two mechanisms in the ehci hc: a host controller global flag a nd per-port control. the configured flag ( cf ) bit (defined in section burstsize), is used to globally set the policy of the routing logic. each port register has a port owner control bit which allows the ehci driver to explicit ly control the routing of individual ports. whenever the cf bit transitions from a zero to a one (this transiti on is only available under program control) the port routing unconditionally routes all of the port registers to the ehci hc (all port owner bits go to zero). while the cf-bit is a one, the ehci driver can control individual ports' routing via the port owner control bit. likewise, whenever the cf bit transitions from a one to a zero (as a result of aux power application, hcreset , or software writing a zero to cf-bit ), the port routing unconditionally routes all of the port registers to the appropriate companion hc . the default value for the ehci hc?s cf bit (after aux power application or hcreset ) is zero. table 30-59 summarizes the default routi ng for all the ports, based on the value of the ehci hc?s cf bit . the view of the port depends on the current owner. a universal or open companion host controller will see port register bits consistent with the appropriate specification. port bit definitions that are required for ehci host controllers are not visible to companion host controllers. table 30-59. default port routing depending on ehci hc cf bit 1.if an implementation includes more than one set of companion and ehci host controllers, they are organized as groups of companion host controllers with intermixed ehci controllers. hs cf bit default port ownership explanation 0b companion hcs the companion host controllers own the ports and only full- and low-speed devices are supported in the system. the exact port assignments are implementation dependent. the ports behave only as full- and low-speed ports in this configuration 1b ehci hc the ehci host controller has default ownership over all of the ports. the routing logic inhibits device connect events from reaching the companion hcs' port status and control registers when the port owner is the ehci hc.the ehci hc has access to the additional port status and control bits defined in this specification (see section portscx). the ehci hc can temporarily release control of the port to a companion hc by setting the portowner bit in the portsc register to a one. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-105 30.8.3.2.2 port routing control via portowner and disconne ct event manipulating the port routing via the cf-bit is an extreme process and not intended to be used during normal operation. the normal m ode of port ownership transferal is on the granularity of individual ports using the port owner bit in the ehci hc?s portsc register (for hand-offs from ehci to companion host controllers). individual port ownership is returned to the ehci controller when the port registers a device disconnect. when the disconnect is detected, the port routing logic immediately returns the port ownership to the ehci controller. the companion host controlle r port register detects the device disconnect and operates normally. under normal operating conditions (a ssuming all hc drivers loaded and operational and the ehci cf-bit is set to a one), the typical port enumeration sequence proceeds as illustrated below: ? initial condition is that ehci is port owner. a device is connected causing the port to detect a connect, set the port connect change bit and issue a port-change interrupt (if enabled). ? ehci driver identifies the port with the new conne ct change bit asserted and sends a change report to the hub driver. hub driver issues a getportstatu s() request and identifies the connect change. it then issues a request to clear the connect change, followed by a request to reset and enable the port. ? when the ehci driver receives the request to rese t and enable the port, it first checks the value reported by the linestatus bits in the portsc register. if they indicate the attached device is a full-speed device (for example, d+ is asserted), then the ehci driver sets the portreset control bit to a one (and sets the portenable bit to a zero) which begins the reset-process. software times the duration of the reset, then terminates reset signaling by writing a zero to the port reset bit. the reset process is actually complete when software reads a zero in the portreset bit. the ehci driver checks the portowner bit in the portsc register. if set to a one, the connected device is a high-speed device and ehci driver (root hub emul ator) issues a change report to the hub driver and the hub driver continues to enumerate the attached device. ? at the time the ehci driver receives the port reset and enable request the linestatus bits might indicate a low-speed device. additionally, when the port reset process is complete, the portenable field may indicate that a full-speed device is attach ed. in either case the ehci driver sets the portowner bit in the portsc register to a one to release port ownership to a companion host controller. ? when the ehci driver sets portowner bit to a one, the port routing logic makes the connection state of the transceiver available to the companion host controller port register and removes the connection state from the ehci hc port. the eh ci portsc register observes and reports a disconnect event via the disconnect change bit. the ehci driver detects the connection status change (either by polling or by port change interr upt) and then sends a change report to the hub driver. when the hub driver requests that port-st ate, the ehci driver responds with a reset complete change set to a one, a connect change set to a one and a connect status set to a zero. this information is derived directly from the ehci port register. this will allow the hub driver to assume the device was disconnected during reset. it will acknowledge the change bits and wait for the next change event. while the ehci controller does not own the port, it simply remains in a state where the port reports no device connected. the device-connect evaluation circuitry of the comp anion hc activates and detects the device, the companion driver detects the connection and enumerates the port. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-106 freescale semiconductor when a port is routed to a companion hc, it remains under the control of the companion hc until the device is disconnected from the root port (ignoring for now the scenario where ehci's cf-bit transitions from a 1b to a 0b). when a disconnect occurs, the disc onnect event is detected by both the companion hc port control and the ehci port ownership control. on the event, the port ownership is returned immediately to the ehci controller. the compani on hc stack detects the disconnect and acknowledges as it would in an ordinary standa lone implementation. subs equent connects will be detected by the ehci port register and the process will repeat. 30.8.3.2.3 example port routing state machine figure 30-51 illustrates an example of how the port owners hip should be managed. the following sections describe the entry conditions to each state. figure 30-51. port owner handoff state machine ehci hc owner entry to this state occurs whenever one of the following events occur: ? when the ehci hc?s configure flag ( cf ) bit in the configflag register transitions from a zero to a one. this signals the fact that the system has a host controller driver for the ehci hc and that all ports in the usb 2.0 host controller must default route to the ehci controller. ? when the port is owned by a companion hc and the device is disconnected from the port. the ehci port routing control logic is notified of th e disconnect, and returns port routing to the ehci controller. the connection state of the compani on hc goes immediately to the disconnected state (with appropriate side effect to connect change , enable and enable change). the companion hc driver will acknowledge the disconne ct by setting the connect status change bit to a zero. this allows the companion hc's driver to interact with the port complete ly through the disconnect process. ? when system software writes a zero to the portowner bit in the portsc register. this allows software to take ownership of a port from a companion host controller. when this occurs, the routing logic to the companion hc effectively signals a disconnect to the companion hc's port status and control register. companion hc owner entry to this state occurs whenever one of the following events occur: ? when the port owner field transitions from a zero to a one. ? when the hs-mode hc?s configure flag ( cf ) is equal to zero. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-107 on entry to this state, the routing logic allows the companion hc port register to detect a device connect. normal port enumeration proceeds. 30.8.3.2.4 port power the port power control ( ppc ) bit in the hcsparams register indicates whether the usb 2.0 host controller has port power control (see section hcsparams?ehci compliant with extensions). when this bit is a zero, then the host controller does not support software control of port power switches. when in this configuration, the port power is always available and the companion host controllers must implement functionality consistent with port power always on. when the ppc bit is a one, then the host controller implementation includes por t power switches. each available switch has an output enable, which is referred to in this discussion as portpoweroutputenable ( ppe ). ppe is controlled based on the state of the combination bits ppc bit, ehci configured ( cf )-bit and individual port power ( pp ) bits. table 30-60 illustrates the summa ry behavioral model. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-108 freescale semiconductor table 30-60. port power enable control rules a) 1 ppe (port power enable). this bit actually turns on the port power switch (if one exists). a) 2 chc (companion host controller). a) 3 ehc (ehci host controller). 30.8.3.2.5 port reporting over-current host controllers are by definition power providers on usb. whether the ports are considered high- or low-powered is a platform implementation issue. each ehci portsc register has an over-current status and over-current change bit. the functionality of thes e bits is specified in the usb specification revision 2.0. the over current detection and limiting logic usually re sides outside the host controller logic. this logic may be associated with one or more ports. when this logic detects an over-current condition it is made available to both the companion and ehci ports. the ef fect of an over-current status on a companion host controller port is beyond the scope of this document. the over-current condition effects the following bits in the portsc register on the ehci port: cf chc 2 (pp) ehc 3 (pp) owner ppe 1 description 0 0 x chc 0 when the ehci controller has not been configured, the port is owned by the companion host controller. when the companion hc's port power select is off, then the port power is off. 0 1 x chc 1 similar to previous entry. when the companion hc's port power select is on, then the port power is on. 1 0 0 chc 0 port owner has port power turned off, the power to port is off. 1 0 0 ehc 0 port owner has port power turned off, the power to port is off. 1 0 1 ehc 1 port owner has port power on, so power to port is on. 1 0 1 chc 1 if either hc has port power turned on, the power to the port is on. 1 1 0 ehc 1 if either hc has port power turned on, the power to the port is on. 1 1 0 chc 1 port owner has port power on, so power to port is on. 1 1 1 chc 1 port owner has port power on, so power to port is on. 1 1 1 ehc 1 port owner has port power on, so power to port is on. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-109 ? over-current active bits are set to a one. when the over-current condition goes away, the over-current active bit will transition from a one to a zero. ? over-current change bits are set to a one. on every transition of the over-current active bit the host controller will set the over-current change bit to a one. software sets the over-current change bit to a zero by writing a one to this bit. ? port enabled/disabled bit is set to a zero. when this change bit gets set to a one, then the port change detect bit in the usbsts register is set to a one. ? port power (pp) bits may optionally be set to a zero. th ere is no requirement in usb that a power provider shut off power in an over cu rrent condition. it is sufficient to limit the current and leave power applied. when the over-current change bit transitions from a zero to a one, the host controller also sets the port change detect bit in the usbsts register to a one. in addition, if the port change interrupt enable bit in the usbintr register is a one, then the host controller will issue an interrupt to the system. refer to table 30-61 for summary behavior for over-current detection when the host controller is halted (sus pended from a device component point of view). 30.8.3.3 suspend/resume the ehci host controller provides an equivalent suspe nd and resume model as that defined for individual ports in a usb 2.0 hub. control mechanisms are provided to allow system software to suspend and resume individual ports. the mechanisms allow the individua l ports to be resumed completely via software initiation. other control mechanisms are provided to parameterize the host controller's response (or sensitivity) to external resume events. in this di scussion, host-initiated, or soft ware initiated resumes are called resume events/actions. bus-initiated resume events are called wake-up events. the classes of wakeup events are: ? remote-wakeup enabled device asserts resume signaling. in similar kind to usb 2.0 hubs, ehci controllers must always respond to explicit devi ce resume signaling and wake up the system (if necessary). ? port connect and disconne ct and over-current events. sensitivity to these events can be turned on or off by using the per-port control bits in the portsc registers. selective suspend is a feature supported by every portsc register. it is used to place specific ports into a suspend mode. this feature is used as a functi onal component for implementing the appropriate power management policy implemented in a particular operating system. when system software intends to suspend the entire bus, it should selectively suspend al l enabled ports, then shut off the host controller by setting the run/stop bit in the usbcmd register to a zero. th e ehci module can then be placed into a lower device state via the pci power management in terface (see appendix a, enhanced host controller interface specification for universal serial bu s, revision 0.95, november 2000, intel corporation. http://www.intel.com). when a wake event occurs the system will resume operation and system software will eventually set the run/stop bit to a one and resume the suspended ports. software must not set the run/stop bit to a one until it is confirmed that the clock to the host controller is stable. this is usually confirmed in a system implementation in that all of the clocks in the sy stem are stable before the cpu is restarted. so, by definition, if software is running, clocks in the system are stable and the run/stop bit in the usbcmd high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-110 freescale semiconductor register can be set to a one. there are also minimum system software delays defined in the pci power management specification. refer to this specification for more information. 30.8.3.3.1 port suspend/resume system software places individual ports into suspe nd mode by writing a one into the appropriate portsc suspend bit. software must only set the suspend bit when the port is in the enabled state ( port enabled bit is a one) and the ehci is the port owner ( port owner bit is a zero). the host controller may evaluate the suspend bit immediately or wait until a micro-frame or frame boundary occurs. if evaluated immediately, the port is not suspended until the current transaction (if one is executing) completes. therefore, there may be se veral micro-frames of activity on the port until the host controller evaluates the suspend bit. the host controller must evaluate the suspend bit at least every frame boundary. system software can initiate a resume on a selectively suspended port by writing a one to the force port resume bit. software should not attempt to resume a port unless the port reports that it is in the suspended state (see section portscx). if system software sets force port resume bit to a one when the port is not in the suspended state, the resulting behavior is unde fined. in order to assure proper usb device operation, software must wait for at least 10 milliseconds after a port indicates that it is suspended ( suspend bit is a one) before initiating a port resume via the force port resume bit. when force port resume bit is a one, the host controller sends resume signaling down the port. system software times the duration of the resume (nominally 20 milliseconds) then sets the force port resume bit to a zero. when the host controller receives the write to transition force port resume to zero, it completes the resume sequence as defined in the usb specification, and sets both the force port resume and suspend bits to zero. software-initiated port resumes do not affect the port change detect bit in the usbsts register nor do they cause an interrupt if the port change interrupt enable bit in the usbintr register is a one. an external usb event may also initiate a resume. the wake events are defi ned above. when a wake event occurs on a suspended port, the resume signaling is detected by the port and the resume is reflected downstream within 100 sec. the port's force port resume bit is set to a one and the port change detect bit in the usbsts register is set to a one. if the port change interrupt enable bit in the usbintr register is a one the host controller will issue a hardware interrupt. system software observes the resume event on the port, delays a port resume time (nominally 20 msec), then terminates the resume sequence by writing zero to the force port resume bit in the port. the host controller receives the write of zero to force port resume , terminates the resume sequence and sets force port resume and suspend port bits to zero. software can determine that the port is enabled (not suspended) by sampling the portsc register and observing that the suspend and force port resume bits are zero. software must ensure that the host controller is running (that is, hchalted bit in the usbsts register is a zero), before terminating a resume by writing a zero to a port's force port resume bit. if hchalted is a one when force port resume is set to a zero, then sofs will not occur down the enabled port and the device will return to suspend mode in a maximum of 10 milliseconds. table 30-61 summarizes the wake-up events. whenever a resume event is detected, the port change detect bit in the usbsts register is set to a one. if the port change interrupt enable bit is a one in the usbintr register, the host controller will also genera te an interrupt on the resume event. software high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-111 acknowledges the resume event interrupt by clearing the port change detect status bit in the usbsts register. [1] hardware interrupt issued if port change interrupt enable bit in the usbintr register is a one. [2] pme# asserted if enabled (note: pme status must always be set to a one). [3] pme# not asserted. table 30-61. behavior during wake-up events port status and signaling type signaled port response device state d0 not d0 port disabled, resume k-state received no effect n/a n/a port suspended, resume k-state received resume reflected downstream on signaled port. force port resume status bit in portsc register is set to a one. port change detect bit in usbsts register set to a one. [1], [2] [2] port is enabled, disabled or suspended, and the port's wkdscnnt_e bit is a one. a disconnect is detected. depending in the initial port state, the portsc connected enable status bits are set to zero, and the connect change status bit is set to a one. port change detect bit in the usbsts register is set to a one. [1], [2] [2] port is enabled, disabled or suspended, and the port's wkdscnnt_e bit is a zero. a disconnect is detected. depending on the initial port state, the portsc connect and enable status bits are set to zero, and the connect change status bit is set to a one. port change detect bit in the usbsts register is set to a one. [1], [3] [3] port is not connected and the port's wkcnnt_e bit is a one. a connect is detected. portsc connect status and connect status change bits are set to a one. port change detect bit in the usbsts register is set to a one. [1], [2] [2] port is not connected and the port's wkcnnt_e bit is a zero. a connect is detected. portsc connect status and connect status change bits are set to a one. port change detect bit in the usbsts register is set to a one. [1], [3] [3] port is connected and the port's wkoc_e bit is a one. an over-current condition occurs. portsc over-current active, over-current change bits are set to a one. if port enable/disable bit is a one, it is set to a zero. port change detect bit in the usbsts register is set to a one [1], [2] [2] port is connected and the port's wkoc_e bit is a zero. an over-current condition occurs. portsc over-current active, over-current change bits are set to a one. if port enable/disable bit is a one, it is set to a zero. port change detect bit in the usbsts register is set to a one. [1], [3] [3] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-112 freescale semiconductor 30.8.3.4 schedule traversal rules the host controller executes transactions for devi ces using a simple, shared-memory schedule. the schedule is comprised of a few data structures, organi zed into two distinct lists. the data structures are designed to provide the maximum flexibility required by usb, minimize memory traffic and hardware/software complexity. system software maintains two schedules for the hos t controller: a periodic schedule and an asynchronous schedule. the root of the periodic schedule is the periodiclistbase register (see section periodiclistbase; deviceaddr). the periodiclistbase register is the physical memory base address of the periodic frame list. the periodic frame list is an array of physical memory pointers. the objects referenced from the frame list must be valid schedule data structures as defined in host data structures. in each micro-frame, if the periodic schedule is enabled (see section periodic schedule ) then the host controller must execute from the periodic schedule before executing from the asynchronous schedule. it will only execute from the asynchronous sc hedule after it encounters the end of the periodic schedule. the host controller traverses the periodic sc hedule by constructing an array offset reference from the periodiclistbase and the frindex registers (see figure 30-52 ). it fetches the element and begins traversing the graph of linked schedule data structures. the end of the periodic schedule is identified by a next link pointer of a schedule data structure having its t-bit set to a one. when the host controller encounters a t-bit set to a one during a horizontal traversal of the periodic list, it interprets this as an end-of-periodic-list mark. this causes the host controller to cease working on the periodic schedule and transitions immediately to traversing the asynchronous schedule. once this transition is made, the host controller ex ecutes from the asynchronous schedule until the end of the micro-frame. figure 30-52. derivation of pointer into frame list array when the host controller determines that it is time to execute from the asynchronous list, it uses the operational register asynclistaddr to access the asynchronous schedule, see figure 30-53 . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-113 figure 30-53. general format of asynchronous schedule list the asynclistaddr register contains a physical memory pointer to the next queue head. when the host controller makes a transition to executing the asynchr onous schedule, it begins by reading the queue head referenced by the asynclistaddr register. software must set queue head horizontal pointer t-bits to a zero for queue heads in the asynchronous schedule. see section asynchronous schedule for complete operational details. 30.8.3.4.1 example?preserving micro-frame integrity one of the requirements of a usb host controller is to maintain frame integrity . this means that the hc must preserve the micro-frame boundaries. for example: sof packets must be generated on time (within the specified allowable jitter), and high-speed eof1,2 thresholds must be enforced. the end of micro-frame timing points eof1 and eof2 are clearl y defined in the usb specification revision 2.0. one implication of this responsibility is that the hc must ensure that it does not start transactions that will not be completed before the end of the micro-frame. more precisely, no transactions should be started by the host controller, which cannot be completed in their entirety before the eof1 point. in order to enforce this rule, the host controller must check each transaction before it starts to ensure that it will complete before the end of the micro-frame. so, what exactly needs to be involved in this check? fundamentally, the transacti on data payload, plus bit stuffing, plus transaction overhead must be taken into consideration. it is possibl e to be extremely accurate on how much time the next transaction will take. take outs for an example. the host controller must fetch all of the out data from memory in order to se nd it onto the usb bus. a host controller implementation could pre-fetch all of the out data, and pre-compute the actual number of bits in the token and data packets. in addition, the system knows the depth of the target endpoint, so it could closely estimate turnaround time for handshake. in addition, the host c ontroller knows the size of a handshake packet. pre-computing effects of bit stuffing and summing up the other overhead numbers could allow the host controller to know exactly whethe r there was enough bus time, before eof1 to complete the out transaction. to accomplish this particular approach takes an inordinate am ount of time and hardware complexity. the alternative is to make a reasonable guess whethe r the next transaction can be started. an example approximation algorithm is described below. this example algorithm relies on the ehci policy that periodic transactions are scheduled first in the micro-frame. it is a reasonable assumption that software will high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-114 freescale semiconductor never over-commit the micro-frame to periodic transac tions greater than the specification allowable 80%. in the available remaining 20% bandwidth, the host controller has some ability (in this example) to decide whether or not to execute a transaction. the result of this algorithm is that sometimes, under some circumstances a transaction will not be executed that could have been executed. however, under all circumstances, a transaction will never be started unl ess there is enough time in th e frame to complete the transaction. transaction fit - a best-fit approximation algorithm a curve is calculated which represents the latest start time for every packet size, at which software will schedule the start of a periodic transaction. this cu rve is the 80% bandwidth curve. another curve is calculated which is the absolute, latest permitted start time for every packet size. this curve represents the absolute latest time, that a transaction of each packet size can be started and completed, in the micro-frame. a plot of these two curves is illustrated in figure 30-54 . the plot y-axis represents the number of byte-times left in a frame. the space between the 80% and the last start plots is bandwidth reclamation area. in this algorithm the host controller may skip transactions during this time if it is prudent. the best-fit approximation method plots a function ( f ( x )) between the 80% and last start curves. the function f ( x ) adds a constant to every transaction's maximum packet size and the result compared with the number of bytes left in the frame. the constant repr esents an approximation of the effects of bit stuffing and protocol overhead. the host controller starts transactions whose results land above the function curve. the host controller will not start transactions whose results land below the function curve. figure 30-54. best fit approximation the laststart line was calculated in this example to assume the absolute worst-case bus overhead per transaction. the particular transaction used was a start-split, zero-length out transaction with a high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-115 handshake. summaries of the component parts are listed in figure 30-62 . the component times were derived from the protocol timings defined in the usb specification revision 2.0. table 30-62. example worse-case transaction timing components the exact details of the function (f(x)) are up to the particular implementation. however, it should be obvious that the goal is to minimize the area under the curve between the approximation function and the last start curve, without dipping below the laststart line, while at the same time keeping the check as simple as possible for hardware implementation. the f(x) in figure was constructed using the following pseudo-code test on each transacti on size data point. this algorithm a ssumes that the host controller keeps track of the remaining bits in the frame. algorithm checktransactionwillfit (maximumpacketsize, hc_bytesleftinframe) begin local temp = maximumpacketsize + 192 local rvalue = true if maximumpacketsize >= 128 then temp += 128 end if if temp > hc_bytesleftinframe then rvalue = false end if component bit time byte time explanation split token 76 9.5 split token as defined in usb core specification. includes sync, token, eop, etc. host 2 host ipg 88 11 number of bit times required between consecutive host packets. token 67 8.375 token as defined in usb core specification. includes sync, token, eop, etc. host 2 host ipg 88 11 same as above data packet (0 data bytes) 66.7 8.34 zero-length data packet. includes sync, pid, crc16, eop, etc. turnaround time 721 90.125 time for packet initiator (host) to see the beginning of a response to a transmitted packet. handshake packet 48 6 handshake packet as defined in usb core specification. includes sync, pid, eop, etc. 144 total high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-116 freescale semiconductor return rvalue end this algorithm takes two inputs, the current maximu m packet size of the transaction and a hardware counter of the number of bytes left in the current mi cro-frame. it unconditionally adds a simple constant of 192 to the maximum packet size to account for a first-order effect of transaction overhead and bit stuffing. if the transaction size is greater than or equal to 128 bytes, then an additional constant of 128 is added to the running sum to account for the additional worst-case bit stuffing of payloads larger than 128. an inflection point was inserted at 128 because the f ( x ) plot was getting close to the laststart line. 30.8.3.5 periodic schedule frame boundaries vs bus frame boundaries the usb specification revision 2.0 requires that th e frame boundaries (sof frame number changes) of the high-speed bus and the full- and low-speed bus(s) below usb 2.0 hubs be strictly aligned. super-imposed on this requirement is that usb 2.0 h ubs manage full- and low-speed transactions via a micro-frame pipeline (see start- (ss) and complete- (cs) splits illustrated in figure 30-55 ). a simple, direct projection of the frame boundary model into the host controller interface schedule architecture creates tension (complexity for both hardware and software) between the frame boundaries and the scheduling mechanisms required to service the full- and low-speed transaction translator periodic pipelines. figure 30-55. frame boundary relationship between hs bus and fs/ls bus the simple projection, as figure 30-55 illustrates, introduces frame-boundary wrap conditions for scheduling on both the beginning and end of a frame. in order to reduce the complexity for hardware and software, the host controller is required to implement a one micro-frame phase shift for its view of frame boundaries. the phase shift elimina tes the beginning of frame and frame-wrap scheduling boundary conditions. the implementation of this phase shift requires that th e host controller use one register value for accessing the periodic frame list and another value for the fram e number value included in the sof token. these two values are separate, but tightly coupled. the periodi c frame list is accessed via the frame list index register (frindex) documented in section frinde x and initially illustrated in section schedule traversal rules . bits frindex[2:0], represent the micro-frame number. the sof value is coupled to the value of frindex[13:3]. both frindex[13:3] and the sof value are increment based on frindex[2:0]. it is required that the sof va lue be delayed from the frindex value by one micro-frame. the one micro-frame delay yields hos t controller periodic schedule and bus frame boundary relationship as illustrated in figure 30-56 . this adjustment allows software to trivially schedule the high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-117 periodic start and complete-split transactions for fu ll-and low-speed periodic endpoints, using the natural alignment of the periodic schedule interface. the re asons for selecting this phase-shift are beyond the scope of this specification. figure 30-56 illustrates how periodic schedule data structur es relate to schedule frame boundaries and bus frame boundaries. to aid the presentation, two terms are defined. the host controller's view of the 1-millisecond boundaries is called h-frames . the high-speed bus's view of the 1-millisecond boundaries is called b-frames . figure 30-56. relationship of periodic schedule frame boundaries to bus frame boundaries h-frame boundaries for the host controller correspond to increments of frindex[13:3]. micro-frame numbers for the h-frame are tracked by frindex[2:0]. b-frame boundaries are visible on the high-speed bus via changes in the sof token's frame number. micro-frame numbers on the high-speed bus are only derived from the sof token's frame number (tha t is, the high-speed bus will see eight sofs with the same frame number value). h-frames and b-frames have the fixed relationship (that is, b-frames lag h-frames by one micro-frame time) illustrated in figure 30-56 . the host controller's periodic schedule is naturally aligned to h-frames . software schedules transactions for full- and low-speed periodic endpoints relative the h-frames . the result is these transactions execute on the high-speed bus at exactly the right time for the usb 2.0 hub periodic pipeline. as described in section frindex, the sof value can be implemented as a shadow register (in this example, called sofv), which lags the frindex register bits [13:3] by one micro-frame count. table 30-63 illustrates the required relationship between the value of frindex and the value of sofv. this la g behavior can be accomplished by incrementing frindex[13:3] based on carry-out on the 7 to 0 in crement of frindex[2:0] and incrementing sofv based on the transition of 0 to 1 of frindex[2:0]. software is allowed to write to frindex. section frindex provides the requirements that software should adhere when writing a new value in frindex. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-118 freescale semiconductor table 30-63. operation of frindex and sofv (sof value register) where [f] = [13:3]; [ f] = [2:0] 30.8.3.6 periodic schedule the periodic schedule traversal is enabled or disabled via the periodic schedule enable bit in the usbcmd register. if the periodic schedule enable bit is set to a zero, then the host controller simply does not try to access the periodic frame list via the periodiclistbase register. likewise, when the periodic schedule enable bit is a one, then the host controller does use the periodiclistbase register to traverse the periodic schedule. the host controller will not react to modifications to the periodic schedule enable immediately. in order to eliminate conflicts with split transactions, the host controller evaluates the periodic schedule enable bit only when frindex[2:0] is zero. sy stem software must not disable the periodic schedule if the schedule contains an activ e split transaction work item that spans the 000b micro-frame. these work items must be removed from the schedule before the periodic schedule enable bit is written to a zero. the periodic schedule status bit in the usbsts register indicates status of the periodic schedule. system software enables (or disables) the pe riodic schedule by writing a one (or zero) to the periodic schedule enable bit in the usbcmd register. software then can poll the periodic schedule status bit to determine when the periodic schedule has made the desired transition. software must not modify the periodic schedule enable bit unless the value of the periodic schedule enable bit equals that of the periodic schedule status bit. the periodic schedule is used to manage all isochronous and interrupt transfer streams. the base of the periodic schedule is the periodic fram e list. software links schedule data structures to the periodic frame list to produce a graph of scheduled data structures. the graph repres ents an appropriate sequence of transactions on the usb. figure illustrates isochronous transfers (usi ng itds and sitds) with a period of one are linked directly to the periodic frame list. inte rrupt transfers (are manage d with queue heads) and isochronous streams with periods other than one are linked following the period-one itd/sitds. interrupt queue heads are linked into the frame list ordered by poll rate. longer poll rates are linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the very end. current next frindex[f] sofv frindex[mf] frindex[f] sofv frindex[mf] n n 111b n+1 n 000b n+1 n 000b n+1 n+1 001b n+1 n+1 001b n+1 n+1 010b n+1 n+1 010b n+1 n+1 011b n+1 n+1 011b n+1 n+1 100b n+1 n+1 100b n+1 n+1 101b n+1 n+1 101b n+1 n+1 110b n+1 n+1 110b n+1 n+1 111b high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-119 figure 30-57. example periodic schedule 30.8.3.7 managing isochronous transfers using itds the structure of an itd is presented in isochronous (high-speed) transfer descriptor (itd). there are four distinct sections to an itd: ? the first field is the next link pointer . this field is for schedule linkage purposes only; ? transaction description array. this area is an ei ght-element array. each element represents control and status information for one micro-frame's worth of transactions for a single high-speed isochronous endpoint. ? the buffer page pointer array is a 7-element a rray of physical memory pointers to data buffers. these are 4k aligned pointers to physical memory. ? endpoint capabilities. this area utilizes the unused low-order 12 bits of the buffer page pointer array. the fields in this area are used across all transactions executed for this itd, including endpoint addressing, transfer direction, maximu m packet size and high-bandwidth multiplier. 30.8.3.7.1 host controller operational model for itds the host controller uses frindex register bits [12:3] to index into the periodic frame list. this means that the host controller visits each frame list elemen t eight consecutive times before incrementing to the next periodic frame list element. each itd contains ei ght transaction descriptions, which map directly to frindex register bits [2:0]. each itd can span 8 micro-frames worth of transactions. when the host controller fetches an itd, it uses frindex register bits [2:0] to index into the transaction description array. if the active bit in the status field of the indexed transaction de scription is set to zero, the host controller ignores the itd and follows the next pointer to the next schedule data structure. when the indexed active bit is a one the host controller continues to parse the itd. it stores the indexed transaction description and the general endpoint info rmation (device address, endpoint number, maximum high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-120 freescale semiconductor packet size, etc.). it also uses the page select (pg) field to index the buffer pointer array, storing the selected buffer pointer and the next sequential buffer pointer . for example, if pg field is a 0, then the host controller will store page 0 and page 1. the host controller constructs a physical data buffer address by concatenating the current buffer pointer (as selected using the current transaction description's pg field) and the transaction description's transaction offset field. the host controller uses the endpoint addressing information and i/o-bit to execute a transaction to the appropriate endpoint. wh en the transaction is complete, the host controller clears the active bit and writes back any additional status information to the status field in the currently selected transaction description. the data buffer associated with the itd must be virtually contiguous memory. seven page pointers are provided to support eight high-bandwidth transactions regardless of the starting packet?s offset alignment into the first page. a starting buffer pointer (physical memory address) is cons tructed by concatenating the page pointer (example: page 0 pointer) sele cted by the active transaction descriptions? pg (example value: 00b) field with the transaction offset field. as the tr ansaction moves data, the host controller must detect when an increment of the current buffer pointer w ill cross a page boundary. when this occurs the host controller simply replaces the current buffer pointer?s page portion with the next page pointer (example: page 1 pointer) and continues to move data. the size of each bus transa ction is determined by the value in the maximum packet size field. an itd supports high-bandwidth pipes via the mult (multiplier) field. when the mult field is 1, 2, or 3, the host controller executes the specified number of maximum packet sized bus transactions for the endpoint in the current micro-frame. in other words, the mult field represents a transaction count for the endpoint in the current micro-frame. if the mult field is zero, the operation of the host controller is undefined. the transfer description is used to service all transactions indicated by the mult field. for out transfers, the value of the transaction x length field represents the total bytes to be sent during the micro-frame. the mult field must be set by software to be consistent with transaction x length and maximum packet size. the host controller will send the bytes in maximum packet size d portions. after each transaction, the host controller decrements it's local copy of transaction x length by maximum packet size . the number of bytes the host controller sends is always maximum packet size or transaction x length , whichever is less. the host controller advances the transfer state in the transfer description, updates the appropriate record in th e itd and moves to the next sche dule data structure. the maximum sized transaction supported is 3 x 1024 bytes. for in transfers, the host controller issues mult transactions. it is assumed that software has properly initialized the itd to accommodate all of the possible data. during each in transaction, the host controller must use maximum packet size to detect packet babble errors. the host controller keeps the sum of bytes received in the transaction x length field. after all transactions for the endpoint have completed for the micro-frame, transaction x length contains the total bytes received. if the final value of transaction x length is less than the value of maximum packet size , then less data than was allowed for was received from the associated endpoint. this short packet condition does not set the usbint bit in the usbsts register to a one. the host controller will not detect this condition. if the device sends more than transaction x length or maximum packet size bytes (whichever is less), then the host controller will set the babble detected bit to a one and set the active bit to a zero. note, that the host controller is not required to update the itd field transaction x length in this error scenario. if the mult field is greater than one, high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-121 then the host controller will au tomatically execute the value of mult transactions. the host controller will not execute all mult transactions if: ? the endpoint is an out and transaction x length goes to zero before all the mult transactions have executed (ran out of data), or ? the endpoint is an in and the endpoint delivers a short packet, or an error occurs on a transaction before mult transactions have been executed. the end of micro-frame may occur before all of the transaction opportunities have been executed. when this happens, the transfer state of the transfer description is advanced to reflect the progress that was made, the result written back to the itd and the host controller proceeds to processing the next micro-frame. refer to appendix d for a table summary of the host controller required behavior for all the high-bandwidth transaction cases. 30.8.3.7.2 software operational model for itds a client buffer request to an isochronous endpoint may span 1 to n micro-frames. when n is larger than one, system software may have to use multiple itds to read or write data with the buffer (if n is larger than eight, it must use more than one itd). figure illustrates the simple model of how a client buf fer is mapped by system software to the periodic schedule (that is, the periodic frame list and a set of it ds). on the right is the client description of its request. the description includes a buffer base addr ess plus additional annota tions to identify which portions of the buffer should be used with each bus tr ansaction. in the middle is the itd data structures used by the system software to service the client reque st. each itd can be initialized to service up to 24 transactions, organized into eight groups of up to three transactions each. each group maps to one micro-frame's worth of transactions. the ehci contro ller does not provide per-transaction results within a micro-frame. it treats the per-micro-frame transactions as a single logical transfer. on the left is the host controller?s frame list. system software establishes re ferences from the appropriate locations in the frame list to each of the appropriate itds. if the buffer is large, then system software can use a small set of itds to service the entire buffer. system software can activ ate the transaction description records (contained in each itd) in any pattern required for the particular data stream. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-122 freescale semiconductor figure 30-58. example association of itds to client request buffer as noted above, the client request includes a pointer to the base of the buffer and offsets into the buffer to annotate which buffer sections are to be used on each bus transaction that occurs on this endpoint. system software must initialize each transaction description in an itd to ensure it uses the correct portion of the client buffer. for example, for each transaction description, the pg field is set to index the correct physical buffer page pointer and the transaction offset field is set relative to the correct buffer pointer page (for example, the same one referenced by the pg field). when the host controller executes a transaction it selects a transaction description record base d on frindex[2:0]. it then uses the current page buffer pointer (as selected by the pg field) and concatenates to the transaction offset field. the result is a starting buffer address for the transaction. as the host controll er moves data for the transaction, it must watch for a page wrap condition and properly advance to the next available page buffer pointer . system software must not use the page 6 buffer pointer in a transaction description where the length of the transfer will wrap a page boundary. doing so will yield undefined behavior . the host controller hardware is not required to 'alias' the page selector to page zero. usb 2.0 isoc hronous endpoints can specify a period greater than one. software can achieve the appropriate scheduling by li nking itds into the appropriate frames (relative to the frame list) and by setting appr opriate transaction description elements active bits to a one. periodic scheduling threshold the isochronous scheduling threshold field in the hccparams capability register is an indicator to system software as to how the host controller pre-fe tches and effectively caches schedule data structures. it is used by system software when adding isochronous work items to the periodic schedule. the value of this field indicates to system software the minimum di stance it can update isochronous data (relative to the current location of the host controller execution in the periodic list) and stil l have the host controller process them. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-123 the itd and sitd data structures each describe 8 mi cro-frames worth of transactions. the host controller is allowed to cache one (or more) of these data structur es in order to reduce memory traffic. there are three basic caching models that account for the fact the isochronous data structures span 8 micro-frames. the three caching models are: no caching, mi cro-frame caching and frame caching. when software is adding new isochronous transactions to the schedule, it always performs a read of the frindex register to determine the current frame and micro-frame the host controller is currently executing. of course, there is no information about where in the micro-frame the host controller is, so a constant uncertainty-factor of one micro-frame has to be assumed. combining the knowledge of where the host controller is executing with the knowledge of the caching model allows the definition of simple algorithms for how closely software can reli ably work to the executing host controller. no caching is indicated with a value of zero in the isochronous scheduling threshold field. the host controller may pre-fetch data structures during a pe riodic schedule traversal (per micro-frame) but will always dump any accumulated schedule state at the end of the micro-frame. at the appropriate time relative to the beginning of every micro-frame, the hos t controller always begins schedule traversal from the frame list. software can use the value of the frindex register (plus the constant 1 uncertainty-factor) to determine the approximate position of the execut ing host controller. when no caching is selected, software can add an isochronous transaction as near as 2 micro-frames in front of the current executing position of the host controller. frame caching is indicated with a non-zero value in bit [7] of the isochronous scheduling threshold field. in the frame-caching model, system software assu mes that the host controller caches one (or more) isochronous data structures for an entire frame (8 mic ro-frames). software uses the value of the frindex register (plus the constant 1 uncertainty) to determine the current micro-frame/frame (assume modulo 8 arithmetic in adding the constant 1 to the micro-fram e number). for any current frame n, if the current micro-frame is 0 to 6, then software can safely add isochronous transactions to frame n + 1. if the current micro-frame is 7, then software can add isochronous transactions to frame n + 2. micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the isochronous scheduling threshold field. system software assumes the host cont roller caches one or more periodic data structures for the number of mi cro-frames indicated in the isochronous scheduling threshold field. for example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worth of state (current micro-frame, plus the next) on-ch ip. on each micro-frame boundary, the host controller releases the current micro-frame state and be gins accumulating the next micro-frame state. 30.8.3.8 asynchronous schedule the asynchronous schedule traversal is enabled or disabled via the asynchronous schedule enable bit in the usbcmd register. if the asynchronous schedule enable bit is set to a zero, then the host controller simply does not try to access the asynchronous schedule via the asynclistaddr register. likewise, when the asynchronous schedule enable bit is a one, then the host controller does use the asynclistaddr register to traverse the asynchronous schedule. modifications to the asynchronous schedule enable bit are not necessarily immediate. rather the new value of the bit will only be taken into consideration the next time the host controller needs to use the value of the asynclistaddr register to get the next queue head. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-124 freescale semiconductor the asynchronous schedule status bit in the usbsts register i ndicates status of the asynchronous schedule. system software enable s (or disables) the asynchronous sche dule by writing a one (or zero) to the asynchronous schedule enable bit in the usbcmd register. software then can poll the asynchronous schedule status bit to determine when the asynchronous sc hedule has made the desired transition. software must not modify the asynchronous schedule enable bit unless the value of the asynchronous schedule enable bit equals that of the asynchronous schedule status bit. the asynchronous schedule is used to manage all control and bulk transf ers. control and bulk transfers are managed using queue head data structur es. the asynchronous schedule is based at the asynclistaddr register. the default value of the asynclistaddr register after reset is undefined and the schedule is disabled when the asynchronous schedule enable bit is a zero. software may only write this register with defined results when the schedule is disabled. for example, asynchronous schedule enable bit in the usbcmd and the asynchronous schedule status bit in the usbsts register are zero. system software enab les execution from the asynchronous schedule by writing a valid memory address (of a queue head) into this register. then software enables the asynchronous schedule by setting the asynchronous schedule enable bit is set to one. the asynchronous schedule is actually enabled when the asynchronous schedule status bit is a one. when the host controller begins servicing the asynchr onous schedule, it begins by using the value of the asynclistaddr register. it reads the first referenced data structure and begins executing transactions and traversing the linked list as appropriate. when the host cont roller ?completes? processing the asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the asynclistaddr register. next time the asynchronous schedule is accessed, this is the first data structure that will be serviced. this provides round-robi n fairness for processing the asynchronous schedule. a host controller ?completes? processing the asynchronous schedule when one of the following events occur: ? the end of a micro-frame occurs. ? the host controller detects an empty list c ondition (that is, see section empty asynchronous schedule detection ) ? the schedule has been disabled via the asynchronous schedule enable bit in the usbcmd register. the queue heads in the asynchronous list are linke d into a simple circular list as shown in figure 30-53 . queue head data structures are the only valid data structures that may be linked into the asynchronous schedule. an isochronous transfer descriptor (itd or sitd) in the asynchronous schedule yields undefined results. the maximum packet size field in a queue head is sized to accommodate the use of this data structure for all non-isochronous transfer types. the usb specification, revision 2.0 specifies the maximum packet sizes for all transfer types and transfer speeds. syst em software should always parameterize the queue head data structures according to th e core specification requirements. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-125 30.8.3.8.1 adding queue heads to asynchronous schedule this is a software requirement section. there are tw o independent events for adding queue heads to the asynchronous schedule. the first is the initial activa tion of the asynchronous list. the second is inserting a new queue head into an activated asynchronous list. activation of the list is simple. system software wr ites the physical memory address of a queue head into the asynclistaddr register, then enables the list by setting the asynchronous schedule enable bit in the usbcmd register to a one. when inserting a queue head into an active list, softwa re must ensure that the schedule is always coherent from the host controllers' point of view. this means that the system software must ensure that all queue head pointer fields are valid. for example qtd pointers have t-bit s set to a one or reference valid qtds and the horizontal pointer references a valid queue head data structure. the following algorithm represents the functional requirements: insertqueuehead (pqheadcurrent, pqueueheadnew) -- -- requirement : all inputs must be properly initialized. -- -- pqheadcurrent is a pointer to a queue head that is -- already in the active list -- pqheadnew is a pointer to the queue head to be added -- -- this algorithm links a new queue head into a existing -- list -- pqueueheadnew.horizontalpointer = pqueueheadcurrent.horizontalpointer pqueueheadcurrent.horizontalpointer = physicaladdressof(pqueueheadnew) end insertqueuehead 30.8.3.8.2 removing queue head s from asynchronous schedule this is a software requirement section. there are two independent events for removing queue heads from the asynchronous schedule. the first is shutting down (deactivating) the asynchronous list. the second is extracting a single queue head from an activated list. software deactivates the asynchronous schedule by setting the asynchronous schedule enable bit in the usbcmd register to a zero. software can determine when the list is idle when the asynchronous schedule status bit in the usbsts register is a zero. the normal mode of operation is that software remove s queue heads from the asynchronous schedule without high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-126 freescale semiconductor shutting it down. software must not remove an active queue head from the schedule. software should first deactivate all active qtds, wait for the queue head to go inactive, then remove the queue head from the asynchronous list. software removes a queue head fr om the asynchronous list via the following algorithm. as illustrated, the unlinking is quite easy. software me rely must ensure all of the link pointers reachable by the host controller are kept consistent. unlinkqueuehead (pqheadprevious, pqueueheadtounlink, pqheadnext) -- -- requirement : all inputs must be properly initialized. -- -- pqheadprevious is a pointer to a queue head that -- references the queue head to remove -- pqheadtounlink is a pointer to the queue head to be -- removed -- pqheadnext is a pointer to a queue head still in the -- schedule. software provides this pointer with the -- following strict rules: -- if the host software is one queue head, then -- pqheadnext must be the same as -- queueheadtounlink.horizontalpointer. if the host -- software is unlinking a consecutive series of -- queue heads, qheadnext must be set by software to -- the queue head remaining in the schedule. -- -- this algorithm unlinks a queue head from a circular list -- pqueueheadprevious.horizontalpointer = pqueueheadtounlink.horizontalpointer pqueueheadtounlink.horizontalpointer = pqheadnext end unlinkqueuehead if software removes the queue head with the h-bit set to a one, it must select another queue head still linked into the schedule and set its h-bit to a one. this should be completed before removing the queue head. the requirement is that software keep one queue head in the asynchronous schedule, with its h-bit set to a one. at the point software has removed one or more queue heads from the asynchronous schedule, it is unknown whether the host controller has a cached pointer to them. similarly, it is unknown how long the host controller might retain the cached information, as it is implementation depende nt and may be affected by the actual dynamics of the schedule load. therefore, once software has removed a queue head from the high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-127 asynchronous list, it must retain the coherency of the queue head (link pointers, etc.). it cannot disturb the removed queue heads until it knows that the host contro ller does not have a local copy of a pointer to any of the removed data structures. the method software uses to determine when it is safe to modify a removed queue head is to handshake with the host controller. the handshake mechanis m allows software to remove items from the asynchronous schedule, then execute a simple, lightweight handshake that is used by software as a key that it can free (or reuse) the memory associated the data structures it has removed from the asynchronous schedule. the handshake is implemented with three bits in the host controller. the first bit is a command bit ( interrupt on async advance doorbell bit in the usbcmd register) that allows software to inform the host controller that something has been removed from its asynchronous schedule. the second bit is a status bit ( interrupt on async advance bit in the usbsts register) that the host controller sets after it has released all on-chip state that may potentially reference one of the data structures just removed. when the host controller sets this status bit to a one, it also sets the command bit to a zero. the third bit is an interrupt enable ( interrupt on async advance bit in the usbintr register) that is matched with the status bit. if the status bit is a one and the interrupt enable bit is a one, then the host controller will assert a hardware interrupt. figure 30-59 illustrates a general example. in this exam ple, consecutive queue heads (b and c) are unlinked from the schedule using the algorithm above. before the unlink operation, the host controller has a copy of queue head a. the unlink algorithm requires that as software unlinks each queue head, the unlinked queue head is loaded with the address of a queue head that will remain in the asynchronous schedule. when the host controller observes that doorbell bit being set to a one, it makes a note of the local reachable schedule information. in this example, the local re achable schedule information includes both queue heads (a and b). it is sufficient that the host controller ca n set the status bit (and clear the doorbell bit) as soon as it has traversed beyond current reachable schedule information (that is, tr aversed beyond queue head (b) in this example). figure 30-59. generic queue head unlink scenario high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-128 freescale semiconductor alternatively, a host controller implementation is allo wed to traverse the entire asynchronous schedule list (for example, observed the head of th e queue (twice)) before setting the advance on async status bit to a one. software may re-use the memory associated with the removed queue heads after it observes the interrupt on async advance status bit is set to a one, following assertion of the doorbell. software should acknowledge the interrupt on async advance status as indicated in the us bsts register, before using the doorbell handshake again. 30.8.3.8.3 empty asynchr onous schedule detection the enhanced host controller interface uses two bits to detect when the asynchronous schedule is empty. the queue head data structure (see figure 30-48 ) defines an h-bit in the queue head, which allows software to mark a queue head as being the head of the reclaim list. the enhanced host controller interface also keeps a 1-bit flag in the usbsts register ( reclamation ) that is set to a zero when the enhanced interface host controller observes a queue head with the h-bit set to a one. the reclamation flag in the status register is set to one when any usb transaction from the asynchronous schedule is executed (or whenever the asynchronous schedule st arts, see section asynchronous schedule traversal : start event ). if the enhanced host controller interface ever encounters an h-bit of one and a reclamation bit of zero, the ehci controller simply stops tr aversal of the asynchronous schedule. a example illustrating the h-bit in a schedule is illustrated in figure 30-60 . figure 30-60. asynchronous schedule list w/annotation to mark head of list software must ensure there is at most one queue head with the h-bit set to a one, and that it is always coherent with respect to the schedule. 30.8.3.8.4 restarti ng asynchronous schedule before eof there are many situations where the host controller will detect an empty list long before the end of the micro-frame. it is important to remember that under many circumstances the schedule traversal has stopped due to nak/nyet responses from all endpoints. an example of particular interest is when a start-sp lit for a bulk endpoint occurs early in the micro-frame. given the ehci simple traversal rules, the complete-split for that transaction may nak/nyet out very high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-129 quickly. if it is the only item in the schedule, then the host controller will cease traversal of the asynchronous schedule very early in the micro-frame. in order to provide reasonable service to this endpoint, the host controller should issue the complete-split before the end of the current micro-frame, instead of waiting until the next micro-frame. wh en the reason for host controller idling asynchronous schedule traversal is because of empty list detect ion, it is mandatory the host controller implement a 'waking' method to resume traversal of the async hronous schedule. an example method is described below. example method for restarting as ynchronous schedule traversal the reason for idling the host controller when the list is empty is to keep the host controller from unnecessarily occupying too much memory bandwidth. the question is: how long should the host controller stay idle before restarting ? the answer in this example is based on deriving a mani fest constant, which is the amount of time the host controller will stay idle before restarting traversal. in this example, the manifest constant is called asyncschedsleeptime , and has a value of 10 sec. the value is derived based on the analysis in section example derivation for asyncschedsleeptime , the traversal algorithm is simple: ? traverse the asynchronous schedule until the either an end-of-micro-frame event occurs, or an empty list is detected. if the event is an end-of -micro-frame, go attempt to traverse the periodic schedule. if the event is an empty list, then set a sleep timer and go to a schedule sleep state. ? when the sleep timer expires, set working cont ext to the asynchronous schedule start condition and go to schedule active state. the start context allows the hc to reload nakcnt fields, etc. so the hc has a chance to run for more than one iteration through the schedule. this process simply repeats itself each micro-frame. figure 30-61 illustrates a sample state machine to manage the active and sleep states of the asynchronous schedule traversal policy. there are three states: actively traversing the asynchronous schedule, sleepi ng, and not active. the last two are similar in terms of interaction with the as ynchronous schedule, but the not active state means that the host controller is busy with the periodic schedule or th e asynchronous schedule is not enabled. the sleeping state is specifically a special state where the host controller is just waiting for a period of time before resuming execution of the asynchronous schedule. figure 30-61. example state machine for managing asynchronous schedule traversal high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-130 freescale semiconductor the actions referred to in figure 30-61 are defined in table 30-64 . table 30-64. asynchronous schedule sm transition actions async sched not active this is the initial state of the traversal state machine after a host controller reset. the traversal state machine will not leave this state when the asynchronous schedule enable bit in the usbcmd register is a zero. this state is entered from async sched acti ve or async sched sleeping states when the end-of-micro-frame event is detected. async sched active this state is entered from the async sched not active state when the periodic schedule is not active. it is also entered from the async sched sleeping states when the asyncrhonoustraversalsleeptimer expires. on every transition into this state, the host controller sets the reclamation bit in the usbsts register to a one. while in this state, the host controller will continua lly traverse the asynchronous schedule until either the end of micro-frame or an empt y list condition is detected. async sched sleeping the state is entered from the async sched active state when a schedule empt y condition is detected. on entry to this state, the host controller sets the asynchronoustraversalsleeptimer to asyncschedsleeptime . example derivation for asyncschedsleeptime the derivation is based on analysis of what work th e host controller could be doing next. it assumes the host controller does not keep any state about what wo rk is possibly pending in the asynchronous schedule. the schedule could contain any mix of the possible comb inations of high- full- or low-speed control and bulk requests. table 30-65 summarizes some of the typical 'next tran sactions' that could be in the schedule, and the amount of time (for example, footprint or wall clock ) the transaction will take to complete. action action description label a on detection of the empty list, the host controller sets the asynchronoustraversalsleeptimer to asyncschedsleeptime . b when the asynchronoustraversalsleeptimer expires, the host controller sets the reclamation bit in the usbsts register to a one and moves the nak counter reload state machine to waitforlisthead (see section operational model for nak counter). c the host controller cancels the sleep timer ( asynchronoustraversalsleeptimer ). high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-131 table 30-65. typical low-/full-speed transaction times a asyncschedsleeptime value of 10 s provides a reasonable relaxation of the system memory load and still provides a good level of service for the various tran sfer types and payload si zes. for example, say we detect an empty list after issuing a start-split for a 64-byte full-speed bulk request. assuming this is the only thing in the list, the host controller will get the results of the full-speed transaction from the hub during the fifth complete-split request. if the full-speed transaction was an in and it nak'd, the 10 s sleep period would allow the host controller to get the nak results on the first complete-split. 30.8.3.8.5 asynchronous schedule traversal : start event once the hc has idled itself via the empty schedule det ection (section 0), it will naturally activate and begin processing from the periodic schedule at the beginning of each micro-frame. in addition, it may have idled itself early in a micro-frame. when this occurs (idles early in the micro-frame) the hc must occasionally re-activate during the micro-frame and traverse the asynchronous schedule to determine whether any progress can be made. th e requirements and method for this restart are described in section restarting asynchronous schedule be fore eof . asynchronous schedule start event s are defined to be: ? whenever the host controller transitions from the periodic schedule to the asynchronous schedule. if the periodic schedule is disabled and the as ynchronous schedule is enabled, then the beginning of the micro-frame is equivalent to the transition from the periodic schedule, or ? the asynchronous schedule traversal restarts fr om a sleeping state (s ee section restarting asynchronous schedule before eof ). 30.8.3.8.6 reclamation status bit (usbsts register) the operation of the empty asynchronous schedule detection feature (section empty asynchronous schedule detection ) depends on the proper management of the reclamation bit in the usbsts register. transaction attributes footprint (time) description speed hs 11.9 ms maximum foot print for a worst-case, full-sized bulk data transaction. size 512 9.45 ms maximum footprint for an approximate best-case, full-sized bulk data transaction. ty p e b u l k speed fs ~50 ms approximate typical for full-sized bulk data. an 8-byte low-speed is about 2x, or between 90 and 100 ms. size 64 ty p e b u l k speed fs ~12 ms approximate typical for 8-byte bulk/control (that is, setup) size 8 ty p e c n t r l high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-132 freescale semiconductor the host controller tests for an empty schedule just af ter it fetches a new queue head while traversing the asynchronous schedule (see section fetch queue head ). it is required that the host controller sets the reclamation bit to a one whenever an asynchronous schedule traversal start event , as documented in section asynchronous sc hedule traversal : start event , occurs. the reclamation bit is also set to a one whenever the host controller executes a transaction while traversing the asynchronous schedule (see section execu te transaction ). the host controller sets the reclamation bit to a zero whenever it finds a queue head with its h - bit set to a one. software should only set a queue head's h - bit if the queue head is in the asynchr onous schedule. if software sets the h - bit in an interrupt queue head to a one, the resulting beha vior is undefined. the host controller may set the reclamation bit to a zero when executing from the periodic schedule. 30.8.3.9 operational model for nak counter this section describes the operational model for the nakcnt field defined in a queue head (see section queue head). software should not use this feature for interrupt queue heads. this rule is not required to be enforced by the host controller. usb protocol has built-in flow control via the nak response by a device. there are several scenarios, beyond the ping feature, where an endpoint may naturally nak or nyet the majority of the time. an example is the host controller management of the sp lit transaction protocol for control and bulk endpoints. all bulk endpoints (high- or full-speed) are serv iced via the same asynchronous schedule. the time between the start-split transaction and the first complete-split transaction could be ve ry short (that is, like when the endpoint is the only one in the asynchr onous schedule). the hub nyets (effectively naks) the complete-split transaction until the classic transaction is complete. this could result in the host controller thrashing memory, repeatedly fetching the queue head and executing the transaction to the hub, which will not complete until after the transaction on the classic bus completes. there are two component fields in a queue head to support the throttling feature: a counter field ( nakcnt ), and a counter reload field ( rl ). nakcnt is used by the host controller as one of the criteria to determine whether or not to execute a transaction to the end point. there are two operational modes associated with this counter: ? not used. this mode is set when the rl field is zero. the host controller ignores the nakcnt field for any execution of transactions through a queue head with an rl field of zero. software must use this selection for interrupt endpoints. ? nak throttle mode. this mode is selected when the rl field is non-zero. in this mode, the value in the nakcnt field represents the maximum number of nak or nyet responses the host controller will tolerate on each endpoint. in this mode, the hc will decrement the nakcnt field based on the token/handshake criteria listed in table 30-66 the host controller must reload nakcnt when the endpoint successfully moves data (for example, policy to reward device for moving data). high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-133 table 30-66. nakcnt field adjustment rules in summary, system software enables the counter by setting the reload field ( rl ) to a non-zero value. the host controller may execute a transaction if nakcnt is non-zero. the host controller will not execute a transaction if nakcnt is zero. the reload mechanism is described in detail in section nak count reload control . note that when all queue heads in the asynchronous sche dule either exhausts all tr ansfers or all nakcnt's go to zero, then the host controller will detect an empty asynchronous schedule and idle schedule traversal (see section empty asynchronous schedule detection ). any time the host controller begins a new traversal of the asynchronous schedule, a start event is assumed, see section asynchronous schedule traversal : start event . every time a start-event occurs, the nak count reload procedure is enabled. 30.8.3.9.1 nak count reload control when the host controller reaches the execute transaction state for a queue head (meaning that it has an active operational state), it checks to determine whether the nakcnt field should be reloaded from rl (see section execute transaction ). if the answer is yes, then rl is copied into nakcnt . after the reload or if the reload is not active, the host controller evaluates whether to execute the transaction. the host controller must reload nak counters ( nakcnt see figure 30-48 ) in queue heads during the first pass through the reclamation list after an asynchr onous schedule start event (see section asynchronous schedule traversal : start event for the definition of the start event). the asynchronous schedule should have at most one queue head marked as the head (see figure 30-60 ). figure 30-62 illustrates an example state machine that satisfies the operational requireme nts of the host controller detecting the first pass through the asynchronous schedule. this state machine is maintained internal to the host controller and is only used to gate reloading of the nak c ounter during the queue head traversal state: execute transaction ( figure 30-62 ). the host controller does not perform the nak counter reload operation if the rl field (see figure 30-48 ) is set to zero. token handshake handshake nak nyet in/ping decrement nakcnt n/a (protocol error) out decrement nakcnt no action 1 start 1 recommended behavior on this response is to reload nakcnt. split decrement nakcnt n/a (protocol error) complete split no action decrement nakcnt high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-134 freescale semiconductor figure 30-62. example hc state machine for controlling nak counter reloads wait for list head this is the initial state. the state machine enters this state from wait for start event when a start event as defined in section asynchronous schedule traversal : start event occurs. the purpose of this state is to wait for the first observation of the head of th e asynchronous schedule. this occurs when the host controller fetches a queue head whose h-bit is set to a one. do reload this state is entered from the wait for list head state when the host controller fetches a queue head with the h-bit set to a one. while in this state, the host c ontroller will perform nak c ounter reloads for every queue head visited that has a non-zero nak reload value ( rl ) field. wait for start event this state is entered from the do reload state when a queue head with the h-bit set to a one is fetched. while in this state, the host controller will not perform nak counter reloads. 30.8.3.10 managing control/bulk/interrupt transfers via queue heads this section presents an overview of how the host controller interacts with queuing data structures. queue heads use the queue element transfer descript or (qtd) structure. one queue head is used to manage the data stream for one endpoint. the queue head structure contains static endpoint characteristics and capabilities. it also contains a working area from where individual bus transactions for an endpoint are executed (see overlay area defined in figure 30-48 ). each qtd represents one or more bus transactions, which is defined in the context of this specification as a transfer . the general processing model for the host controller's use of a queue head is simple: ? read a queue head, ? execute a transaction from the overlay area, high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-135 ? write back the results of the transaction to the overlay area ? move to the next queue head. if the host controller encounters errors during a transac tion, the host controller will set one (or more) of the error reporting bits in the queue head's status field. the status field accumulates all errors encountered during the execution of a qtd (for example, the error bits in the queue head status field are 'sticky' until the transfer (qtd) has completed). this state is always written back to the source qtd when the transfer is complete. on transfer (for example, buffer or halt conditions) boundaries, the host controller must auto-advance (without software intervention) to the next qtd. additionally, the hardware must be able to halt the queue so no additional bus transactions will occur for the endpoint and the host controller will not advance the queue. an example host controller operational state machin e of a queue head traversal is illustrated in figure 30-63 . this state machine is a model for how a hos t controller should traver se a queue head. the host controller must be able to advance the queue from the fetch qh state in order to avoid all hardware/software race conditions. this simple mechanism allows software to simply link qtds to the queue head and activate them, then the host controller will always find them if/when they are reachable. figure 30-63. host controller queue head traversal state machine high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-136 freescale semiconductor this traversal state machine applies to all queue heads, regardless of transfer type or whether split transactions are required. the following sections descri be each state. each state description describes the entry criteria. the execute transaction state (section execute transaction ) describes the basic requirements for all endpoints. sections split tr ansactions for asynchronous transfers and split transaction interrupt describe details of the required extensions to the execute transaction state for endpoints requiring split transactions. note: prior to software placing a queue head into e ither the periodic or asynchronous list, software must ensure the queue head is properly initialized. minima lly, the queue head should be initialized to the following (see section queue head for layout of a queue head): ? valid static endpoint state ? for the very first use of a queue head, software may zero-out the queue head transfer overlay, then set the next qtd pointer field value to reference a valid qtd. 30.8.3.10.1 fetch queue head a queue head can be referenced from the physical address stored in the asynclistaddr register (section asynclistaddr; endpointlistaddr). a dditionally, it may be referenced from the next link pointer field of an itd, sitd, fstn or another queu e head. if the referencing link pointer has the typ field set to indicate a queue head, it is assumed to reference a queue head structure as defined in figure 30-48 . while in this state, the host controller performs ope rations to implement empty schedule detection (section empty asynchronous schedule detec tion ) and nak counter reloads (section operational model for nak counter). after the queue head has been fetched, the host controller conducts the following queries for empty schedule detection: ? if queue head is not an interrupt queue head (that is, s-mask is a zero), and ? the h - bit is a one, and ? the reclamation bit in the usbsts register is a zero. when these criteria are met, the host controller will stop traversing the asynchronous list (as described in section empty asynchronous schedule detection ). wh en the criteria are not met, the host controller continues schedule traversal. if the queue head is not an interrupt and the h - bit is a one and the reclamation bit is a one, then the host controller sets the reclamation bit in the usbsts register to a zero before completing this state. the operations for relo ading of the nak counter are described in detail in section operational model for nak counter. this state is complete when the queue head has been read on-chip. 30.8.3.10.2 advance queue to advance the queue, the host controller must find the next qtd, adjust pointers, perform the overlay and write back the results to the queue head. this state is entered from the fetchqhd state if the overlay active and halt bits are set to zero. on entry to this state, the host controller determines which ne xt pointer to use to fetch a qtd, fetches a qtd and determines whether or not to perform an overlay. note that if the i-bit is a one and the active bit is a zero, high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-137 the host controller immediately skips processing of this queue head, exits this state and uses the horizontal pointer to the next schedule data structure. if the field bytes to transfer is not zero and the t-bit in the alternate next qtd pointer is set to zero, then the host controller uses the alternate next qtd pointer . otherwise, the host controller uses the next qtd pointer . if next qtd pointer ?s t-bit is set to a one, then the host controller exits this state and uses the hor izontal pointer to the next schedule data structure. using the selected pointer the host controller fetches the referenced qtd. if the fetched qtd has it?s active bit set to a one, the host controller moves the pointer value used to reach the qtd ( next or alternate next ) to the current qtd pointer field, then performs the overlay. if the fetched qtd has its active bit set to a zero, the host controller aborts the queue advance a nd follows the queue head's horizontal pointer to the next schedule data structure. th e host controller performs the overlay based on the following rules: ? the value of the data toggle ( dt ) field in the overlay area depends on the value of the data toggle control ( dtc ) bit (see table 30-54 ). ? if the eps field indicates the endpoint is a high-speed endpoint, the ping state field is preserved by the host controller. the value of this field is not changed as a result of the overlay. ? c-prog-mask field is set to zero (field from incoming qtd is ignored, as is the current contents of the overlay area). ? frame tag field is set to zero (field from incoming qtd is ignored, as is the current contents of the overlay area). ? nakcnt field in the overlay area is loaded from the rl field in the queue head's static endpoint state. ? all other areas of the overlay are set by the incoming qtd. the host controller exits this state when it has committed the write to the queue head. 30.8.3.10.3 execute transaction the host controller enters this state from the fetch queue head state only if the active bit in status field of the queue head is set to a one. on entry to this state, the host controller executes a few pre-operations, then checks some pre-condition criteria before committing to executing a transaction for the queue head. the pre-operations performed and the pre-condition criteria depend on whether the queue head is an interrupt endpoint. the host controller can determine that a queue head is an interrupt queue head when the queue head?s s-mask field contains a non-zero value. it is th e responsibility of software to ensure the s-mask field is appropriately initialized based on the transfer type. there are other criteria that must be met if the eps field indicates that the endpoint is a low- or full-speed endpoint, see sections split transactions for asynchronous transfers and split transaction interrupt . interrupt transfer pre-condition criteria if the queue head is for an interrupt endpoint (for example, non-zero s-mask field), then the frindex[2:0] field must identify a bit in the s-mask field that has a one in it. for example, an s-mask value of 00100000b would evaluate to true only when frindex[2:0] is equal to 101b. if this condition is met then the host controller considers this queue head for a transaction . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-138 freescale semiconductor asynchronous transfer pre-operations and pre-condition criteria if the queue head is not for an inte rrupt endpoint (for example, a zero s-mask field), then the host controller performs one pre-operation and then evaluates one pre-condition criteria: the pre-operation is: checks the nak counter reload state (section operat ional model for nak counter). it may be necessary for the host controller to reload the nak counter field. the reload is performed at this time. the pre-condition evaluated is: ? whether or not the nakcnt field has been reloaded, the host controller checks the value of the nakcnt field in the queue head. if nakcnt is non-zero, or if the reload nak counter field is zero, then the host controller considers this queue head for a transaction. transfer type independent pre-operations regardless of the transfer type, the host controller al ways performs at least one pre-operation and evaluates one pre-condition. the pre-operation is: ? a host controller internal transaction (down) counter qhtransactioncounter is loaded from the queue head?s mult field. a host controller implementation is allowed to ignore this for queue heads on the asynchronous list. it is mandatory for interrupt queue heads. software should ensure that the mult field is set appropriately for the transfer type. the pre-conditions evaluated are: ? the host controller determines whether there is enough time in the micro-frame to complete this transaction (see section transaction fit - a be st-fit approximation algorithm for an example evaluation method). if there is not enough time to complete the transaction, the host controller exits this state. ? if the value of qhtransactioncounter for an interrupt endpoint is zero, then the host controller exits this state. when the pre-operations are complete and pre-conditions are met, the host controller sets the reclamation bit in the usbsts register to a one and then begins executing one or more transactions using the endpoint information in the queue head. the host controller iterates qhtransactioncounter times in this state executing transactions. after each transaction is executed, qhtransactioncounter is decremented by one. the host controller will exit this state when one of the following events occurs: ? the qhtransactioncounter decrements to zero, or ? the endpoint responds to the transaction with any handshake other than an ack, 4 or ? the transaction experiences a transaction error, or ? the active bit in the queue head goes to a zero, or ? there is not enough time in the micro-frame left to execute the next transaction (see section transaction fit - a best-fit approximation algor ithm for example method for implementing the frame boundary test). 4 note that for a high-bandwidth interrupt out endpoint, the host controller may optionally immediately retry the transaction if it fails. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-139 the results of each transaction is recorded in the on-chip overlay area. if data was successfully moved during the transaction, the transfer state in the overlay area is advanced. to advance queue head?s transfer state, the total bytes to transfer field is decremented by the number of bytes moved in the transaction, the data toggle bit ( dt ) is toggled, the current page offset is a dvanced to the next appropriate value (for example, advanced by the number of bytes successfully moved), and the c_page field is updated to the appropriate value (if necessary). see section buffer pointer list use for data streaming with qtds . note that the total bytes to transfer field may be zero when all the other criteria for executing a transaction are met. when this occurs, the host c ontroller will execute a zero-length transaction to the endpoint. if the pid_code field indicates an in transaction and th e device delivers data, the host controller will detect a packet babble condition, set the babble and halted bits in the status field, set the active bit to a zero, write back the results to the source qtd, then exit this state. in the event an in token receives a data pid mi smatch response, the host controller must ignore the received data (for example, not advance the transfer state for the bytes received). additionally, if the endpoint is an interrupt in, then the host controller must record that the transaction occurred (for example, decrement qhtransactioncounter ). it is recommended (but not required) the host controller continue executing transactions for this endpoint if the resultant value of qhtransactioncounter is greater than one. if the response to the in bus transaction is a nak (or nyet) and rl is non-zero, nakcnt is decremented by one. if rl is zero, then no write-back by the host controlle r is required (for a transaction receiving a nak or nyet response and the value of cerr did not change). software should set the rl field to zero if the queue head is an interrupt endpoint. host controller hardware is not required to enforce this rule or operation. after the transaction has finished and the host contro ller has completed the post processing of the results (advancing the transfer state and possibly nakcnt , the host controller writes back the results of the transaction to the queue head?s overlay area in main memory. the number of bytes moved during an in transaction depends on how much data the device endpoint delivers. the maximum number of bytes a device can send is maximum packet size . the number of bytes moved during an out transaction is either maximum packet length bytes or total bytes to transfer , whichever is less. if there was a transaction error during the transaction, th e transfer state (as defined above) is not advanced by the host controller. the cerr field is decremented by one and the status field is updated to reflect the type of error observed. transaction errors ar e summarized in section transaction error . the following events will cause the host controller to clear the active bit in the queue head?s overlay status field. when the active bit transitions from a one to a zero, the transfer in the overlay is considered complete. the reason for the transfer completion (clearing the active bit) determines the next state. ? cerr field decrements to zero. when this occurs the halted bit is set to a one and active is set to a zero. this results in the hardware not advanci ng the queue and the pipe halts. software must intercede to recover. ? the device responds to the transaction with a stall pid. when this occurs, the halted bit is set to a one and the active bit is set to a zero. this results in the hardware not advancing the queue and the pipe halts. software must intercede to recover. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-140 freescale semiconductor ? the total bytes to transfer field is zero after the transaction completes. note that for a zero length transaction, it was zero before the transaction was started. when this condition occurs, the active bit is set to zero. ? the pid code is an in, and the number of bytes moved during the transaction is less than the maximum packet length . when this occurs, the active bit is set to zero and a short packet condition exists. the short-packet condition is detected during the advance queue state. refer to section split transactions for additional rules for managing low- and full-speed transactions. with the exception of a nak response (when rl field is zero), the host controller always writes the results of the transaction back to the overlay area in main memory. this includes when the transfer completes. for a high-speed endpoint, the queue head information wr itten back includes minimally the following fields: the pid code field indicates an in and the device sends more than the expected number of bytes (e.g. maximum packet length or total bytes to transfer bytes, whichever is less) (e.g. a packet babble). this results in the host controller setting the halted bit to a one. ? nakcnt, dt, total bytes to transfer, c_page, status, cerr, and current offset for a low- or full-speed device the queue head information written back also includes the fields: ? c-prog-mask, frametag and s-bytes. the duration of this state depends on the time it takes to complete the transaction(s) and the status write to the overlay is committed. halting a queue head a halted endpoint is defined only for the transfer t ypes that are managed via queue heads (control, bulk and interrupt). the following events indicate that the endpoint has reached a condition where no more activity can occur without intervention from the driver: ? an endpoint may return a stall handshake during a transaction, ? a transaction had three consecutive error conditions, or ? a packet babble error occurs on the endpoint. when any of these events occur (for a queue head) th e host controller halts the queue head and set the usberrint status bit in the usbsts register to a one. to halt the queue head, the active bit is set to a zero and the halted bit is set to a one. there may be other error status bits that are set when a queue is halted. the host controller always writes back the overl ay area to the source qtd when the transfer is complete, regardless of the reason (normal completion, short packet or halt). the host controller will not advance the transfer state on a transaction that results in a halt condition (e.g. no updates necessary for total bytes to transfer , c_page , current offset, and dt ). the host controller must update cerr as appropriate. when a queue head is halted, the usb error interrupt bit in the usbsts register is set to a one. if the usb error interrupt enable bit in the usbintr register is set to a one, a hardware interrupt is generated at the next interrupt threshold. asynchronous schedule park mode asynchronous schedule park mode is a special executi on mode that can be enabled by system software, where the host controller is permitted to execute more than one bus transaction from a high-speed queue head in the asynchronous schedule before continuing horizontal traversal of the asynchronous schedule. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-141 this feature has no effect on queue he ads or other data structures in th e periodic schedule. this feature is similar in intent as the mult feature that is used in the periodic schedule. where-as the mult feature is a characteristic that is tunable for each endpoint; park-mode is a policy that is applied to all high-speed queue heads in the asynchronous schedule. it is essentially th e specification of an iterator for consecutive bus transactions to the same endpoint. all of the rules fo r managing bus transactions and the results of those as defined in section execute transaction apply. this feature merely specifies how many consecutive times the host controller is permitted to execute from the same queue head before moving to the next queue head in the asynchronous list. this feature should allow the host controller to attain better bus utilization for those devices that are capable of moving data at maximum rate, while at the same time providing a fair service to all endpoints. a host controller exports its capability to suppor t this feature to system software by setting the asynchronous schedule park capability bit in the hccparams register to a one. this information keys system software that the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the usbcmd regist er are modifiable. system software enables the feature by writing a one to the asynchronous schedule park mode enable bit. when park-mode is not enabled (e.g. asynchronous schedule park mode enable bit in the usbcmd register is a zero), the host controller must not exec ute more than one bus transaction per high-speed queue head, per traversal of the asynchronous schedule. when park-mode is enabled, the host controller must not apply the feature to a queue head whose eps field indicates a low/full-speed device (i.e. only one bus transaction is allowed from each low/full-speed que ue head per traversal of the asynchronous schedule). park-mode may only be applied to queue heads in the asynchronous schedule whose eps field indicates that it is a high-speed device. the host controller must apply pa rk mode to queue heads whose eps field indicates a high-speed endpoint. the maximum number of consecutive bus transactions a host controller may execute on a high-speed queue head is determined by the value in the asynchronous schedule park mode count field in the usbcmd register. software must not set asynchronous schedule park mode enable bit to a one and also set asynchronous schedule park mode count field to a zero. the resulting behavior is not defined. an example behavioral example descri bes the operational requirements for the host controller implementing park-mode. this feature does not affect how the host c ontroller handles the bus transaction as defined in section execute transaction . it only effects how many consecutive bus transactions for the current queue head can be executed. all boundary conditions, error dete ction and reporting applies as usual. this feature is similar in concept to the use of the mult field for high-bandwidth interrupt for queue heads in the periodic schedule. the host controller effectively loads an internal down-counter pm-count from asynchronous schedule park mode count when asyncrhonous schedule park mode enable bit is a one, and a high-speed queue head is first fetched and meets all the criteria for executing a bus transaction. after the bus transaction, pm-count is decremented. the host controller may continue to execute bus transactions from the current queue head until pm-count goes to zero, an error is detected, the buff er for the current transfer is exhausted or the endpoint responds with a flow-control or stall handshake. table 30-67 summarizes the responses that effect whether the host controller continues with another bus transaction for the current queue head. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-142 freescale semiconductor table 30-67. actions for park mode, based on endpoint response and residual transfer state 30.8.3.10.4 write back qtd this state is entered from the execute transaction state when the active bit is set to a zero. the source data for the write-back is the transfer results area of the queue head overlay area (see figure 30-48 ). the host controller uses the current qtd pointer field as the target address for the qtd. the queue head transfer result area is written back to the transfer result area of the target qtd. this state is also referred to as: qtd retirement. the fields that must be written back to the source qtd include total bytes to transfer , cerr , and status . the duration of this state depends on when the qtd write-back has been committed. pid endpoint response transfer state after transaction action pm-count bytes to transfer in data[0,1] w/maximum packet sized data not zero not zero allowed to perform another bus transaction. 1,2 1 note, the host controller may continue to execute bus transactions from the current high-speed queue head (if pm-count is not equal to zero), if a pid mismatch is detected (e.g. expected data1 and received data0, or visa-versa). , 2 note, this specification does not require that the host controller execute another bus transaction when pm-count is non-zero. implementations are encouraged to make appropriate complexity and performance trade-offs. not zero zero retire qtd and move to next qh zero don?t care move to next qh. data[0,1] w/short packet don?t care don?t care retire qtd and move to next qh. nak don?t care don?t care move to next qh. stall, xacterr don?t care don?t care move to next qh. out ack not zero not zero allowed to perform another bus transaction. 2 not zero zero retire qtd and move to next qh zero don?t? care move to next qh. nyet, nak don?t care don?t care move to next qh. stall, xacterr don?t care don?t care move to next qh ping ack not zero not zero allowed to perform another bus transaction. 2 nak don?t care don?t care move to next qh stall, xacterr don?t care don?t care move to next qh high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-143 30.8.3.10.5 follow queue head horizontal pointer the host controller must use the horizontal pointer in the queue head to the next schedule data structure when any of the following conditions exist: ? if the active bit is a one on exit from the execute transaction state, or ? when the host controller exits the write back qtd state, or ? if the advance queue state fails to advance the queue beca use the target qtd is not active, or ? if the halted bit is a one on exit from the fetch qh state. there is no functional requirement that the host contro ller wait until the current transaction is complete before using the horizontal pointer to read the next linked data structure. however, it must wait until the current transaction is complete before executing the next data structure. 30.8.3.10.6 buffer pointer list use for data st reaming with qtds a qtd has an array of buffer pointers, which is used to reference the data buffer for a transfer. this specification requires that the buffer associated with the transfer be virtually contiguous . this means: if the buffer spans more than one physical page, it must obey the following rules ( figure 30-64 illustrates an example): ? the first portion of the buffer must begin at some offset in a page and extend through the end of the page. ? the remaining buffer cannot be allocated in small chunks scattered around memory. for each 4k chunk beyond the first page, each buffer portion matche s to a full 4k page. the final portion, which may only be large enough to occupy a portion of a page, must start at the top of the page and be contiguous within that page. the buffer pointer list in the qtd is long enough to support a maximum transfer size of 20k bytes. this case occurs when all five buffer pointers are used and the first offset is zero. a qtd handles a 16kbyte buffer with any starting buffer alignment. the host controller uses the field c_page field as an index value to determine which buffer pointer in the list should be used to start the current transaction. the host controller uses a different buffer pointer for each physical page of the buffer. this is always true, even if the buffer is physically contiguous. the host controller must detect when the current tr ansaction will span a page boundary and automatically move to the next available buffer pointer in the page pointer list. the next available pointer is reached by incrementing c_page and pulling the next page pointer from the list. software must ensure there are sufficient buffer pointers to move the amount of data specified in the bytes to transfer field. figure 30-64 illustrates a nominal example of how system software would initialize the buffer pointers list and the c_page field for a transfer size of 16383 bytes. c_page is set to zero. the upper 20-bits of page 0 references the start of the physical page. current offset (the lower 12-bits of queue head dword 7) holds the offset in the page e.g. 2049 (e.g. 4096-2047). the re maining page pointers are set to reference the beginning of each subsequent 4k page. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-144 freescale semiconductor figure 30-64. example mapping of qtd buffer pointers to buffer pages for the first transaction on the qtd (assuming a 512-byt e transaction), the host controller uses the first buffer pointer (page 0 because c_page is set to zero) and concatenates the current offset field. the 512 bytes are moved during the transaction, the current offset and total bytes to transfer are adjusted by 512 and written back to the queue head working area. during the 4 th transaction, the host controller needs 511 bytes in page 0 and one byte in page 1. the host controller will increment c_page (to 1) and use the page 1 pointer to move the final byte of the transaction. after the 4 th transaction, the active page pointer is the page 1 pointer and current offset has rolled to one, and both are written back to the overlay area. the trans actions continue for the rest of the buffer, with the host controller automatically moving to the next page pointer (i.e. c_page ) when necessary. there are three conditions for how the host controller handles c_page . ? the current transaction does not span a page boundary. the value of c_page is not adjusted by the host controller. ? the current transaction does span a page boundary. the host controller must detect the page cross condition and advance to the next buffer while streaming data to/from the usb. ? the current transaction comple tes on a page boundary (i.e. the last byte moved for the current transaction is the last byte in the page for the current page pointer). the host controller must increment c_page before writing back status for the transaction. note that the only valid adjustment the host controller may make to c_page is to increment by one. 30.8.3.10.7 adding interrupt queu e heads to the periodic schedule the link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can be executed for the queue head. queue heads are linked into the periodic schedule so they are polled at the appropriate rate. system software sets a bit in a queue head's s-mask to indicate which micro-frame with-in a 1 millisecond period a transaction should be ex ecuted for the queue head. software must ensure high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-145 that all queue heads in the periodic schedule have s-mask set to a non-zero value. an s-mask with a zero value in the context of the periodi c schedule yields undefined results. if the desired poll rate is greater than one frame, sy stem software can use a combination of queue head linking and s-mask values to spread interrupts of equal poll rates through the schedule so that the periodic bandwidth is allocated and managed in the most effi cient manner possible. some examples are illustrated in table 30-68 . table 30-68. example periodic reference patterns for interrupt transfers with 2ms poll rate 30.8.3.10.8 managing transfer complete interrupts from queue heads the host controller will set an interrupt to be signaled at the next interrupt threshold when the completed transfer (qtd) has an interrupt on complete ( ioc ) bit set to a one, or whenever a transfer (qtd) completes with a short packet. if system software needs multiple qtds to complete a client request (i.e. like a control transfer) the intermediate qtds do not require interrupt s. system software may only need a single interrupt to notify it that the complete buffer has been transferred. system software may set ioc's to occur more frequently. a motivation for this may be that it wants early notification so that interface data structures can be re-used in a timely manner. 30.8.3.11 ping control usb 2.0 defines an addition to the protocol for high- speed devices called ping. ping is required for all usb 2.0 high-speed bulk and control endpoints. ping is not allowed for a split-transaction stream. this extension to the protocol eliminates the bad side-effects of naking out endpoints. the status field has a ping state bit, which the host controller uses to determine the next actual pid it will use in the next transaction to the endpoint (see table 30-51 ). the ping state bit is only managed by the host controller for queue heads that meet the following criteria: ? queue head is not an interrupt and ? eps field equals high-speed and ? pidcode field equals out frame # reference sequence description 0, 2, 4, 6, 8, etc. s-mask = 01h a queue head for the binterval of 2 milliseconds (16 micro-frames) is linked into the periodic schedule so that it is reachable from the periodic frame list locations indicated in the previous column. in addition, the s-mask field in the queue head is set to 01h, indicating that the transaction for the endpoint should be executed on the bus during micro-frame 0 of the frame. 0, 2, 4, 6, 8, etc. s-mask = 02h another example of a queue head with a binterval of 2 milliseconds is linked into the periodic frame list at exactly the same interval as the previous example. however, the s-mask is set to 02h indicating that the transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-146 freescale semiconductor table 30-69 illustrates the state transition table for the host controller's responsibility for maintaining the ping protocol. refer to chapter 8 in the usb spec ification revision 2.0 for de tailed description on the ping protocol. table 30-69. ping control state transition table the defined ping protocol (see usb 2.0 specif ication, chapter 8) allows the host to be imprecise on the initialization of the ping protocol (i.e. start in do out when we don't know whether there is space on the device or not). the host controller manages the ping state bit. system software sets the initial value in the queue head when it initializes a queue head. the host controller preserves the ping state bit across all queue advancements. this means that when a new qtd is written into the queue head overlay area, the previous value of the ping state bit is preserved. event current host device next do ping ping nak do ping do ping ping ack do out do ping ping xacterr 1 1 transaction error (xacterr) is any time the host misses the handshake. do ping do ping ping stall n/c 2 do 2 no transition change required for the ping state bit. the stall handshake results in the endpoint being halted (e.g. active set to zero and halt set to a one). software intervention is required to restart queue. 3 a nyet response to an out means that the device has accepted the data, but cannot receive any more at this time. host must advance the transfer state and additionally, transition the ping state bit to do ping . the ping state bit has the following encoding: out out nak do ping do out out nyet do ping do out out ack do out do out out xacterr 1 do ping do out out stall n/c 2 value meaning 0b do out the host controller will use an out pid during the next bus transaction to this endpoint. 1b do ping the host controller will use a ping pid during the next bus transaction to this endpoint. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-147 30.8.3.12 split transactions usb 2.0 defines extensions to the bus protocol for managing usb 1.x data streams through usb 2.0 hubs. this section describes how the host controller uses th e interface data structures to manage data streams with full- and low-speed devices, connected belo w usb 2.0 hub, utilizing the split transaction protocol. refer to usb 2.0 specification for the complete defi nition of the split transaction protocol. full- and low-speed devices are enumerated identically as high-speed devices, but the transactions to the full- and low-speed endpoints use the split-transaction prot ocol on the high-speed bus. the split transaction protocol is an encapsulation of (or wrapper around) the full- or low-speed transaction. the high-speed wrapper portion of the protocol is addressed to the usb 2.0 hub and tr ansaction translator below which the full- or low-speed device is attached. the ehci interface uses dedicated data structures for managing full-speed isochronous data streams (see section split transaction isochronous transfer descri ptor (sitd)). control, bulk and interrupt are managed using the queuing data structures (see sections queue head). the interface data structures need to be programmed with the device address and the transaction translator number of the usb 2.0 hub operating as the low-/full-speed host controller for th is link. the following sections describe the details of how the host controller must process a nd manage the split tr ansaction protocol. 30.8.3.12.1 split transactions for asynchronous transfers a queue head in the asynchronous schedule with an eps field indicating a full-or low-speed device indicates to the host controller that it must use split transactions to stream data for this queue head. all full-speed bulk and full-, low-speed control are ma naged via queue heads in the asynchronous schedule. software must initialize the queue head with the appropriate device addre ss and port number for the transaction translator that is serving as the full/l ow-speed host controller for the links connecting the endpoint. software must also initializ e the split transaction state bit ( splitxstate ) to do-start-split . finally, if the endpoint is a control endpoi nt, then system software must set the control transfer type ( c ) bit in the queue head to a one. if this is not a control transfer type endpoint, the c bit must be initialized by software to be a zero. this information is used by the host controller to properly set the endpoint type (et) field in the split transaction bus token. when the c bit is a zero, the split transaction token's et field is set to indicate a bulk endpoint. when the c bit is a one, the split transaction token's et field is set to indicate a control endpoint. refer to chapter 8 of usb specification revision 2.0 for details. figure 30-65. host controller asynchronous schedule split-transaction state machine high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-148 freescale semiconductor asynchronous - do start split this is the state which software must initialize a full- or low-speed asynchronous queue head. this state is entered from the do complete split state only after a complete-split transaction receives a valid response from the transaction translator that is not a nyet handshake. for queue heads in this state, the host controller will execute a start-split transaction to the appropriate transaction translator. if the bus transaction completes without an error and pidcode indicates an in or out transaction, then the host controll er will reload the error counter ( cerr ). if it is a successful bus transaction and the pidcode indicates a setup, the host controller will not reload the error counter. if the transaction translator responds with a nak, the queue head is left in this state, and the host controller proceeds to the next queue h ead in the asynchronous schedule. if the host controller times out the transaction (no respons e, or bad response) the host controller decrements cerr and proceeds to the next queue head in the asynchronous schedule. asynchronous - do complete split this state is entered from the do start split state only after a start-split transaction receives an ack handshake from the transaction translator. for queue heads in this state, the host controller will ex ecute a complete-split transaction to the appropriate transaction translator. if the transaction translator re sponds with a nyet handshake , the queue head is left in this state, the error counter is reset and the host controller proceeds to the next queue head in the asynchronous schedule. when a nyet handshake is recei ved for a bus transaction where the queue head?s pidcode indicates an in or out, the host cont roller will reload the error counter ( cerr ). when a nyet handshake is received for a complete-split bus transaction where the queue head?s pidcode indicates a setup, the host controller must not adjust the value of cerr . independent of pidcode , the following responses have the effects: ? transaction error (xacterr). timeout or data crc failure, etc. the error counter ( cerr ) is decremented by one and the complete split transaction is immediately retried (if possible). if there is not enough time in the micro-frame to execute th e retry, the host controller must ensure that the next time the host controller begins executing from the asynchronous schedule, it must begin executing from this queue head. if another start- split (for some other endpoint) is sent to the transaction translator before the complete-split is really completed, the transaction translator could dump the results (which were never delivered to the host). this is why the core specification states the retries must be immediate. a method to acco mplish this behavior is to not advance the asynchronous schedule. when the host controller re turns to the asynchronous schedule in the next micro-frame, the first transaction from the schedule will be the retry for this endpoint. if cerr went to zero, the host controller must halt the queue. ? nak. the target endpoint nak'd the full- or low-sp eed transaction. the state of the transfer is not advanced and the state is exited. if the pidcode is a setup, then the nak response is a protocol error. the xacterr status bit is set to a one and the cerr field is decremented. ? stall. the target endpoint responded with a st all handshake. the host controller sets the halt bit in the status byte, retires the qtd but does not attempt to advance the queue. ? if the pidcode indicates an in, then any of following responses are expected: high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-149 ? data0/1. on reception of data, the host controll er ensures the pid matches the expected data toggle and checks crc. if the packet is good , the host controller will advance the state of the transfer, e.g. move the data pointer by the number of bytes received, decrement bytestotransfer field by the number of bytes received, and toggle the dt bit. the host controller will then exit this state. the response and advancement of transfer may trigger other processing events, such as retirement of the qtd and advancement of the queue. ? if the data sequence pid does not match the expecte d, the data is ignored, the transfer state is not advanced and this state is exited. if the pidcode indicates an out/setup, then any of following responses are expected: ? ack. the target endpoint accepted the data, so th e host controller must advance the state of the transfer. the current offset field is incremented by maximum packet length or bytes to transfer , whichever is less. the field bytes to transfer is decremented by the same amount and the data toggle bit ( dt ) is toggled. the host controller will then exit this state. ? advancing the transfer state may cause other proce ssing events such as retirement of the qtd and advancement of the queue (see section managing control/bulk/i nterrupt transfers via queue heads). 30.8.3.12.2 split transaction interrupt split-transaction interrupt-in/out endpoints are ma naged via the same data structures used for high-speed interrupt endpoints. they both co-exist in the periodic schedule. queue heads/qtds offer the set of features required for reliable data delivery, whic h is characteristic to interrupt transfer types. the split-transaction protocol is mana ged completely within this defined functional transfer framework. for example, for a high-speed endpoint, the host controll er will visit a queue head, execute a high-speed transaction (if criteria are met) and advance the transfer state (or not) depending on the results of the entire transaction. for low- and full-speed endpoints, the details of the execution phase are different (i.e. takes more than one bus transaction to complete), but the remainder of the operational framework is intact. this means that the transfer advancement, etc. occurs as defined in section managing control/bulk/interrupt transfers via queue heads, but only occurs on the completion of a split transaction. split transaction scheduling mechanisms for interrupt full- and low-speed interrupt queue heads have an eps field indicating full- or low-speed and have a non-zero s-mask field. the host controller can detect this combination of parame ters and assume the endpoint is a periodic endpoint. low- and full-speed interrupt queue heads require the use of the split transaction protocol. the host controller sets the endpoint type (et) field in the split token to indicate the transaction is an interrupt. these transactions ar e managed through a transaction translator's periodic pipeline. software should not set these fields to indi cate the queue head is an interrupt unless the queue head is used in the periodic schedule. system software manages the per/transaction tr anslator periodic pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for each endpoint will occur. the characteristics of the transaction translator are such that the high-speed transac tion protocol must execute during explicit micro-frames, or the data or response information in the pipeline is lost. figure illustrates the general scheduling boundary conditions that are supported by the ehci periodic schedule and queue high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-150 freescale semiconductor head data structure. the s and c x labels indicate micro-frames where so ftware can schedule strt-splits and complete splits (respectively). figure 30-66. split transaction, interrupt scheduling boundary conditions the scheduling cases are: ? case 1: the normal scheduling case is where the entire split transaction is completely bounded by a frame ( h-frame in this case). ? case 2a through case 2c: the usb 2.0 hub pipeli ne rules states clearly, when and how many complete-splits must be scheduled to account for ea rliest to latest execution on the full/low-speed link. the complete-splits may span the h-frame boundary when the start-split is in micro-frame 4 or later. when this occurs, the h-frame to b-frame alignment requires that the queue head be reachable from consecutive periodic frame list locati ons. system software cannot build an efficient schedule that satisfies this requi rement unless it uses fstns. figure 30-67 illustrates the general layout of the periodic schedule. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-151 figure 30-67. general structure of ehci peri odic schedule utilizing interrupt spreading the periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root. each level in the tree corresponds to a 2 n poll rate. software can efficiently manage periodic bandwidth on the usb by spreading interrupt queue heads that have the sa me poll rate requirement across all the available paths from the frame list. for example, sy stem software can schedule eight poll rate 8 queue heads and account for them once in the high-speed bus bandwidth allocation. when an endpoint is allocated an execution footprin t that spans a frame boundary, the queue head for the endpoint must be reachable from consecutive locations in the frame list. an example would be if 8 0b where such an endpoint. without additional support on the interface, to get 8 0b reachable at the correct time, software would have to link 8 1 to 8 0b . it would then have to move 4 1 and everything linked after into the same path as 4 0 . this upsets the integrity of the binary tree and disallows the use of the spreading technique. fstn data structures are used to preserve the integr ity of the binary-tree structure and enable the use of the spreading technique. section host controller oper ational model for fstns defines the hardware and software operational model requirements for using fstns. the following queue head fields are initialized by system software to instruct the host controller when to execute portions of the split-transaction protocol. ? splitxstate . this is a single bit residing in the status field of a queue head (see table 30-51 ). this bit is used to track the current state of the split transaction. ? frame s-mask . this is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an h-frame ) that the host controller should execute a start-split transaction. this is always qualified by the value of the splitxstate bit in the status field of the queue head. for example, referring to figure , case one, the s-mask would have a value of 00000001b indicating that if the queue head is traversed by the host controller, and the splitxstate indicates do_start , and the current micro-frame as indicated by frindex[2:0] is 0, then execute a start-split transaction. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-152 freescale semiconductor ? frame c-mask. this is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an h-frame ) that the host controller should execute complete-split transactions. the interpretation of this fi eld is always qualified by the value of the splitxstate bit in the status field of the queue head. for example, referring to figure , case one, the c-mask would have a value of 00011100b indicating that if the que ue head is traversed by the host controller, and the splitxstate indicates do_complete , and the current micro-frame as indicated by frindex[2:0] is 2, 3, or 4, then execute a complete -split transaction. it is software's responsibility to ensure that the translation between h-frames and b-frames is correctly performed when setting bits in s-mask and c-mask host controller operational model for fstns the fstn data structure is used to manage low/full- speed interrupt queue heads that need to be reached from consecutive frame list locations (i.e. boundary cases 2a through 2c). an fstn is essentially a back pointer , similar in intent to the back pointer field in the sitd data structure (see section sitd back link pointer). this feature provides software a simple primitive to sa ve a schedule position, redirect the host controller to traverse the necessary queue heads in the previous frame, then restore the original schedule position and complete normal traversal. there are four components to the use of fstns: ? fstn data structure. ?a save place indicator. this is always an fstn with its back path link pointer. t-bit set to zero. ?a restore indicator. this is always an fstn with its back path link pointer.t-bit set to a one. ? host controller fstn traversal rules. host controller operat ional model for fstns when the host controller encounters an fstn during micro-frames 2 through 7 it simply follows the node?s normal path link pointer to access the next schedule data st ructure. note that the fstn?s normal path link pointer.t-bit may set to a one, which the host controller mu st interpret as the end of periodic list mark. when the host controller encounters a save-place fstn in micro-frames 0 or 1, it will save the value of the normal path link pointer and set an internal flag indicating that it is executing in recovery path mode. recovery path mode modifies the host controller?s rules fo r how it traverses the schedule and limits which data structures will be considered for execution of bus transactions. the host controller continues executing in recovery path mode until it encounters a restore fstn or it determines that it has reached the end of the micro-frame (see details in the list below). the rules for schedule traversal and limited execution while in recovery path mode are: ? always follow the normal path link pointer when it encounters an fstn that is a save-place indicator. the host controller must not recursively follow save-place fstns. therefore, while executing in recovery path mode, it must never follow an fstn?s back path link pointer . ? do not process an sitd or, itd data structure. simply follow its next link pointer . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-153 ? do not process a qh (queue head) whose eps field indicates a high-speed device. simply follow its horizontal link pointer . ? when a qh?s eps field indicates a full/low-speed device, the host controller will only consider it for execution if its splitxstate is docomplete (note: this applies whether the pid code indicates an in or an out). see sections execute transa ction and tracking split transaction progress for interrupt transfers for a complete list of additiona l conditions that must be met in general for the host controller to issue a bus transaction. note that the host controller must not execute a start-split transaction while executing in recovery path mode. see section periodic interrupt - do complete split for special handling when in recovery path mode. ? stop traversing the recovery path when it encounters an fstn that is a restore indicator. the host controller unconditionally uses the saved value of the save-place fstn?s normal path link pointer when returning to the normal path traversal. the host controller must clear the context of executing a recovery path when it restores schedule traversal to the save-place fstn?s normal path link pointer . ? if the host controller determines that there is no t enough time left in the micro-frame to complete processing of the periodic schedule, it abandons traversal of the recovery path, and clears the context of executing a recovery path. the result is that at the start of the next consecutive micro-frame, the host controller starts traversal at the frame list. an example traversal of a periodic schedule that includes fstns is illustrated in figure 30-68 . figure 30-68. example host controller traversal of recovery path via fstns in frame n+1 (micro-frames 0 and 1), when the hos t controller encounters save-path fstn (save-n), it observes that save-n.back path link pointer.t-bit is zero (definition of a save-path indicator). the host controller saves the value of sa ve-n.normal path link pointer a nd follows save-n.back path link pointer. at the same time, it sets an internal flag indicating that it is now in recovery path mode (the recovery path is annotated in figure 30-9 with a large dashed line). the host controller continues traversing data structures on the recovery path and executing only those bus transactions as noted above, on the recovery path until it reaches restore fstn (restore-n). restore-n.back path link pointer.t-bit is set to a one (definition of a restore indicator), so the host controller exits recovery path mode by clearing the internal recovery path mode flag and commences (restores) schedule traversal using the high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-154 freescale semiconductor saved value of the save-place fstn?s normal path link pointer (e.g. save-n.normal path link pointer). the nodes traversed during these micro-frames include: {8 3.0 , 8 3.1 , 8 3.2 , save-a, 8 2.2 , 8 2.3 , 4 2 , 2 0 , restore-n , 4 3 , 2 1 , restore-n, 1 0 ?}. the nodes on the recovery-path are bolded.in frame n (micro-frames 0-7), for this example, the host controller will traverse all of th e schedule data structures utilizing the normal path link pointers in any fstns it encounters. this is because the host controller has not yet encountered a save-place fstn so it not executing in recovery path mode. when it encounters the restore fstn, (restore-n), during micro-frames 0 and 1, it uses restore-n.normal path link pointer to traverse to the next data structure (i .e. normal schedule traversal) . this is because the host controller must use a restore fstn?s normal path link pointer when not executing in a recovery-path mode. the nodes traversed during frame n include: {8 2.0 , 8 2.1 , 8 2.2 , 8 2.3 , 4 2 , 2 0 , restore-n, 1 0 ?}. in frame n+1 (micro-frames 2-7), when the host c ontroller encounters save-path fstn save-n, it will unconditionally follow save-n.normal path link pointe r. the nodes traversed during these micro-frames include: {8 3.0 , 8 3.1 , 8 3.2 , save-a, 4 3 , 2 1 , restore-n, 1 0 ?}. software operational model for fstns software must create a consistent, coherent schedul e for the host controller to traverse. when using fstns, system software must adhere to the following rules: ?each save-place indicator requires a matching restore indicator. ? the save-place indicator is an fstn with a valid back path link pointer and t-bit equal to zero. note that back path link pointer.typ field must be set to indicate the referenced data structure is a queue head. the restore indicator is an fstn with its back path link pointer.t-bit set to a one. ?a restore fstn may be matched to one or more save-place fstns. for example, if the schedule includes a poll-rate 1 level, then system software only needs to place a restore fstn at the beginning of this list in order to match all possible save-place fstns. ? if the schedule does not have elements linked at a poll-rate level of one, and one or more save-place fstns are used, then system software must ensure the restore fstn?s normal path link pointer ?s t-bit is set to a one, as this will be use to mark the end of the periodic list. ? when the schedule does have elements linked at a poll rate level of one, a restore fstn must be the first data structure on the poll rate one list. all traversal paths from the frame list converge on the poll-rate one list. system software must ensure that recovery path mode is exited before the host controller is allowed to traverse the poll rate level one list. ?a save-place fstn?s back path link pointer must reference a queue head data structure. the referenced queue head must be reachable from the previous frame list location. in other words, if the save-place fstn is reachable from frame list offset n, then the fstn?s back path link pointer must reference a queue head that is reachable from frame list offset n-1. software should make the schedule as efficient as possible. what this means in this context is that software should have no more than one save-place fstn reachable in any single frame. note there will be times when two (or more, depending on the implementation) coul d exist as full/low-speed footprints change with bandwidth adjustments. this could occur, for ex ample when a bandwidth rebalance causes system software to move the save-place fstn from one poll rate level to another. during the transition, software must preserve the integrity of the previous schedule until the new schedule is in place. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-155 tracking split transaction progress for interrupt transfers to correctly maintain the data stream, the host controller must be able to detect and report errors where data is lost. for interrupt-in transf ers, data is lost when it makes it into the usb 2.0 hub, but the usb 2.0 host system is unable to get it from the usb 2.0 hub and into the system before it expires from the transaction translator pipeline. when a lost data c ondition is detected, the queue must be halted, thus signaling system software to recover from the error. a data-loss condition exists whenever a start-split is issued, accepted and successfully executed by the us b 2.0 hub, but the complete -splits get unrecoverable errors on the high-speed link, or the complete-splits do not occur at the correct times. one reason complete-splits might not occur at the right time would be due to host-induced system hold-offs that cause the host controller to miss bus transactions because it cannot get timely access to the schedule in system memory. the same condition can occur for an interrupt-out, but the result is not an endpoint halt condition, but rather effects only the progress of the transfer. the queue head has the following fields to track the progress of each split transaction. these fields are used to keep incremental state about which (and when) portions have been executed. ? c-prog-mask . this is an eight-bit bit-vector wher e the host controller keeps track of which complete-splits have been executed. due to the nature of the transaction translator periodic pipeline, the complete-splits need to be executed in-order. the host controller needs to detect when the complete-splits have not been executed in order. this can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. c-prog-mask is a simple bit-vector that the host controller sets one of the c-prog- mask bits for each complete-split executed. the bit position is determined by the micro-frame number in which the complete-split was executed. the host controller always checks c-prog-mask before executing a complete-split transaction. if the previous complete-splits have not been executed then it means one (or more) have been skipped and data has potentially been lost. ? frametag . this field is used by the host controller during the complete-split portion of the split transaction to tag the queue head with the frame number ( h-frame number) when the next complete split must be executed. ? s - bytes . this field can be used to store the number of data payload bytes sent during the start-split (if the transaction was an out). the s-bytes field must be used to accumulate the data payload bytes received during the complete-splits (for an in). split transaction execution state machine for interrupt in the following presentation, all references to micro-frame are in the context of a micro-frame within an h-frame. as with asynchronous full- and low-speed endpoints, a split-transaction state machine is used to manage the split transaction sequence. aside from the fields defined in the queue head for scheduling and tracking the split transaction, the host controller calculates one internal mechanism that is also used to manage the split transaction. the internal calculated mechanism is: ? cmicroframebit . this is a single-bit encoding of the current micro-frame number. it is an eight-bit value calculated by the host controller at the beginni ng of every micro-frame. it is calculated from the three least significant bits of the frindex register (i.e. cmicroframebit = (1 high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-156 freescale semiconductor shifted-left( frindex [2:0]))). the cmicroframebit has at most one bit asserted, which always corresponds to the current micro-frame number. for example, if the current micro-frame is 0, then cmicroframebit will equal 00000001b. the variable cmicroframebit is used to compare against the s-mask and c-mask fields to determine whether the queue head is marked for a start- or complete-splt transaction for the current micro-frame. figure 30-69 illustrates the state machine for managing a complete interrupt split transaction. there are two phases to each split transaction. the first is a single start-split transaction, which occurs when the splitxstate is at do_start and the single bit in cmicroframebit has a corresponding bit active in qh.s-mask . the transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller unconditionally transitions the state to do_complete . due to the available jitter in the transaction translator pipeline, th ere will be more than one comple te-split transaction scheduled by software for the do_complete state. this translates simply to the fact that there are multiple bits set to a one in the qh.c-mask field. the host controller keeps the queue head in the do_complete state until the split transaction is complete (see definition below), or an error condition triggers the three-strikes-rule (e.g. after the host tries the same transaction three times, and each encounters an error, the host controller will stop retrying the bus transaction and halt the endpoint, thus requiring syst em software to detect the condition and perform system-dependent recovery). figure 30-69. split transaction state machine for interrupt **see previous section for the frame tag management rules. periodic interrupt - do start split this is the state software must initialize a full- or low-speed interrupt queue head startxstate bit. this state is entered from the do_complete split state only after the split transaction is complete. this occurs when one of the following events occur: the transaction tr anslator responds to a comp lete-split transaction with one of the following: ? nak. a nak response is a propagation of the full- or low-speed endpoint's nak response. ? ack. an ack response is a propagation of the fu ll- or low-speed endpoint's ack response. only occurs on an out endpoint. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-157 ? data 0/1. only occurs for ins. indicates that this is the last of the data from the endpoint for this split transaction. ? err. the transaction on the low-/full-speed link be low the transaction translator had a failure (e.g. timeout, bad crc, etc.). ? nyet (and last). the host controller issued the la st complete-split and the transaction translator responded with a nyet handshake. this means that the start-split was not correctly received by the transaction translator, so it never executed a transaction to the full- or low-speed endpoint, see section periodic interrupt - do complete split for the definition of ?last?. each time the host controller visits a queue head in this state (once within the execute transaction state), it performs the following test to deter mine whether to execute a start-split. ? qh.s-mask is bit-wise anded with cmicroframebit . if the result is non-zero, then the host controller will issue a start-split transaction. if the pidcode field indicates an in transaction, the host controller must zero-out the qh.s-bytes field. after the split-transaction has been executed, the host controller sets up state in th e queue head to track the progress of the complete-split phase of the split transaction. sp ecifically, it records the expected frame number into qh.frametag field (see section managing qh.frametag field ), set c-prog-mask to zero (00h), and exits this state. note that the host controller must not adjust the value of cerr as a result of completion of a start-split transaction. periodic interrupt - do complete split this state is entered unconditionally from the do start split state after a start-split transaction is executed on the bus. each time the host controller visits a queue head in this state (once within the execute transaction state), it checks to determine whether a complete-split transaction should be executed now. there are four tests to determine whether a complete-split transaction should be executed. ? te st a . cmicroframebit is bit-wise anded with qh.c-mask field. a non-zero result indicates that software scheduled a complete-split for this endpoint, during this micro-frame. ? te st b . qh.frametag is compared with the current contents of frindex [7:3]. an equal indicates a match. ? te st c . the complete-split progress bit vector is checked to determine whether the previous bit is set, indicating that the previous complete-split was appropriately executed. an example algorithm for this test is provided below: algorithm boolean checkpreviousbi t(qh.c-prog-mask, qh.c-mask, cmicroframebit) begin -- return values: -- true - no error -- false - error -- boolean rvalue = true; previousbit = cmicroframebit logical-rotate-right(1) high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-158 freescale semiconductor -- bit-wise anding previousbit with c-mask indicates -- whether there was an intent -- to send a complete split in the previous micro-frame. so, -- if the -- 'previous bit' is set in c-mask, check c-prog-mask to -- make sure it -- happened. if (previousbit bitand qh.c-mask)then if no t(previousbit bitand qh.c-prog-mask) then rvalue = false; end if end if -- if the c-prog-mask already has a one in this bit position, -- then an aliasing -- error has occurred. it will probably get caught by the -- frametag test, but -- at any rate it is an error condition that as detectable here -- should not allow -- a transaction to be executed. if (cmicroframebit bitand qh.c-prog-mask) then rvalue = false; end if return (rvalue) end algorithm ? te st d. check to see if a start-split should be executed in this micro-frame. note this is the same test performed in the do start split state (see section periodic interrupt - do start split ). whenever it evaluates to true and the contro ller is not processing in the context of a recovery path mode, it means a start-split should occur in this micro-frame. test d and test a evaluating to true at the same time is a system so ftware error. behavior is undefined. if (a .and. b .and. c .and. not(d)) then the host controlle r will execute a complete-split transaction. when the host controller commits to executing the complete-split tr ansaction, it updates qh.c-prog-mask by bit-oring with cmicroframebit . on completion of the complete-split transaction, the host controller records the result of the transaction in the queue head and sets qh.frametag to the expected h-frame number (see section managing qh.frametag field ). the effect to the state of the queue head and thus the state of the transfer depends on the response by the transaction translator to the complete-split high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-159 transaction. the following responses have the effects ( note that any responses that result in decrementing of the cerr will result in the queue head being halted by th e host controller if the result of the decrement is zero): ? nyet (and last). on each nyet response, the host controller checks to determine whether this is the last complete-split for this split transacti on. last is defined in this context as the condition where all of the scheduled complete-splits have been executed. if it is the last complete-split (with a nyet response), then the transfer state of the queue head is not advanced (never received any data) and this state exited. the transaction translat or must have responded to all the clompete-splits with nyets, meaning that the start-split issued by the host controller was not received. the start-split should be retried at the next poll period. ? the test for whether this is the last complete split can be performed by xor qh.c-mask with qh.c-prog-mask . if the result is all zeros then all complete-splits have been executed. when this condition occurs, the xacterr status bit is set to a one and the cerr field is decremented. ? nyet (and not last). see above description for testing for last . the complete-split transaction received a nyet response from the transaction tran slator. do not update any transfer state (except for c-prog-mask and frametag ) and stay in this state. the host controller must not adjust cerr on this response. ? transaction error (xacterr). timeout, data crc failure, etc. the cerr field is decremented and the xacterr bit in the status field is set to a one. the complete split transaction is immediately retried (if cerr is non-zero).if there is not enough time in th e micro-frame to complete the retry and the endpoint is an in, or cerr is decremented to a zero from a one, the queue is halted. if there is not enough time in the micro-frame to complete the retry and the endpoint is an out and cerr is not zero, then this state is exited (i.e. return to do start split ). this results in a retry of the entire out split transaction, at the next poll period. refe r to chapter 11 hubs (specifically the section full- and low-speed interrupts) in the usb spec ification revision 2.0 for detailed requirements on why these errors must be immediately retried. ? ack. this can only occur if the target endpoint is an out. the target endpoint ack'd the data and this response is a propagation of the endpoint ack up to the host controller. the host controller must advance the state of the transfer. the current offset field is incremented by maximum packet length or bytes to transfer , whichever is less. the field bytes to transfer is decremented by the same amount. and the data toggle bit ( dt ) is toggled. the host controller will then exit this state for this queue head. the host controller must reload cerr with maximum value on this response. advancing the transfer state may cause other proc ess events such as retirement of the qtd and advancement of the queue (see section managing control/bulk/i nterrupt transfers via queue heads). ? mdata. this response will only occur for an in endpoint. the transaction translator responded with zero or more bytes of data and an mdata pi d. the incremental number of bytes received is accumulated in qh.s-bytes . the host controller must not adjust cerr on this response. ? data0/1. this response may only occur for an in endpoint. the number of bytes received is added to the accumulated byte count in qh.s-bytes . the state of the transfer is advanced by the result and the host controller will exit this state for this queue head. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-160 freescale semiconductor ? advancing the transfer state may cause other proce ssing events such as retirement of the qtd and advancement of the queue (see section managing control/bulk/i nterrupt transfers via queue heads). ? if the data sequence pid does not match the expected, the entirety of the data received in this split transaction is ignored, the transfer state is not advanced and this state is exited. ? nak. the target endpoint nak'd the full- or low-sp eed transaction. the state of the transfer is not advanced, and this state is exite d. the host controller must reload cerr with maximum value on this response. ? err. there was an error during the full- or low-speed transaction. the err status bit is set to a one, cerr is decremented, the state of the transfer is not advanced, and this state is exited. ? stall. the queue is halted (an exit condition of the execute transaction state). the status field bits: active bit is set to zero and the halted bit is set to a one and the qtd is retired. responses which are not enumerated in the list or which are received out of sequence are illegal and may result in undefined host controller behavior. the other possible combinations of tests a, b, c, and d may indicate that data or response was lost. table 30-70 lists the possible combinations and the appropriate action. table 30-70. interrupt in/out do comp lete split state execution criteria condition action description not(a) not(d) ignore qhd neither a start nor complete-split is scheduled for the current micro-frame.host controller should continue walking the schedule. a not(c) if pidcode = in halt qhd if pidcode = out retry start-split progress bit check failed. these means a complete-split has been missed. there is the possibility of lost data. if pidcode is an in, then the queue head must be halted. if pidcode is an out, then the transfer state is not advanced and the state exited (e.g. start-split is retried). this is a host-induced error and does not effect cer r. in either case, set the missed micro-frame bit in the status field to a one. a not(b) c if pidcode = in halt qhd if pidcode = out retry start-split qh.frametag test failed. this means that exactly one or more h-frames have been skipped. this means complete-splits and have missed. there is the possibility of lost data. if pidcode is an in, then the queue head must be halted. if pidcode is an out, then the transfer state is not advanced and the state exited (e.g. start-split is retried). this is a host-induced error and does not effect cer r. in either case, set the missed micro-frame bit in the status field to a one. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-161 managing qh.frametag field the qh.frametag field in a queue head is completely mana ged by the host controller. the rules for setting qh.frametag are simple: ? rule 1: if transitioning from do start split to do complete split and the current value of frindex [2:0] is 6 qh.frametag is set to frindex [7:3] + 1. this accommodates split transactions whose start-split and complete-splits are in different h-frames (case 2a, see figure 30-70 ). ? rule 2: if the current value of frindex [2:0] is 7, qh.frametag is set to frindex [7:3] + 1. this accommodates staying in do complete split for cases 2a, 2b, and 2c ( figure 30-70 ). ? rule 3: if transitioning from do_start split to do complete split and the current value of frindex [2:0] is not 6, or currently in do complete split and the current value of ( frindex [2:0]) is not 7, frametag is set to frindex [7:3]. this accommodates all other cases ( figure 30-70 ). rebalancing the periodic schedule system software must occasionally adjust a periodi c queue head?s s-mask a nd c-mask fields during operation. this need occurs when adjustments to th e periodic schedule create a new bandwidth budget and one or more queue head?s are assigned new executi on footprints (i.e. new s-mask and c-mask values). it is imperative that system software must not update these masks to new values in the midst of a split transaction. in order to avoid any race conditions with the update, the ehci host controller provides a simple assist to system software. system software sets the inactivate-on-next-transaction ( i ) bit to a one to signal the host controller that it intends to updat e the s-mask and c-mask on this queue head. system a b c not(d) execute complete-split this is the non-error case where the host controller executes a complete-split transaction. d if pidcode = in halt qhd if pidcode = out retry start-split this is a degenerate case where the start-split was issued, but all of the complete-splits were skipped and all possible intervening opportunities to detect the missed data failed to fire. if pidcode is an in, then the queue head must be halted. if pidcode is an out, then the transfer state is not advanced and the state exited (e.g. start-split is retried). this is a host-induced error and does not effect cer r. in either case, set the missed micro-frame bit in the status field to a one. note: when executing in the context of a recovery path mode, the host controller is allowed to process the queue head and take the actions indicated above, or it may wait until the queue head is visited in the normal processing mode. regardless, the host controller must not execute a start-split in the context of a executing in a recovery path mode. condition action description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-162 freescale semiconductor software will then wait for the host controller to observe the i-bit is a one and transition the active bit to a zero. the rules for how and when the host controller sets the active bit to zero are enumerated below: ? if the active bit is a zero, no action is taken. the host controller does not atte mpt to advance the queue when the i-bit is a one. ? if the active bit is a one and the splitxstate is dostart (regardless of the value of s-mask ), the host controller will simply set active bit to a zero. the host controller is not required to write the transfer state back to the current qtd. note that if the s-mask indicates that a start-split is scheduled for the current micro-frame, the host controller must not i ssue the start-split bus transaction. it must set the active bit to zero. system software must save transfer state before setting the i-bit to a one. this is required so that it can correctly determine what transfer progress (if any) occurred after the i-bit was set to a one and the host controller executed it?s final bus-transaction and set active to a zero. after system software has updated th e s-mask and c-mask, it must then reactivate the queue head. since the active bit and the i-bit cannot be updated with the same write, system software needs to use the following algorithm to coherently re-activat e a queue head that has been stopped via the i-bit . 4. set the halted bit to a one, then 5. set the i-bit to a zero, then 6. set the active bit to a one and the halted bit to a zero in the same write. setting the halted bit to a one inhibits the host controller fr om attempting to advance the queue between the time the i-bit goes to a zero and the active bit goes to a one. 30.8.3.12.3 split transaction isochronous full-speed isochronous transfers are managed usi ng the split-transaction protocol through a usb 2.0 transaction translator in a usb2.0 hub. the ehci c ontroller utilizes sitd data structure to support the special requirements of isochronous split-transactions. this data structure uses the scheduling model of isochronous tds (itd, section isochronous (high-sp eed) transfer descriptor (itd)) (see section managing isochronous transfers using itds for the ope rational model of itds) with the contiguous data feature provided by queue heads. this simple arra ngement allows a single is ochronous scheduling model and adds the additional feature that all data receive d from the endpoint (per split transaction) must land into a contiguous buffer. split transaction scheduling mechanisms for isochronous full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. as with full- and low-speed interrupt, system software ma nages each transaction translator's periodic pipeline by budgeting and scheduling exactly during which micro -frames the start-splits and complete-splits for each full-speed isochronous endpoint occur. the re quirements described in section split transaction scheduling mechanisms for interrupt apply. figure 30-70 illustrates the general scheduling boundary conditions that are supported by the ehci periodic schedule. the s x and c x labels indicate micro-frames where software can schedule start- a nd complete-splits (respectively). the h-frame boundaries are marked with a large, solid bold vertical line. the b-frame boundaries are marked with a large, bold, dashed line. the bottom of the figure illustrates the relationship of an sitd to the h-frame . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-163 figure 30-70. split transaction, isochronous scheduling boundary conditions when the endpoint is an isochronous out, there are only start-splits, and no complete-splits. when the endpoint is an isochronous in, there is at most one start-split and one to n complete-splits. the scheduling boundary cases are: ? case 1 : the entire split transaction is completely bounded by an h-frame. for example: the start-splits and complete-splits are all scheduled to occur in the same h-frame . ? case 2a : this boundary case is where one or more (at most two) complete-splits of a split transaction in are scheduled across an h-frame boundary. this can only occur when the split transaction has the possibility of moving data in b-frame, micro-frames 6 or 7 ( h-frame micro-frame 7 or 0). when an h-frame boundary wrap condition occurs, the scheduling of the split transaction spans more than one location in the pe riodic list.(e.g. it takes two sitds in adjacent periodic frame list locations to fully describe the scheduling for the split transaction). ? although the scheduling of the split transaction may take two data structures, all of the complete-splits for each full-speed in isochronous transaction must use only one data pointer. for this reason, sitds contain a back pointer , the use of which is described below. ? software must never schedule full-speed isochronous outs across an h-frame boundary. ? case 2b : this case can only occur for a very large isochronous in. it is the only allowed scenario where a start-split and complete-split for the same endpoint can occur in the same micro-frame. software must enforce this rule by scheduling the large transaction first. large is defined to be anything larger than 579 byte maximum packet size. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-164 freescale semiconductor a subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed in sitds to schedule and track the portions of isoc hronous split transactions. the following fields are initialized by system software to instruct the host controller when to execute portions of the split transaction protocol. ? splitxstate . this is a single bit residing in the status field of an sitd (see table 30-46 ). this bit is used to track the current state of the split transaction. the rules for managing this bit are described in section in the following presentation, all refere nces to micro-frame are in the context of a micro-frame within an h-frame.split transaction execution state machine for isochronous . ? frame s-mask . this is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an h-frame ) that the host controller should execute a start-split transaction. this is always qualified by the value of the splitxstate bit. for example, referring to the in example in figure 30-70 , case one, the s-mask would have a value of 00000001b indicating that if the sitd is traversed by the host controller, and the splitxstate indicates do start split , and the current micro-frame as indicated by frindex[2:0] is 0, then execute a start-split transaction. ? frame c-mask. this is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an h-frame ) that the host controller should execute complete-split transactions. the interpretation of this fiel d is always qualified by the value of the splitxstate bit. for example, referring to the in example in figure 30-70 , case one, the c-mask would have a value of 00111100b indicating that if the sitd is traversed by the host controller, and the splitxstate indicates do complete split , and the current micro-frame as indicated by frindex [2:0] is 2, 3, 4, or 5, then execute a complete-split transaction. ? back pointer . this field in a sitd is used to complete an in split-transaction using the previous h-frame 's sitd. this is only used when the scheduling of the complete-splits span an h-frame boundary. there exists a one-to-one relationship between a hi gh-speed isochronous split transaction (including all start- and complete-splits) and one full-speed isoc hronous transaction. an sitd contains (amongst other things) buffer state and split transaction scheduling info rmation. an sitd's buffer state always maps to one full-speed isochronous data payload. this means that for any full-speed transaction payload, a single sitd's data buffer must be used. th is rule applies to both in an outs. an sitd's scheduling information usually also maps to one high-speed isochronous split transaction. the exception to this rule is the h-frame boundary wrap cases mentioned above. the sitd data structure describes at most, one fr ame's worth of high-speed transactions and that description is strictly bounded within a frame boundary. figure 30-71 illustrates some examples. on the top are examples of the full-speed transaction f ootprints for the boundary scheduling cases described above. in the middle are time-frame references for both the b-frames (hs/fs/ls bus) and the h-frames . on the bottom is illustrated the relationship betwee n the scope of an sitd description and the time references. each h-frame corresponds to a single location in the periodic frame list. the implication is that each sitd is reachable from a sing le periodic frame list location at a time. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-165 figure 30-71. sitd scheduling boundary examples each case is described below: ? case 1 : one sitd is sufficient to describe and co mplete the isochronous split transaction because the whole isochronous split transaction is tightly contained within a single h-frame . ? case 2a, 2b : although both ins and outs can have thes e footprints, outs always take only one sitd to schedule. however, ins (for these boundary cases) require two sitds to complete the scheduling of the isochronous split transaction . sitd x is used to always issue the start-split and the first n complete-splits. the full-speed transaction (for these cases) can deliver data on the full-speed bus segment during micro-frame 7 of h-frame y+1 , or micro-frame 0 of h-frame y+2. the complete splits are scheduled using sitd x+2 (not shown). the complete-splits to extract this data must use the buffer pointer from sitd x+1 . the only way for the host controller to reach sitd x+1 from h-frame y+2 is to use sitd x+2 's back pointer. the host controller rules for when to use the back pointer are described is sectio n periodic isochronous - do complete split . software must apply the following rules when cal culating the schedule and linking the schedule data structures into the periodic schedule: ? software must ensure that an isochronous split-transa ction is started so that it will complete before the end of the b-frame . ? software must ensure that for a single full-spe ed isochronous endpoint, there is never a start-split and complete-split in h-frame, micro-frame 1 . this is mandated as a rule so that case 2a and case 2b can be discriminated. according to the core usb specification, the long isochronous transaction illustrated in case 2b, could be scheduled so that the start-split was in micro-frame 1 of h-frame n and the last complete-split would need to occur in micro-frame 1 of h-frame n+1. however, it is impossible to discriminate between cases 2a and case 2b, which has significant impact on the complexity of the host controller. tracking split transaction prog ress for isochronous transfers to correctly maintain the data stream, the host controller must be able to detect and report errors where device to host data is lost. is ochronous endpoints do not employ the concept of a halt on error, however the host is required to identify and report per-packet errors observed in the data stream. this includes schedule traversal problems (skipped micro-frames), timeouts and corrupted data received. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-166 freescale semiconductor in similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in the micro-frames they are scheduled. the queue head data structure used to manage full- and low-speed interrupt has several mechanisms for tracking when portions of a transaction have occurred. isochronous transfers use sitds, for their transfers, and the data structures are only reachable via the schedule in the exact micro-frame in which they are required (so all the mechanism employed for tracking in queue heads is not required for sitds). software has the option of reusing sitd several times in the complete periodic schedule. however, it must ensure that the results of split transaction n are consumed and the sitd reinitialized (activated) before the host controller gets back to the sitd (in a future micro-frame). split-transaction isochronous outs uti lize a low-level protocol to indi cate which portions of the split transaction data have arrived. control over the low-leve l protocol is exposed in an sitd via the fields transaction position ( tp ) and transaction count ( t-count ). if the entire data payload for the out split transaction is larger than 188 bytes, there will be mo re than one start-split transaction, each of which require proper annotation. if host hold-offs occur, then the sequence of annotations received from the host will not be complete, which is de tected and handled by the transacti on translator. see section periodic isochronous - do start split for a description on how these fields are used during a sequence of start-split transactions. the fields sitd.t-count and sitd.tp are used by the host controller to drive and sequence the transaction position annotations. it is the responsibility of system software to properly initialize these fields in each sitd. once the budget for a split-transac tion isochronous endpoint is established, s-mask , t-count , and tp initialization values for all the sitd associated with the endpoint are constant. they remain constant until the budget for the endpoint is recalculated by software and the periodic schedule adjusted. for in-endpoints, the transaction translator simply annotates the response data packets with enough information to allow the host controller to identify the la st data. as with split transaction interrupt, it is the host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. the following field in the sitd is used to track and detect errors in the execution of a split transaction for an in isochronous endpoint. ? c-prog-mask . this is an eight-bit bit-vector wher e the host controller keeps track of which complete-splits have been executed. due to the nature of the transaction translator periodic pipeline, the complete-splits need to be executed in-order. the host controller needs to detect when the complete-splits have not been executed in order. this can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. c-prog-mask is a simple bit-vector that the host controller sets a bit for each complete-split executed. the bit position is determined by the micro-frame (frindex[2:0]) number in which the complete-split was executed. the host controller always checks c-prog-mask before executing a complete-split transaction. if the previous complete-splits have not been executed, then it means one (or more) have been skipped and data has potentially been lost. system software is required to initialize this field to zero before setting an sitd's active bit to a one. if a transaction translator returns with the final data before all of the complete-s plits have been executed, the state of the transfer is advanced so that the remaining complete-splits are not executed. refer to section periodic isochronous - do complete split for a descri ption on how the state of the transfer is advanced. it is important to note that an in sitd is retired based solely on the responses from the transaction translator to the complete-split transactions. this mean s, for example, that it is possible for a transaction translator to respond to a complete-split with an md ata pid. the number of bytes in the mdata's data high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-167 payload could cause the sitd field total bytes to transfer to decrement to zero. this response can occur, before all of the scheduled comple te-splits have been executed. in ot her interface, data structures (e.g. high-speed data streams through queue heads), the transition of total bytes to transfer to zero signals the end of the transfer and results in setting of the active bit to zero. however, in this case, the result has not been delivered by the transaction translator and th e host must continue with the next complete-split transaction to extract the residual transaction state. th is scenario occurs because of the pipeline rules for a transaction translator (see chapter 11 of the universal serial bus revision 2.0). in summary the periodic pipeline rules require that on a micro-fram e boundary, the transaction translator will hold the final two bytes received (if it has not seen an end of packet (eop)) in the full-speed bus pipe stage and give the remaining bytes to the high-speed pipeline stage. at the micro-frame boundary, the transaction translator could have received the entire packet (including both crc bytes) but not received the packet eop. in the next micro-frame, the transaction transl ator will respond with an mdata and send all of the data bytes (with the two crc bytes being held in the full-speed pipeline stage). this could cause the sitd to decrement it's total bytes to transfer field to zero, indicating it has received all expected data. the host must still execute one more (scheduled) complete-split transaction in order to extract the results of the full-speed transaction from the transaction translator (for example, the transaction translator may have detected a crc failure, and this re sult must be forwarded to the host). if the host experiences hold-offs that cause the host cont roller to skip one or more (but not all) scheduled split transactions for an isochronous out, then the protocol to the transaction translator will not be consistent and the transaction translator will detect and react to the problem. likewise, for host hold-offs that cause the host controller to skip one or more (but not all) scheduled split transactions for an isochronous in, the c-prog-mask is used by the host controller to de tect errors. however, if the host experiences a hold-off that causes it to skip all of an sitd, or an sitd expires during a host hold off (e.g. a hold-off occurs and the sitd is no longer reachable by the host controller in order for it to report the hold-off event), then system software must detect that the sitds have not been processed by the host controller (e.g. state not advanced) and report the appropriate error to the client driver. in the following presentation, all references to micro-frame are in the context of a micro-frame within an h-frame. split transaction execution state machine for isochronous if the active bit in the status byte is a zero, the host controller will i gnore the sitd and continue traversing the periodic schedule. otherwise the host controller will process the sitd as specified below. a split transaction state machine is used to manage the spl it-transaction protocol seque nce. the host controller uses the fields defined in section tracking split transaction progress for isochronous transfers , plus the variable cmicroframebit defined in section split transaction execution state machine for interrupt to track the progress of an is ochronous split transaction. figure 30-72 illustrates the state machine for managing an sitd through an isochronous split transact ion. bold, dotted circles denote the state of the active bit in the status field of a sitd. the bold, dotted arcs denote the transitions between these states. solid circles denote the states of the split transaction state machine and the solid arcs denote the transitions between these states. dotted arcs and boxes reference actions that take place either as a result of a transition or from being in a state. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-168 freescale semiconductor figure 30-72. split transaction state machine for isochronous periodic isochronous - do start split isochronous split transaction outs use only this state. an sitd for a split-transaction isochronous in is either initialized to this state, or the sitd transitions to this state from do complete split when a case 2a (in) or 2b scheduling boundary isochr onous split-transaction completes. each time the host controller reaches an active sitd in this state, it checks the sitd.s - mask against cmicroframebit . if there is a one in the appropriate position, the sitd will execute a start-split transaction. by definition, the host controller cannot reach an sitd at the wrong time. if the i/o field indicates an in, then the start-split transaction includes only the extended token plus the full-speed token. software must initialize the sitd.total bytes to transfer field to the number of bytes expected. this is usually the maximum packet size for the full-speed endpoint. the hos t controller exits this state when the start-split transaction is complete. the remainder of this section is specific to an isochronous out endpoint (i.e. the i/o field indicates an out). when the host controller executes a start-split transaction for an isochronous out it includes a data payload in the start-split transaction. the memory buf fer address for the data payload is constructed by concatenating sitd.current offset with the page pointer indicated by the page selector field ( sitd.p ). a zero in this field selects page 0 and a 1 selects page 1. during the start-split for an out, if the data transfer crosses a page boundary during the transaction, the host controller must detect the page cross, update the sitd.p -bit from a zero to a one, and begin using the sitd.page 1 with sitd.current offset as the memory address pointer. the field sitd.tp is used to annotate each start-split transaction with the indication of which part of the split-transaction data the current payload represents (all, begin, mid, end). in all cases the host controller simply uses the value in sitd.tp to mark the start-split with the correct transaction position code. t-count is always initialized to the number of start-splits for the current frame. tp is always initialized to the first required transaction position identifier. the scheduling boundary case (see figure 30-71 ) is used to determine the initial value of tp . the initial cases are summarized in table 30-71 . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-169 table 30-71. initial conditions for out sitd's tp and t-count fields after each start-split transaction is complete, the host controller updates t-count and tp appropriately so that the next start-split is correctly annotated. table 30-72 illustrates all of the tp and t-count transitions, which must be accomplished by the host controller. table 30-72. transaction position (tp)/tra nsaction count (t-count) transition table the start-split transactions do not receive a handshake from the transaction translator, so the host controller always advances the transfer state in the sitd after th e bus transaction is complete. to advance the transfer state the following operations take place: ? the sitd.total bytes to transfer and the sitd.current offset fields are adjusted to reflect the number of bytes transferred. ? the sitd.p (page selector) bit is updated appropriately. ? the sitd.tp and sitd.t-count fields are updated appr opriately as defined in table 30-72 . these fields are then written back to the memory based sitd. the s-mask is fixed for the life of the current budget. as mentioned above, tp and t-count are set specifically in each sitd to reflect the data to be sent from this sitd. therefore, regardless of the value of s-mask , the actual number of start-split transactions depends on t-count (or equivalently, total bytes to transfer ). the host controller must set the active bit to a zero when it detects that all of the schedule data has been sent to the bus. the preferred method is to detect when t-count decrements to zero as a result of a start-split bus transaction. equivalently, the host case t-count tp description 1, 2a =1 all when the out data payload is less than (or equal to) 188 bytes, only one start-split is required to move the data. the one start-split must be marked with an all. 1, 2a !=1 begin when the out data payload is greater than 188 bytes more than one start-split must be used to move the data. the initial start-split must be marked with a begin. tp t- c o u n t next tp next description all 0 n/a transition from all, to done. begin 1 end transition from begin to end. occurs when t-count starts at 2. begin !=1 mid transition from begin to mid. occurs when t-count starts at greater than 2. mid !=1 mid tp stays at mid while t-count is not equal to 1 (e.g. greater than 1). this case can occur for any of the scheduling boundary cases where the t-count starts greater than 3. mid 1 end transition from mid to end. this case can occur for any of the scheduling boundary cases where the t-count starts greater than 2. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-170 freescale semiconductor controller can detect when total bytes to transfer decrements to zero. either implementation must ensure that if the initial condition is total bytes to transfer equal to zero and t-count is equal to a one, then the host controller will issue a single start-split, with a zero-length data payload. software must ensure that tp , t-count and total bytes to transfer are set to deliver the appropriate number of bus transactions from each sitd. an inconsistent combination will yield undefined behavior. if the host experiences hold-offs that cause the host controller to skip start-split transactions for an out transfer, the state of the transfer will not progress appropriately. the transaction translator will observe protocol violations in the arrival of the start-spl its for the out endpoint (i.e. the transaction position annotation will be incorrect as re ceived by the transaction translator). example scenarios are described in section split transaction for isochronous - processing examples . a host controller implementation can optionally track the progress of an out split transaction by setting appropriate bits in the sitd.c-prog-mask as it executes each scheduled start-split. the checkpreviousbit () algorithm defined in section periodic isochronous - do comp lete split can be used prior to executing each start-split to determine whether start-splits were sk ipped. the host controller can use this mechanism to detect missed micro-frames. it can then set the sitd?s active bit to zero and stop execution of this sitd. this saves on both memory and high-speed bus bandwidth. periodic isochronous - do complete split this state is only used by a split-transaction isochr onous in endpoint. this state is entered unconditionally from the do start state after a start-split transaction is executed for an in endpoint. each time the host controller visits an sitd in this state, it conducts a number of tests to deter mine whether it should execute a complete-split transaction. the individual tests are listed below. the sequence they are applied depends on which micro-frame the host controller is currently executing which means that the tests might not be applied until after the sitd referenced from the back pointer has been fetched. ? te st a . cmicroframebit is bit-wise anded with sitd.c-mask field. a non-zero result indicates that software scheduled a complete-split for this endpoint , during this micro-frame. this test is always applied to a newly fetched sitd that is in this state. ? te st b . the sitd.c-prog-mask bit vector is checked to determine whether the previous complete splits have been executed. an example algorithm is below (this is slightly different than the algorithm used in section periodic interrupt - do complete split ). the sequence in which this test is applied depends on the current value of frinde x[2:0]. if frindex[2:0] is 0 or 1, it is not applied until the back pointer has been used. otherwise it is applied immediately. algorithm boolean checkpreviousbit( sitd.c-prog-mask, sitd.c-mask, cmicroframebi t) begin boolean rvalue = true; previousbit = cmicroframebit rotate-right(1) -- bit-wise anding previousbit with c-mask indicates whether there was an intent -- to send a complete split in the previous micro-frame. so, if the -- 'previous bit' is set in c-mask, check c-prog-mask to make sure it -- happened. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-171 if previousbit bitand sitd.c-mask then if not (previousbit bitand sitd.c-prog-mask) then rvalue = false end if end if return rvalue end algorithm if test a is true and frindex[2:0] is zero or one, then this is a case 2a or 2b scheduling boundary (see figure 30-70 ). see section periodic isochronous - do comp lete split for details in handling this condition. if test a and test b evaluate to true, then the host co ntroller will execute a complete-split transaction using the transfer state of the current sitd. when the hos t controller commits to executing the complete-split transaction, it updates qh.c-prog-mask by bit-oring with cmicroframebit . the transfer state is advanced based on the completion status of the complete-s plit transaction. to advance the transfer state of an in sitd, the host controller must: ? decrement the number of bytes received from sitd . total bytes to transfer, ? adjust sitd.current offset by the number of bytes received, ? adjust sitd.p (page selector) field if the transfer caused the host controller to use the next page pointer, and ? set any appropriate bits in the sitd . status field, depending on the results of the transaction. note that if the host contro ller encounters a condition where sitd.total bytes to transfer is zero, and it receives more data, the host controller must not write the additional data to memory. the sitd.status.active bit must be set to zero and the sitd.status . babble detected bit must be set to a one. the fields sitd.total bytes to transfer , sitd.current offset , and sitd.p (page selector) are not required to be updated as a result of this transaction attempt. the host controller must accept (assuming good data pa cket crc and sufficient room in the buffer as indicated by the value of sitd.total bytes to transfer ) mdata and data0/1 data payloads up to and including 192 bytes. a host controller implementation may optionally set sitd . status active to a zero and sitd.status.babble detected to a one when it receives and mdata or data0/1 with a data payload of more than 192 bytes. the following responses have the noted effects: ? err. the full-speed transaction completed with a time-out or bad crc and this is a reflection of that error to the host. the host controller sets the err bit in the sitd.status field and sets the active bit to a zero. ? transaction error (xacterr). the complete-split transaction encounters a timeout, crc16 failure, etc. the sitd.status field xacterr field is set to a one and the complete-split transaction must be retried immediately. the host controller must use an internal error counter to count the number of retries as a counter field is not provided in the sitd data structure. the host controller will not retry high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-172 freescale semiconductor more than two times. if the host controller exhausts the retries or the end of the micro-frame occurs, the active bit is set to zero. ? datax (0 or 1). this response signals that the final data for the split transaction has arrived. the transfer state of the sitd is advanced and the active bit is set to a zero. if the bytes to transfer field has not decremented to zero (including th e reception of the data payload in the datax response), then less data than was expected, or allowed for was actually received. this short packet event does not set the usbint status bit in the usbsts register to a one. the host controller will not detect this condition. ? nyet (and last). on each nyet response, the hos t controller also checks to determine whether this is the last complete-split for this split tr ansaction. last was defined in section periodic interrupt - do complete split . if it is the last complete-split (with a nyet response), then the transfer state of the sitd is not advanced (never received any data) and the active bit is set to a zero. no bits are set in the status field because this is essen tially a skipped transaction. the transaction translator must have responded to all the scheduled clompete-splits with nyets, meaning that the start-split issued by the host co ntroller was not received. this result should be interpreted by system software as if the transact ion was completely skipped. the test for whether this is the last complete split can be perfo rmed by xoring c-mask with c-prog-mask. a zero result indicates that all complete-splits have been executed. ? mdata (and last). see above description for testing for last . this can only occur when there is an error condition. either there has been a babbl e condition on the full-speed link, which delayed the completion of the full-speed transaction, or software set up the s-mask and/or c-mask s incorrectly. the host controller must set xacterr bit to a one and the active bit is set to a zero. ? nyet (and not last). see above description for testing for last . the complete-split transaction received a nyet response from the transaction tran slator. do not update any transfer state (except for c-prog-mask ) and stay in this state. ? mdata (and not last). the transaction translator responds with an mdata when it has partial data for the split transaction. for example, the full-speed transaction da ta payload spans from micro-frame x to x+1 and during micro-frame x, th e transaction translator will respond with an mdata and the data accumulated up to the end of micro-frame x. the host controller advances the transfer state to reflec t the number of bytes received. if test a succeeds, but test b fails, it means that one or more of the complete-splits have been skipped. the host controller sets the missed micro-frame status bit and sets the active bit to a zero. complete-split for schedul ing boundary cases 2a, 2b boundary cases 2a and 2b (ins only) (see figure 30-70 ) require that the host controller use the transaction state context of the previous sitd to finish the split transaction. table 30-73 enumerates the transaction state fields. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-173 table 30-73. summary sitd split transaction state if software has budgeted the schedule of this data stream with a frame wrap case, then it must initialize the sitd.back pointer field to reference a valid sitd and will have the sitd.back pointer.t-bit in the sitd.back pointer field set to a zero. otherwise, software must set the sitd.back pointer.t-bit in the sitd.back pointer field to a one. the host controller's rules for interpreting when to use the sitd.back pointer field are listed below. these rules apply only when the sitd's active bit is a one and the splitxstate is do complete split . ? when cmicroframebit is a 1h and the sitdx.back pointer.t-bit is a zero, or ? if cmicroframebit is a 2h and sitdx.s-mask[0] is a zero when either of these conditions apply, then the hos t controller must use the transaction state from sitd x-1 . in order to access sitd x-1 , the host controller reads on-chip the sitd referenced from sitd x .back pointer . the host controller must save the entire state from sitd x while processing sitd x-1 . this is to accommodate for case 2b processing. the host contro ller must not recursively walk the list of sitd.back pointers . if sitd x-1 is active ( active bit is a one and splitxstat is do complete split ), then both test a and test b are applied as described above. if these criteria to execute a complete-split are met, the host controller executes the complete split and evaluates the results as described above. the transaction state (see table 30-73 ) of sitd x-1 is appropriately advanced based on the re sults and written back to memory. if the resultant state of sitd x-1 's active bit is a one, then the host controller returns to the context of sitd x , and follows its next pointer to the next schedule item. no updates to sitd x are necessary. if sitd x-1 is active ( active bit is a one and splitxstat is do start split ), then the host controller must set active bit to a zero and missed micro-frame status bit to a one and the resultant status written back to memory. if sitd x-1 's active bit is a zero, (because it was zero when the host controller first visited sitd x-1 via sitd x 's back pointer, it transitioned to zero as a result of a detected error, or the results of sitd x-1 's complete-split transaction transitioned it to zero), then the host controller returns to the context of sitd x and transitions its splitxstate to do start split . the host controller then determines whether the case 2b start split boundary condition exists (i.e. if cmicroframebit is a 1b and sitd x .s-mask [0] is a 1b). if this criterion is met the host controller immediately executes a start-split transaction and appropriately buffer state status execution progress to t a l b y t e s to tr a n s fe r p (page select) current offset tp (transaction position) t-count (transaction count) all bits in the status field c-prog-mask note: tp and t-count are used only for host to device (out) endpoints. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-174 freescale semiconductor advances the transaction state of sitd x , then follows sitd x .next pointer to the next schedule item. if the criterion is not met, the host controller simply follows sitd x .next pointer to the next schedule item. note that in the case of a 2b boundary case, the split-transaction of sitd x-1 will have its active bit set to zero when the host controller returns to the context of sitd x . also, note that software should not initialize an sitd with c-mask bits 0 and 1 set to a one and an s-mask with bit zero set to a one. this scheduling combination is not supported and the behavi or of the host controller is undefined. split transaction for isochr onous - proces sing examples there is an important difference between how the hardware/software manages the isochronous split transaction state machine and how it manages the asynchronous and interrupt split transaction state machines. the asynchronous and interrupt split transacti on state machines are encapsulated within a single queue head. the progress of the data stream depends on the progress of each split transaction. in some respects, the split-transaction state machine is sequenced via the execute transaction queue head traversal state machine (see figure 30-63 ). isochronous is a pure time-oriented transaction/data stream. the interface data structures are optimized to efficiently describe transactions that need to occur at specific times. the isochronous split-transaction state machine must be managed across these time-oriented da ta structures. this means that system software must correctly describe the scheduling of split-tr ansactions across more than one data structure. then the host controller must make the appropriate state transitions at the appropriate times, in the correct data structures. for example, table 30-74 illustrates a couple of frames worth of scheduling required to schedule a case 2a full-speed isochronous data stream. table 30-74. example case 2a - software scheduling sitds for an in endpoint this example shows the first three sitds for the tran saction stream. since this is the case-2a frame-wrap case, s - mask s of all sitds for this endpoint have a valu e of 10h (a one bit in micro-frame 4) and c - mask value of c3h (one-bits in micro-frames 0,1, 6 a nd 7). additionally, sofware ensures that the back pointer field of each sitd references the a ppropriate sitd data structure (and the back pointer t-bits are set to zero). sitd x micro-frames initial splitxstate #masks0 1 23456 7 x s-mask 1 do start split c-mask 1 1 1 1 x+1 s-mask 1 do complete split c-mask 1 1 1 1 x+2 s-mask 1 do complete split c-mask 1 1 1 1 x+3 s-mask repeats previous pattern do complete split c-mask high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-175 the initial splitxstate of the first sitd is do start split . the host controller will visit the first sitd eight times during frame x. the c-mask bits in micro -frames 0 and 1 are ignored because the state is do start split . during micro-frame 4, the host controller determines that it can run a start-split (and does) and changes splitxstate to do complete split . during micro-frames 6 and 7, the host controller executes complete-splits. notice the sitd for frame x+1 has it's splitxstate initialized to do complete split . as the host controller continues to traverse the schedule during h-frame x+1, it will visit the second sitd eight times. during micro-frames 0 and 1 it will de tect that it must execute complete-splits. during h-frame x+1, micro-frame 0, the host controller detects that sitd x+1 's back pointer . t-bit is a zero, saves the state of sitd x+1 and fetches sitd x . it executes the complete split transaction using the transaction state of sitd x . if the sitd x split transaction is complete, sitd's active bit is set to zero and results written back to sitd x . the host controller retains the fact that sitd x is retired and transitions the splitxstate in the sitd x+1 to do start split. at this point, the host controller is prepared to execute the start-split for sitd x+1 when it reaches micro-frame 4. if the split-transaction completes early (transaction-complete is defined in section periodic is ochronous - do complete split ), i.e. before all the scheduled complete-splits have been exec uted, the host controller will transition sitd x . splitxstate to do start split early and naturally skip the remaining scheduled complete-split transactions. for this example, sitd x+1 does not receive a data0 response until h-frame x+2, micro-frame 1. during h-frame x+2, micro-frame 0, the host controller detects that sitd x+2 's back pointer.t-bit is a zero, saves the state of sitd x+2 and fetches sitd x+1 . as described above, it executes another split transaction, receives an mdata response, updates the transfer state, but does not modify the active bit. the host controller returns to the context of sitd x+2 , and traverses it's next pointer without any state change updates to sitd x+2 . s during h-frame x+2 , micro-frame 1, the host controller detects sitd x+2 's s-mask[0] is a zero, saves the state of sitd x+2 and fetches sitd x+1 . it executes another complete-split transaction, receives a data0 response, updates the transfer state and sets the active bit to a zero. it returns to the state of sitd x+2 and changes its splitxstate to do start split . at this point, the host controller is prepared to execute start-splits for sitd x+2 when it reaches micro-frame 4. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-177 30.8.3.15 interrupts the ehci host controller hardware provides interrupt capability based on a number of sources. there are several general groups of interrupt sources: ? interrupts as a result of executing transactions from the schedule (success and error conditions), ? host controller events (port change events, etc.), and ? host controller error events all transaction-based sources are maskable through the host controller?s interrupt enable register (usbintr, see section usbintr). additionally, indi vidual transfer descriptors can be marked to generate an interrupt on completion. this section describes each interrupt source and the processing that occurs in response to the interrupt. during normal operation, interrupts may be immediate or deferred until the next interrupt threshold occurs. the interrupt threshold is a tunable parameter via the interrupt threshold control field in the usbcmd register. the value of this register controls when the host controller will generate an interrupt on behalf of normal transaction execution. when a transaction co mpletes during an interrupt interval period, the interrupt signaling the completion of the transfer will not occur until the interrupt threshold occurs. for example, the default value is eight micro-frames. this means that the host controller will not generate interrupts any more frequently than once every eight micro-frames. section host system error details effects of a host system error. if an interrupt has been scheduled to be generated for the current interr upt threshold interval, the interrupt is not signaled until after the status for the last complete transaction in the interval has been written back to host memory. this may sometimes result in the interrupt not being signaled until the next interrupt threshold. initial interrupt processing is the same, regardless of the reason for the interrupt. when an interrupt is signaled by the hardware, cpu control is transferred to host controller's usb interrupt handler. the precise mechanism to accomplish the transfer is os specific. for this discussion it is just assumed that control is received. when the interrupt handler receives control, its first action is to reads the usbsts (usb status register). it then acknowledges the interrupt by clearing all of the interrupt status bits by writing ones to these bit positions. the handler then determines whet her the interrupt is due to schedule processing or some other event. after acknowledging the interrupt , the handler (via an os-specific mechanism), schedules a deferred procedure call (dpc) which will ex ecute later. the dpc routine processes the results of the schedule execution. the precise mechanisms used are beyond the scope of this document. note: the host controller is not required to de-assert a currently active interrupt condition when software sets the interrupt enables (in the usbinr register , see section usbintr) to a zero. the only reliable method software should use for acknowledging an interrupt is by transitioning the appropriate status bits in the usbsts register (section usbsts) from a one to a zero. 30.8.3.15.1 transfer/transaction based interrupts these interrupt sources are associated with transfer and transaction progress. they are all dependent on the next interrupt threshold. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-178 freescale semiconductor transaction error a transaction error is any error that caused the host controller to think that the transfer did not complete successfully. table 30-75 lists the events/responses that the host can observe as a result of a transaction. the effects of the error counter and interrupt status are summarized in the following paragraphs. most of these errors set the xacterr status bit in the appropriate interface data structure. there is a small set of protocol errors that rela te only when executing a queue head and fit under the umbrella of a wrong pid error that are significant to explicitly identify. when these errors occur, the xacterr status bit in the queue head is set and the cerr field is decremented. when the pidcode indicates a setup, the following responses are protocol errors and result in xacterr bit being set to a one and the cerr field being decremented. ? eps field indicates a high-speed device an d it returns a nak handshake to a setup. ? eps field indicates a high-speed device and it returns a nyet handshake to a setup. ? eps field indicates a low- or full-speed device and the complete-split receives a nak handshake. table 30-75. summary of transaction errors 1 if occurs in a queue head, then usberrint is asserted only when cerr counts down from a one to a zero. in addition the queue is halted, see section section , ?halting a queue head .? 2 the host controller received a response from the device, but it could not recognize the pid as a valid pid. serial bus babble when a device transmits more data on the usb than th e host controller is expecting for this transaction, it is defined to be babbling. in general, this is called a packet babble . when a device sends more data than the maximum length number of bytes, the host controller sets the babble detected bit to a one and halts the endpoint if it is using a queue head (see section section , ?halting a queue head ?). maximum length is defined as the minimum of total bytes to transfer and maximum packet size . the cerr field is not decremented for a packet babble condition (only applie s to queue heads). a babble condition also exists if in transaction is in progress at high-speed eof2 point. this is called a frame babble. a frame babble condition is recorded into the appropriate schedule da ta structure. in addition, the host controller must disable the port to which the frame babble is detected. the usberrint bit in the usbsts register is set to a one and if the usb error interrupt enable bit in the usbintr register is a one, then a hardware interr upt is signaled to the system at the next interrupt event / result queue head/qtd/itd/sitd side-effects usb status register (usbsts) cerr status field usberrint crc -1 xacterr set to a one. 1 1 timeout -1 xacterr set to a one. 1 1 bad pid 2 -1 xacterr set to a one. 1 1 babble n/a section serial bus babble 1 buffer error n/a section data buffer error high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-179 threshold. the host controller must never start an out transaction that will babble across a micro-frame eof. note when a host controller detects a data pid mismatch, it must either: disable the packet babble checking for the dur ation of the bus transaction or do packet babble checking based solely on maximum packet size . the usb core specification defines the requi rements on a data receiver when it receives a data pid mismatch (e.g. expects a data0 and gets a data1 or visa-versa). in summary, it must ignore the received data and respond with an ack handshake, in order to advance the transmitter's data sequence. the ehci interface allows system softwa re to provide buffers for a control, bulk or interrupt in endpoint that are not an even multiple of the maximum packet size specified by the device. whenever a device misses an ack for an in endpoint, the host and device are out of synchronization with respect to the progress of the data transfer. the host controller may have advanced the transfer to a buffer that is less than maximum packet size. the device will re-send its maximum packet size data packet, with the original data pid, in response to the next in toke n. in order to properly manage the bus protocol, the host controller must disa ble the packet babble check when it observes the data pid mismatch. data buffer error this event indicates that an overrun of incoming data or a underrun of outgoing data has occurred for this transaction. this would generally be caused by the hos t controller not being able to access required data buffers in memory within necessary latency requirem ents. these conditions are not considered transaction errors, and do not effect the error count in the queue head. when these errors do occur, the host controller records the fact the error occurred by setting the data buffer error bit in the queue head, itd or sitd. if the data buffer error occurs on a non-isochronous in, the host controller will not issue a handshake to the endpoint. this will force the endpoint to resend the sa me data (and data toggle) in response to the next in to the endpoint. if the data buffer error occurs on an out, the host contro ller must corrupt the end of the packet so that it cannot be interpreted by the device as a good data pack et. simply truncating the packet is not considered acceptable. an acceptable implementation option is to 1's complement the crc bytes and send them. there are other options suggested in the transaction translator section of the usb specification revision 2.0. usb interrupt (interrupt on completion (ioc)) transfer descriptors (itds, sitds, and queue heads (qtds)) contain a bit that can be set to cause an interrupt on their completion. the completion of the transfer associated with that schedule item causes the usb interrupt (usbint) bit in the usbsts register to be set to a one. in addition, if a short packet is encountered on an in transaction associated with a queue head, then this event also causes usbint to be set to a one. if the usb interrupt enable bit in the usbintr register is set to a one, a hardware interrupt high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-180 freescale semiconductor is signaled to the system at the next interrupt th reshold. if the completion is because of errors, the usberrint bit in the usbsts register is also set to a one. short packet reception of a data packet that is less than the endpoi nt?s max packet size during control, bulk or interrupt transfers signals the completion of the transfer. when ever a short packet completion occurs during a queue head execution, the usbint bit in the usbsts register is set to a one. if the usb interrupt enable bit is set in the usbintr register, a hardware interrupt is si gnaled to the system at the next interrupt threshold. 30.8.3.15.2 host controller event interrupts these interrupt sources are independent of the inte rrupt threshold (with the one exception being the interrupt on async advance, see sect ion interrupt on async advance ). port change events port registers contain status and stat us change bits. when the status change bits are set to a one, the host controller sets the port change detect bit in the usbsts register to a one. if the port change interrupt enable bit in the usbintr register is a one, then the host controller will issue a hardware interrupt. the port status change bits include: ? connect status change ? port enable/disable change ? over-current change ? force port resume frame list rollover this event indicates that the host controller has wrap ped the frame list. the current programmed size of the frame list effects how often this interrupt occurs . if the frame list size is 1024, then the interrupt will occur every 1024 milliseconds, if it is 512, then it will occur every 512 milliseconds, etc. when a frame list rollover is detected, the host controller sets the frame list rollover bit in the usbsts register to a one. if the frame list rollover enable bit in the usbintr register is set to a one, the host controller issues a hardware interrupt. this interrupt is not delayed to the next interrupt threshold. interrupt on async advance this event is used for deterministic removal of queue heads from the asynchronous schedule. whenever the host controller advances the on-chip context of th e asynchronous schedule, it evaluates the value of the interrupt on async advance doorbell bit in the usbcmd register. if it is a one, it sets the interrupt on async advance bit in the usbsts register to a one. if the interrupt on async advance enable bit in the usbintr register is a one, the host controller issues a hardware interrupt at th e next interrupt threshold. a detailed explanation of this feature is describe d in section removing queue heads from asynchronous schedule . high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-181 host system error the host controller is a bus master and any interac tion between the host controller and the system may experience errors. the type of host error may be catastrophic to the host controller (such as a master abort) making it impossible for the host controller to conti nue in a coherent fashion. in the presence of non-catastrophic host errors, such as parity errors, the host controller could potentially continue operation. the recommended behavior for these types of errors is to escalate it to a catastrophic error and halt the host controller. host-based error must result in the following actions: ? the run/stop bit in the usbcmd register is set to a zero. ? the following bits in the usbsts register are set: ? host system error bit is to a one. ? hchalted bit is set to a one. ? if the host system error enable bit in the usbintr register is a one, then the host controller will issue a hardware interrupt. this interrupt is not delayed to the next interrupt threshold. table 30-76 summarizes the required actions taken on the various host errors. table 30-76. summary behavior of ehci host controller on host system errors [o] potentially, a host controller im plementation could continue operati on without a halt. however, the recommended behavior is to halt the host controller. cycle type master abort target abort data phase parity frame list pointer fetch (read) fatal fatal fatal [o] sitd fetch (read) fatal fatal fatal [o] sitd status write-back (write) fatal [o] fatal [o] fatal [o] itd fetch (read) fatal fatal fatal [o] itd status write-back (write) fatal [o] fatal [o] fatal [o] qtd fetch (read) fatal fatal fatal [o] qhd status write-back (write) fatal [o] fatal [o] fatal [o] data write fatal [o] fatal [o] fatal [o] data read fatal fatal fatal [o] note after a host system error , software must reset the host controller via hcreset in the usbcmd register before re-initializing and restarting the host controller. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-182 freescale semiconductor 30.8.4 ehci deviation for the purposes a dual-role host/device controller with support for on-the-go applications, it is necessary to deviate from the ehci specification e nhanced host controller interface specification for universal serial bus, revision 0.95, november 2000, in tel corporation. http://www.intel.com. device operation & on-the-go operation is not specified in the ehci and thus the implementation supported in this core is proprietary. the host mode operation of the core is near ehci compatible with few minor differences documented in this section. the particulars of the deviations occur in the areas summarized here: ? embedded transaction translator?allows direct a ttachment of fs and ls devices in host mode without the need for a companion controller. ? device operation - in host mode the device operati onal registers are generally disabled and thus device mode is mostly transparent when in hos t mode. however, there are a couple exceptions documented in the following sections. ? embedded design interface - this core does not a pci interface and therefore the pci configuration registers described in the ehci specification are not applicable. ? on-the-go operation - this design includes an on-the-go controller for port #1. 30.8.4.1 embedded transaction translator function the arc usb-hs otg high-speed usb on-the-go otg controller supports directly connected full and low speed devices without requiring a companion controller by including the capabilities of a usb 2.0 high speed hub transaction trasnslator. although there is no separate tranaction translator block in the system, the transaction translator function norma lly associated with a high speed hub has been implemented within the dma and protocol engine bloc ks. the embedded transaction translator fuction is an extension to ehci interface, but makes use of the standard data structures and operational models that exist in the ehci specification to support full and low speed devices. 30.8.4.1.1 capability registers the following additions have been added to the ca pability registers to suppor t the embedded transaction translator function: ? n_tt added to hcsparams?host control structural parameters ? n_ptt added tohcsparams?host control structural parameters 30.8.4.1.2 operational registers the following additions have been added to the operational registers to support the embedded tt: ? is a new register. ? addition of two-bit port speed (pspd) to the portscx register. 30.8.4.1.3 discovery in a standard ehci controller design, the ehci host controller driver detects a full speed (fs) or low speed (ls) device by noting if the port enable bit is se t after the port reset operation. the port enable will high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-183 only be set in a standard ehci c ontroller implementation after the port reset operation and when the host and device negotiate a high-speed connec tion (i.e. chirp completes successfully). since this controller has an embedded transaction translator, the port enable will always be set after the port reset operation regardless of the result of the host device chirp result and the resulting port speed will be indicated by the pspd field in portscx. therefore, the standard ehci host controller driver re quires an alteration to handle directly connected full and low speed devices or hubs. the change is a fundamental one in that is summarized in table 30-77 . 30.8.4.1.4 data structures the same data structures used for fs/ls transac tions though a hs hub are also used for transactions through the root hub with sm embedded transaction tr anslator. here it is demonstrated how the hub address and endpoint speed fields should be set for directly attached fs/ls devices and hubs: 1. qh (for direct attach fs/ls)?async. (b ulk/control endpoints) periodic (interrupt) ? hub address = 0 ? transactions to direct attached device/hub. ? qh.eps = port speed ? transactions to a device downstream from direct attached fs hub. ? qh.eps = downstream device speed table 30-77. summary of ehci standard ehci ehci with embedded transaction translator after port enable bit is set following a connection and reset sequence, the device/hub is assumed to be hs. after port enable bit is set following a connection and reset sequence, the device/hub speed is noted from portscx. fs and ls devices are assumed to be downstream from a hs hub thus, all port-level control is performed through the hub class to the nearest hub. fs and ls device can be either downstream from a hs hub or directly attached. when the fs/ls device is downstream from a hs hub, then port-level control is done using the hub class through the nearest hub. when a fs/ls device is directly attached, then port-level control is accomplished using portscx. fs and ls devices are assumed to be downstream from a hs hub with hubaddr=x. [where hubaddr > 0 and hubaddr is the address of the hub where the bus transitions from hs to fs/ls (ie. split target hub)] fs and ls device can be either downstream from a hs hub with hubaddr = x [hubaddr > 0] or directly attached [where hubaddr = 0 and hubaddr is the address of the root hub where the bus transitions from hs to fs/ls (ie. split target hub is the root hub) ] note: when qh.eps = 01 (ls) and portscx.pspd = 00 (fs), a ls-pre-pid will be sent before the transmitting ls traffic. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-184 freescale semiconductor ? maximum packet size must be less than or equal 64 or undefined behaviour may result. 2. sitd (for direct attach fs)?periodic (iso endpoint) ? all fs iso transactions: ? hub address = 0 ? sitd.eps = 00 (full speed) ? maximum packet size must less than or equal to 1023 or undefined behaviour may result. 30.8.4.1.5 operational model the operational models are well defi ned for the behavior of the transaction translator (see usb 2.0 specification universal serial bus specificati on, revision 2.0, april 2000, compaq, hewlett-packard, intel, lucent, microsoft, nec, philips. http://www .usb.org) and for the ehci controller moving packets between system memory and a usb-hs hub. since the em bedded transaction translator exists within the host controller there is no physical bus between ehci host controller driver and the usb fs/ls bus. these sections will briefly discuss the operational mode l for how the ehci and transaction translator operational models are combined without the physical bus between. the following sections assume the reader is familiar with both the ehci and us b 2.0 transaction translator operational models. micro- frame pipeline the ehci operational model uses the concept of h-fra mes and b-frames to describe the pipeline between the host (h) and the bus (b). the embedded transacti on translator shall use the same pipeline algorithms specified in the usb 2.0 specification for a hub-based transaction translator. all periodic transfers always begin at b-frame 0 (after sof) and continue until the stored periodic transfers are complete. as an example of the micro-frame pipeline implemented in the embedded transaction translator, all periodic transfers that are tagged in eh ci to execute in h-frame 0 will be ready to execute on the bus in b-frame 0. it is important to note that when programming the s- mask and c-masks in the ehci data structures to schedule periodic transfers for the embedded transaction translator, the ehci host controller driver must follow the same rules specified in ehci for pr ogramming the s-mask and c-mask for downstream hub-based transaction translators. once periodic transfers are exhausted, any stored asynchronous transfer wi ll be moved. asynchronous transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to h-frame and b-frame boundaries with the exception that an asynchronous transfer can not babble through the sof (start of b-frame 0.) split state machines the start and complete split operational model differs from ehci slightly because there is no bus medium between the ehci controller and th e embedded transaction translator. where a start or complete-split operation would occur by requesting the split to the hs hub, the start/complete split operation is simple an high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-185 internal operation to the embedded transaction translator. table 30-78 summarizes the conditions where handshakes are emulated from internal state instea d of actual handshakes to hs split bus traffic. note: the un-shaded cells represent start-splits and the shaded cells represent complete-splits. asynchronous transaction sche duling and buffer management the following usb 2.0 specification items are implem ented in the embedded transaction translator: usb 2.0?11.17.3 ? sequencing is provided & a packet length estimator ensures no full-speed/low-speed packet babbles into sof time. usb 2.0?11.17.4 ? transaction tracking for 2 data pipes. usb 2.0?11.17.5 ? clear_tt_buffer capability provided though the use of the register. periodic transaction schedu ling and buffer management the following usb 2.0 specification items are implem ented in the embedded transaction translator: usb 2.0?11.18.6.[1-2] ? abort of pending start-splits ? eof (and not started in micro-frames 6) ? idle for more than 4 micro-frames table 30-78. summary of the conditons of handshakes condition emulate tt response start-split : all asynchronous buffers full. nak start-split : all periodic buffers full. err start-split : success for start of async. transaction. ack start-split : start periodic transaction. no handshake (ok) complete-split : failed to find transaction in queue. bus time out complete-split : transaction in queue is busy. nyet complete-split : transaction in queue is complete. [actual handshake from ls/fs device] high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-186 freescale semiconductor ? abort of pending complete-splits ?eof ? idle for more than 4 micro-frames usb 2.0?11.18.[7-8] ? transaction tracking for up to 16 data pipes. ? some applications may not require transaction trac king up to a maximum of 16 periodic data pipes. the option to limit the tracking to only 4 periodic data pipes exists in the by changing the configuration constant vusb_hs_tt_periodic_con texts to 4. the result is a significant gate count savings to the core given the limitations implied. ? complete-split transaction searching. multiple transaction translators the maximum number of embedded transaction translators that is currently supported is one as indicated by the n_tt field in the hcsparams?host c ontrol structural parameters register. 30.8.4.2 device operation the co-existence of a device operational controller within the host controller has little effect on ehci compatibility for host operation except as noted in this section. 30.8.4.3 usbmode register given that the dual-role controller is initialized in neither host nor device mode, the usbmode register must be programmed for host operation before the ehci host controller driv er can begin ehci host operations. caution note: limiting the number of tracking pipes in the embedded ?tt to four (4) will impose the restriction that no more than 4 periodic transactions (interrupt/isochronous) can be scheduled through the embedded-tt per frame. the number 16 was chosen in the usb specification because it is sufficient to ensure that the high-speed to full-speed periodic pipeline can remain full. keeping the pipeline full puts no constraint on the number of periodic transactions that can be scheduled in a frame and the only limit becomes the flight time of the packets on the bus. note: there is no data schedule mechanism for these transactions other than the micro-frame pipeline. the embedded tt assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-187 30.8.4.3.1 non-zero fiel ds the register file. some of the reserved fields and reserved addresses in the capability registers and operational register have use in device mode, the following must be adhered to: ? write operations to all ehci reserved fields (s ome of which are device fields) with the operation registers should always be written to zero. this is an ehci requirement of the device controller driver that must be adhered to. ? read operations by the host controller must prope rly mask ehci reserved fields (some of which are device fields) because fields that are used exclusive for device are undefined in host mode . 30.8.4.3.2 sof interrupt this sof interrupt used for device mode is shared as a free running 125us interrupt for host mode. ehci does not specify this interrupt but it has been added fo r convenience and as a poten tial software time base. see usbsts and usbintr registers. 30.8.4.4 embedded design interface this is an embedded usb host controller as de fined by the ehci specification and thus does not implement the pci configuration registers. 30.8.4.4.1 frame adjust register given that the optional pci configur ation registers are not included in this implementation, there is no corresponding bit level timing adjustments like is provi ded by the frame adjust register in the pci configuration registers. starts of micro-frames are timed precisely to 125 us using the transceiver clock as a reference clock. i.e. 60 mhz transcei ver clock for 8-bit physical interfaces & full-speed serial interfaces or 30 mhz transceiver clock for 16-bit physical interfaces. 30.8.4.5 miscellaneous variations from ehci 30.8.4.5.1 programmable physical interface behaviour this design supports multiple physical interfaces whic h can operate in differing modes when the core is configured with software programma ble physical interface modes. software programmability allows the selection of the physical interface part during the board design phase instead of during the chip design phase. the control bits for selecting the physical interface operating mode have been added to the portscx register providing a capability that is not defined by ehci. 30.8.4.5.2 discovery port reset the port connect methods specified by ehci require sett ing the port reset bit in the portscx register for a duration of 10ms. due to the complexity required to support the attachment of devices that are not high speed there are counter already present in the design that can count the 10ms reset pulse to alleviate the high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-188 freescale semiconductor requirement of the software to measure this duration. therefore, the basic connection is then summarized as the following: ? [port change interrupt] port connect change occurs to notify the host controller driver that a device has attached. ? software shall write a ?1? to the reset the device. ? software shall write a ?0? to the reset the device after 10 ms. ? this step, which is necessary in a standard ehci design, may be omitted with this implementation. should the ehci host controller driver attempt to write a ?0? to the reset bit while a reset is in progress the write will simple be ignored and the reset will continue until completion. ? [port change interrupt] port enable change occu rs to notify the host controller that the device in now operational and at this point th e port speed has been determined. port speed detection after the port change interrupt indicates that a port is enabled, the ehci stack should determine the port speed. unlike the ehci implementation which will re-assign the port owner for any device that does not connect at high-speed, this host controller supports di rect attach of non high-speed devices. therefore, the following differences are important regarding port speed detection: ? port owner is read-only and always reads 0. ? a 2-bit port speed indicator has been added to portsc to provide the current operating speed of the port to the host controller driver. ? a 1-bit high speed indicator has been added to po rtsc to signify that the port is in high-speed vs. full/low speed? this information is redundant with the 2-bit port speed indicator above. 30.8.4.5.3 port test mode port test control mode behaves fully as described in ehci since the release of revision 3.2.1. in earlier product revisions, the test packet mo de was not ehci compatible. an alternate host controller driver procedure is no longer necessary or supported. 30.8.5 device data structures this section defines the interface da ta structures used to communicate control, status, and data between device controller driver (dcd) software and the device controller. the data structure definitions in this chapter support a 32-bit memory buffer address space. the interface consists of device queue heads and transfer descriptors. the data structures defined in the chapter are (from the device controller?s perspective) a mix of read-only and read/ writeable fields. the device controller must preserve the read-only fiel ds on all data structure writes. note: software must ensure that no interface data structure reachable by the device controller spans a 4k-page boundary. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-189 the arc usb-hs otg high-speed usb on-the-go core includes dcd software called the usb 2.0 device api. the device ap i provides an easy to use application program interface for developing device (peripheral) applications using the arc usb-hs otg high-speed usb on-the-go core. the device api incorporates and abstracts for the application deve loper all of the elements of the program interface. figure 30-73. end point queue head organization device queue heads are arranged in an array in a continuous area of memory pointed to by the endpointlistaddr pointer. the even ?numbered device qu eue heads in the list support receive endpoints (out/setup) and the odd-numbered queue he ads in the list are used for transmit endpoints (in/interrupt). the device controller will inde x into this array based upon the endpoint number received from the usb bus. all information necessary to respond to transactions for all primed transfers is contained in this list so the device controller can readily respond to incoming requests without having to traverse a linked list. 30.8.5.1 endpoint queue head (dqh) the device endpoint queue head (dqh) is where all transfers are managed. the dqh is a 48-byte data structure, but must be aligned on 64-byte boundaries . during priming of an endpoint, the dtd (device transfer descriptor) is copied into the overlay area of the dqh, which starts at the nexttd pointer dword and continues through the end of the buffer pointers dwor ds. after a transfer is complete, the dtd status dword is updated in the dtd pointed to by the currenttd pointer. while a packet is in progress, the overlay area of the dqh is used as a staging area for the dtd so that the device controller can access needed information with little minimal latency. note the endpoint queue head list must be aligned to a 2k boundary. 31302928272625242322212019181716 15 14131211 109876543210 mult zl 0 maximum packet length io 0 current dtd pointer 0 up to 32 elements endpoint qh 0 ? in endpointlistaddr endpoint qh 1 ? out endpoint transfer descriptor endpoint queue heads transfer buffer pointer transfer buffer transfer buffer transfer buffer transfer buffer transfer buffer pointer transfer buffer pointer transfer buffer pointer endpoint qh 0 ? out high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-190 freescale semiconductor figure 30-74. endpoint queue head (dqh) 30.8.5.1.1 endpoint capab ilities/characteristics this dword specifies static inform ation about the endpoint, in other words, this information does not change over the lifetime of the endpoint. device cont roller software should not attempt to modify this information while the corresponding endpoint is enabled. next dtd pointer 0 t 0 total bytes io 0 multo 0 status buffer pointer (page 0) current offset buffer pointer (page 1) reserved buffer pointer (page 2) reserved buffer pointer (page 3) reserved buffer pointer (page 4) reserved reserved set-up buffer bytes 3?0 set-up buffer bytes 7?4 device controller read/write device controller read only. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-191 30.8.5.1.2 transfer overlay the seven dwords in the overlay area represent a tran saction working space for the device controller. the general operational model is that the device controlle r can detect whether the overlay area contains a description of an active transfer. if it does not contain an active transfer, then it will not read the associated endpoint. after an endpoint is readied, the dtd will be copied into this queue head overlay area by the device controller. until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor. when the transfer is complete, the device controller will write the results back to the original transfer descriptor and advance the queue. see dtd for a description of the overlay fields. 30.8.5.1.3 current dtd pointer the current dtd pointer is used by the device controller to locate the transfer in progress. this word is for device controller (hardware) use only and should not be modified by dcd software. table 30-79. endpoint capabilities/characteristics bit description 31:30 mult. this field is used to indicate the number of packets executed per transaction description as given by the following: 00?execute n transactions as demonstrated by the usb variable length packet protocol where n is computed using the maximum packet length (dqh) and the total bytes field (dtd) 01 execute 1 transaction. 10 execute 2 transactions. 11 execute 3 transactions. note: non-iso endpoints must set mult=?00?. note: iso endpoints must set mult = 01, 10, or 11, as needed. 29 zero length termination select. this bit is used to indicate when a zero length packet is used to terminate transfers where to total transfer length is a multiple . this bit is not relevant for isochronous 0?enable zero length packet to terminate transfers equal to a multiple of the maximum packet length. (default). 1?disable the zero length packet on transfers that are equal in length to a multiple maximum packet length. 28:27 reserved. these bit reserved for future use and should be set to zero. 26:16 maximum packet length. this directly corresponds to the maximum packet size of the associated endpoint (wmaxpacketsize). the maximum value this field may contain is 0x400 (1024). 15 interrupt on setup (ios). this bit is used on control type endpoints to indicate if usbint is set in response to a setup being received. 14:0 reserved. bits reserved for future use and should be set to zero. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-192 freescale semiconductor table 30-80. next dtd pointer 30.8.5.1.4 set-up buffer the set-up buffer is dedicated storage for the 8-byte data that follows a set-up pid. table 30-81. multiple m ode control (hccparams) 30.8.5.2 endpoint transfer descriptor (dtd) the dtd describes to the device controller the location and quantity of data to be sent/received for given transfer. the dcd should not attempt to modify any fiel d in an active dtd except the next like pointer, which should only be modified as described in sec tion managing transfers with transfer descriptors. bit description 31:5 current dtd. this field is a pointer to the dtd that is represented in the transfer overlay area. this field will be modified by the device controller to next dtd pointer during endpoint priming or queue advance. 4:0 reserved. bit reserved for future use and should be set to zero. note: each endpoint has a tx and an rx dqh associated with it, and only the rx queue head is used for receiving setup data packets. dword bits description 1 31:0 setup buffer 0. this buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller to be read by software. 2 31:0 setup buffer 1. this buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device controller to be read by software. 31 30 29 28 27 2625 24 2322 2120 19 18 17 16 15 14 13 12 11 10 9876543210 next link pointer 0 t 0 to t a l b y t e s i o 0multo 0 status buffer pointer (page 0) current offset buffer pointer (page 1) 0 frame number buffer pointer (page 2) reserved buffer pointer (page 3) reserved high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-193 figure 30-75. endpoint transfer descriptor (dtd) table 30-82. next dtd pointer table 30-83. dtd token buffer pointer (page 4) reserved device controller read/write device controller read only. bit description 31:5 next transfer element pointer. this field contains the physical memory address of the next dtd to be processed. the field corresponds to memory address signals [31:5], respectively. 4:1 reserved. bits reserved for future use and should be set to zero. 0 terminate (t). 1=pointer is invalid. 0=pointer is valid (points to a valid transfer element descriptor). this bit indicates to the device controller that there are no more valid entries in the queue. bit description 31 reserved. bit reserved for future use and should be set to zero. 30:16 total bytes. this field specifies the total number of bytes to be moved with this transfer descriptor. this field is decremented by the number of bytes actually moved during the transaction and only on the successful completion of the transaction. the maximum value software may store in the field is 5*4k(5000h). this is the maximum number of bytes 5 page pointers can access. although it is possible to create a transfer up to 20k this assumes the 1 st offset into the first page is 0. when the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16k**. therefore, the maximum recommended transfer is 16k(4000h). if the value of the field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the device controller executes a zero-length transaction and retires the transfer descriptor. it is not a requirement for in transfers that total bytes to transfer be an even multiple of maximum packet length . if software builds such a transfer descriptor for an in transfer, the last transaction will always be less that maximum packet length . 15 interrupt on complete (ioc). this bit is used to indicate if usbint is to be set in response to device controller being finished with this dtd. 14:12 reserved. bits reserved for future use and should be set to zero. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-194 freescale semiconductor table 30-84. dtd buffer page pointer list 30.8.6 device operational model the function of the device operation is to transfer a request in the memory image to and from the universal serial bus. using a set of linked list transfer descriptors , pointed to by a queue head , the device controller will perform the data transfers. the followi ng sections explain the use of the device controller from the device controller driver (dcd) point-of-view and further describe how specific usb bus events relate to status changes in the de vice controller programmer's interface. the arc usb-hs otg high-speed usb on-the-go is shipped with a dcd called the arc usb-hs otg high-speed usb on-the-go device api. th e arc usb-hs otg high-speed usb on-the-go 11:10 multiplier override (multo). this field can be used for transmit iso?s (ie. iso-in) to override the multiplier in the qh. this field must be zero for all packet types that are not transmit-iso. example: if qh.multiplier = 3; maximum packet size = 8; total bytes = 15; multio = 0 [default] three packets are sent: {data2(8); data1(7); data0(0)} if qh.multiplier = 3; maximum packet size = 8; total bytes = 15; multio = 2 two packets are sent: {data1(8); data0(7)} for maximal efficiency, software should compute multo = greatest integer of (total bytes / max. packet size) except for the case when total bytes = 0; then multo should be 1. note: non-iso and non-tx endpoints must set multo=?00?. 9:8 reserved. bits reserved for future use and should be set to zero. 7:0 status. this field is used by the device controller to communicate individual command execution states back to the device controller software. this field contains the status of the last transaction performed on this qtd. the bit encodings are: bit status field description 7active. 6 halted. 5 data buffer error. 3 transaction error. 4,2,0reserved. bit description 31:12 buffer pointer. selects the page offset in memory for the packet buffer. non virtual memory systems will typically set the buffer pointers to a series of incrementing integers. 0;11:0 current offset. offset into the 4kb buffer where the packet is to begin. 1;10:0 frame number. written by the device controller to indicate the frame number in which a packet finishes. this is typically be used to correlate relative completion times of packets on an iso endpoint. bit description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-195 device api provides an easy to use application interface for developing usb device (peripheral) applications. the arc usb-hs otg high-speed us b on-the-go device api incorporates and abstracts for the application developer all of the in formation contained in the device operational model. for more information on the arc usb-hs otg high- speed usb on-the-go device api, refer to the "software design document for th e precise usb 2.0 device api". 30.8.6.1 device controller initialization after hardware reset, the device is disabled until the r un/stop bit is set to a ?1?. in the disabled state, the pull-up on the usb d+ is not active which prevents an attach event from occurring. at a minimum, it is necessary to have the queue heads setup for endpoint ze ro before the device attach occurs. shortly after the device is enabled, a usb reset will occur follo wed by setup packet arriving at endpoint 0. a queue head must be prepared so that the device controller can store the incoming setup packet. in order to initialize a device, the software should perform the following steps: 1. set controller mode in the usbmode register to device mode. 2. allocate and initialize device queue heads in system memory. ? minimum: initialize device queue heads 0 tx & 0 rx. ? for information on device queue heads, refer to section device data structures. 3. configure endpointlistaddr pointer. ? for additional information on endpoin tlistaddr, refer to the register table. 4. enable the microprocessor interrupt associat ed with the arc usb-hs otg high-speed usb on-the-go core. ? recommended: enable all device interrupts including: usbint, usberrint, port change detect, usb reset re ceived, dcsuspend. ? for a list of available interrupts refer to the usbintr and the usbsts register tables. 5. set run/stop bit to run mode. ? after the run bit is set, a device reset will occur. the dcd must monitor the reset event and adjust the software state as described in the bus reset section of the following port state and control section below. note: transitioning from host mode to device mode requires a device controller reset before modifying usbmode. note: all device queue heads must be initialized for control endpoints must be initialized before the endpoint is enabled. non-control device queue heads before the endpoint can be used. note: endpoint 0 is designed as a control endpoint only and does not need to be configured using endptctrl0 register. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-196 freescale semiconductor it is also not necessary to initially prime endpoint 0 b ecause the first packet received will always be a setup packet. the contents of the first setup packet wi ll require a response in accordance with usb device framework (chapter 9) command set. 30.8.6.2 port state and control from a chip or system reset, the device controller enters the powered state. a transition from the powered state to the attach state occurs when the run/stop bit is set to a ?1?. after receiving a reset on the bus, the port will enter the defaultfs or defaulths state in accordance with the reset protocol described in appendix c.2 of the usb specification rev. 2.0. the following state diagram depi cts the state of a usb 2.0 device. table 30-85. device state diagram states powered, attach, defaultfs/hs, suspendfs/hs are implemented in the device controller and are communicated to the dcd using the following status bits: device configured address assigned reset when the host resets the device returns to the default state. power interruption bus activity bus activity bus activity bus inactive bus inactive bus inactive attach default fs/hs configured fs/hs address fs/hs suspend fs/hs suspend fs/hs suspend fs/hs device deconfigured software onl y state powered active state inactive state set run/stop bit to run mode high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-197 table 30-86. device controller state information bits it is the responsibility of the dcd to maintain a state variable to differentiate between the defaultfs/hs state and the address/configured states. change of state from default to address and the configured states is part of the enumeration proce ss described in the device framework section of the usb 2.0 specification. as a result of entering the address state, the device address register ( deviceaddr ) must be programmed by the dcd. entry into the configured indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the endptctrlx registers and initializing the associated queue heads. 30.8.6.2.1 bus reset a bus reset is used by the host to initialize downstream devices. when a bus reset is detected, the device controller will renegotiate its attachment speed, re set the device address to 0, and notify the dcd by interrupt (assuming the usb reset interrupt enable is set). after a reset is received, all endpoints (except endpoint 0) are disabled and any primed transacti ons will be cancelled by the device controller. the concept of priming will be clarified below, but the dcd must perform the following tasks when a reset is received: clear all setup token semaphores by reading the endptsetupstat register and writing the same value back to the endptsetupstat register. clear all the endpoint complete status bits by reading the endptcomplete register and writing the same value back to the endptcomplete register. cancel all primed status by waiting until all bits in the endptprime are 0 and then writing 0xffffffff to endptflush . read the reset bit in the portscx register and make su re that it is still active. a usb reset will occur for a minimum of 3 ms and the dcd must reach this point in the reset cleanup before end of the reset occurs, otherwise a hardware reset of the devi ce controller is recommended (rare.) ? a hardware reset can be performed by writing a one to the device controller reset bit in the usbcmd reset. note: a hardware reset will caus e the device to detach from the bus by clearing the run/stop bit. thus, the dcd must complete ly re-initialize the device controller after a hardware reset. free all allocated dtds because they will no longer be ex ecuted by the device controller. if this is the first time the dcd is processing a usb reset event, then it is likely that no dtds have been allocated. bit register dcsuspend high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-198 freescale semiconductor at this time, the dcd may release control back to the os because no further changes to the device controller are permitted until a port change detect is indicated. after a port change detect, the de vice has reached the default state and the dcd can read the portscx to determine if the device is operating in fs or hs mode. at this time, the device controller has reached normal operating mode and dcd can begin enumerat ion according to the usb chapter 9 - device framework. in some applications, it may not be possible to enable one or more pipes while in fs mode. beyond the data rate issue, there is no difference in dcd operation between fs and hs modes. 30.8.6.2.2 suspend/resume suspend suspend description in order to conserve power, usb devices automatica lly enter the suspended state when the device has observed no bus traffic for a specified period. when suspended, the usb device maintains any internal status, including its address and configuration. attached devices must be prepared to suspend at any time they are powered, regardless of if they have been a ssigned a non-default address, are configured, or neither. bus activity may cease due to the host entering a susp end mode of its own. in addition, a usb device shall also enter the suspended state when the hub port it is attached to is disabled. a usb device exits suspend mode when there is bus activity. a usb device may also request the host to exit suspend mode or selective susp end by using electrical signaling to indicate remote wakeup. the ability of a device to signal remote wakeup is optional. if the usb device is capable of remote wakeup signaling, the device must support the ability of the host to enable and disable this capability. when the device is reset, remote wakeup signaling must be disabled. suspend operational model the device controller moves into the suspend state when suspend signaling is detected or activity is missing on the upstream port for more than a specific pe riod. after the device controller enters the suspend state, the dcd is notified by an interrupt (assuming dc suspend interrupt is enabled). when the dcsuspend bit in the portscx is set to a ?1?, the device controller is suspended. dcd response when the device controller is suspended is application specific and may involve switching to low power operation. information on the bus power limits in suspend state can be found in usb 2.0 specification. note: the device dcd may use the fs/hs mode information to determine the bandwidth mode of the device. note: review system level clocking issues defined in section (ref: signals-clocking) for the clocking requirements of a suspended device controller. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-199 resume if the device controller is suspended, its operation is resumed when any non-idle signaling is received on its upstream facing port. in addition, the device ca n signal the system to resume operation by forcing resume signaling to the upstream port. resume signaling is sent upstream by writing a ?1? to the resume bit in the in the portscx while the device is in suspend state. sending resume signal to an upstream port should cause the host to issue resume signaling and br ing the suspended bus segment (one more devices) back to the active condition. port test modes contact arc international for port test mode capabilities. 30.8.6.2.3 managing endpoints the usb 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a usb device that can source or sink data in a communications channel between the host and the device. the endpoint addre ss is specified by the combination of the endpoint number and the endpoint direction. the channel between the host and an endpoint at a spec ific device represents a data pipe. endpoint 0 for a device is always a control type data channel used for device di scovery and enumeration. other types of endpoints support by usb include bulk, interrupt , and isochronous . each endpoint type has specific behavior related to packet response and error handl ing. more detail on endpoint operation can be found in the usb 2.0 specification. the arc usb-hs otg high-speed usb on-the-go device controller hardware supports up to the usb 2.0 maximum of 32 endpoint specified numbers. each additional endpoint beyond the required endpoint position adds additional hardware logic. the maximu m number of endpoint numbers available to the dcd is configured at hardware synthesis timer. after synthesis, the dcd can enab le, disable and configure endpoint type up to the maximum selected during synthesis. each endpoint direction is essentially independent and can be configured with differing behavior in each direction. for example, the dcd can configure endpoi nt 1-in to be a bulk endpoint and endpoint 1-out to be an isochronous endpoint. this helps to conser ve the total number of endpoints required for device operation. the only exception is that control endpoint s must use both directions on a single endpoint number to function as a control endpoint. endpoint 0 is, for example, is always a control endpoint and uses the pair of directions. each endpoint direction requires a queue head allocated in memory. if the maximum of 16 endpoint numbers, one for each endpoint direction are be ing used by the device controller, then 32 queue heads are required. the operation of an endpoint and use of queue heads are described later in this document. note: before resume signaling can be used, the host must enable it by using the set feature command defined in device framework (chapter 9) of the usb 2.0 specification. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-200 freescale semiconductor 30.8.6.2.4 endpoint initialization after hardware reset, all endpoint s except endpoint zero are uninitia lized and disabled. the dcd must configure and enable each endpoint by writing to configuration bit in the endptctrlx register. each 32-bit endptctrlx is split into an upper and lower half. the lower half of endptctrlx is used to configure the receive or out endpoint and the upper ha lf is likewise used to configure the corresponding transmit or in endpoint. control endpoints must be c onfigured the same in both the upper and lower half of the endptctrlx register otherwise the behavior is unde fined. the following table shows how to construct a configuration word for endpoint initialization. table 30-87. device controller endpoint initialization 30.8.6.2.5 stalling there are two occasions where the device contro ller may need to return to the host a stall the first occasion is the functional stall , which is a condition set by the dcd as described in the usb 2.0 device framework. a functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the endpoint stall bit in the endptctrlx register associated with the given endpoint and the given direction. in a functional sta ll condition, the device controller will continue to return stall responses to all transactions occu rring on the respective endpoint and direction until the endpoint stall bit is cleared by the dcd. a protocol stall , unlike a function stall, is used on control endpoints is automatically cleared by the device controller at the start of a new control transaction (s etup phase). when enabling a protocol stall, the dcd should enable the stall bits (both directions) as a pair. a single write to the endptctrlx register can ensure that both stall bits are set at the same instant. field value data toggle reset ?1? data toggle inhibit ?0? endpoint type 00 control 01 isochronous 10 bulk 11 interrupt endpoint stall ?0? note: any write to the endptctrlx register during operational mode must preserve the endpoint type field (i.e. perform a read-modify-write). high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-201 table 30-88. device controller stall response matrix 30.8.6.2.6 data toggle data toggle is a mechanism to maintain data cohere ncy between host and device for any given data pipe. for more information on data toggle, refer to the usb 2.0 specification. data toggle reset the dcd may reset the data toggle state bit and caus e the data toggle sequence to reset in the device controller by writing a ?1? to the data toggle reset bit in the endptctrlx register. this should only be necessary when configuring/initializing an endpoint or returning from a stall condition. data toggle inhibit note: this feature is for test purposes only and should never be used during normal device controller operation. setting the data toggle inhibit bit active (?1?) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state. in normal operation, the device controller checks th e data0/data1 bit against the data toggle to determine if the packet is valid. if data pid does not match the data toggle state bit maintained by the device controller for that endpoint, the data toggle is considered not valid. if the data toggle is not valid, the device controller assumes the packet was already r eceived and discards the packet (not reporting it to the dcd). to prevent the host controller from re-sending the same packet, the device controller will respond to the error packet by acknowledging it with either an ack or nyet response. usb packet endpoint stall bit. effect on stall bit. usb response setup packet received by a non-control endpoint. n/a none. stall in/out/ping packet received by a non-control endpoint. ?1? none. stall in/out/ping packet received by a non-control endpoint. ?0? none. ack/ nak/ nyet setup packet received by a control endpoint. n/a cleared ack in/out/ping packet received by a control endpoint ?1? none stall in/out/ping packet received by a control endpoint. ?0? none. ack/ nak/ nyet high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-202 freescale semiconductor 30.8.6.3 operational model for packet transfers all transactions on the usb bus are initiated by the hos t and in turn, the device must respond to any request from the host within the turnaround time stated in the usb 2.0 specification. at usb 1.1 full or low speed rates, this turnaround time was significant a nd the usb 1.1 device controllers were architected so that the device controller could access main memory or interrupt a host protocol processor in order to respond to the usb 1.1 transaction. the architecture of the usb 2.0 device controller must be different because same methods will not meet usb 2.0 hi gh-speed turnaround time requirements by simply increasing clock rate. a usb host will send requests to the device controller in an order that can not be precisely predicted as a single pipeline, so it is not possible to prepare a singl e packet for the device controller to execute. however, the order of packet requests is predictable when the endpoint number and direction is considered. for example, if endpoint 3 (transmit direction) is configur ed as a bulk pipe, then we can expect the host will send in requests to that endpoint. this device controller is architected in such a way that it can prepare packets for each endpoint/direction in anticipation of the host request. the process of preparing the device controller to send or receive data in response to hos t initiated transaction on the bus is referred to as ? priming ? the endpoint. this term will be used throughout the following documentation to describe the device controller operation so the dc d can be architected properly use pr iming. further, note that the term ? flushing ? is used to describe the action of clearing a packet that was queued for execution. priming transmit endpoints priming a transmit endpoint will cause the device contro ller to fetch the device transfer descriptor (dtd) for the transaction pointed to by the device queue head (dqh). after the dtd is fetched, it will be stored in the dqh until the device controller completes the transfer described by the dtd. storing the dtd in the dqh allows the device controller to fetch the operati ng context needed to handle a request from the host without the need to follow the linked list, starting at the dqh when the host request is received. after the device has loaded the dtd, the leading data in the packet is stored in a fifo in the device controller. this fifo is split into virtual channels so that the leading data can be stored for any endpoint up to the maximum number of endpoints c onfigured at device synthesis time. after a priming request is complete , an endpoint state of primed is indicated in the endptstatus register. for a primed transmit endpoint, the device cont roller can respond to an in request from the host and meet the stringent bus turnaround time of high speed usb. since only the leading data is stored in the device cont roller fifo, it is necessary for the device controller to begin filling in behind leading data after the transa ction starts. the fifo must be sized to account for the maximum latency that can be incurred by the syst em memory bus. more information about fifo sizing is presented in section . priming receive endpoints priming receive endpoints is identical to priming of tran smit endpoints from the point of view of the dcd. at the device controller the major difference in the ope rational model is that there is no data movement of the leading packet data simply because the data is to be received from the host. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-203 note as part of the architecture, the fifo for the re ceive endpoints is not partiti oned into multiple channels like the transmit fifo. thus, the size of the rx fifo does not scale with the number of endpoints. 30.8.6.3.1 interrupt/bulk e ndpoint operational model the behaviors of the device controller for interrupt and bulk endpoints are identic al. all valid in and out transactions to bulk pipes will handshake with a nak unless the endpoint had been primed. once the endpoint has been primed, da ta delivery will commence. a dtd will be retired by the device controller when th e packets described in the transfer descriptor have been completed. each dtd describes n packets to be transferred according to the usb variable length transfer protocol. the formula and table on the fo llowing page describe how the device controller computes the number and length of the packets to be sent/received by the usb vary according to the total number of bytes and maximum packet length. with zero length termination (zlt) = 0 n = int(number of bytes/max. packet length) + 1 with zero length termination (zlt) = 1 n = maxint(number of bytes/max. packet length) table 30-89. variable length transfer protocol example (zlt = 0) table 30-90. variable length transfer protocol example (zlt = 1) tx-dtd is complete when: ? all packets described dtd were successfully transmitted. *** total bytes in dtd will equal zero when this occurs. bytes (dtd) max. packet length (dqh) n p1 p2 p3 511 256 2 256 255 512 256 3 256 256 0 512 512 2 512 0 bytes (dtd) max. packet length (dqh) n p1 p2 p3 511 256 2 256 255 512 256 2 256 256 512 512 1 512 note: the mult field in the dqh must be set to ?00? for bulk, interrupt, and control endpoints. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-204 freescale semiconductor rx-dtd is complete when: ? all packets described in dtd were successfully received. *** total bytes in dtd will equal zero when this occurs. ? a short packet (number of bytes < maximum packet length) was received. *** this is a successful transfer completion; dcd must check total bytes in dtd to determine the number of bytes that are remaining. from the total bytes remaining in the dtd, the dcd can compute the actual bytes received. ? a long packet was received (number of bytes > ma ximum packet size) or (total bytes received > total bytes specified). *** this is an error condition. the device controller will discard the remaining packet, and set the buffer error bit in the dtd. in addition, the endpoint will be flushed and the usberr interrupt will become active. on the successful completion of the packet(s) descri bed by the dtd, the active bit in the dtd will be cleared and the next pointer will be followed when the terminate bit is clear. when the terminate bit is set, the device controller will flush the endpoint/d irection and cease operations for that endpoint/direction. on the unsuccessful completion of a packet (see long p acket above), the dqh will be left pointing to the dtd that was in error. in order to recover from this error condition, the dcd must properly reinitialize the dqh by clearing the active bit and update the nexttd poi nter before attempting to re-prime the endpoint. there is no required interaction with the dcd for handling such errors. interrupt/bulk endpoint bus response matrix table 30-91. interrupt/bulk endpoint bus response matrix bs error = force bit stuff error nyet/ack?nyet unless the transfer descriptor has packets remaining according to the usb variable length protocol then ack. syserr?system error should never occur when the latency fifos are correctly sized and the dcd is responsive. note: all packet level errors such as a missing handshake or crc error will be retried automatically by the device controller. stall not primed primed underflow overflow setup ignore ignore ignore n/a n/a in stall nak transmit bs error n/a out stall nak receive + nyet/ack n/a nak ping stall nak ack n/a n/a invalid ignore ignore ignore ignore ignore high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-205 30.8.6.3.2 control endpoi nt operation model setup phase all requests to a control endpoint begin with a se tup phase followed by an op tional data phase and a required status phase. the device c ontroller will always accept the set up phase unless the setup lockout is engaged. the setup lockout will engage so that future setup pa ckets are ignored. lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet. in hardware versions 2.3 and later, the setup lockout mechanism can be disabled and a new tripwire type semaphore will ensure that the setup packet payloa d is extracted from the queue head without being corrupted be an incoming setup packet. this is th e preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue. setup packet handling (pre-2.3 hardware) ? after receiving an interrupt and inspecting us bmode to determine that a setup packet was received on a particular pipe: ? 1. duplicate contents of dqh.ssetupbuffer into local software byte array. ? 2. write '1' to clear corresponding endptsetupstat bit and thereby disabling setup lockout. (i.e. the setup lockout activates as s oon as a setup arrives. by writing to the endptsetupstat, the device controller will accept new setup packets.) ? 3. process setup packet using local software byte array copy and execute status/handshake phases. ? note: after receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. these should be flushed & deallocated before linking a new status and/or handshake dtd for the most recent setup packet. setup packet handling (2.3 hardware and later) ? disable setup lockout by writing ?1? to setup lockout mode (slom) in usbmode. (once at initialization). setup lockout is not necessary when using th e tripwire as described below. ? after receiving an interrupt and inspecting en dptsetupstat to determine that a setup packet was received on a particular pipe: ? 1. write '1' to clear corresponding bit endptsetupstat. note: to limit the exposure of setup packets to the setup lockout mechanism (if used), the dcd should designate the priority of responding to setup packets above responding to other packet completions. note: leaving the setup lockout mode as ?0? will result in pre-2.3 hardware behavior. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-206 freescale semiconductor ? 2. write ?1? to setup tripwire (sutw) in usbcmd register. ? 3. duplicate contents of dqh.setupbuffer into local software byte array. ? 4. read setup tripwire (sutw) in usbcmd regi ster. (if set - continue; if cleared - goto 2) ? 5. write '0' to clear setup tripwire (sutw) in usbcmd register. ? 6. process setup packet using local software byte array copy and execute status/handshake phases. note: note: after receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. these should be flushed & deallocated before linking a new status and/or handshake dtd for the most recent setup packet. data phase following the setup phase, the dcd must create a device transfer descriptor for the data phase and prime the transfer. after priming the packet, the dcd must verify a new setup packet has not been received by reading the endptsetupstat register immediately verifying that the prime had completed. a prime will complete when the associated bit in the endptprime register is zero and the associated bit in the endptstat register is a one. if a prime fails, ie. the endptprime bit goes to zero and the endptstat bit is not set, then the prime has failed. this can only be due to improper setup of the dqh, dtd or a setup arriving during the prime operation. if a new setup packet is in dicated after the endptprime bit is cleared, then the transfer descriptor can be freed and the dcd must reinterpret the setup packet. should a setup arrive after the data stage is primed, th e device controller will automatically clear the prime status ( endptstat ) to enforce data coherency with the setup packet. status phase similar to the data phase, the dcd must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. the dcd must also perform the same checks of the endptsetupstat as described above in the data phase. note: the mult field in the dqh must be set to ?00? for bulk, interrupt, and control endpoints. note: error handling of data phase packets is the same as bulk packets described previously. note: the mult field in the dqh must be set to ?00? for bulk, interrupt, and control endpoints. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-207 control endpoint bus response matrix shown in the following table is the device controll er response to packets on a control endpoint according to the device controller state. table 30-92. control endpoint bus response matrix bs error = force bit stuff error nyet/ack?nyet unless the transfer descriptor has packets remaining according to the usb variable length protocol then ack. syserr?system error should never occur when the latency fifos are correctly sized and the dcd is responsive. 30.8.6.3.3 isochronous endpoi nt operational model isochronous endpoints are used for real-time scheduled delivery of data and their operational model is significantly different than the host throttled bulk, in terrupt, and control data pipes. real time delivery by the device controller will is accomplished by the following: ? exactly mult packets per (micro)frame are transmitted/received. note: mult is a two-bit field in the device queue head. the variable length packet protocol is not used on isochronous endpoints. ? nak responses are not used. instead, zero length pack ets and sent in response to an in request to an unprimed endpoints. for unprimed rx endpoints, the response to an out transaction is to ignore the packet within the device controller. ? prime requests always schedule the transfer descri bed in the dtd for the next (micro)frame. if the iso-dtd is still active after that frame, then the iso-dtd will be held ready until executed or canceled by the dcd. note: error handling of data phase packets is the same as bulk packets described previously. token type endpoint state setup lockout stall not primed primed underflow overflow setup ack ack ack n/a syserr in stall nak transmit bs error n/a n/a out stall nak receive + nyet/ack n/a nak n/a ping stall nak ack n/a n/a n/a invalid ignore ignore ignore ignore ignore ignore high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-208 freescale semiconductor an ehci compatible host controller uses the periodic frame list to schedule data exchanges to isochronous endpoints. the operational model for device mode does not use such a data structure. instead, the same dtd used for control/bulk/interrupt endpoints is also used for isochronous endpoints. the difference is in the handling of the dtd. the first difference between bulk and iso-endpoints is that priming an iso- endpoint is a delayed operation such that an endpoint will become primed only after a sof is received. after the dcd writes the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller completed a priming the dtd for transfer. internal to the design, the device controller hardware masks that prime start until the next frame boundary. this beha vior is hidden from the dcd but occurs so that the device controller can match the dt d to a specific (micro)frame. another difference with isochronous endpoints is that the transaction must wholly complete in a (micro)frame. once an iso transaction is started in a (micro)frame it will retire the corresponding dtd when mult transactions occur or the devi ce controller finds a fulfillment condition. the transaction error bit set in the status field indi cates a fulfillment error condition. when a fulfillment error occurs, the frame after the transfer failed to co mplete wholly, the device controller will force retire the iso-dtd and move to the next iso-dtd. it is important to note that fulfillment errors are only caused due to partially completed packets. if no activity occurs to a primed iso-dtd, the transaction will stay primed indefinitely. this means it is up to software discard transmit iso-dtds that pile up from a failure of the host to move the data. finally, the last difference with iso packets is in the data level error handling. when a crc error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. instead, the crc is noted by setting the transaction error bit and the data is stored as usual for the application software to sort out. ? tx packet retired ? mult counter reaches zero. ? fulfillment error [ transaction error bit is set] ? # packets occurred > 0 and # packets occurred < mult ? rx packet retired: ? mult counter reaches zero. ? non-mdata data pid is received** ? ** exit criteria only valid in hardware version 2.3 or later. previous to hardware version 2.3, any pid sequence that did not match the mu lt field exactly would be flagged as a transaction error due to pid mismatch or fulfillment error. ? overflow error: ? packet received is > maximum packet length. [ buffer error bit is set] note: for tx-iso, mult counter can be loaded with a lesser value in the dtd multiplier override field in hardware versions 2.3 and later. if the multiplier override is zero, the mult counter is initialized to the multiplier in the qh. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-209 ? packet received exceeds total bytes allocated in dtd. [ buffer error bit is set] ? fulfillment error [ transaction error bit is set] ? # packets occurred > 0 and # packets occurred < mult ? crc error [ transaction error bit is set ] isochronous pipe synchronization when it is necessary to synchronize an isochroous data pipe to the host, the (micro)frame number (frindex register) can be used as a marker. to cause a packet transfer to occur at a specific (micro)frame number [n], the dcd should interrupt on sof during frame n-1. when the frindex=n?1, the dcd must write the prime bit. the device controller w ill prime the isochronous endpoint in (micro)frame n?1 so that the device controller will execute delivery during (micro)frame n. isochronous endpoint bus response matrix table 30-93. isochronous endpoint bus response matrix bs error = force bit stuff error null packet = zero length packet note: for iso, when a dtd is retired, the next dtd is primed for the next frame. for continuous (micro)frame to (micro)frame operation the dcd should ensure that the dtd linked-list is out ahead of the device controller by at least two (micro)frames. caution priming an endpoint towards the end of (micro)frame n-1 will not guarantee delivery in (micro)frame n. the delivery may actually occur in (micro)frame n+1 if device controller does not have enough time to complete the prime before the sof for packet n is received. stall not primed primed underflow overflow setup stall stall stall n/a n/a in null packet null packet transmit bs error n/a out ignore ignore receive n/a drop packet ping ignore ignore ignore ignore ignore invalid ignore ignore ignore ignore ignore high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-210 freescale semiconductor 30.8.6.4 managing queue heads figure 30-76. end point queue head diagram the device queue head (dqh) points to the linked list of transfer tasks, each depicted by the device transfer descriptor (dtd). an area of memory pointed to by endpointlistaddr contains a group of all dqh?s in a sequential list as shown in figure 30-76 . the even elements in the list of dqh?s are used for receive endpoints (out/setup) and the odd elements are used for transmit endpoints (in/interrupt). device transfer descriptors are linked head to tail star ting at the queue head and ending at a terminate bit. once the dtd has been retired, it will no longer be part of the linked list from the queue head. therefore, software is required to track all transfer descript ors since pointers will no longer exist within the queue head once the dtd is retired (see section software link pointers). in addition to the current and next pointers and the dtd overlay examined in section operational model for packet transfers, the dqh also contains the following parameters for the associated endpoint: multipler, maximum packet length, interrupt on set up. the complete initialization of the dqh including these fields is demonstrated in the next section. 30.8.6.4.1 queue head initialization one pair of device queue heads must be initialized for each active endpoint. to initialize a device queue head: ? write the wmaxpacketsize field as required by th e usb chapter 9 or application specific protocol. ? write the multiplier field to 0 for control, bulk, and interrupt endpoints. for iso endpoints, set the multiplier to 1,2, or 3 as required bandwidth an in conjuction with the usb chapter 9 protocol. note: in fs mode, the multiplier field can only be 1 for iso endpoints. ? write the next dtd terminate bit field to ?1?. up to 32 elements endpoint qh 0 ? in endpoint qh 0 ? out endpointlistaddr endpoint qh 1 ? out endpoint transfer descriptor endpoint queue heads transfer buffer pointer transfer buffer transfer buffer transfer buffer transfer buffer transfer buffer pointer transfer buffer pointer transfer buffer pointer high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-211 ? write the active bit in the status field to ?0?. ? write the halt bit in the status field to ?0?. 30.8.6.4.2 operational model for setup transfers as discussed in section control endpoint operation m odel, setup transfer requires special treatment by the dcd. a setup transfer does not use a dtd but inst ead stores the incoming data from a setup packet in an 8-byte buffer within the dqh. upon receiving notification of the se tup packet, the dcd should handle the setup transfer as demonstrated here: 1. copy setup buffer contents from dqh - rx to software buffer. 2. acknowledge setup backup by writing a ?1? to the corresponding bit in endptsetupstat . 3. check for pending data or status dtd?s from prev ious control transfers and flush if any exist as discussed in section flushing/de-priming an endpoint. 4. decode setup packet and prepare data phase [optional] and status phase transfer as required by the usb chapter 9 or application specific protocol. 30.8.6.5 managing transfers with transfer descriptors 30.8.6.5.1 software link pointers it is necessary for the dcd software to maintain head and tail pointers to the for the linked list of dtds for each respective queue head. this is necessary be cause the dqh only maintains pointers to the current working dtd and the next dtd to be executed. the ope rations described in next section for managing dtd will assume the dcd can use reference the head and tail of the dtd linked list. note: the dcd must only modify dqh if the associated endpoint is not primed and there are no outstanding dtd?s. note: the acknowledge must occur before continuing to process the setup packet. note: after the acknowledge has occurred, the dcd must not attempt to access the setup buffer in the dqh?rx. only the local software copy should be examined. note: it is possible for the device controller to receive setup packets before previous control transfers complete. existing control packets in progress must be flushed and the new control packet completed. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-212 freescale semiconductor figure 30-77. software link pointers 30.8.6.5.2 building a transfer descriptor before a transfer can be executed from the linked list, a dtd must be built to describe the transfer. use the following procedure for building dtds. allocate 8-dword dtd block of memory aligned to 8-dword boundaries. example: bit address 4:0 would be equal to ?00000? write the following fields: 1. initialize first 7 dwords to 0. 2. set the terminate bit to ?1?. 3. fill in total bytes with transfer size. 4. set the interrupt on complete if desired. 5. initialize the status field with the active bit se t to ?1? and all remaining status bits set to ?0?. 6. fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer. 30.8.6.5.3 executing a transfer descriptor to safely add a dtd, the dcd must be follow this procedure which will handle the event where the device controller reaches the end of the dtd list at the same ti me a new dtd is being added to the end of the list. determine whether the link list is empty: ? check dcd driver to see if pipe is empty (int ernal representation of li nked-list should indicate if any packets are outstanding) ? case 1: link list is empty ? 1. write dqh next pointer and dqh terminate bit to 0 as a single dword operation. ? 2. clear active & halt bit in dqh (in case set from a previous error). note: to conserve memory, the reserved fields at the end of the dqh can be used to store the head & tail pointers but it still remains the responsibility of the dcd to maintain the pointers. endpoint qh next current completed dtds queued dtds head pointer tail pointer high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-213 ? 3. prime endpoint by writing ?1? to correct bit position in endptprime . ? case 2: link list is not empty ? 1. add dtd to end of linked list. ? 2. read correct prime bit in endptprime? if ?1? done. ? 3. set atdtw bit in usbcmd register to ?1?. ? 4. read correct tatus bit in endptstat . (store in tmp. variable for later) ? 5. read atdtw bit in usbcmd register. ? if ?0? goto 3. ? if ?1? continue to 6. ? 6. write atdtw bit in usbcmd register to ?0?. ? 7. if status bit read in (3) is ?1? done. ? 8. if status bit read in (3) is ?0? then goto case 1: step 1. 30.8.6.5.4 transfer completion after a dtd has been initialized and the associated e ndpoint primed the device controller will execute the transfer upon the host-initiated request. the dcd will be notified with a usb interrupt if the interrupt on complete bit was set or alternately, the dcd can poll the endpoint complete register to find when the dtd had been executed. after a dtd has been executed, dcd can check the status bits to determine success or failure. by reading the status fields of the completed dtds , the dcd can determine if the transfers completed successfully. success is determined with th e following combination of status bits: ? active = 0 ? halted = 0 ? transaction error = 0 ? data buffer error = 0 should any combination other than the one shown above exist, the dcd must take proper action. transfer failure mechanisms are indicated in the device error matrix . in addition to checking the status bit the dcd must re ad the transfer bytes field to determine the actual bytes transferred. when a transfer is complete, the total bytes transferred is by decremented by the actual bytes transferred. for transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the usb variable length packet protocol. caution multiple dtd can be completed in a single endpoint complete notification. after clearing the notification, dcd must search the dtd linked list and retire all dtds that have finished (active bit cleared). high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-214 freescale semiconductor 30.8.6.5.5 flushing/de -priming an endpoint it is necessary for the dcd to flush to de-prime one more endpoints on a usb device reset or during a broken control transfer. there may also be application specific requireme nts to stop transfers in progress. the following procedure can be used by the dcd to stop a transfer in progress: 1. write a ?1? to the corresponding bit(s) in endptflush . 2. wait until all bits in endptflush are ?0?. ? software note: this operation may take a large amount of time depending on the usb bus activity. it is not desirable to have this wait loop within an interrupt service routine. 3. read endptstat to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now ?0?. if the corresponding bi ts are ?1? after step #2 has finished, then the flush failed as described in the following: ? explanation: in very rare cases, a packet is in progress to the particular endpoint when commanded flush using endptflush . a safeguard is in place to refuse the flush to ensure that the packet in progress completes successful ly. the dcd may need to repeatedly flush any endpoints that fail to flush be repeating steps 1-3 until each endpoint is successfully flushed. 30.8.6.5.6 device error matrix the following table summarizes packet errors that are not automatically handled by the device controller. table 30-94. device error matrix notice that the device controller handles all errors on bulk/control/interrupt endpoints except for a data buffer overflow. however, for iso endpoints, errors packets are not retried and errors are tagged as indicated. error descriptions: error direction packet type data buffer error bit transaction error bit overflow ** rx any 1 0 iso packet error rx iso 0 1 iso fulfillment error both iso 0 1 error description overflow number of bytes received exceeded max. packet size or total buffer length. ** this error will also set the halt bit in the dqh and if there are dtds remaining in the linked list for the endpoint, then those will not be executed. high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 30-215 30.8.6.6 servicing interrupts the interrupt service routine must consider that th ere are high-frequency, low-frequency operations, and error operations and order accordingly. 30.8.6.6.1 high-fre quency interrupts high frequency interrupts in particular should be hande d in the order below. the most important of these is listed first because the dcd must acknowledge a setup buffer in the timeliest manner possible. table 30-95. high frequency interrupt events ** it is likely that multiple interrupts to stack up on any call to the interrupt service routine and during the interrupt serv ice routine. 30.8.6.6.2 low-frequency interrupts the low frequency events include the following interr upts. these interrupt can be handled in any order since they don?t occur often in comparison to the high-frequency interrupts. iso packet error crc error on received iso packet. contents not guaranteed to be correct. iso fulfillment error hst failed to complete the number of packets defined in the dqh mult field within the given (micro)frame. for scheduled data delivery the dcd may need to readjust the data queue because a fulfillment error will cause device controller to cease data transfers on the pipe for one (micro)frame. during the ?dead? (micro)frame, the device controller reports error on the pipe and primes for the following frame. execution order interrupt action 1a usb interrupt ** - endptsetupstatus copy contents of setup buffer and acknowledge setup packet (as indicated in section managing queue heads). process setup packet according to usb 2.0 chapter 9 or application specific protocol. 1b usb interrupt ** - endptcomplete handle completion of dtd as indicated in section managing queue heads. 2 sof interrupt action as deemed necessary by application. this interrupt may not have a use in all applications. error description high-speed usb on-the-go (hs usb-otg) MCIMX27 multimedia applications processor reference manual, rev. 0.2 30-216 freescale semiconductor table 30-96. low frequency interrupt events 30.8.6.6.3 error interrupts error interrupts will be least frequent and should be placed last in the interrupt service routine. table 30-97. error interrupt events interrupt action port change change software state information. sleep enable (suspend) change software state information. low power handling as necessary. reset received change software state information. abort pending transfers. interrupt action usb error interrupt. this error is redundant because it combines usb interrupt and an error status in the dtd. the dcd will more aptly handle packet-level errors by checking dtd status field upon receipt of usb interrupt (w/ endptcomplete). system error unrecoverable error. immediate reset of core; free transfers buffers in progress and restart the dcd. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 5: timer peripherals introduction the i.mx27 processor provides a variety of timers for timing and scheduling of software applications, as well as peripherals and audio wave form generation. the timers covered in this part are as follows: chapter 31, ?general purpose timer (gpt) ,? on page 31-1 chapter 32, ?pulse-width modulator (pwm) ,? on page 32-1 chapter 33, ?real time clock (rtc) ,? on page 33-1 chapter 34, ?watchdog timer (wdog) ,? on page 34-1 general purpose timer (gpt) the general purpose timer (gpt) has a 32 bit up-counter . the timer counter value can be captured in a register using an event on an external pin. the capt ure trigger can be programmed to be a rising or/and falling edge. the gpt can also generate an event on ipp_do_cmpout pins and an interrupt when the timer reaches a programmed value. it has a 12-bit presca ler providing a programmable clock frequency derived from multiple clock sources. the gpt has one 32 b it up-counter with clock source selection, including external clock, two input capture channels with programmable trigger edge, and three output compare channels with programmable output mode. the gpt can perform a forced compare and can configured to be programmed to be active in low power and de bug modes interrupt generation can be programmed for capture, compare, rollover events and the timers offers both restart or free-run modes of operation. pulse-width modulation module (pwm) while the pulse-width modulation module (pwm) is a timer/counter, its primary use is for sound and melody generation. the pwm of the i.mx27 uses a 16- bit counter which is optimized to generate sound from stored sample audio images and it can also generate tones. it uses the 16-bit resolution and a 4 16 data fifo to generate sound. the pw m follows ip bus protocol for interfacing with the arm9 processor core. it does not have any interface signals with any ot her module inside the chip except for clock and reset inputs from the clock and reset controller module and in terrupt signals to the processor interrupt handler. there is a single output signal going to a pin in the i.mx27. the pwm module of the i.mx27 offers the following features: ? pulse-width modulation (pwm) m odule has the following features: ? 4 x 16 fifo to minimize interrupt overhead MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor ? 16-bit resolution ? sound and melody generation ? secondary display contrast control real time clock (rtc) the real time clock (rtc) module provides a curren t stamp of seconds, minutes, hours and days. alarm and timer functions are also available for progr amming. rtc support dates from the year 1980 to 2050. the rtc module includes the following features: ? full clock?days, hours, minutes, seconds ? minute countdown timer with interrupt ? programmable daily alarm with interrupt ? sampling timer with interrupt ? once-per-day, once-per-hour, once-per- minute, and once-per-second interrupts ? operation at 32.768 khz or 32 khz, or 38.4 kh z (determined by reference clock crystal) watchdog timer (wdog) the watchdog (wdog) timer module protects the i.mx27 against system failures by providing a method of escaping from unexpected events or programming errors. once the wdog module is activated, it must be servi ced by software on a periodic basis. if servicing does not take place, the timer times out. upon a time -out, the wdog timer module either asserts the wdog signal or a system reset signal wdog_rst depending on software configuration. the wdog timer module also generates a system reset via a software write to the watchdog control register (wcr) a detection of a clock monitor event, an external reset, an external jtag reset signal, or if a power-on-reset has occurred. the wdog signal is asserted via a software write to the w cr, a detection of a clock monitor event, or upon a watchdog time-out. in case of a time-out even, the fo llowing actions can be programmed: ? interrupt to the arm9 ? internal reset (can follow the interrupt after a predefined time-out) ? external pin toggle for external devices rese t (issued together with the internal reset) the wdog module can continue/suspend the timer opera tion in the low power modes (wait, doze and stop). for arm (doze and stop), it emulates these modes. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-1 chapter 31 general purpose timer (gpt) 31.1 introduction the i.mx27 device contains six identical 32-bit general-purpose timers (gpt) with programmable prescalers and compare and capture registers. each timer ?s counter value can be captured using an external event and can be configured to trigger a capture even t on either the leading or trailing edges of an input pulse. each gpt can also generate an interrupt wh en the timer reaches a programmed value. each gpt has an11-bit prescaler providing a programmable cloc k frequency derived from multiple clock sources. figure 31-1 illustrates the general-purpose timer block diagram for one of the timers. the general-purpose timers have the following features: ? programmable sources for the cloc k input, including external clock ? input capture capability with programmable trigger edge ? output compare with programmable mode ? free-run and restart modes ? software reset function general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-2 freescale semiconductor figure 31-1. general-purpose timer block diagram 31.2 operation after a hardware reset the counter, control, prescaler, status and capture registers of the gpt are reset. the compare value is set to 0xffffffff. the output pin (tout) is also reset. the gpt is enabled when the ten bit in the gpt control register (tctl) is set and the counter starts running. it is recommended that all the registers be set to appropriate values first before enabling the gpt. when the ten bit is cleared the counter value freezes or clears depending on cc bit in gpt control register (tctl). all other register values are retained. there is a software reset bit (swr) in the tctl register. when this bit is set the gpt generates a reset signal for 3 ipg_clk periods and this bit clears afte r 5 ipg_clk periods. the software reset results in all the registers in the gpt being reset except for the ten bit which is not cleared by software reset if set. the software reset can be asserted with the ten bit off, however, the ipg_clk clock (module clock) signals to gpt must be on for the software reset to be functional. 1 / 4 sync prescaler 11bit 1... 2048 timer counter timer input capture timer output compare cmp input capture logic output control logic irqen frr tin ipg_clk_32k comp status ip-bus reg r/w pclk register register register module interrupt line tout ipg_clk_perclk mclk general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-3 31.2.1 clocks the clock that feeds the prescaler can be selected from the following: ? ipg_clk_perclk (divided by 1 or by 4). the fre quency of ipg_clk_perclk is constant and is independent of changes to the ipg_clk. the module internally synchronizes perclk to the ipg_clk. this clock is synchronized inside the module to ipg_clk. hence the frequency of this clock has to be at least 1/4 that of ipg_clk if the prescaler is programmed to divide by 1. ? gpt i/o pin (ipp_gpt_tin). extern al clock from outside the chip. ? 32 khz clock (ipg_clk_32k). this is the 32 khz low reference clock which is provided by crm. this clock is supposed to be on in low power mode when the ipg_clk is turned off. thus the gpt can be run on this clock in low power mode. the crm is expected to provide this clock after synchronizing it to ahb_clk in normal functional mode and switch to the unsynchronized version in the low power mode. the clock input source is determined by the cl ksource field of the gp t control register. the clksource value should only be changed when the gpt is disabled. the external clock coming from the ipp_gpt_tin pin is not synchronized with ipg_clk. the gpt prescaler register (tprer) se lects the divide ratio of the input clock that drives the main counter (tcn). the prescaler can divide the input clock by a value between 1 and 2048. 31.2.2 operation during low-power mode in low-power mode when the ipg_clk (modul e clock used for register accesses) and ipg_clk_perclk clocks are switched off, the gpt ca n also work only if the ipg_clk_32k is available. the counter continues to run, when it reaches the value contained in the compare register, the compare interrupt will occur. the capture interrupt can also be produced in low-power mode if the capture function is enable. when the capture interrupt or compare interrupt occurs, the status register can be written on the positive edge of mclk. 31.2.3 capture event each gpt have a 32-bit capture register that takes a snapshot of the counter when a defined transition of tin is detected by the capture edge detector. the type of transition that triggers this capture is selected by the cap field of the gpt control register (tctl). because the capture event is triggered by mclk, so each transition must be valid for at least two mclk periods to ensure a capture event is triggered. when a capture event occurs, the corresponding status bit is set in the gpt status register (tstat) and an interrupt is posted if the capture function is enabled a nd if the capten bit of the gpt control register is set. if another capture event occurs the new count value will still be captured in the capture register even if the interrupt is not serviced and capture status bit is set. 31.2.4 compare event each gpt have a 32-bit compare register. when the value in this register matches with the value of the counter register a compare event occurs. on a comp are event the appropriate gpt output pin (tout) is general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-4 freescale semiconductor toggled or an active low pulse (for one count period) is generated on it according to the setting of output mode (om) bit in the gpt control register. when in toggle mode the toggling takes place at the end of the count period in which the match has occurred. the corresponding status bit is set in the status register and an interrupt is posted if the compen bit of the gpt control register is set. the gpt output pi n continues to produce an output on a compare event even if the interrupt is not serviced and compare status bit is set. 31.2.5 modes of operation the gpt can be configured for free-run or restart modes by programming the free -run/restart bit (frr) of the gpt control register. ? restart mode: in restart mode, when a compare event occurs, the counter resets to 0x00000000. subsequently it resumes counting up. ? freerun mode: in free-run mode, when a compare event occurs, it has no effect on the counter value. the counter continues counting until 0xfff fffff is reached and then it is reset to 0x00000000 and resumes counting. 31.3 programming model the general-purpose timer modules each have six user -accessible 32-bit registers. they are shown with offsets from their respective base addresse s in the detailed register descriptions. table 31-1 summarizes the general-purpose timer registers and their addresses. figure 31-2 provides the detailed register summary. table 31-1. gpt register summary description name address gpt control register 1 tctl1 0x10003000 gpt control register 2 tctl2 0x10004000 gpt control register 3 tctl3 0x10005000 gpt control register 4 tctl4 0x10019000 gpt control register 5 tctl5 0x1001a000 gpt control register 6 tctl6 0x1001f000 gpt prescaler register 1 tprer1 0x10003004 gpt prescaler register 2 tprer2 0x10004004 gpt prescaler register 3 tprer3 0x10005004 gpt prescaler register 4 tprer4 0x10019004 gpt prescaler register 5 tprer5 0x1001a004 gpt prescaler register 6 tprer6 0x1001f004 gpt compare register 1 tcmp1 0x10003008 general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-5 gpt compare register 2 tcmp2 0x10004008 gpt compare register 3 tcmp3 0x10005008 gpt compare register 4 tcmp4 0x10019008 gpt compare register 5 tcmp5 0x1001a008 gpt compare register 6 tcmp6 0x1001f008 gpt capture register 1 tcr1 0x1000300c gpt capture register 2 tcr2 0x1000400c gpt capture register 3 tcr3 0x1000500c gpt capture register 4 tcr4 0x1001900c gpt capture register 5 tcr5 0x1001a00c gpt capture register 6 tcr6 0x1001f00c gpt counter register 1 tcn1 0x10003010 gpt counter register 2 tcn2 0x10004010 gpt counter register 3 tcn3 0x10005010 gpt counter register 4 tcn4 0x10019010 gpt counter register 5 tcn5 0x1001a010 gpt counter register 6 tcn6 0x1001f010 gpt status register 1 tstat1 0x10003014 gpt status register 2 tstat2 0x10004014 gpt status register 3 tstat3 0x10005014 gpt status register 4 tstat4 0x10019014 gpt status register 5 tstat5 0x1001a014 gpt status register 6 tstat6 0x1001f014 table 31-2. general purpose timer register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1000_3000 (tctl1)? 0x1000_f000 (tctl6) r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 00000 cc om frr cap cap t en com p en clk source ten w swr table 31-1. gpt register summary (continued) description name address general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-6 freescale semiconductor 31.3.1 gpt control registers the gpt control (tctl) register controls the overall operation of the timer. figure 31-2 shows field assignments for this register and table 31-3 provides the field descriptions. 0x1000_3004 (tprer1)? 0x1000_f004 (tprer6) r0000000000 0 00000 w r0 0 0 0 0 prescaler w 0x1000_3008 (tcmp1)? 0x1000_f008 (tcmp6) r compare value w r compare value w 0x1000_300c (tcr1)? 0x1000_f00c (tcr6) r capture value w r capture value w 0x1000_3010 (tcn1)? 0x1000_f010 (tcn6) r counter value w r counter value w 0x1000_3014 (tstat1)? 0x1000_f014 (tstat6) r0000000000 0 00000 w r 0000000000 0 000 cap t co mp w w1c w1c table 31-2. general purpose timer register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-7 0x1000_3000 (tctl1) 0x1000_4000 (tctl2) 0x1000_5000 (tctl3) 0x1000_9000 (tctl4) 0x1000_a000 (tctl5) 0x1000_f000 (tctl6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 00 0 00 0 0 0 w reset0000000000000000 1514131211109876543210 r swr 0 0 00 cc om frr cap capt en com p en clk source ten w reset0000000000000000 figure 31-2. gpt control register table 31-3. gpt control registers field descriptions name description 31?16 reserved. swr 15 software reset. gpt is reset when this bit is set to 1. this bit is set when the module is in reset state and is cleared when the reset procedure is over. the reset signal is asserted 2 clock cycles (ipg_clk) after this bit is set and the reset remains asserted for 3 clock cycles. the whole reset procedure is complete 5 clock cycles after this bit is asserted this software reset does not reset the ten bit. 0 gpt is not reset. 1 gpt is reset. 14?11 reserved. these bits are reserved and should not be used. 10 cc counter clear. this bit determines whether the counter is to be cleared when ten=0 (timer disabled). 0 counter is halted at the current count when ten = 0. 1 counter will be reset when ten=0. 9 om output mode. this bit controls the output mode of the timer after compare event occurs. 0 active-low pulse for one clock period. 1 toggle output. 8 frr free-run/restart. this bit controls how the timer operates after a compare event occurs. in free-run mode, the timer continues counting till 0xffffffff. in restart mode, the counter resets to 0x00000000 and resumes counting. 0 restart mode 1 free-run mode general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-8 freescale semiconductor 31.3.2 gpt prescaler register the gpt prescaler register (tprer) contro ls the divide value of the prescaler. figure 31-3 shows field assignments for this register and table 31-4 provides the field descriptions. 7?6 cap capture edge. this field controls the operation of the capture function. the value in the counter is loaded into the capture register on the detection of an event on the tin pin. the event which will trigger this capture is determined by this field. 00 capture function disabled 01 capture on rising edge and generate interrupt 10 capture on falling edge and generate interrupt 11 capture on rising or falling edge and generate interrupt 5 capt en capture interrupt enable. this bit enables the capture interrupt. 0 capture interrupt is disabled. 1 capture interrupt is enabled. 4 comp en compare interrupt enable. this bit enables the compares interrupt. 0 compare interrupt disabled. 1 compare interrupt enabled. 3?1 clksource clock source. this field controls the source of the clock to the prescaler. the stop-count freezes the timer at its current value. note: this field value should only be changed when the gpt is disabled. 000 stop count (clock disabled). 001 perclk1 to prescaler. 010 perclk1 divided by 4 to prescaler. 011 tin to prescaler. 1xx 32 khz clock to prescaler. 0 ten timer enable. ten bit enables the general-purpose timer. the bit can be cleared either by writing 0 or by a hardware reset. the bit cannot be cleared by asserting the software reset. 0 timer is disabled 1 timer is enabled. table 31-3. gpt control registers field descriptions (continued) name description general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-9 . 31.3.3 gpt compare register the gpt compare (tcmp) register contains the valu e that is compared with the free-running counter. a compare event is generated when the counter matches th e value in this register. this register reset to 0xffffffff. figure 31-4 shows field assignments for this register and table 31-5 provides the field descriptions. 0x1000_3004 (tprer1) 0x1000_4004 (tprer2) 0x1000_5004 (tprer3) 0x1000_9004 (tprer4) 0x1000_a004 (tprer5) 0x1000_f004 (tprer6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 00 0 00 0 0 0 w reset0000000000000000 1514131211109876543210 r swr 0 0 00 prescaler w reset0000000000000000 figure 31-3. gpt control register table 31-4. gpt prescaler register description name description 31?11 reserved. 10?0 prescaler counter clock prescaler. this field determines the division value of the prescaler between 1 and 2048. 0x00 divides by 1 and 0x7ff divides by 2048.note: when ipg_clk_perclk freq.= ipg_clk freq. the minimum value to be programmed in prescaler field should be > 2 to get proper functioning of the module. 0x00 = divide by 1 ... 0x7ff = divide by 2048 general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-10 freescale semiconductor 31.3.4 gpt capture register this register is read only, and resets to 0x00000000. the gpt capture register (tcr) stores the counter value when a capture event occurs. figure 31-5 shows field assignments for this register and table 31-6 provides the field descriptions. 0x1000_3008 (tcmp1) 0x1000_4008 (tcmp2) 0x1000_5008 (tcmp3) 0x1000_9008 (tcmp4) 0x1000_a008 (tcmp5) 0x1000_f008 (tcmp6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r compare value w reset1111111111111111 1514131211109876543210 r compare value w reset1111111111111111 figure 31-4. gpt compare register table 31-5. gpt compare registers descriptions name description 31?0 compare compare value. a compare event occurs when the counter value matches the value in this field. general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-11 31.3.5 gpt counter register the read-only gpt counter (tcn) register can be re ad at anytime without disturbing the current count. figure 31-6 shows field assignments for this register and table 31-7 provides the field descriptions. 0x1000_300c (tcr1) 0x1000_400c (tcr2) 0x1000_500c (tcr3) 0x1000_900c (tcr4) 0x1000_a00c (tcr5) 0x1000_f00c (tcr6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r capture value w reset0000000000000000 1514131211109876543210 r capture value w reset0000000000000000 figure 31-5. gpt capture register table 31-6. gpt capture registers description name description 31?0 capture capture value. this field stores the counter value at the time of a capture event. general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-12 freescale semiconductor 31.3.6 gpt status register the gpt status (tstat) register (write 1 to clear) i ndicates the gpt?s status. when a capture event occurs, the capt bit is set. when a compare event occurs, th e comp bit is set. these bits can only be cleared by writing 1 to clear the interrupt status. figure 31-6 shows field assignments for this register and table 31-7 provides the field descriptions. 0x1000_3010 (tcn1) 0x1000_4010 (tcn2) 0x1000_5010 (tcn3) 0x1000_9010 (tcn4) 0x1000_a010 (tcn5) 0x1000_f010 (tcn6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r counter value w reset0000000000000000 1514131211109876543210 r counter value w reset0000000000000000 figure 31-6. gpt counter register table 31-7. gpt counter register field descriptions name description 31?0 count count value. this field contains the current count value. whenever there is an update of compare register the counter is reset to zero and the count starts afresh. general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 31-13 0x1000_3014 (tstat1) 0x1000_4014 (tstat2) 0x1000_5014 (tstat3) 0x1000_9014 (tstat4) 0x1000_a014 (tstat5) 0x1000_f014 (tstat6) access: user read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 00 0 00 0 0 0 w reset000000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 00 0 00 0 capt comp w reset00000000000000w1cw1c figure 31-7. gpt status register table 31-8. gpt status register field descriptions name description 31?2 reserved. 1 capt capture event. this bit indicates that a capture event has occurred. 0 no capture event 1 a capture event has occurred 0 comp compare event. this bit indicates that a compare event has occurred. 0 no compare event 1 a compare event has occurred general purpose timer (gpt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 31-14 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-1 chapter 32 pulse-width modulator (pwm) the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. it uses 16-bit re solution and a 4 x 16 data fifo to generate sound. 32.1 overview this section presents an overview of the pwm. figure 32-1 illustrates the pwm block diagram. figure 32-1. pulse-width modulator block diagram ipg_clk ipg_clk_32k 16-bit counter register 16-bit period register 16-bit sample register 4x16-bit fifo cmp cmp 12-bit prescaler system peripheral bus irq_b cmpie rovie irqen rov cmp clksrc prescaler clock output (pclk) pwm interrupts clock off s r poutc pwmo poutc ipg_clk_highfreq pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-2 freescale semiconductor the following features characterize the pwm: ? 16-bit up-counter with clock source selection ? 4 x 16 fifo to minimize interrupt overhead ? 12-bit prescaler for division of clock ? sound and melody generation ? active high or active low configurable output ? can be programmed to be active in low power and debug modes ? interrupts at compare and rollover 32.2 signal description the pwm follows ip bus protocol for interfacing with the processor core. it does not have any interface signals with any other module inside the chip exce pt for clock and reset inputs from the clock control module (ccm) and interrupt signals to the processo r interrupt handler. there is a single output signal going outside the chip boundary. figure 32-2 shows the pwm signals at the module boundary. pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-3 figure 32-2. pwm module signals 32.2.1 external signals pwm has a single output signal to the i.mx27 chip boundary named pwmo. table 32-1 describes the external signals for the i.mx27 device. table 32-1. i.mx27 external signals name direction function reset state pull-up pwmo output this is the functional output of the pwm. the modulated signal of the module is observed at this pin 0 ? ipg_clk ipg_clk_32k ipg_clk_s ips_module_en ips_addr[13:2] ips_rwb ips_byte_31_24 ips_byte_23_16 ips_byte_15_8 ips_byte_7_0 ips_wdata[31:0] ipt_mode ipt_reset ipg_hard_async_reset ipg_enable_clk ipi_int_pwm_rovi ips_rdata[31:0] ipp_do_pwmo ips_xfr_err ipt_se_async ipt_se_gatedclk ipg_debug ipg_doze ipg_wait ipg_stop ipi_int_pwm_cmpi ipi_int_pwm_fifoi ipi_int_pwm ipp_obe_pwmo pulse width modulator ipg_clk_highfreq ips_xfr_wait resp_sel pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-4 freescale semiconductor 32.2.1.1 pwmo signal the pwmo is the modulated output signal of the pwm. this signal can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the pwm. the smallest period can be two ipg_clk clock periods with duty cycle of 50%. 32.3 memory map and register definition the pwm module includes 6 user-accessible 32-bit registers. section 32.3.2, ?register descriptions ? provides the detailed descriptions for all of the pwm registers. 32.3.1 register summary figure 32-3 shows the key to the register fields, and table 32-3 shows the register figure conventions. table 32-2. pwm memory map address register access reset value section/page 0x1000_6000 (pwmcr) pwm control register (pwmcr) r/w 0x0000_0000 32.3.2.1/32-6 0x1000_6004 (pwmsr) pwm status register (pwmsr) r/w 0x0000_0008 32.3.2.2/32-8 0x1000_6008 (pwmir) pwm interrupt register (pwmir) r/w 0x0000_0000 32.3.2.3/32-9 0x1000_600c (pwmsar) pwm sample register (pwmsar) r/w 0x0000_0000 32.3.2.4/32-10 0x1000_6010 (pwmpr) pwm period register (pwmpr) r/w 0x0000_fffe 32.3.2.5/32-11 0x1000_6014 (pwmcnr) pwm counter register (pwmcnr) r 0x0000_0000 32.3.2.6/32-11 figure 32-3. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 32-3. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-5 table 32-4 shows the pwm register summary. 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 32-4. pwm register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1000_6000 (pwmcr) r0000 fwm sto pen doz en wai ten db ge n bct r hct r poutc clksrc w r prescaler sw r repeat en w 0x1000_6004 (pwmsr) r0000000000000000 w r000000000 fw e cm p rov fe fifoav w w1c w1c w1c w1c 0x1000_6008 (pwmir) r0000000000000000 w r0000000000000 cie rie fie w 0x1000_600c (pwmsar) r0000000000000000 w r sample[15:0] w 0x1000_6010 (pwmpr) r0000000000000000 w r period[15:0] w table 32-3. register figure conventions (continued) convention description pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-6 freescale semiconductor 32.3.2 register descriptions this section contains the detailed register descriptions for the pwm registers. 32.3.2.1 pwm control register (pwmcr) the pwm control register (pwmcr) is used to confi gure the operating settings of the pwm. it contains the prescaler for the clock division. figure 32-4 shows the register; table 32-5 provides its field descriptions. 0x1000_6014 (pwmcnr) r0000000000000000 w r count[15:0] w 0x1000_6000 (pwmcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 0 fwm stop en doz en wait en dbg en bct r hct r poutc clksrc w reset0000 0 0 0 000000000 1514131211109 876543210 r prescaler swr repeat en w reset0000 0 0 0 000000000 figure 32-4. pwm control register (pwmcr) table 32-5. pwmcr field descriptions field description 31?28 reserved reserved. these reserved bits are always read as zero. 27?26 fifo water mark. these bits are used to set the data level at which the fifo empty flag will be set and the corresponding interrupt generated 00 fifo empty flag is set when there are more than or equal to 1 empty slots in fifo. 01 fifo empty flag is set when there are more than or equal to 2 empty slots in fifo. 10 fifo empty flag is set when there are more than or equal to 3 empty slots in fifo. 11 fifo empty flag is set when there are more than or equal to 4 empty slots in fifo. table 32-4. pwm register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-7 25 stopen sleep mode enable. this bit keeps the pwm functional while in sleep mode. when this bit is cleared, the input clock is gated off in sleep mode. this bit is not affected by software reset. it is cleared by hardware reset. 0 inactive in sleep mode 1 active in sleep mode 24 dozen doze mode enable. this bit keeps the pwm functional in doze mode. when this bit is cleared, the input clock is gated off in doze mode. this bit is not affected by software reset. it is cleared by hardware reset. 0 inactive in doze mode 1 active in doze mode 23 waiten wait mode enable. this bit keeps the pwm functional in wait mode. when this bit is cleared, the input clock is gated off in wait mode. this bit is not affected by software reset. it is cleared by hardware reset. 0 inactive in wait mode 1 active in wait mode 22 dbgen debug mode enable. this bit keeps the pwm functional in debug mode. when this bit is cleared, the input clock is gated off in debug mode. this bit is not affected by software reset. it is cleared by hardware reset. 0 inactive in debug mode 1 active in debug mode 21 bctr byte data swap control. this bit determines the byte ordering of the 16-bit data when it goes into the fifo from the sample register. 0 byte ordering remains the same. 1 byte ordering is reversed. 20 hctr halfword data swap control. this bit determines which halfword data from the 32-bit ip-bus interface is written into the lower 16 bits of the sample register. 0 halfword swapping does not take place. 1 halfwords from write data bus are swapped. 19?18 poutc pwm output configuration. this bit field determines the mode of pwm output on the output pin. 00 output pin is set at rollover and cleared at comparison 01 output pin is cleared at rollover and set at comparison 10 pwm output is disconnected. 11 pwm output is disconnected. 17?16 clksrc select clock source. these bits determine which clock input will be selected for running the counter. after reset the system functional clock is selected. the input clock can also be turned off if these bits are set to 00. this field value should only be changed when the pwm is disabled 00 clock is off 01 ipg_clk 10 ipg_clk_highfreq 11 ipg_clk_32k 15?4 prescaler counter clock prescaler value. this bit field determines the value by which the clock will be divided before it goes to the counter. 0x000 divide by 1 0x001 divide by 2 ... 0xfff divide by 4096 table 32-5. pwmcr field descriptions (continued) field description pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-8 freescale semiconductor 32.3.2.2 pwm status register (pwmsr) the pwm status register (pwmsr) contains seven bits which display the state of the fifo and the occurrence of rollover and compare events. the fifoav bit is read-only but the other four bits can be cleared by writing 1 to them. fe, rov, and cmp bits are associated to fifo-empty, roll-over, and compare interrupts, respectively. figure 32-5 shows the register; table 32-6 provides its field descriptions. 3 swr software reset. pwm is reset when this bit is set to 1. it is a self clearing bit. a write 1 to this bit is a single wait state write cycle. when the module is in reset state this bit is set and is cleared when the reset procedure is over. setting this bit resets all the registers to their reset values except for the stopen, dozen, waiten, and dbgen bits in this control register. 0 pwm is out of reset. 1 pwm is undergoing reset. 2?1 repeat sample repeat. this bit field determines the number of times each sample from the fifo is to be used. 00 use each sample once 01 use each sample twice 10 use each sample four times 11 use each sample eight times 0 en pwm enable. this bit enables the pwm. if this bit is not enabled, the clock prescaler and the counter is reset. when the pwm is enabled, it begins a new period, the output pin is set to start a new period while the prescaler and counter are released and counting begins. 0pwm is disabled. 1 pwm is enabled. 0x1000_6004 (pwmsr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r000000000fwecmprovfe fifoav w w1c w1c w1c w1c reset0000000000001000 figure 32-5. pwm status register (pwmsr) table 32-5. pwmcr field descriptions (continued) field description pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-9 32.3.2.3 pwm interrupt register (pwmir) the pwm interrupt register (pwmir) contains three bits that control the generation of the compare, rollover and fifo empty interrupts. figure 32-6 shows the register; table 32-7 provides its field descriptions. table 32-6. pwmsr field descriptions field description 31?7 reserved reserved. these reserved bits are always read as zero. 6 fwe fifo write error status. this bit shows that an attempt has been made to write fifo when it is full. 0 fifo write error has not occurred. 1 fifo write error has occurred. 5 cmp compare status. this bit shows that a compare event has occurred. 0 compare event has not occurred. 1 compare event has occurred. 4 rov roll-over status. this bit shows that a roll-over event has occurred. 0 roll-over event has not occurred. 1 roll-over event has occurred. 3 fe fifo empty status bit. this bit indicates the fifo data level in comparison to the water level set by fwm field in the control register. 0 data level is above water mark. 1 the data level falls below the mark set by the fwm field. 2?0 fifoav fifo available. these read-only bits indicate the data level remaining in the fifo. an attempted write to these bits will not affect their value and no transfer error is generated. 000 no data available 001 1 word of data in fifo 010 2 words of data in fifo 011 3 words of data in fifo 100 4 words of data in fifo 101 unused 110 unused 111 unused 0x1000_6008 (pwmir) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000000 cie rie fie w reset0000000000000000 figure 32-6. pwm interrupt register (pwmir) pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-10 freescale semiconductor 32.3.2.4 pwm sample register (pwmsar) the pwm sample register (pwmsar) is the input to the fifo. 16-bit words are loaded into the fifo. the fifo can be written and read when the pwm is disabled. the pwm runs at the last set duty-cycle setting if all the values of the fifo has been utilized, until the fifo is reloaded or the pwm is disabled. when a new value is written, the duty cycle changes after the current period is over. a value of zero in the sample register will result in the ipp_pwm_pwmo output signal being always low/high (poutc =00 it will be low and poutc = 01 it will be high), and hence no output waveform will be produced. if the value in this register is higher than the period + 1, the output will never be reset/set depending on poutc value. figure 32-7 shows the register; table 32-8 provides its field descriptions. table 32-7. pwmir field descriptions field description 31?3 reserved reserved. these reserved bits are always read as zero. 2 cie compare interrupt enable. this bit controls the generation of the compare interrupt. 0 compare interrupt is not enabled. 1 compare interrupt is enabled. 1 rie roll-over interrupt enable. this bit controls the generation of the rollover interrupt. 0 roll-over interrupt is not enabled. 1 roll-over interrupt is enabled. 0 fie fifo empty interrupt enable. this bit controls the generation of the fifo empty interrupt. 0 fifo empty is interrupt disabled. 1 fifo empty is interrupt enabled. 0x1000_600c (pwmsar) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sample w reset0000000000000000 figure 32-7. pwm sample register (pwmsar) pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-11 32.3.2.5 pwm period register (pwmpr) the pwm period register (pwmpr) determines the pe riod of the pwm output signal. after the counter value matches period + 1, the counter is reset to start another period. pwmo (hz) = pclk(hz)/(period +2) a value of zero in the pwmpr results in a period of two clock cycles for the output signal. writing 0xffff to this register achieves the same result as writing 0xfffe. a change in the period value due to a write in pwmpr results in the counter being reset to zero and the start of a new count period. figure 32-8 shows the register; table 32-9 provides its field descriptions. 32.3.2.6 pwm counter register (pwmcnr) the read-only pulse-width modulator counter register (pwmcnr) contains the current count value and can be read at any time without disturbing the counter. figure 32-9 shows the register; table 32-10 provides its field descriptions. table 32-8. pwmsar field descriptions field description 31?16 reserved these are reserved bits and writing a value will not affect the functionality of pwm and are always read as zero. 15?0 sample sample value. this is the input to the 4x16 fifo. the value in this register denotes the value of the sample being currently used. 0x1000_6010 (pwmpr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0 00000000000 w reset0000 0 00000000000 1514131211109876543210 r period w reset1111 1 11111111110 figure 32-8. pwm period register (pwmpr) table 32-9. pwmpr field descriptions field description 31?16 reserved these are reserved bits and writing a value will not affect the functionality of pwm and are always read as zero. 15?0 period period value. these bits determine the period of the count cycle. the counter counts up to [period value] +1 and is then reset to 0x0000. pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-12 freescale semiconductor 32.4 functional description the following sections detail the pwm operation and function. 32.4.1 operation the output of the pwm is a toggling signal whos e frequency and duty cycle can be modulated by programming the appropriate registers. it has a 16-bit up counter which counts from 0x0000 until the counter value equals the [value in period register] + 1. after this match occurs the counter is reset to 0x0000. at the beginning of a count period cycle, the pwmo pi n is set to one (default) and the counter begins counting up from 0x0000. the sample value in the sample fifo is compared on each count of prescaler clock. when the sample and count values match, the pw mo signal is cleared to zero (default). the counter continues counting until the period match occurs and subsequently anothe r period cycle begins. when the pwm is enabled the counter starts running and generates an output with the reset values in the period and sample registers. it is recommended that the programming of these registers be done before pwm is enabled. a hardware reset results in all th e pwm count and sample registers begin cleared and the fifo being flushed. the control register shows that fifo is empt y and it can be written into, and the pwm is disabled. a software reset has the same results, however the state of the stopen, dozen, waiten, and dbgen 0x1000_6014 (pwmcnr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0 00000000000 w reset0000 0 00000000000 1514131211109876543210 rcount w reset0000 0 00000000000 figure 32-9. pwm counter register (pwmcnr) table 32-10. pwmcnr field descriptions field description 31?16 reserved these are reserved bits and writing a value will not affect the functionality of pwm and are always read as zero. 15?0 count counter value. these bits are the counter register value and denotes the current count state the counter register is in. pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-13 bits in the control register are not affected. softwa re reset can be asserted even when the pwm is in disabled state. 32.4.1.1 clocks the clock that feeds the prescaler can be selected from the following: ? high frequency clock (ipg_clk_highfreq) pat_ref or ckih this is a high frequency clock provided by the clock control module (ccm). this clock is supposed to be on in the low power mode when the ipg_clk is turned off. thus the pwm can be run on this clock in the low power mode. the cr m is expected to provide this clock after synchronizing it to ahb_clk in the normal functional mode and switch to the unsynchronized version in the low power mode. ? low reference clock (ipg_clk_32k) ckil this is the 32 khz low reference clock which is provided by the ccm. this clock is supposed to be on in the low power mode when ipg_clk is turned off. thus pwm can be run on this clock in the low power mode. the crm is expected to provi de this clock after synchronizing it to ahb_clk in the normal functional mode and switch to the unsynchronized version in the low power mode. ? global functional clock (ipg_clk) this clock is supposed to be on in normal operations. in low power modes it can be switched off. the clock input source is determined by the clksrc field of the pwm control register. the clksrc value should only be changed when the pwm is disabled. the pwm input clock can be divided from 1 to 4096 by using a prescaler by a ppropriately setting the prescaler field in the control register. a change in the value of the prescaler field is immediately reflected on its output clock frequency. 32.4.1.2 fifo digital sample values can be loaded into the pulse-width modulator as 16-bit words. the endianness can be changed using the bctr and hctr bits of the c ontrol register. a 4-word (16-bit) fifo minimizes interrupt overhead. a maskable interr upt is generated when the number of data words fall below the water level set by the fwm field in the control register. a write in the sample register results in the value being stored into the fifo if it is not full. a write when the fifo is full sets fwe (fifo write error) bit in the status register and the fifo contents remain unchanged. the fifo can be written into when the pwm is disabled. the fifoav field shows how many data words are currently contained in the fifo and if it can be written into. a read on the sample register yields the current fifo value being used or will be used by the pwm for generation on the output signal. therefore a write and a subsequent read on the sample register may result in different values being obtained. 32.4.1.3 rollover and compare event the counter is reset to 0x0000 after its value equals the period + 1 and resumes counting thereafter. this event is referred to as a rollover. when period = 0x0000, the counter is reset after count reaches 0x0001. pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-14 freescale semiconductor therefore period = 0xffff or 0xfffe results in the counter value being reset after count till 0xffff. during a rollover event the output is either set (default), reset or has no effect according to the programming of the poutc field in the control register. this event can also generate an interrupt if the respective interrupt enable bit is set in the control register. when the counter value reaches the sample value the output of the pwm is reset (default), set or has no effect according to the programming of the poutc field of control register. this event is referred to as a compare event. this event can also generate an interrupt if the respective interrupt enable bit is set in the control register. if the rollover event sets the pwm output signal the compare event will reset it and vice versa for a particular programming conf iguration of poutc field. 32.4.1.4 low power mode behavior in low power modes if the clock from the selected cl ock source is available, the pwm counter continues to run and an output is produced depending on whether the control bit for that mode is set. in the absence of the clock itself or if the corresponding low power bit in the control register is 0, the counter is reset and resumes counting when it exits the low power mode. 32.4.1.5 debug mode behavior in debug mode, pwm has the option of continuing to r un or be halted. if the dbgen bit is not set in the pwmcr, the pwm is halted. if the dbgen bit is set, then the pwm will continue to run in the debug mode. 32.5 pwm clocking figure 32-10 shows the relationship of clocks used by the pwm. pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 32-15 figure 32-10. pwm clocking 32.5.1 pwm clock inputs figure 32-11 shows the clock that feeds the prescaler (sys_clk). figure 32-11. clock distribution inside pwm ipg_clk ips_module_en crm_module_en ipg_clk ipg_enable_clk aipi ipg_clk_s clock gating cell clock gating cell pwm lpg low power gate ipg_clk_32k ipg_clk_highfreq registers clock mux and counter ccm clock selection and division unit pwm_crm pwm_fifo pwm_reg pwm_outputgen pclk is used in interrupt generation ipg_clk_s is used for register r/w pclk ipg_clk_s ipg_clk ipg_clk_32k ipg_clk_highfreq pclk is used to run the pwm main counter and generate output pclk is used for fifo read flag update ipg_clk_s is used for write into sample register and update its associated flags pulse-width modulator (pwm) MCIMX27 multimedia applications processor reference manual, rev. 0.2 32-16 freescale semiconductor the clock that feeds the prescaler shown in figure 32-11 can be selected from the following clock inputs: ? high frequency clock (ipg_clk_highfreq) pat_ref or ckih ? low reference clock (ipg_clk_32k) ckil ? global functional clock (ipg_clk) the selected clock sys_clk is prescaled with a 12-bit pr escaler value. the sys_clk is gated with an enable signal that is generated from a prescaler counter and pwm enable to get the pclk. the main pwm counter runs on pclk. pclk is used to generate the output signal of pwm and also the interrupts. ipg_clk_s is the clock used for register read/write. the only hand instantiated clock gating inside the module is done inside pwm_crm submodule for division of sys_clk to generate the pclk. figure 32-12 shows an overview of the clock selection and division unit. figure 32-12. clock selection and division unit 32.5.2 ipg_enable_clk generation whenever the module is enabled and ipg_clk is selected, this signal is asserted. figure 32-13 shows the ipg_enable_clk generation logic. figure 32-13. ipg_enable_clk generation logic sys_clk ipf_clk_highfreq ipg_clk_32k ipg_clk pclk 12-bit prescaler pclk enable clock off clksrc pwm_enable_bit ipg_enable_clk clksrc[0] clksrc[1] MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-1 chapter 33 real time clock (rtc) 33.1 introduction see figure 33-1 for a block diagram of the functional organi zation of the real time clock (rtc) block. the block consists of the following blocks: ? prescaler ? time-of-day (tod) clock counter ?alarm ? sampling timer ? minute stopwatch ? associated control and bus interface hardware figure 33-1. real time clock block diagram sampling timer prescaler second minute interrupt control interrupt enable clock control interrupt status alarm comparator second latch hour-minute latch hour latch minute stopwatch 32.768k or 32k or 38.4k 1 ppm ipbus decode hour day tod clock 1 pps 1 pph 1 ppd clk2hz clk32hz rtc_int ip bus real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-2 freescale semiconductor 33.2 overview this section discusses how to operate and program the real-time clock (rtc) module that maintains the system clock, provides stopwatch, alar m, and interrupt functions, and s upports the features described in section 33.2.1, ?features .? 33.2.1 features the rtc module includes the following features: ? full clock: days, hours, minutes, seconds ? minute countdown timer with interrupt ? programmable daily alarm with interrupt ? sampling timer with interrupt ? once-per-day, once-per-hour, once-per- minute, and once-per-second interrupts ? operation at 32.768 khz or 32 khz, or 38.4 kh z (determined by reference clock crystal) 33.2.2 modes of operation the prescaler converts the incoming crystal reference cloc k to a 1 hz signal that is used to increment the seconds, minutes, hours, and days tod counters. th e alarm functions, when enabled, generate rtc interrupts when the tod settings reach progr ammed values. the sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries. ? prescaler and counter the prescaler divides the reference clock down to 1 hz. the reference frequencies of 32.768 khz, 38.4 khz and 32 khz are supported. the counter portion of the rtc module consists of four groups of counters that are physically located in three registers: ? the 6-bit seconds counter is located in the seconds register ? the 6-bit minutes counter and the 5-bit hour s counter are located in the hourmin register ? the 16-bit day counter is located in the dayr register ?alarm there are three alarm registers that mirror the thre e counter registers. an alarm is set by accessing the real-time clock alarm registers (alrm_hm , alrm_sec, and dayalarm) and loading the exact time that the alarm should generate an in terrupt. when the tod clock value and the alarm value coincide, an interrupt occurs. ? sampling timer the sampling timer is designed to support applic ation software. the sampling timer generates a periodic interrupt with the frequency specified by the samx bits of the rtcienr register. this timer can be used for digitizer sampling, keyboard debouncing, or communication polling. the sampling timer operates only if the real-time clock is enabled. see table 33-15 for the list of the interrupt frequencies of the sampling t imer for the possible reference clocks. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-3 ? minute stopwatch the minute stopwatch performs a countdown with a one minute resolution. it can be used to generate an interrupt on a minute boundary. 33.3 external signal description the rtc has no external signals. 33.3.1 overview there are no signals connected off the chip. see table 33-1 for a complete list of rt c block level signal names. 33.4 memory map and register definition the rtc module has ten 32-bit registers. section 33.4.3, ?register descriptions ? provides the detailed descriptions for all of the rtc registers. 33.4.1 memory map table 33-2 shows the rtc memory map. 33.4.2 register summary figure 33-2 shows the key to the register fields and table 33-3 shows the register figure conventions. table 33-2. rtc register memory map address register access reset values section/page 0x1000_7000 (hourmin) rtc hours and minutes counter register (hourmin) r/w 0x0000_? ? ? ? 33.4.3.1/33-6 0x1000_7004 (seconds) rtc seconds counter register (seconds) r/w 0x0000_00 ? ? 33.4.3.2/33-7 0x1000_7008 (alrm_hm) rtc hours and minutes alarm register (alrm_hm) r/w 0x0000_0000 33.4.3.3/33-7 0x1000_700c (alrm_sec) rtc seconds alarm register (alrm_sec) r/w 0x0000_0000 33.4.3.4/33-8 0x1000_7010 (rtcctl) rtc control register (rcctl) r/w 0x0000_0000 33.4.3.5/33-9 0x1000_7014 (rtcisr) rtc interrupt status register (rtcisr) r/w 0x0000_0000 33.4.3.6/33-10 0x1000_7018 (rtcienr) rtc interrupt enable register (rtcienr) r/w 0x0000_0000 33.4.3.7/33-13 0x1000_701c (stpwch) stopwatch minutes register (stpwch) r/w 0x0000_0000 33.4.3.8/33-14 0x1000_7020 (dayr) rtc days counter register (dayr) r/w 0x0000_? ? ? ? 33.4.3.9/33-15 0x1000_7024 (dayalarm) rtc days alarm register (dayalarm) r/w 0x0000_0000 33.4.3.10/33-16 real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-4 freescale semiconductor figure 33-2. key to register fields table 33-4 shows the rtc register summary. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 33-3. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 33-4. rtc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1000_7000 (hourmin) r0000000000000000 w r000 hour 00 minutes w 0x1000_7004 (seconds) r0000000000000000 w r0000000000 seconds w real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-5 0x1000_7008 (alrm_hm) r0000000000000000 w r000 hour 00 minutes w 0x1000_700c (alrm_sec) r0000000000000000 w r0000000000 seconds w 0x1000_7010 (rtcctl) r0000000000000000 w r0000000 en xtl 0 0 0 ge n sw r w 0x1000_7014 (rtcisr) r0000000000000000 w r sa m7 sa m6 sa m5 sa m4 sa m3 sa m2 sa m1 sa m0 2hz 0 hr 1hz day al m min sw w 0x1000_7018 (rtcienr) r0000000000000000 w r sa m7 sa m6 sa m5 sa m4 sa m3 sa m2 sa m1 sa m0 2hz 0 hr 1hz day al m min sw w 0x1000_701c (stpwch) r0000000000000000 w r0000000000 cnt w 0x1000_7020 (dayr) r0000000000000000 w r days w 0x1000_7024 ( daya l a r m ) r0000000000000000 w r daysal w table 33-4. rtc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-6 freescale semiconductor 33.4.3 register descriptions this section consists of register descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of re gister bits and field functions follow the register diagrams in their bit order. 33.4.3.1 rtc hours and minutes counter register (hourmin) the real-time clock hours and minutes counter register (hourmin) is used to program the hours and minutes for the tod clock. it can be read or written at any time. after a write, the time changes to the new value. this register cannot be reset since th e real-time clock is always enabled at reset. see figure 33-3 for an illustration of valid bits in th e hours and minutes counter register and table 33-5 for descriptions of the bit fields. 0x1000_7000 (hourmin) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 hour 00 minutes w reset0 0 0 ????? 0 0 ???? ?? figure 33-3. rtc hours and minutes counter register table 33-5. rtc hours and minutes counter register field descriptions field description 31?13 reserved 12?8 hour hour setting indicates the current hour that can be set to any value between 0 and 23. 00000 current hour is 0. 00001 current hour is 1. ...... ...... 10111 current hour is 23: indicates the current hour that can be set to any value between 0 and 23. 7?5 reserved 5?0 minutes minutes setting indicates the current minutes that can be set to any value between 0 and 59. 000000 current minute is 0. 000001 current minute is 1. ...... ...... 111011 current minute is 59. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-7 the hours and minutes are not affected by any of the hardware or software reset, their reset values are ?not unknown? but we just do not know the exact values to put into the table. 33.4.3.2 rtc seconds counter register (seconds) the real-time clock seconds register (seconds) is used to program the seconds for the tod clock. it can be read or written at any time . after a write, the time changes to the new value. this register cannot be reset since the real-time cloc k is always enabled at reset. see figure 33-4 for an illustration of valid bits in the rtc seconds counter register and table 33-6 for descriptions of the bit fields. the seconds are not affected by any of the hardware or software reset, their reset values are ?not unknown,? but we just do not know the exact values to put into the table. 33.4.3.3 rtc hours and minutes alarm register (alrm_hm) the real-time clock hours and minutes alarm (alrm_hm ) register is used to configure the hours and minutes setting for the alarm. the alarm settings can be read or written at any time. see figure 33-5 for an illustration of valid bits in the rtc hours and minutes alarm register and table 33-7 for descriptions of the bit fields. 0x1000_7004 (seconds) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 seconds w reset0000000000?????? figure 33-4. rtc seconds counter register table 33-6. rtc seconds counter register field descriptions field description 31?6 reserved 5?0 seconds seconds setting indicates the current seconds that can be set to any value between 0 and 59. 000000 current second is 0. 000001 current second is 1. ...... ...... 111011 current second is 59. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-8 freescale semiconductor 33.4.3.4 rtc seconds alarm register (alrm_sec) the real-time clock seconds alarm (alrm_sec) register is used to configure the seconds setting for the alarm. the alarm settings can be read or written at any time. see figure 33-6 for an illustration of valid bits in the rtc seconds alarm register and table 33-8 for descriptions of the bit fields. 0x1000_7008 (alrm_hm) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 hour 00 minutes w reset00000000000000 0 0 figure 33-5. rtc hours and minutes alarm register table 33-7. rtc hours and minutes alarm register field descriptions field description 31?13 reserved 12?8 hours hour setting of the alarm hours that can be set to any value between 0 and 23. 00000 current hour is 0. 00001 current hour is 1. ...... ...... 10111 current hour is 23. 7?6 reserved 5?0 minutes minutes setting of the alarm minutes that can be set to any value between 0 and 59. 000000 current minute is 0. 000001 current minute is 1. ...... ...... 111011 current minute is 59. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-9 33.4.3.5 rtc control register (rtcctl) the real-time clock control (rtcctl) register is us ed to enable the real-time clock module and specify the reference frequency information for the prescaler. see figure 33-7 for an illustration of valid bits in the rtc control register and table 33-9 for descriptions of the bit fields. 0x1000_700c (alrm_sec) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 seconds w reset00000000000000 00 figure 33-6. rtc seconds alarm register table 33-8. rtc seconds alarm register field descriptions field description 31?6 reserved 5?0 seconds seconds setting of the alarm seconds, can be set to any value between 0 and 59. 000000 current second is 0. 000001 current second is 1. ...... ...... 111011 current second is 59. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-10 freescale semiconductor 33.4.3.6 rtc interrupt status register (rtcisr) the real-time clock interrupt status register (rtcisr) indicates the status of the various real-time clock interrupts. when an event of the types included in this re gister occurs, then the bit will be set in this register regardless of its corresponding interrupt enable bit.th ese bits are cleared by writing a value of 1, which also clears the interrupt. interrupts may occur while the system clock is idle or in sleep mode. every interrupt status bit is independent of each other. 0x1000_7010 (rtcctl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 en xtl 0 0 0 gen swr w reset00000000000000 00 figure 33-7. rtc control register table 33-9. rtc control register field descriptions field description 31?8 reserved 7 en enables/disables the real-time clock. the software reset bit (swr) has no effect on this bit. 0 disables the real-time clock 1 enables the real-time clock 6?5 xtl crystal selection. selects the proper input crystal frequency. it is important to set these bits correctly or the real-time clock will be inaccurate. 00 input crystal frequency is 32.768 khz. 01 input crystal frequency is 32 khz. 10 input crystal frequency is 38.4 khz. 11 input crystal frequency is 32.768 khz. 4?2 reserved 1 gen gen ? ipg_clk gating enable. decides whether to enable or disable the ipg_clk gating. upon reset the ipg_clk gating is enabled. 0 enables ipg_clk gating 1 disables ipg_clk gating 0 swr software reset. resets the module to its default state. however, a software reset will have no effect on the rtc enable (en) bit. 0no effect 1 reset the module to its default state real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-11 see figure 33-8 for an illustration of valid bits in the rtc interrupt status register and table 33-10 for descriptions of the bit fields. 0x1000_7014 (rtcisr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 2hz 0 hr 1hz day alm min sw w reset00000000000000 00 figure 33-8. rtc interrupt status register table 33-10. rtc interrupt status register field descriptions field description 31?16 reserved 15 sam7 sampling timer interrupt flag at sam7 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 512, 500, or 600 hz depending on different input clock. 0 no sam7 interrupt has occurred. 1 a sam7 interrupt has occurred. 14 sam6 sampling timer interrupt flag at sam6 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 256, 250, or 300 hz depending on different input clock. 0 no sam6 interrupt has occurred. 1 a sam6 interrupt has occurred. 13 sam5 sampling timer interrupt flag at sam5 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 128, 125, or 150 hz depending on different input clock. 0 no sam5 interrupt has occurred. 1 a sam5 interrupt has occurred. 12 sam4 sampling timer interrupt flag at sam4 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 64, 62.5, or 75 hz depending on different input clock. 0 no sam4 interrupt has occurred. 1 a sam4 interrupt has occurred. 11 sam3 sampling timer interrupt flag at sam3 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 32, 31.25, or 37.5 hz depending on different input clock. 0 no sam3 interrupt has occurred. 1 a sam3 interrupt has occurred. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-12 freescale semiconductor 10 sam2 sampling timer interrupt flag at sam2 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 16, 15.625, or 18.75 hz depending on different input clock. 0 no sam2 interrupt has occurred. 1 a sam2 interrupt has occurred. 9 sam1 sampling timer interrupt flag at sam1 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 8, 7.8125, or 9.375 hz depending on different input clock. 0 no sam1 interrupt has occurred. 1 a sam1 interrupt has occurred. 8 sam0 sampling timer interrupt flag at sam0 frequency. indicates that an interrupt has occurred. if enabled, this bit is periodically set at a rate of 4, 3.90625, or 4.6875 hz depending on different input clock. 0 no sam0 interrupt has occurred. 1 a sam0 interrupt has occurred. 7 2 hz 2 hz flag. indicates that an interrupt has occurred. if enabled, this bit is set at every 2 hz frequency. 0 no 2 hz interrupt has occurred. 1 a 2 hz interrupt has occurred. 6 reserved 5 hr hour flag. indicates that the hour counter has increment. if enabled, this bit is set on every increment of the hour counter in the time-of-day clock. 0 no 1-hour interrupt has occurred. 1 a 1-hour interrupt has occurred. 4 1 hz 1 hz flag. indicates that the second counter has increment. if enabled, this bit is set on every increment of the second counter of the time-of-day clock. 0 no 1 hz interrupt has occurred. 1 a 1 hz interrupt has occurred. 3 day day flag. indicates that the day counter has increment. if enabled, this bit is set on every increment of the day counter of the time-of-day clock. 0 no 24-hour rollover interrupt has occurred. 1 a 24-hour rollover interrupt has occurred. 2 alm alarm flag. indicates that the real-time clock matches the value in the alarm registers. the alarm will reoccur every 65536 days. for a single alarm, clear the interrupt enable for this bit in the interrupt service routine. 0 no alarm interrupt has occurred. 1 an alarm interrupt has occurred. 1 min minute flag. indicates that the minute counter has increment. if enabled, this bit is set on every increment of the minute counter in the time-of-day clock. 0 no 1-minute interrupt has occurred. 1 a 1-minute interrupt has occurred. 0 sw stopwatch flag. indicates that the stopwatch countdown timed out. 0 the stopwatch did not time out. 1 the stopwatch timed out. table 33-10. rtc interrupt status register field descriptions (continued) field description real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-13 33.4.3.7 rtc interrupt enable register (rtcienr) the real-time clock interrupt enable register (rtcienr) is used to enable/disable the various real-time clock interrupts. masking an interrupt bit has no eff ect on its corresponding status bit. every interrupt enable bit is independent of each other. see figure 33-9 for an illustration of valid bits in the rtc interrupt enable register and table 33-11 for descriptions of the bit fields. 0x1000_7018 (rtcienr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 2hz 0 hr 1hz day alm min sw w reset00000000000000 00 figure 33-9. rtc interrupt enable register table 33-11. rtc interrupt enable register field descriptions field description 31?16 reserved 15 sam7 sampling timer interrupt flag at sam7 interrupt. enables/disables the real-time sampling timer interrupt 7. 0 the sam7 interrupt is disabled. 1 the sam7 interrupt is enabled. 14 sam6 sampling timer interrupt flag at sam 6 interrupt. enables/disables the real-time sampling timer interrupt 6. 0 the sam6 interrupt is disabled. 1 the sam6 interrupt is enabled. 13 sam5 sampling timer interrupt flag at sam5 interrupt. enables/disables the real-time sampling timer interrupt 5. 0 the sam5 interrupt is disabled. 1 the sam5 interrupt is enabled. 12 sam4 sampling timer interrupt flag at sam4 interrupt. enables/disables the real-time sampling timer interrupt 4. 0 the sam4 interrupt is disabled. 1 the sam4 interrupt is enabled. 11 sam3 sampling timer interrupt flag at sam3 interrupt. enables/disables the real-time sampling timer interrupt 3. 0 the sam3 interrupt is disabled. 1 the sam3 interrupt is enabled. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-14 freescale semiconductor 33.4.3.8 rtc stopwatch minutes register (stpwch) the stopwatch minutes (stpwch) re gister contains the current stopwatch countdown value. when the minute counter of the tod clock increments, the value in this register decrements. 10 sam2 sampling timer interrupt flag at sam2 interrupt. enables/disables the real-time sampling timer interrupt 2. 0 the sam2 interrupt is disabled. 1 the sam2 interrupt is enabled. 9 sam1 sampling timer interrupt flag at sam1 interrupt. enables/disables the real-time sampling timer interrupt 1. 0 the sam1 interrupt is disabled. 1 the sam1 interrupt is enabled. 8 sam0 sampling timer interrupt flag at sam0 interrupt. enables/disables the real-time sampling timer interrupt 0. 0 the sam0 interrupt is disabled. 1 the sam0 interrupt is enabled. 7 2 hz 2 hz interrupt enable. enables/disables an interrupt at a 2 hz rate. 0 the 2-hz interrupt is disabled. 1 the 2-hz interrupt is enabled. 6 reserved 5 hr hour interrupt enable. enables/disables an interrupt whenever the hour counter of the real-time clock increments. 0 the 1-hour interrupt id disabled. 1 the 1-hour interrupt is enabled. 4 1hz 1 hz interrupt enable. enables/disables an interrupt whenever the second counter of the real-time clock increments. 0 the 1-hz interrupt is disabled. 1 the 1-hz interrupt is enabled. 3 day day interrupt enable. enables/disables an interrupt whenever the hours counter rolls over from 23 to 0. (midnight rollover) 0 the 24-hour interrupt is disabled. 1 the 24-hour interrupt is enabled. 2 alm alarm interrupt enable. enables/disables the alarm interrupt. 0 the alarm interrupt is disabled. 1 the alarm interrupt is enabled. 1 min minute interrupt enable. enables/disables an interrupt whenever the minute counter of the real-time clock increments. 0 the 1-minute interrupt is disabled. 1 the 1-minute interrupt is enabled. 0 sw stopwatch interrupt enable. enables/disables the stopwatch interrupt. note: the stopwatch counts down and remains at decimal -1 until it is reprogrammed. if this bit is enabled with -1 (decimal) in the stpwch register, an interrupt will be posted on the next minute tick. 0 stopwatch interrupt is disabled. 1 stopwatch interrupt is enabled. table 33-11. rtc interrupt enable register field descriptions (continued) field description real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-15 see figure 33-10 for an illustration of valid bits in the stopwatch minutes counter register and table 33-12 for descriptions of the bit fields. 33.4.3.9 rtc days counter register (dayr) the real-time clock days counter register (dayr) is used to program the day for the tod clock. when the hour field of the hourmin register rolls over from 23 to 00, the day counter increments. it can be read or written at any time. after a write, the time ch anges to the new value. this register cannot be reset since the real-time clock is always enabled at reset. see figure 33-11 for an illustration of valid bits in the counter register and table 33-13 for descriptions of the bit fields. 0x1000_701c (stpwch) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 cnt w reset00000000000000 00 figure 33-10. rtc stopwatch minutes register table 33-12. rtc stopwatch minutes register field descriptions field description 31?6 reserved 5-0 cnt stopwatch count. contains the stopwatch countdown value. note: the stopwatch counter is decremented by the minute (min) tick output from the real-time clock, so the average tolerance of the count is 0.5 minutes. for better accuracy, enable the stopwatch by polling the min bit of the rtcisr register or by polling the minute interrupt service routine. 000000 stopwatch countdown value is 0. 000001 stopwatch countdown value is 1. ...... ...... 111111 stopwatch countdown value is 63. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-16 freescale semiconductor the days are not affected by any of the hardware or software reset, their reset values are ?not unknown,? but we just do not know the exact values to put into the table. 33.4.3.10 rtc day alarm register (dayalarm) the real-time clock day alarm (dayalarm) register is used to configure the day for the alarm. the alarm settings can be read or written at any time. see figure 33-12 for an illustration of valid bits in the rtc day alarm register and table 33-14 for descriptions of the bit fields. 0x1000_7020 (dayr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r days w reset?????????????? ?? figure 33-11. rtc days counter register table 33-13. rtc days counter register field descriptions field description 31?16 reserved 15?0 days day setting. indicates the current day count, can be set to any values between 0 and 65535. 0x0000 current day count is 0. 0x0001 current day count is 1. ...... ...... 0xffff current day count is 65535. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-17 33.5 functional description the prescaler converts the incoming crystal reference cl ock to a 1 hz signal which is used to increment the seconds, minutes, hours, and days tod counters. the alarm functions, when enabled, generate rtc interrupts when the tod settings reach progr ammed values. the sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries. 33.5.1 prescaler and counter the prescaler divides the reference clock down to 1 hz. the reference frequencies of 32.768 khz, 38.4 khz, and 32 khz are supported. the prescaler st ages are tapped to support the sampling timer. the counter portion of the rtc module consists of four groups of counters that are physically located in three registers: ? the 6-bit seconds counter is located in the seconds register. ? the 6-bit minutes counter and the 5-bit hours counter are located in the hourmin register. ? the 16-bit day counter is located in the dayr register. these counters cover a 24-hour clock over 65536 days. all three registers can be read or written at any time. 0x1000_7024 (dayalarm) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r daysal w reset00000000000000 00 figure 33-12. rtc day alarm register table 33-14. rtc day alarm register field descriptions field description 31?16 reserved 15?0 daysal day setting of the alarm. indicates the current day setting of the alarm. it can be set to any value between 0 and 65535. 0x0000 current day setting of alarm is 0. 0x0001 current day setting of alarm is 1. ...... ...... 0xffff current day setting of alarm is 65535. real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-18 freescale semiconductor interrupts signal when each of the four counters increm ents, and can be used to indicate when a counter rolls over. for example, each tick of the seconds counter causes the 1 hz interrupt flag to be set. when the seconds counter rolls from 59 to 00, the minute counter increments and the min interrupt flag is set. the same is true for the minute counter with the hr signal, and the hour counter with the day signal. 33.5.2 alarm there are three alarm registers that mirror the three counter registers: ?alrm_hm ?alrm_sec ? dayalarm an alarm is set by accessing the three real-time clock alarm registers and loading the exact time that the alarm should generate an interrupt. when the tod clock value and the alarm value coincide, if the alm bit in the real-time clock interrupt enable register (rtcienr) is set, an interrupt occurs. note if the alarm is not disabled, it will reoccur every 65536 days. if a single alarm is desired, the alarm function must be disabled through the rtc interrupt enable register (rtcienr). 33.5.3 sampling timer the sampling timer is designed to support application software. the sampling timer generates a periodic interrupt with the frequency specified by the samx bits of the rtcienr register. this timer can be used for digitizer sampling, keyboard debouncing, or comm unication polling. the sampling timer operates only if the real-time clock is enabled. see table 33-15 for the list of the interrupt frequencies of the sampling timer for the possible reference clocks. multiple samx bits may be set in the rtc interrupt enable register (rtcienr). the corresponding bits in the rtc interrupt status register (rtcis r) will be set at the noted frequencies. table 33-15. sampling timer frequencies sampling frequency 32.768 khz reference clock 32 khz reference clock 38.4 khz reference clock sam7 512 hz 500 hz 600 hz sam6 256 hz 250 hz 300 hz sam5 128 hz 125 hz 150 hz sam4 64 hz 62.5 hz 75 hz sam3 32hz 31.25 hz 37.5 hz sam2 16 hz 15.625 hz 18.75 hz sam1 8 hz 7.8125 hz 9.375 hz sam0 4 hz 3.90625 hz 4.6875 hz real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 33-19 33.5.4 minute stopwatch the minute stopwatch performs a countdown with a one minute resolution. it can be used to generate an interrupt on a minute boundary. for example, to turn off the lcd controller after five minutes of inactivity, program a value of 0x04 into the stopwatch count (cnt) field of the stopwatch minutes (stpwch) register. at each minute, the valu e in the stopwatch is decremented. when the stopwatch value reaches ?1, the interrupt occurs. the value of the register does not change until it is reprogrammed. note the actual delay includes the seconds from setting the stopwatch to the next minute tick. 33.6 initialization/app lication information 33.6.1 flowchart of rtc operation see figure 33-13 for the illustration of the flowchart of a typical rtc operation. refer to example 33-1 for the code example of arm instruction for configuring rtc. figure 33-13. flowchart of rtc operation configure rtc control register config rtc days counter register config rtc hr/min counter register config rtc alarm registers config rtc interrupt enable reg check rtc interrupt status register config rtc seconds counter reg real time clock (rtc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 33-20 freescale semiconductor 33.6.2 code example of arm instruction example 33-1. code example of arm instruction ldr r1,=rtc_base_addr ldr r2,[r1,#0x10] orr r2,r2,#0x21 str r2,[r1,#0x10] ; software reset and 32k crystal ldr r3,=0x0000 str r3,[r1,#0x20] ;day ldr r3,=0x00038 str r3,[r1,#0x04] ;second ldr r3,=0x173b str r3,[r1] ;hr, min ldr r3,=0x0001 str r3,[r1,#0x24] ;alarm day ldr r3,=0x0000 str r3,[r1,#0x08] ;alarm hour, minute ldr r3,=0x01 str r3,[r1,#0x0c] ;alarm seconds ldr r2,[r1,#0x18] ;set alarm interrupt orr r2,r2,#0x4 str r2,[r1,#0x18] alarm_status_3 ldr r2,[r1,#0x18] ;check alarm status flag tst r2,#0x04 bne alarm_status_3 MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-1 chapter 34 watchdog timer (wdog) the watchdog (wdog) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. figure 34-1 shows the wdog block diagram. figure 34-1. wdog block diagram 34.1 overview once the wdog module is activated, it must be servi ced by the software on a periodic basis. if servicing does not take place, the timer times out. upon a time -out, the wdog timer module either asserts the wdog signal or a system reset signal, wdog_rst , depending on the software configuration. the wdog timer module also generates a system reset via a software write to th e watchdog control register (wcr). the wdog signal is asserted via a software write to the wcr, a detection of a clock monitor event, or upon a watchdog time-out. a state machine of the counter operation is shown in figure 34-6 , which demonstrates the time-out operation. the wdog module cannot be deactivated again after activation. ~8khz prescaler (div by 4) debug wdbg wdzst low power stop/doze mode watchdog control register (wcr) 8-bit counter watchdog service register (wsr) wdzst wdbg wde prescaler (div by 4096) ~2hz watchdog reset status register (wrsr) (time-out) logic logic ~32khz wdw wdw low power wait mode logic watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-2 freescale semiconductor the input clocks to the wdog module (ipg_clk_32k, ipg_c lk, and ipg_clk_s) must be synchronized with each other. note ipg_clk_32k is the synchronized version of the input ~32k clock (ckil) on the ip global functional clock. beca use the synchronized version is not available (the ip global functional clock is off) in low-power mode, it will receive the raw ckil (ipg_clk_32k) clock from the crm. these synchronizers will be bypassed while going into low power modes in crm. the wdog module can continue or suspend the timer operation in the low power modes (wait and stop). 34.1.1 features the wdog features are as follows: ? time-out periods from 0.5 seconds up to 128 seconds ? time resolution of 0.5 seconds ? configurable counters that can be programed to run or stop during low-power modes ? configurable counters that can be programed to run or stop during debug mode 34.2 external signal description the wdog module port signals going to pins are listed in table 34-2 . 34.2.1 detailed external signal descriptions 34.2.1.1 ipp_wdog , ipp_wdog_oe the ipp_wdog signal can be provided externally to the ic. it is asserted by a software request (setting the wcr bits) or a clock monitor event. the ipp_ wdog_oe signal is the output enable for the pin. 34.2.2 internal port signals the wdog internal port signals are listed in table 34-3 . table 34-2. signal properties name port function reset state pull-up ipp_wdog ? asserted by software timeout event 1 ? ipp_wdog_oe ? wdog output enable at pin 0 ? watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-3 table 34-3. wdog module port list port name direction description ipg_enable_clk output (o) ip global clock gating signal. it is available to the clock controller to gate off the clock to the wdog module for power saving. ipg_clk input (i) ip global functional clock. all functionality inside the wdog module is synchronized to this clock. ipg_clk_s i ip slave bus clock. this clock is synchronized to ipg_clk and is only used for register read/write operations. ipg_clk_32k i low frequency (32.768 khz) clock that continues to run in low-power mode. it is assumed that the clock controller will provide this clock signal synchronized to ipg_clk in the normal mode, and switch to a non-synchronized signal in low-power mode when the ipg_clk is off. ipg_hard_async_reset i ip global hardware reset (active low) ipg_por i power-on-reset signal (active low) ipg_debug i ip global signal indicating that wdog should enter debug mode operation ipg_stop i ip global signal indicating that wdog should enter low-power sleep mode operation ipg_wait i ip global signal indicating that wdog should enter low-power wait mode operation ips_rdata[15:0] o ip slave bus read data line ips_xfr_wait o ip slave bus transfer wait indicator ips_xfr_err o ip slave bus transfer error indicator ips_module_en i ip slave bus module enable signal. this signal indicates when a module bus transaction is occurring. ips_rwb i ip slave bus read/write signal. shows whether a bus transaction is read or write. ips_addr[13:1] i ip slave bus address signal. denotes the register being accessed during a bus transaction. ips_wdata[15:0] i ip slave bus write date line ips_byte_15_8 i ip slave bus byte enable signal for bits 15 to 8 ips_byte_7_0 i ip slave bus byte enable signal for bits 7 to 0 ipt_reset i ip scan reset signal used to work in place of generated resets in scan mode (active low) ipt_se_async i ip scan signal for bypassing generated resets and making latches transparent in scan mode ipt_scan_mode i ip scan mode signal ipt_se_gatedclk i ip scan mode clock gating signal wdog_rst o watchdog timer reset (active low) resp_sel i indicates if the error response needs to be generated on access on unimplemented registers or not. refer to section 34.5.4, ?generation of transfer error on the ip bus ? for details. watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-4 freescale semiconductor 34.3 memory map and register definitions the wdog module has three, user-accessible, 16-bit regi sters used to configure, operate, and monitor the state of the watchdog timer. section 34.4, ?register descriptions ? provides the detailed descriptions for all of the wdog registers. 34.3.1 watchdog timer memory map table 34-4 shows the wdog memory map. 34.3.2 register summary figure 34-2 shows the key to the register fields, and table 34-5 shows the register figure conventions. table 34-4. wdog memory map address register access reset value section/page 0x1000_2000 (wcr) watchdog control register r/w 0x0030 34.4.1/34-5 0x1000_2002 (wsr) watchdog status register r/w 0x0010 34.4.2/34-6 0x1000_2004 (wrsr) watchdog reset status register r 0x00? ? 34.5.6/34-10 figure 34-2. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 34-5. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-5 table 34-6 shows the wdog register summary. 34.4 register descriptions 34.4.1 watchdog control register (wcr) the watchdog control register (wcr) is a 16-bit read /write register. it controls the wdog operation. all bits except for bits[5:4] are cleared during reset. bits[5:4] are set to 1 during reset. figure 34-3 shows the register; table 34-7 provides its field descriptions. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 34-6. wdog register summary name 1514131211109876543210 0x1000_2000 (wcr) r wt 0 woe wda srs wre wde wdb g wdzs t w 0x1000_2002 (wsr) r wsr w 0x1000_2004 (wrsr) r0000000000jrstpwrext cmo n tout sftw w 0x1000_2000 (wcr) access: user read/write 1514131211109876543210 r wt 00 wda srs wre wde wdb g wdz st w reset0000000000110000 figure 34-3. watchdog control register table 34-7. wcr register descriptions field description 15?8 wt watchdog timeout field. this 8-bit field contains the time-out value that is loaded into the watchdog counter after the service routine has been performed. after reset, wt[7:0] must have a value written to it before enabling the watchdog. 7?6 reserved 5 wda wdog assertion. controls the software assertion of the wdog signal. 0 assert wdog output. 1 no effect on system. table 34-5. register figure conventions (continued) convention description watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-6 freescale semiconductor 34.4.2 watchdog service register (wsr) when enabled, the wdog requires that a service seque nce be written to the watchdog service register (wsr). figure 34-4 shows the register; table 34-8 provides its field descriptions. 4 srs software reset signal. controls the software assertion of the wdog-generated reset signal. this bit automatically resets to ?1? after it has been asserted to ?0?. note: this bit does not generate the software reset to the module. the ipg_clk must be on to write to this bit. 0 assert system reset signal 1 no effect on the system 3 wre wdog /wdog_rst enable. determines if the watchdog generates a reset signal or a wdog signal upon a watchdog timeout. this is a write once-only bit. 0 generate a reset signal 1 generate a wdog signal 2 wde watchdog enable. enables or disables the wdog module. software can only write ?1? in this bit. it is not possible to reset this bit by a software write, once the bit is set. note: this bit can be set/reset as per the ip writes in debug mode (exception). 0 disable the watchdog 1 enable the watchdog 1 wdbg watchdog debug enable. determines the operation of the wdog module during debug mode. this bit is write once-only. 0 continue wdog timer operation 1 suspend the watchdog timer 0 wdzst watchdog low power. determines the operation of the wdog module during low-power modes. this bit is write once-only. note: the wdog module can continue/suspend the timer operation in the low-power modes (wait and stop). 0 continue timer operation 1 suspend the watchdog timer 0x1000_2002 (wsr) access: user read/write 1514131211109876543210 r wsr w reset0000000000000000 figure 34-4. watchdog service register (wsr) table 34-7. wcr register descriptions (continued) field description watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-7 34.4.2.1 watchdog reset status register (wrsr) the wrsr is a read-only register that records the s ource of the output reset assertion. it is not cleared by a hard reset. it records the source of the output re set assertion. therefore, only one bit in the wrsr will always be asserted high. the register will alwa ys indicate the source of the last reset. a reset can be generated by the following sources, as listed in priority from highest to lowest: ? power-on reset ? external reset ? watchdog time-out ? software reset figure 34-5 shows the register; table 34-8 provides its field descriptions. note do not write to this register. attempting to write to the wrsr register generates a bus error . table 34-8. watchdog service register description field description 15?0 wsr watchdog service register. this 15-bit field contains the watchdog service sequence. both writes must occur in the order listed prior to the time-out, but any number of instructions can be executed between the two writes. the service sequence must be performed as follows: write 0x 5555 to the watchdog service register (wsr) write 0x aaaa to the watchdog service register (wsr) 0x1000_2004 (wrsr) access: user read-only 1514131211109876543210 r 00000000000pwrext0toutsftw w reset0000000000000000 figure 34-5. watchdog reset status register (wrsr) table 34-9. watchdog reset status register field descriptions field description 15?5 reserved?these bits are read as 0 4 pwr power-on reset. indicates whether the reset was a result of a power-on reset. 0 reset is not a result of a power-on reset 1 reset is a result of a power-on reset 3 ext external reset. indicates whether the reset was a result of an external reset. 0 reset is not a result of an external reset 1 reset is a result of an external reset 2 reserved?this bit reads 0 watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-8 freescale semiconductor 34.5 functional description this section describes the timing information for the wdog module. 34.5.1 timing specifications the wdog provides time-out periods from 0.5 seconds up to 128 seconds with a time resolution of 0.5 seconds. it uses the ipg_clk_32k clock (32.768 khz fre quency clock) as an input to prescalers. the prescalers divide the clock by a fixed value of 16384 (divide by 4 and divide by 4096) to achieve a resolution of 0.5 seconds at a frequency of 2 hz. the output of the prescaler circuitry is connected to the input of an 8-bit counter to obtain a range of 0.5 to 128 seconds. the user can determine the time-out period by writing a time-out value to the wdog time-out field (wt[7:0]) in the wdog control register (wcr). 34.5.2 watchdog during reset a system reset resets all registers (except the wrsr) to their initial default values, and places the counter in the idle state until the wdog is enabled. the watchdog reset status register (wrsr) contains the source of the reset event and is not reset by a system reset. 34.5.3 watchdog after reset the following subsections define the wdog timer state after reset. 34.5.3.1 initial load the watchdog control register (wcr) field wt[7:0] mu st have a time-out value written to it before the watchdog can be enabled. the wdog is enabled by se tting the watchdog enable (wde) bit in the wcr. the time-out value is loaded into the counter afte r the service sequence is written to the watchdog service register (wsr), or after the wdog has been enabled. the service sequence is described in section 34.5.3.3, ?reloading the counter .? (the counter state machine is shown in figure 34-6 .) 34.5.3.2 timer countdown the counter is activated and begins to count down from its initial programmed value after the wdog is enabled. if any system errors occur that prevent the software from servicing the watchdog service register (wsr), the timer will time-out when the counter reaches zero. if the wsr is serviced prior to the counter 1 tout time-out. indicates whether the reset was a result of wdog time-out. 0 reset is not the result of wdog time-out 1 reset is the result of a wdog time-out 0 sftw software reset. indicates whether the reset was a result of a software reset. 0 reset is not a result of a software reset 1 reset is a result of a software reset table 34-9. watchdog reset status regi ster field descriptions (continued) field description watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-9 reaching zero, the wdog reloads its counter to the time -out value indicated by bits wt[7:0] of the wcr, and it re-starts the countdown. a system reset will reset the counter and place it in the idle state at any time during the countdown. (the counter state machine is shown in figure 34-6 .) 34.5.3.3 reloading the counter the proper service sequence to write a time-out va lue to the counter begins by writing 0x 5555 followed by 0x aaaa to the wsr. to reload the counter, the writes must take place within the time-out value indicated by bits wt[7:0] of the wcr. any number of instructions can be executed between the two writes. this service sequence is also used to activate the counter during the initial load. see section 34.5.3.1, ?initial load .? if the wsr is not loaded with 0x 5555 prior to writing 0x aaaa to the wsr, the counter is not reloaded. if any value other than 0x aaaa is written to the wsr after 0x 5555, the counter is not reloaded. 34.5.3.4 time-out if the counter reaches zero, the wdog outputs either a system reset or the wdog signal, depending on the state of the wre bit in the wcr. a ?0? written to the wre bit configures the wdog to generate a system reset. a ?1? causes the wdog to generate the wdog signal. (the counter state machine is shown in figure 34-6 .) 34.5.4 generation of transfer error on the ip bus the wdog module asserts a transfer error signal (ips_xfr_error) on the ip bus in the following cases: ? receiving an ip access to an address that is not implemented ? a write access to the wrsr register that is a read-only register an error on an unimplemented address is generated only if the input pin resp_sel is low. otherwise, an error is only asserted on a write access to the wrsr register (a read-only register). 34.5.5 low-power and debug modes the wdog module can either continue or suspend the timer operation during low-power modes (wait and stop) and debug mode. 34.5.5.1 low-power mode (wait, stop) while in low-power mode, the wdog timer can be configured for continual operation or its operation can be suspended. if the wdog low-power enable (wdzst) bit in the wcr is set to ?0?, the wdog continues to operate using the ipg_clk_32k clock ( 32.768 khz frequency clock) as its source. if the low-power enable (wdzst) bit is set to ?1?, then the wdog operation is suspended during low-power mode. upon exiting low-power mode, the wdog returns to the operational mode it was in prior to entering low-power mode. watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-10 freescale semiconductor 34.5.5.2 debug mode the wdog timer can be configured for continual operation, or the operation can be suspended during debug mode. if the wdog debug enable (wdbg) bit is set to ?1? in the watchdog control register (wcr), the wdog module operation is suspended in de bug mode. at this point, the counter is stopped, but register read and write accesses continue to function normally. also, while in debug mode, the wde bit can be enabled-disabled directly. note if the wde bit is cleared while in debug mode, it will remain cleared upon exiting debug mode. if the wde bit is not cleared while in debug mode, the wdog count will continue from its value before debug mode was entered. 34.5.6 watchdog reset control the wdog generated reset signal wdog_rst can be asserted by a software write to the software reset signal (srs) bit of the wcr. it can also be generated by the following event: ? wdog time-out the wdog_rst is generated for 0.5 seconds for a time-out, but is deasserted early if a system reset is detected. in case of a software reset, the wdog_rst is asserted after three clocks of resetting the srs bit and remains asserted for three ipg clocks (ip global functiona l clock). if a system reset is asserted in between, it deasserts before three ipg clocks have elapsed. . the watchdog-generated reset signal wdog_rst is an output to the (ccm) for system reset generation. note the ccm of the ic generates the system reset signal on assertion of wdog_rst . 34.5.7 wdog operation wdog can be asserted through software writes to the wdog assertion (wda) bit of the wcr. it can also be generated as a result of a wdog time-out. if asserted by a software write to the wda bit, it remains asserted as long as the wda bit is ?0?. the counter timeout asserts it for 0.5 seconds. both a syst em reset and a power-on reset can deassert it in between. wdog is applied to the wdog pin . after reset, the woe bit in the wcr register controls the direction of this pin. watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-11 34.6 initialization/app lication information 34.6.1 state machine the watchdog state machine is shown in figure 34-6 . watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-12 freescale semiconductor idle resets negated ? timeout value? watchdog enabled start counter decrement counter low power suspend counter suspended stop or doze exited? debug mode? counter suspended debug exited? wsr serviced? reload counter count = 0? assert timeout indication (continued) (from ?system reset asserted??) no yes yes no no yes yes yes yes no yes yes yes no yes no yes no yes no ? watchdog enabled ? watchdog ? suspend watchdog ? no no no no mode? watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 34-13 figure 34-6. counter state machine assert system reset asserted ? assert signal assert reset (from ?assert timeout indication?) (to ?idle? state) yes no yes no note: a system reset will force the state machine to ?idle? at any time during countdown. wdog ? wdog clock reset module (crm) watchdog timer (wdog) MCIMX27 multimedia applications processor reference manual, rev. 0.2 34-14 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 6: system control peripherals introduction the transfer of data between modules are contro lled by the following system control peripherals: chapter 35, ?ahb-lite ip interface (aipi) module ,? on page 35-1 chapter 36, ?multi-layer ahb crossbar switch (max) ,? on page 36-1 chapter 37, ?direct memory access controller (dmac) ,? on page 37-1 ahb-lite to ips (aipi) the ahb-lite to ips (aipi) interfaces?aipi1 and aipi2?facilitate proper communication between the arm-11 platform and devices that use ahb-lite with peripherals that are ips-compliant. each aipi in this device handles a separate mcu peripheral bus: aipi1 interfaces to the mcu peripheral bus 1, which supports 16 on-platform peripherals; aipi2 interfaces to the mcu peripheral bus 2, which also supports 32 on-platform peripherals). the aipi provides all of the necessary bus structure and handshaking signals to allow high-speed communication between these periphe ral devices and the internal bus structure of the arm-11. multi-layer ahb crossbar switch (max) the purpose of the max is to concurrently support up to five simultaneous connections between master ports and slave ports. the max supports a 32-bit addres s bus width, and a 32-bit data bus width at all master and slave ports. direct memory access controller (dmac) the direct memory access controller (dmac) of i.mx27 device provides 16 dma channels supporting linear memory, 2d memory and fifo transfers to provide support for a wide variety of dma operations. MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 35-1 chapter 35 ahb-lite ip interface (aipi) module this chapter provides an overview of the ahb-lite to ip bus interface (aipi) module. the aipi acts as an interface between the advanced arm high-perform ance bus ?lite? (ahb-lite) and lower bandwidth peripherals conforming to the freescale ip bus specification . there are two aipi modules in i.mx27?aipi1 and aipi2. the following list summarizes the key features of the aipi: ? all peripheral read transactions require a minimum of 2 system clocks (r-ahb side) and all write transactions require a minimum of 3 system clocks (r-ahb side). ? the aipi supports 8-bit, 16-bit and 32-bit ip bus peripherals. (byte, half word and word reads and write are supported to each.) ? the aipi supports multi-cycle accesses (16-b it operations to 8-bit peripherals and 32-bit operations to 16-bit and 8-bit peripherals). ? the aipi supports 31 external ip bus periphera ls each with a 4 kbyte memory map (a slot). table 35-1. ahb-lite to ip bus v2.0 interface operation (little endian) transfer size haddr ip bus size ips_addr active bus section (r-ahb to ip bus) [1] [0] [1] [0] r-ahb[31:24] r-ahb[23:16] r-ahb[15:8] r-ahb[7:0] byte 0 0 8 bit 0 0 ? ? ? ips_data[7:0] 0 1 0 1 ? ? ips_data[7:0] ? 1 0 1 0 ? ips_data[7:0] ? ? 1 1 1 1 ips_data[7:0] ? ? ? 0 0 16 bit 0 x ? ? ? ips_data[7:0] 0 1 ? ? ips_data[15:8] ? 1 0 1 x ? ips_data[7:0] ? ? 1 1 ips_data[15:8] ? ? ? 0 0 32 bit x x ? ? ? ips_data[7:0] 0 1 ? ? ips_data[15:8] ? 1 0 x x ? ips_data[23:16] ? ? 1 1 ips_data[31:24] ? ? ? ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 35-2 freescale semiconductor 35.1 programming model there are three registers that reside inside the aipi . these registers correspond to the first slot (4 kbyte memory region) of each of the 2 aipis in i.mx21 at 0x1000_0000 and 0x1002_0000, respectively. all three registers are 32-bit registers and can only be accessed in supervisor mode. additionally, these registers can only be read from or written to by a 32-bit access. two system clocks are required for read accesses and three system clocks are required for write accesses to the aipi registers. caution writing to reserved register locations within the 4 kbyte memory map of the aipi register space (other than the three aipi registers) will result in unknown behavior and an abort exception. access to reserved or unoccupied locations in the aipi space will result in an abort exception. half word 0 na 8 bit 0 0 ? ? ? ips_data[7:0] 1 ? ? ips_data[7:0] ? 1 1 0 ? ips_data[7:0] ? ? 1 ips_data[7:0] ? ? ? 0 16 bit 0 x ? ? ips_data[15:8] ips_data[7:0] 1 1 x ips_data[15:8] ips_data[7:0] ? ? 0 32 bit x x ? ? ips_data[15:8] ips_data[7:0] 1 x x ips_data[31:24] ips_data[23:16] ? ? word na na 8 bit 0 0 ? ? ? ips_data[7:0] 1 ? ? ips_data[7:0] ? 1 0 ? ips_data[7:0] ? ? 1 ips_data[7:0] ? ? ? 16 bit 0 x ? ? ips_data[15:8] ips_data[7:0] 1 x ips_data[15:8] ips_data[7:0] ? ? 32 bit x x ips_data[31:24] ips_data[23:16] ips_data[15:8] ips_data[7:0] table 35-1. ahb-lite to ip bus v2.0 interf ace operation (little endian) (continued) transfer size haddr ip bus size ips_addr active bus section (r-ahb to ip bus) [1] [0] [1] [0] r-ahb[31:24] r-ahb[23:16] r-ahb[15:8] r-ahb[7:0] ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 35-3 35.1.1 peripheral size registers[1:0] these registers are used to tell the aipi what size of ip bus peripheral is in each ip bus peripheral location. peripheral locations that are not occupied should ha ve their corresponding bits in the peripheral size registers (psrs) programmed to 1 in each register. the least significant bit in the psrs is a read-only b it as it governs the aipi registers themselves. they are set and cleared appropriately to indicate the registers are 32-bit. the psrs work together to indicate the size of the ip bus peripheral occupying the corresponding location, or to indicate there is no ip bus peripheral occupying the corresponding location. table 35-2 shows how to program the psr registers based on the size or availability of an ip bus peripheral. psr0 peripheral size register 0 addr 0x1000_0000 0x1002_0000 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 psr1 peripheral size register 1 addr 0x1000_0004 0x1002_0004 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 table 35-2. psr 1?0 data bus size encoding psr 1?0 ip bus peripheral size [x] 00 8-bit 01 16-bit 10 32-bit 11 unoccupied ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 35-4 freescale semiconductor 35.1.2 peripheral access register the peripheral access register (par) tells the aipi whether the ip bus peripheral corresponding to the bit location in this register may be accessed in user mode. if the peripheral may be accessed in supervisor mode only and a user mode access is attempted, an abort is generated and no ip bus activity occurs. the least significant bit in the par is a read-only bit as it governs the aipi registers themselves. it is set to indicate supervisor access only. 35.2 aipi1 and aipi2 peripher al widths and psr setting table 35-5 shows the data bus widths of the peripherals on the aipi1 and the aipi2 interfaces. system software should make use of information in the column, ?data bus width? to configure the psr registers, accordingly. table 35-3 and table 35-4 show psr settings for aipi1 and aipi2. table 35-5 shows the peripheral sizes for the occupied, re served and unoccupied locations. all reserved locations must be programmed as 32-bit locations. pa r peripheral access register 1 1 a ?1? indicates the corresponding peripheral is a supervisor access only peripheral. a ?0? indicates the decision is left up to the peripheral (the aipi allows user accesses). addr 0x1000_0008 0x1002_0008 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ty p e rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 table 35-3. aipi1 psr setting psr setting psr[1] 0xfffb_fcfb psr[0] 0x0004_0304 table 35-4. aipi2 psr setting psr setting psr[1] 0xffff_ffff psr[0] 0x3ffc_0000 ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 35-5 table 35-5. i.mx21 aipi peripheral access sizes and ip access types location peripheral psr[1] psr[0] data bus width 16-bit 8-bit read write read write aipi1 0 aipi1 control 1 0 32-bit ? ? ? ? 1 dma 1 0 32-bit y y y y 2 wdog 0 1 16-bit ? y y 3 gpt1 1 0 32-bit n n n n 4 gpt2 1 0 32-bit n n n n 5 gpt3 1 0 32-bit n n n n 6 pwm 1 0 32-bit n n n n 7 rtc 1 0 32-bit y y y y 8 kpp 0 1 16-bit ? n n 9 1-wire 0 1 16-bit ? n n 10 uart1 1 0 32-bit n y n y 11 uart2 1 0 32-bit n y n y 12 uart3 1 0 32-bit n y n y 13 uart4 1 0 32-bit n y n y 14 cspi1 1 0 32-bit n n n n 15 cspi2 1 0 32-bit n n n n 16 ssi1 1 0 32-bit n n n n 17 ssi2 1 0 32-bit n n n n 18 i2c 0 1 16-bit ? y y 19 sdhc1 1 0 32-bit n n n n 20 sdhc2 1 0 32-bit n n n n 21 gpio 1 0 32-bit n n n n 22 audmux 1 0 32-bit n n n n 23 cspi3 1 0 32-bit n n n n 23-31 reserved 1 0 32-bit n n n n aipi2 0 aipi2 1 0 32-bit ? 1 lcdc 1 0 32-bit n n n n 2 slcdc 1 0 32-bit n n n n 3 reserved 1 0 32-bit n n n n ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 35-6 freescale semiconductor 35.3 interface timing this section describes aipi interface timing characteristics. 35.3.1 read cycles two clock read accesses are possible with the aipi when the requested access size is equal to or smaller than the size of the targeted ip bus peripheral. if the requested access size is larger than that of the targeted ip bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a minimum of three clocks are required to complete the access. 35.3.2 write cycles three clock write accesses are possible with the aipi wh en the requested access size is equal to or smaller than the size of the targeted ip bus peripheral. if the requested access size is larger than that of the targeted ip bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a mi nimum of four clocks are required to complete the access. 35.3.3 aborted cycles the aipi follows a standard procedure when a cycle is aborted and the abort is initiated by the aipi itself or the targeted ip bus peripheral. the aipi either fa ils to initiate or immediately terminates any ip bus activity that is ongoing. there are several conditions that can cause the aipi to abort the current operation and report an error. the first is the case in which the targeted ip bus peripheral asserts its internal error signal. in this case the aipi immediately terminates access to the targeted ip bus peripheral. whether the current ip bus access is a multi-cycle access or a single cycle access has no bear ing on the behavior of the aipi. the aipi responds identically in both cases. 4 usb otg 1 0 32-bit n n y y 5 usb otg 1 0 32-bit n n n n 6 emma 1 0 32-bit n n n n 7 crm 1 0 32-bit y y y y 8 firi 1 0 32-bit y y y y 9 reserved ? ? ? ? ? ? ? 10-17 reserved 1 0 32-bit n n n n 18-29 unoccupied 1 1 ? n n n n table 35-5. i.mx21 aipi peripheral access sizes and ip access types (continued) location peripheral psr[1] psr[0] data bus width 16-bit 8-bit read write read write ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 35-7 the second case that can cause an error response to th e ahb-lite is when a user-mode access is attempted to an ip bus peripheral whose corresponding par bit indi cates it is a supervisor-only peripheral. in this case the aipi does not initiate any ip bus activity but instead responds immediately by following the abort procedure described above. the third case that can cause an error response to the ahb-lite is when an access is attempted to a location at which the psrs indicate there is no ip bus peripheral. in this case the aipi does not initiate any ip bus activity but instead responds immediately by following the abort procedure described above. ahb-lite ip interface (aipi) module MCIMX27 multimedia applications processor reference manual, rev. 0.2 35-8 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-1 chapter 36 multi-layer ahb crossbar switch (max) this chapter provides an overview of multi-layer ahb crossbar switch (max). the purpose of max is to concurrently support up to three simultaneous connections between 6 master ports and 3 slave ports. 36.1 features the max module has the ability to gain control of all the slave ports and prevent any masters from making accesses to the slave ports. this feature is useful when the user wishes to turn off the clocks to the system and needs to ensure that no bus activity will be inte rrupted. max can put each slave port into a low power park mode so that slave port will not dissipate any power transitioning address, control or data signals when not being actively accessed by a master port. each slave port can also support multiple master prio rity schemes. each slave port has a hardware input which selects the master priority sc heme so the user can dynamically ch ange master priority levels on a slave port by slave port basis. the max allows concurrent transactions to occur from any master port to any slave port. it is possible for three master ports and all slave ports to be in use at the same time as a result of independent master requests. if a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownershi p of the slave port. all other masters requesting that slave port will stalled until the higher priority master completes its transactions. 36.2 overview the max module routes bus transactions initiated on the master ports to the appropriate slave ports. there is no provision included to route trans actions initiated on the slave ports to other slave ports or to master ports. simply put, the slave ports do not support the bus request/bus grant protocol, the max assumes it is the sole master of each slave port. since the max does not support the bus request/bus grant protocol, if multiple masters are to be connected to a single master port an external arbiter will n eed to be used.,each master and slave port is fully ahb-lite + amba v6 extensions compliant. the por ts are not fully ahb compliant because the max does not support splits or retrys. note i.mx27 arm9 platform implements a 6 master by 3 slave configuration. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-2 freescale semiconductor figure 36-1. max block diagram 36.3 general operation when a master makes an access to the max, access will be immediately taken by the max. if the targeted slave port of the access is available then the access wi ll be immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the max. if the targeted slave port of the master 0 write data slave port 0 mstr port(s) request mstr port(s) addr mstr port(s) cntrl mstr port(s) wdata hready to mstr(s) hresp0 to mstr(s) slv hready slv hresp0 slave 0 read data slv addr slv cntrl slv wdata ip cntrl ip wdata ip rdata ip term halt request halt grant slave port 2 mstr port(s) request mstr port(s) addr mstr port(s) cntrl mstr port(s) wdata hready to mstr(s) hresp0 to mstr(s) slv hready slv hresp0 slave 2 read data slv addr slv cntrl slv wdata ip cntrl ip wdata ip rdata ip term halt request halt grant master port 5 mstr addr mstr control master 5 write data ip rdata mstr port request mstr port addr mstr read data mstr hready mstr hresp0 slv port hready(s) slv port hresp0(s) slv port hrdata(s) general purpose logic ip cntrl ip wdata ip rdata ip term ip term(s) ip wdata(s) ip rdata(s) slv ip cntrl max halt request max_halted halt grant(s) mstr port cntrl ip term ip cntrl ip wdata master port 0 mstr addr mstr control ip rdata mstr port request mstr port addr mstr read data mstr hready mstr hresp0 slv port hready(s) slv port hresp0(s) slv port hrdata(s) mstr port cntrl ip term ip cntrl ip wdata multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-3 access is busy or parked on a different master port the re questing master will simply see wait states inserted ( hready held negated) until the targeted slave port can service the master?s request. latency in servicing the request will depend on each master?s priority level and the responding peri pheral?s access time. since max appears to be just another slave to the mast er device, master device will have no knowledge of whether or not it actually owns the slave port it is ta rgeting. when the master does not have control of the slave port it is targeting, it will simply be wait stated. a master will be given control of the targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newl y targeted slave port. this prevents deadlock from occurring when a master has an outstanding request to one slave port that has a long response time, has a pending access to a different slave port, and a lower prio rity master is also maki ng a request to the same slave port as the pending access of the higher priority master. once the master has control of the slave port it is targeting the master will remain in control of that slave port until it gives up the slave port by running an idle cycle or by leaving that slave port for its next access. the master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a locked or fixed length burst transfer it will retain control of the slave port until that transfer is completed. based on the aulb bit in the mgpcr (master general purpose control register) the master will either retain control of the slave port when doing undefined length incrementing burst transfers or will lose the bus to a higher priority master. the max terminates all master idle transfers (as oppos ed to allowing the termination to come from one of the slave busses). additionally, when no master is requesting access to a slave port, max will drive idle transfers onto the slave bus, even though a default master may be granted access to the slave port. when max is controlling the slave bus (that is, during low power park or halt mode), hmaster field will indicate 4?b0000. when a slave bus is being idled by the max, it can park the slave port on the master port indicated by the park bits in the sgpcr or asgpcr. this can be done in an attempt to save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrat e to gain control of the slave port. the slave port can also be put into low pow er park mode in attempt to save power. 36.4 memory map and register definition this section provides the register progr amming information for the max registers. 36.4.1 register summary there are four registers that reside in each slave por t of the max and one register that resides in each master port of the max. these registers are ip bus compliant registers. read and write transfers both require two ip bus clock cycles. the registers can only be read from and written to in privileged mode. additionally, these registers can only be read from or written to by 32-bit accesses. the registers are fully decoded and an error response is returned if an unimplemented location is accessed within the max. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-4 freescale semiconductor the slave registers also feature a bit, which when writ ten with a 1, will make it readable, and future write attempts will have no effect on the registers, thus resulting in an error response. memory map for the max program-visible registers is shown in table 36-1 . 36.4.2 memory map table 36-1 shows the max memory map. 36.4.3 register summary figure 36-2 shows the key to the register fields, and table 36-2 shows the register figure conventions. table 36-1. max memory map address register access reset value section/page 0x1003_f000 (mpr0) 0x1003_f100 (mpr1) 0x1003_f200 (mpr2) master priority register for slave port 0 master priority register for slave port 1 master priority register for slave port 2 r/w 0x0054_3210 36.4.5/36-6 0x1003_f004 (ampr0) 0x1003_f104 (ampr1) 0x1003_f204 (ampr2) alternate master priority register for slave port 0 alternate master priority register for slave port 1 alternate master priority register for slave port 2 r/w 0x0000_0000 36.4.6/36-7 0x1003_f010 (sgpcr0) 0x1003_f110 (sgpcr1) 0x1003_f210 (sgpcr2) general purpose control register for slave port 0 general purpose control register for slave port 1 general purpose control register for slave port 2 r/w 0x0000_0000 36.4.7/36-9 0x1003_f014 (asgpcr0) 0x1003_f114 (asgpcr1) 0x1003_f214 (asgpcr2) alternate sgpcr for slave port 0 alternate sgpcr for slave port 1 alternate sgpcr for slave port 2 r/w 0x0000_0000 36.4.8/36-11 0x1003_f800 (mgpcr0) ? 0x1003_fd00 (mgpcr5) general purpose control register for master port 0 ? general purpose control register for master port 5 r/w 0x0054_3210 36.4.5/36-6 figure 36-2. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 36-2. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-5 w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 36-3. max detailed register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1003_f000 (mpr0) 0x1003_f100 (mpr1) 0x1003_f200 (mpr2) r000000000 mstr_5 0 mstr_4 w r 0 mstr_3 0 mstr_2 0 mstr_1 0 mstr_0 w 0x1003_f004 (ampr0) 0x1003_f104 (ampr1) 0x1003_f204 (ampr2) r000000000 mstr_5 0 mstr_4 w r 0 mstr_3 0 mstr_2 0 mstr_1 0 mstr_0 w 0x1003_f010 (sgpcr0) 0x1003_f110 (sgpcr1) 0x1003_f210 (sgpcr2) rrohlp00000000000000 w r000000 arb 00 pctl 0 park w 0x1003_f014 (asgpcr0) 0x1003_f114 (asgpcr1) 0x1003_f214 (asgpcr2) r0hlp00000000000000 w r000000 arb 00 pctl 0 park w 0x1003_f800 (mgpcr0) ? 0x1003_fd00 (mgpcr5) r0000000000000000 w r0000000000000 aulb w table 36-2. register figure conventions (continued) convention description multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-6 freescale semiconductor 36.4.4 max register descriptions this section contains the detailed register descriptions for the max registers. 36.4.5 master priority registers (mpr0?mpr2) the master priority register (mpr) sets the prior ity of each master port on a per slave port basis and resides in each slave port. the master priority register can only be accessed in supervisor mode with 32-bit accesses. once the ro (read only) bit has been set in the slave general pur pose control register the master priority register can only be read from, attempts to write to it will ha ve no effect on the mpr and result in an error response. additionally, no two available master ports may be programmed with the same priority level. attempts to program two or more available masters with the same priority level will result in an error response and the mpr will not be updated. 0x1003_f000 (mpr0) 0x1003_f100 (mpr1) 0x1003_f200 (mpr2) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 000000000mstr_50mstr_4 w reset0000000001010100 1514131211109876543210 r 0 mstr_3 0 mstr_2 0 mstr_1 0 mstr_0 w reset0011001000010000 table 36-4. master priority register (mpr0?mpr2) table 36-5. master priority register field descriptions field description 31?23 reserved. they are read as zero and should be written with zero for upward compatibility. 22?20 mstr_5 master 5 priority. these bits set the arbitration priority for master port 5 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 19 reserved. they are read as zero and should be written with zero for upward compatibility. 18?16 mstr_4 master 4 priority . these bits set the arbitration priority for master port 4 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 15 reserved . they are read as zero and should be written with zero for upward compatibility. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-7 36.4.6 alternate master priority register for slave port 0?2 (ampr0?2) the alternate master priority register ampr sets alternate priorities of each master port on a per slave port basis. ampr has identical function like mpr. ampr purpose is to allow the user to set up an alternate set of priorities in the event they want to do some sort of context switching. a hardware input to the max controls (on a slave port by slave port basis) whether or not the slave port uses mpr or ampr. refer table 36-5 for ampr bit descriptions as they are iden tical to mpr. ampr can only be accessed in privileged mode with 32-bit accesses. once the ro (r ead only) bit is set in the general purpose control register, ampr can only be read from, attempts to write to it will result in an error response. additionally, no two available master ports may be programmed with the same priority level. attempts to program two or more available masters with the same priority level will result in an error response and the ampr will not be updated. 14?12 mstr_3 master 3 priority. these bits set the arbitration priority for master port 3 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 11 reserved . they are read as zero and should be written with zero for upward compatibility. 10?8 mstr_2 master 2 priority. these bits set the arbitration priority for master port 2 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 7 reserved . they are read as zero and should be written with zero for upward compatibility. 6?4 mstr_1 master 1 priority. these bits set the arbitration priority for master port 1 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 3 reserved . they are read as zero and should be written with zero for upward compatibility. 2?0 mstr_0 master 0 priority. these bits set the arbitration priority for master port 0 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. table 36-5. master priority register field descriptions (continued) field description multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-8 freescale semiconductor 0x1003_f004 (ampr0) 0x1003_f104 (ampr1) 0x1003_f204 (ampr2) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 000000000mstr_50mstr_4 w reset0000000001010100 1514131211109876543210 r 0 mstr_3 0 mstr_2 0 mstr_1 0 mstr_0 w reset0011001000010000 table 36-6. alternate priority register (mpr0?mpr2) table 36-7. alternate priority register field descriptions field description 31?23 reserved. they are read as zero and should be written with zero for upward compatibility. 22?20 mstr_5 master 5 priority. these bits set the arbitration priority for master port 5 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 19 reserved. they are read as zero and should be written with zero for upward compatibility. 18?16 mstr_4 master 4 priority . these bits set the arbitration priority for master port 4 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 15 reserved . they are read as zero and should be written with zero for upward compatibility. 14?12 mstr_3 master 3 priority. these bits set the arbitration priority for master port 3 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 11 reserved . they are read as zero and should be written with zero for upward compatibility. 10?8 mstr_2 master 2 priority. these bits set the arbitration priority for master port 2 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. 7 reserved . they are read as zero and should be written with zero for upward compatibility. 6?4 mstr_1 master 1 priority. these bits set the arbitration priority for master port 1 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-9 36.4.7 general purpose control register for slave port 0?2 (sgpcr0?2) the slave general purpose control register (sgpcr) controls severa l features of each slave port. the read only (ro) bit will prevent any registers a ssociated with this slave port from being written to once set. this bit may be written with 0 as many times as the user desires, but once it is written to a 1 only a reset condition will allow it to be written again. the halt low priority (hlp) bit will set the priority of the max_halt_request input to the lowest possible priority for initial arbitration of the slave ports. by default it is the highest priority. note setting this bit will not effect the max_halt_request from attaining highest priority once it has control of the slave ports. the pctl bits determine how the slave port will park when no master is actively making a request. the available options are to park on the master defined by the park bits, park on the last master to use the slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive states when no master is requesting an access. the low power park feature can result in an overall power savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in use because it will not be parked on any master. the park bits determine which master the slave will park on when no master is making an active request and the max_halt_request input is negated. caution only select master ports that are actually present in the i.mx27. if you program the park bits to a master not present in the i.mx27 undefined behavior will result. see figure 36-3 for an illustration of valid bits in the sgpcr, and table 36-8 for its field descriptions. 3 reserved . they are read as zero and should be written with zero for upward compatibility. 2?0 mstr_0 master 0 priority. these bits set the arbitration priority for master port 0 on the associated slave port. these bits are initialized by hardware reset. 000 this master has the highest priority when accessing the slave port. 111 this master has the lowest priority when accessing the slave port. table 36-7. alternate priority register field descriptions (continued) field description multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-10 freescale semiconductor 0x1003_f010 (sgpcr0) 0x1003_f110 (sgpcr1) 0x1003_f210 (sgpcr2) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ro 1 1 once this bit is written to a 1, then only hardware reset will return it to a 0. hlp 0000000 0000000 w reset0000000000000000 1514131211109876543210 r0 0 0 0 0 0 arb 00 pctl 0 pa r k w reset0000000000000000 figure 36-3. slave general purpose control register (sgpcr0-2) table 36-8. slave general purpose control register field descriptions field description 31 ro read only. this bit is used to force all of a slave port?s registers to be read only. once written to 1 it can only be cleared by hardware reset. this bit is initialized by hardware reset. 0 all of this slave port?s registers can be written. 1 all of this slave port?s registers are read only and cannot be written (attempted writes have no effect and result in an error response). 30 hlp halt low priority . this bit is used to set the initial arbitration priority of the max_halt_request input. this bit is initialized by hardware reset. 0 the max_halt_request input has the highest priority for arbitration on this slave port 1 the max_halt_request input has the lowest initial priority for arbitration on this slave port. 29?10 reserved . they read as zero and should be written with zero for upward compatibility. 9?8 arb arbitration mode. these bits are used to select the arbitration policy for the slave port. these bits are initialized by hardware reset. 00 fixed priority. 01 round robin (rotating) priority 10 reserved 11 reserved 7?6 reserved. they read as zero and should be written with zero for upward compatibility. 5?4 pctl parking control.these bits determine the parking control used by this slave port. these bits are initialized by hardware reset. 00 when no master is making a request the arbiter will park the slave port on the master port defined by the park bit field. 01 when no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 when no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 reserved multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-11 note: reserved bits are for future expansion. it is read as zero and should be written with zero for upward compatibility 36.4.8 alternate sgpcr for slave port 0?2 (asgpcr0?2) the asgpcr has identical function as the sgpcr with the notable exception that it lacks the ro (read only) bit contained in the sgpcr. asgpcr purpose is same as ampr, to allow the user to set up an alternate set of general control fields in the even t they want to do some sort of context switching. a hardware input to the max controls (on a slave port by slave port basis) whether or not the slave port uses the sgpcr or asgpcr. refer table 36-8 for descriptions of bit fields in asgpcr as they are identical except for the ro bit. asgpcr can only be accessed in privileged mode with 32-bit accesses. once the ro (read only) bit has been set in the sgpcr the asgpcr can only be read from, attempts to write to it will have no effect on the asgpcr and result in an error response. note asgpcr does not contain a ro (read only) bit. ro bit in sgpcr has control over the asgpcr?s ability to be written. 3 reserved . they read as zero and should be written with zero for upward compatibility. 2?0 pa r k park. these bits are used to determine which master port this slave port parks on when no masters are actively making requests and the pctl bits are set to 00. these bits are initialized by hardware reset. 000 park on master port 0 001 park on master port 1 010 park on master port 2 011 park on master port 3 100 park on master port 4 101 park on master port 5 110 reserved 111 reserved table 36-8. slave general purpose control register field descriptions (continued) field description multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-12 freescale semiconductor ) 0x1003_f014 (asgpcr0) 0x1003_f114 (asgpcr1) 0x1003_f214 (asgpcr2) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 hlp 0000000 0000000 w reset0000000000000000 1514131211109876543210 r0 0 0 0 0 0 arb 00 pctl 0 pa r k w reset0000000000000000 figure 36-4. alternate sgpcr for slave port0?2 (asgpcr0-2) table 36-9. alternate slave general purpose control register field descriptions field description 31 reserved . they read as zero and should be written with zero for upward compatibility. 30 hlp halt low priority . this bit is used to set the initial arbitration priority of the max_halt_request input. this bit is initialized by hardware reset. 0 the max_halt_request input has the highest priority for arbitration on this slave port 1 the max_halt_request input has the lowest initial priority for arbitration on this slave port. 29?10 reserved . they read as zero and should be written with zero for upward compatibility. 9?8 arb arbitration mode. these bits are used to select the arbitration policy for the slave port. these bits are initialized by hardware reset. 00 fixed priority. 01 round robin (rotating) priority 10 reserved 11 reserved 7?6 reserved. they read as zero and should be written with zero for upward compatibility. 5?4 pctl parking control.these bits determine the parking control used by this slave port. these bits are initialized by hardware reset. 00 when no master is making a request the arbiter will park the slave port on the master port defined by the park bit field. 01 when no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 when no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 reserved multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-13 36.4.8.1 general purpose control register for master port 0?5 (mgpcr0?5) the master general purpose control register (mgp cr) presently controls only whether or not the master?s undefined length burst accesses will be allowed to complete unin terrupted or whether they can be broken by requests from higher priority masters. the aulb (arbitrate on undefined length bursts) bit field determines whether (and when) or not the max will arbitrate away the slave port the master owns when the master is performing undefined length burst accesses. see figure 36-5 for an illustration of valid bits in the mgpcr, and table 36-10 for its field descriptions. 3 reserved . they read as zero and should be written with zero for upward compatibility. 2?0 pa r k park. these bits are used to determine which master port this slave port parks on when no masters are actively making requests and the pctl bits are set to 00. these bits are initialized by hardware reset. 000 park on master port 0 001 park on master port 1 010 park on master port 2 011 park on master port 3 100 park on master port 4 101 park on master port 5 110 reserved 111 reserved 0x1003_f800 (mgpcr0) 0x1003_f900 (mgpcr1) 0x1003_fa00 (mgpcr2) 0x1003_fb00 (mgpcr3) 0x1003_fc00 (mgpcr4) 0x1003_fd00 (mgpcr5) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 0 0 0 0 000000000 w reset0000000000000000 1514131211109876543210 r0 0 0 0 0 0 0 000000 aulb w reset0000000000000000 figure 36-5. master general purpose control registers (mgpcr0-5) table 36-9. alternate slave general purpose control register field descriptions (continued) field description multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-14 freescale semiconductor 36.5 function this section describes the functiona lity of the max in greater detail. 36.5.1 arbitration max supports two arbitration schemes; a simple fi xed-priority comparison algorithm, and a simple round-robin fairness algorithm. arbitr ation schemes are independently programmable for each slave port. 36.5.1.1 arbitration during undefined length bursts arbitration points during an undefi ned length burst are defined by the current master?s mgpcr aulb field setting. when a defined length is imposed on th e burst via the aulb bits the undefined length burst will be treated as a single or series of si ngle back to back fixed length burst accesses. example: a master runs an undefined length burst a nd aulb bits in mgpcr indicate arbitration will occur after fourth beat of the burst. master runs two se quential beats and then starts what will be an 12 beat undefined length burst access to a new address within the same slave port region as the previous access. max will not allow an arbitration point until the f ourth overall access (second beat of second burst). at that point all remaining accesses will be open for arbitration until the master loses control of the slave port. assume master loses control of the slave port after fi fth beat of the second burst. once the master regains control of the slave port, no arbitra tion point will be available until mast er has run four more beats of its burst. after fourth beat of the (now continued) burst (9th beat of sec ond burst from master?s perspective) is taken, all beats of the burst will once again be open for arbitration until the master loses control of the slave port. assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst (10th beat of sec ond burst from master?s perspective). once the master regains control of the slave port it will be allowed to complete its fi nal two beats of its burst without facing arbitration. note fixed length burst accesses will not be affected by aulb bits. all fixed length burst accesses will lock out arbitration until the last beat of the fixed length burst. table 36-10. master general purpose control register field descriptions field description 31?3 reserved . they read as zero and should be written with zero for upward compatibility. 2?0 aulb arbitrate on undefined length bursts . these bits are used to select the arbitration policy during undefined length bursts by this master. these bits are initialized by hardware reset. 000 no arbitration will be allowed during an undefined length burst. 001 arbitration will be allowed at any time during an undefined length burst. 010 arbitration will be allowed after four beats of an undefined length burst. 011 arbitration will be allowed after eight beats of an undefined length burst. 100 arbitration will be allowed after 16 beats of an undefined length burst. 101 reserved 110 reserved 111 reserved multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-15 36.5.1.2 fixed priority operation when operating in fixed-priority mode, each master is assigned a unique priority level in the mpr and ampr. if two masters both request access to a slave port the master with the highest priority in the selected priority register will gain control over the slave port. any time a master makes a request to a slave port the slave port checks to see if the new requesting master?s pr iority level is higher than that of the master that currently has control over the slave port (unless the slav e port is in a parked state). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) ha s control of the slave port. if the new requesting master?s priority level is higher th an that of the current master that has control of the slave port, the new requesting master will be granted control over the slave port at the next clock edge. the exception to this rule is if the master that curren tly has control over the slave port is running a fixed length burst transfer or a locked transfer. in this case the ne w requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port. if the master is running an undefined length burst transf er, the new requesting master must wait until an arbitration point for the undefined length burst transfer before it will be granted control of the slave port. arbitration points for an undefined length burst are defined in mgpcr for each master. if the new requesting master?s priority level is lower than that of the current master that has control of the slave port, the new requesting master will be forced to wait until the current master has control of the slave port either runs an idle cycle or runs a non idle cycle to a location other than the current slave port. 36.5.1.3 round-robin priority operation when operating in round-robin mode, each master is assigned a relative priority based on the master number. this relative priority is compared to the id of the last master to perform a transfer on the slave bus. the highest priority requesting master will become owner of the slave bus as the next transfer boundary (accounting for locked and fixed-length burst tr ansfers). priority is based on how far ahead the id of the requesting master is to the id of the last master (id is defined by master port number, not hmaster field). once granted access to a slave port, a master ma y perform as many transfers as desired to that port until another master makes a request to the same slav e port. the next master in line will be granted access to the slave port at the next assertion of sx_hready, or possibly on the next clock cycle if the current master has no pending access request. as an example of arbitration in round-robin mode, a ssume the max is implemented with master ports 0, 1, 2, 3, 4 and 5. if the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, (master ports 2 and 3 make no requests), th ey will be serviced in the order 4, 5 and then 0. parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the parked master actually performs a transfer. hand-off will occur to the next master in line after one cycle of arbitration. if the slave port is put into low power park mode the round-robin pointer will be reset to point at master port 0, giving it the highest priority. 36.5.2 priority assignment each master port needs to be assi gned a unique 3 bit priority level. if an attempt is made to program multiple master ports with the same priority level within a register (mpr or ampr) the max will respond with an error and the registers will not be updated. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-16 freescale semiconductor 36.5.2.1 context switching the max has a hardware input per slave port (sx_ampr_s el) which is used to select which registers the master priority levels and genera l purpose control bits will be taken from. when sx_ampr_sel is 0, mpr and sgpcr will be selected and when sx_ampr_se l is 1, ampr and asgpcr will be selected. this hardware input is useful for context switching so the user does not have to rewr ite the mpr or sgpcr if a particular slave port would temporarily benefit from modifying the master priority levels or functions affected by the bits in the sgpcr. 36.5.3 master port functionality 36.5.3.1 general each master port consists of two dec oders, a capture unit, a register slic e, a mux and a small state machine. the first decoder is used to decode haddr and contro l signals coming directly from the master, telling the state machine where the master?s next access will be and if it is in fact a legal access. the second decoder gets its input from the capture unit, so it may be looking directly at the signals coming from the master or it may be looking at captured signals coming from th e master, depending entirely on the targeted slave port state. the second decoder is then used to genera te the access requests that go to the slave ports. capture unit is used to capture the address and cont rol information coming from the master in the event that the targeted slave port cannot immediately service the master. capture unit is controlled by outputs from the state machine which tell it to either pass thr ough the original master signa ls or the captured signals register slice contains the registers associated with the specific master port. the registers have a quasi-ip bus interface at this level for reads and writes and the outputs feed directly into the state machine. the mux is used simply to select which slave?s read data is sent back to the master. the mux is controlled by the state machine. the state machine controls all aspe cts of the master port. it knows which slave port the master wants to make a request to and controls when that request is made. it also has knowledge of each slave port, knowing whether or not the slave port is ready to accept an access from the master port. this will determine whether or not the master may immediately have its request taken by the slave port or whether the master port will have to capture the master?s request and queue it at the slave port boundary. a block diagram of the master port can be seen in figure 36-6 . multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-17 figure 36-6. max master port block diagram 36.5.3.2 decoders decoders are very simple as they ensure an access re quest is allowed to be made and that the slave port targeted is actually present in the design. the decode rs feeding the state machin e are always enabled. the decoders that select the slave are enabled only when the master port controlling state machine wants to make a request to a slave port. this is necessary so that if a master port is making an access to a slave port and is being wait stated, and its next access is to a different slave port, the request to the second slave port can be held off until the access to the first slave port is terminated. the decoders also output a ?hole decoder addr/ctrl next_slave_port[2:0] illegal_access capture unit addr/ctrl async/flopped_sel addr/ctrl decoder addr/ctrl slave_port_rqst[2:0] request_enable state machine next_slave_port[2:0] illegal_access request_enable async/flopped_sel rdata_sel slv_hready[2:0] slv_hresp0[2:0] hready_in hready_out slv_is_mine[2:0] hresp0 hrdata slv_hrdata[2:0] sel registers read_sel write_sel xfr_wait xfr_error wdata rdata control_bits control_bits mux multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-18 freescale semiconductor decode? or illegal access signal which tells the state m achine that the master is trying to access a slave port that does not exist. 36.5.3.3 capture unit the capture unit simply captures the state of the master?s address and control signals if the max cannot immediately pass the master?s request through to the proper slave port. the capture unit consists of a set of flops and a mux which selects either the asynchr onous path from address and control or the flopped (captured) address and control information. 36.5.3.4 registers registers in the master port are only those registers asso ciated with this particular master port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals are routed this deep in the design. there is a register control block at the same level of the master port and slave port instantiations in the max. this control block ensures that all accesses are 32-bit privileged accesses before passing them on to the master ports. the register outputs are connected directly to the state machine. 36.5.3.5 state machine 36.5.3.5.1 states the master side state machine?s main function is to monitor the master port activities. there are six states: busy, idle, stalled, steady state, first cycle error response and second cycle error response. the busy state is used when the master runs a busy cycle to the master port. the master port maintains its request to the slave port if it currently owns the slave port; however, if it loses control of the slave port it will no longer maintain its request. if the master port loses control of th e slave port it will not be allowed to make another request to the slave port until it runs a nseq or seq cycle. the idle state is used when the master runs a vali d idle cycle to the master port. the master port makes no requests to the slave ports (disables the slave port decoder) and terminates the idle cycle. the stalled state is used when the master makes a request to a slave port that is not immediately ready to receive the request. in this case the state machine will direct the capture unit to send out the captured address and control signals and will enable the slave port decoder to indicate a pending request to the appropriate slave port. the steady state is used when the master port and slave port are in fully asynchronous mode, making the max completely transparent in the access. the st ate machine selects the appropriate slave?s hresp0, hready and hrdata to pass back to the master. the first cycle error response and second cycle error re sponse states are self explanatory. the max will respond with an error response to the master if th e master tries to access an unimplemented memory location through the max (that is, a slave port that does not exist). multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-19 36.5.3.5.2 slave swapping the design of the master side state machine is fairly straight forward. the one real decision to be made is how to handle the master moving from one slave port access to another slave port access. the approach that was taken was to minimize or e liminate, when possible, any ?bubbles? that would get inserted into the access due to switching slave ports. the state machine will not allow the master to request access to another slave port until the current access being made is terminated. this prevents a single master from owning two slave ports at the same time (the slave port it is currently accessing and the slave port it wishes to access next). the state machine also maintains watch on the slave port the master is accessing as well as the slave port the master wishes to switch to. if the new slave port is parked on the master then the master will be able to make the switch without incurring any delays. the te rmination of the current access will also act as the launch of the new access on the new slave port. if the new slave port is not parked on the master then the master will incur a minimum one clock delay before it can launch its access on the new slave port. this is the same for switching from the busy or idle state to actively accessing a slave port. if the slave port is parked on the master the state machine will go to the steady state and the access will begin immediately. if the slave port is not parked on the master (serving another master, parked on another master or in low power park mode) then the state machine will transition to the stalled state and at least a one clock penalty will be paid. 36.5.4 slave port functionality 36.5.4.1 general each slave port consists of a register slice, a bank of muxes and a state machine. the register slice contains the registers associated with the specific slave port. th e registers have a quasi-ip bus interface at this level for reads and writes and the outputs feed directly into the state machine. a block diagram of a slave port can be seen in figure 36-7 . 36.5.4.2 muxes figure 36-7 shows only one block for all the muxes. in rea lity that block instantiates many 6 to 1 muxes, one for each master-to-slave signal in fact. all the m uxes are designed in an and - or fashion, so that if no master is selected the output of the muxes will be zero. (this is an important feature for low power park mode.) the muxes also have an override signal which is used by the slave port to asynchronously force idle cycles onto the slave bus. when the state machin e forces an idle cycle it zeros out htrans and hmastlock, making sure the slave bus sees a valid idle cycle being run by the max. the mux controlling htrans also contains an additiona l control signal from the state machine so that a nseq transaction can be forced. this is done at any time when the slave port switches masters to ensure that no idle-seq, busy-seq or nseq-seq transacti ons are seen on the slave port when they shouldn?t be. if the state machine indicates to run both idle a nd nseq cycle, the idle directive will have priority. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-20 freescale semiconductor note idle-seq is in fact an illegal access, but a possible scenario given the multi-master environment in the max unless corrected by the max. figure 36-7. max slave port block diagram 36.5.4.3 registers there is a register control block at the same level of the master port and slave port instantiations in the max. this control block ensures that all accesses are 32-bit privileged accesses before passing them on to the master and slave ports. the registers in the sl ave port are only those registers associated with this particular slave port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals are routed this deep in the design. the register outputs are connected directly to the slave state machine with the sx_a mpr_sel input determining which priority register values, halt priority value, arbitration algorithm and parking control bits are passed to the state machine. the registers can be read from an unlimited number of times. the registers can only registers read_sel write_sel xfr_wait xfr_error wdata rdata control_bits state machine master_requests[5:0] m[5:0]_high_priority slv_hresp0 master_sel[5:0] force_idle control_bits slv_hready slave_halted current_master[5:0] master_hready[5:0] force_nseq halt_request ampr_sel master_hresp0[5:0] muxes master_addr[5:0] master_cntrl[5:0] master_wdata[5:0] slv_addr_signals slv_cntrl_signals slv_wdata master_sel[5:0] force_idle force_nseq multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-21 be written to as long as the ro bit is written to 0 in the sgpcr, once it is written to a 1 only a hardware reset will allow the registers to be written again. 36.5.4.4 state machine 36.5.4.4.1 states at the heart of the slave port is the state machine. the state machine is simplicity itself, requiring only four states?steady state, transition state, transition hold state and hold stat e . either the slave port is owned by the same master it was in the last clock cycle (eith er by active use or by parking), it is transitioning to a new master (either for active use or parking), it is tr ansitioning to a new master during wait states or it is being held on the same master pe nding a transition to a new master. 36.5.4.4.2 arbitration the real work of the state machine is to determine which master port will be in control of the slave port in the next clock cycle. each master is programmed with a fixed 3 bit priori ty level. the max uses these bits in determining priority levels wh en programmed for fixed priority m ode of operation. arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not violate ahb-lite protocols. valid arbitrations point s include any clock cycle in which sx_hready is asserted (provide the master is not performing a burst or locked cycle) a nd any wait state in which the master owning the bus indicates a transfer type of idle (provided the master is not performing a locked cycle). since arbitration can occur on every clock cycle the slave port masks of f all master requests if the current master is performing a locked transfer or a protected burst tran sfer, guaranteeing that no matter how low its priority level it will be allowed to finish its lock ed or protected portion of a burst sequence. 36.5.4.4.3 master hand-off the only times slave port will switch masters when pr ogrammed for fixed priority mode of operation is when a higher priority master makes a request or when the current master is the highest priority and it gives up the slave port by either running and idle cycle to the slave port or running a valid access to a location other than the slave port. if the current master loses control of the slave port beca use a higher priority master takes it away the slave port will not incur any wasted cycles. the current master will get its current cycle terminated by the slave port at the same time the new master ?s address and control informati on will be recognized by the slave port. this will look like a seamless transition on the slave port. if the current master is being wait stated when the higher priority master makes its request, then the current master will be allowed to make one more transaction on the slave bus before giving it up to the new master. figure 36-8 illustrates the effect of a higher priority mast er taking control of the bus when the slave port is programmed for a fixed priority mode of operation. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-22 freescale semiconductor figure 36-8. low to high priority mastership change figure 36-9. high to low priority mastership change if current master is the highest priority master a nd it gives up the slave port by running an idle cycle or a valid cycle to another location other than the slave port, the next highest priority master will gain control of the slave port. if the current access incurs any wait states then the transition will be seamless and no bandwidth will be lost; however, if the current trans action is terminated without wait states, then one idle cycle will be forced onto the slave bus by the max before the new master will be able to take control of 123456789 master 5 master 5 master 4 master 3 master 2 master 3 master 4 none max master 5 master 5 master 2 master 3 master 4 max idle nseq nseq nseq nseq nseq idle hclk m2 request m3 request m4 request m5 request htrans hready requester priority highest address/cntrl owner 10 12345678 9 master 0 master 2 none master 4 none max master 0 max master 2 max master 4 max idle nseq idle nseq idle nseq idle hclk m0 request m2 request m4 request highest address/cntrl htrans hready priority requester owner multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-23 the slave port. if no other master is requesting the bus then idle cycles will be run by the max but no bandwidth will be lost since no master is making a request. figure 36-9 illustrates the effect of a higher priority master giving up control of the bus. when the slave port is programme d for round-robin mode of arbitration, then it will switch masters at any time th ere is more than one master actively making a request to it. this will happen because any master other than the one which presently owns the bus will be considered to have higher priority. figure 36-10 shows an example of round-robin mode of operation. figure 36-10. round-robin mastership change 36.5.4.4.4 parking if no master is currently making a request to the slave por t then the slave port will be parked. it will park in one of four places, dictated by the pctl and park bits in the gpcr or agpcr (depending on the state of the sx_ampr_sel) and the locked state of the last master to access it. if the last master to access the slave port ran a locked cycle and continues to run locked cycles even after leaving the slave port, the slave port will park on that ma ster irrespective of gpcr bit settings and without regard to pending requests from other masters. this is done so that a master can run a locked transfer to the slave port, leave it, and return to it and be guarant eed that no other master accessed it. if locking is not an issue for parking the gpcr b its will dictate the parking method. if pctl bits are set for ?low power park? mode then th e slave port will enter low power park mode. it will not recognize any master as being in control of it and it will not select any master?s signals to pass through to the slave bus. in this case all slave bus activity will effectively halt because all slave bus signals being driven from the max will be 0. this of course can sa ve quite a bit of power if the slave port will not be in use for some time. the down side is that when a master does make a request to the slave port it will be delayed by one clock since it will have to arbitrate to acquire ownership of the slave port. if pctl bits are set to ?park on last? mode then the sl ave port will park on the last master to access it, passing all that masters signals through to the slav e bus. max will asynchronously force htrans[1:0], hmaster[3:0], hburst[2:0] and hmastlock to 0 for all acce ss that the master does not run to the slave port. 12345678910 master 1 master 4 master 0 master 4 master 5 none max master 1 master 4 master 5 master 0 master 4 master 5 max idle nseq nseq nseq nseq nseq nseq idle hclk m0 request m1 request m4 request m5 request highest address/cntrl htrans hready priority requester owner master 5 multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-24 freescale semiconductor when that master access the slave port again it will not pay any arbitration pena lty; however, if any other master wishes to access the slave port a one clock arbitration penalty will be imposed. figure 36-11 illustrates parking on the last master. note that in cycle 6 simultaneous requests are made by master 2 and master 4. although master 2 has higher priority, the slave bus is parked on master 4 so master 4?s access will be taken first. the slave port parks on master 2 once it has given control to master 2. this same situation can occur when parking on a specific master as well. figure 36-11. parking on last master 12345678 9 last master master 0 master 4 master 2 master 0 none master 4 none master 2 none max master 0 max master 4 max master 4 master 2 max idle nseq idle nseq idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-25 figure 36-12. parking on a specific master if pctl bits are set to ?use park/apark? mode, then the slave port will park on the master designated by the park bits. the behavior here is the same as for the ?park on last? mode with the exception that a specific master will be parked on instead of the last master to access the slave port. if the master designated by the park bits tries to access the slave port it will not pay an arbitration penalty while any other master will pay a one clock penalty. figure 36-12 illustrates parking on a specific master. 36.5.4.4.5 halt mode if max_halt_request input is asserted, sl ave port will eventually halt all slave bus activity and go into halt mode, which is almost identical to low power park m ode. hlp bit in gpcr controls the priority level of max_halt_request in arbitration algorithm. if hlp bit is cleared, then max_halt_request will have the highest priority of any master and will gain control of the slave port at the next arbitration point (most likely the next bus cycle, unless current master is r unning a locked or fixed length burst transfer). if hlp bit is set, then the slave port will wait until no mast ers are actively making requests before moving to halt mode. regardless of hlp bit state, once slave port has gone into halt mode as a result of max_halt_request being asserted, it will remain in halt mode until max_ halt_request is negated, re gardless of the priority level of any masters that ma y make requests. in halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0. 36.6 initialization/app lication information no initialization is required by or for max. hardwa re reset ensures all register bits used by max are properly initialized. 12345678 9 master 2 master 0 none master 2 none master 4 none master 2 none max master 0 master 2 max max master 4 master 2 max idle nseq nseq idle idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-26 freescale semiconductor 36.7 interface max main goal is to increase overall system performance by allowing multiple masters to communicate in parallel with multiple slaves. in order to maximi ze data throughput, it is esse ntial to keep arbitration delays to a minimum. this section examines data thr oughput from the point of view of masters and slaves, detailing when max will stall the masters or insert bubbl es on the slave side. master accesses will receive one of four responses from max. they will either be terminated, taken, stalled or responded to an error. 36.7.1 master ports master accesses will receive one of four responses from the max. they will either be terminated, taken, stalled or responded to with an error. terminated accesses: a master access will be terminated if the transfer type is idle. max will terminate the access and it will not be allowed to pass through the max. taken accesses: a master access will be taken if the transfer type is non idle and the slave port to which the access decodes is either curre ntly servicing the master or is parked on the master. in this case max will be completely transparent and the master?s access will be immediately seen on the slav e bus and no arbitrati on delays will be incurred. stalled accesses: a master access will be stalled if transfer type is non idle and access decodes to a slave port that is busy serving another master, parked on another master or is in low power park mode. max will indicate to the master that address phase of the access has been taken but will then queue the access to appropriate slave port to enter into arbitration for access to that slave port. if the slave port is currently parked on another master or is in low power park mode and no other master is requesting access to it, then only one clock of arbitration will be incurred. if the slave port is currently serving another master of a lower priority and the master has a higher priority than all other reque sting masters then the master will gain control over the slave port as soon as th e data phase of the current access is completed (burst and locked transfers excluded). if the slave port is currently servicing another master of a higher priority then the master will gain control of the slave port once the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. error response terminated accesses: a master access will be responded to with an error if the transfer type is non idle and the access decodes to a location not occupied by a slave port. this is the only time the max will respond with an error response. all other error responses received by the master are result of error responses on the slave ports being passed through max. 36.7.2 slave ports the goal of max with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. in order to do this, max must not in sert any bubbles onto the slave bus unless absolutely multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 36-27 necessary. there is only one instance when max will force a bubble onto the slave bus when a master is actively making a request. this occurs when a higher pr iority master has control of the slave port and is running single clock (zero wait state) access while a lowe r priority master is sta lled waiting for control of the slave port. when higher priority master either leaves the slave port or runs an idle cycle to the slave port, max will take control of the slave bus and r un a single idle cycle before giving the slave port to the lower priority master that was waiting for control of the slave port. the only other times, max will have control of the sl ave port is when max is halting or when no masters are making access requests to the slave port and the max is forced to either park the slave port on a specific master or put the slave port into low power park mode. in most instances when max has control of slave port, it will indicate idle for the transfer t ype, negate all control signa ls and indicate ownership of the slave bus via the hmaster encoding of 4?b0000. one exception to this rule is when a master running locked cycles has left the slave port but continues to run locked cycles. in this case, max will control the slave port and will indicate idle for the transfer type but it will not affect any other signals. note when a master runs a locked cycle through the max, master will be guaranteed ownership of all slave por ts it accesses while running locked cycles for one cycle beyond when the ma ster finishes running locked cycles. multi-layer ahb crossbar switch (max) MCIMX27 multimedia applications processor reference manual, rev. 0.2 36-28 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-1 chapter 37 direct memory access controller (dmac) the direct memory access controller (dmac) of i.mx27 device provides 16 dma channels supporting linear memory, 2d memory and fifo transfers to provide support for a wide variety of dma operations. figure 37-1 shows a simplified block diagram of the dmac. figure 37-1. block diagram of dmac 37.1 features ? sixteen channels support linear memory, 2d me mory, fifo for both source and destination. ? dma chaining for variable length buffer exch anges and high allowabl e interrupt latency requirement. ? increment, decrement, and no-change suppor t for source and destination addresses. ? each channel is configurable to respond to any of the 64 dma request signals. ? supports 8, 16, or 32-bit fifo and me mory port size data transfers. ? dma burst length configurable up to a maximum of 16 words, 32 half-words, or 64 bytes for each channel. ? bus utilization control for the channel that is not trigger by a dma request. ? burst time-out errors terminates the dma cycle when the burst cannot be completed within a programmed time count. ? buffer overflow error terminates the dma cycle when the internal buffer receives more than 64 bytes of data. ? transfer error terminates the dma cycle when a transfer error is detected during a dma burst. ? dma request time-out errors are generated for channels that are triggered by dma requests to interrupt the cpu when a dma burst does not star t on that channel after a programmed time count. cspi csi i2s uart ahb dma aipi ip bus dma_req [63:0], dma_ack , ip bus ip bus ahb crossbar switch (max) ahb bus ahb bus direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-2 freescale semiconductor ? interrupts are provided to the interrupt contro ller (and subsequently to the core) on bulk data transfer complete or transfer error. ? each peripheral that supports dm a transfer generates a dma_req signal to the dma controller, assuming that each fifo has a unique system address and generate s a dedicated dma_req signal to the dma controller. for example, a usb device with 8 end-points has 8 dma request signals to the dma if they all support dma transfer. ? dma controller provides an acknow ledge signal to the peripheral after dma burst is complete. this signal is sometimes used by the peripheral to clear the status bits. ? repeat data transfer function supports automa tic usb?host?usb device bulk/iso data stream transfer. ? dedicated external dma request signal. dma has a fifo for storing data read from ahb bus. this fifo is 32-bits wide and 16 deep to store up to 64 bytes. this fifo is common for all channels and is used by the active channel. 37.2 dma request and acknowledge initiation of a dma cycle can be done through software control (setting cen = 1 and ren =0 in channel control register) or by dma request assertion (setting cen = 1 and ren =1 in channel control register). a dma cycle consists of a number of dma bursts de pending on burst length and count register settings. table 37-1 contains the dma request map. 37.2.1 dma request a typical dma request is an active low signal assert ed by the peripheral. the sampling of this signal is done when ren and cen bits in channel control register are set and there is no other ongoing dma transfer on the ahb bus. there is no configurable prio rity associated with any request. however, the 16 channels have a fixed priority; channel 15 has the highe st priority and channel 0 has the lowest priority. the priority of any request depends on the channe l number to which the request is mapped (through request source select register settings). dmac doe s not store dma request inputs, it processes on the highest priority channel request out of the asserted channel requests (when no other transfer is taking place). a peripheral must keep the request asserted until it is serviced by dmac. there are 64 input dma request signals available. 1 dma request will initia te 1 dma burst. once a dma burst has started, dma request can be de-asserted by the peripheral. the peripheral should de-assert the dma request based on data read from or written into it. if the request is not de-asserted till the end of the dma burst, it can initiate another dma burst. 37.2.2 external dma request and grant after assertion of external dma request, the dma burst will start when the corresponding dma channel becomes the highest priority channel. external dma request should be kept asserted until it is serviced by the dmac. one external request will initiate at least one dma burst. the output external grant signal from the dmac is an active-low signal. this signal will be asserted during the time when a dma burst is ongoing for an external dma request, when the following conditions are true: direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-3 ? the dma channel for which the dma burst is ongoing has requested source as external dma request (as per rssr settings). ? ren and cen bit of this channel are set ? external dma request is asserted once the grant is asserted, external dma request w ill not be sampled until completion of the dma burst. the priority of external request will become low fo r the next consecutive burst , if another dma request signal is asserted. the waveforms are shown for the wors t case, that is, smallest burst (1 byte read/write). minimum and maximum timings for external request and external grant signal are present in the data sheet. figure 37-2 shows the minimum time for which the external grant signal remains asserted if external dma request is de-asserted immediately after sensing grant signal active. figure 37-2. assertion of dma external grant signal figure 37-3 shows the safe max time for which external dma request can be kept asserted, after sensing grant signal active as if a new burst is not initiated. figure 37-3. safe maximum timings for external request de-assertion 37.3 dma request mapping table 37-1 shows requests connection from various modul es in the i.mx27 to dma request input of dmac table 37-1. dma request mapping dma request number module assigned channel name dma_req[63:38] reserved reserved dma_req[37] emi nfc ext_dmareq ext_dmagrant t min_assert ext_dmareq data read from external device data written to external device ext_dmagrant t max_write t max_read t max_req_assert note: assuming in worst case the data is read /written from/to external device as per the above waveform. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-4 freescale semiconductor dma_req[36] sdhc3 sdhc3 dma_req[35] uart6 uart6_rx_fifo dma_req[34] uart6 uart6_tx_fifo dma_req[33] uart5 uart5_rx_fifo dma_req[32] uart5 uart5_tx_fifo dma_req[31] csi csi_rx_fifo dma_req[30] csi csi_stat_fifo dma_req[29] ata ata_rcv_fifo dma_req[28] ata ata_tx_fifo dma_req[27] uart1 uart1_tx_fifo dma_req[26] uart1 uart1_rx_fifo dma_req[25] uart2 uart2_tx_fifo dma_req[24] uart2 uart2_rx_fifo dma_req[23] uart3 uart3_tx_fifo dma_req[22] uart3 uart3_rx_fifo dma_req[21] uart4 uart4_tx_fifo dma_req[20] uart4 uart4_rx_fifo dma_req[19] cspi1 cspi1_tx_fifo dma_req[18] cspi1 cspi1_rx_fifo dma_req[17] cspi2 cspi2_tx_fifo dma_req[16] cspi2 cspi2_rx_fifo dma_req[15] ssi1 ssi1_tx1_fifo dma_req[14] ssi1 ssi1_rx1_fifo dma_req[13] ssi1 ssi1_tx0_fifo dma_req[12] ssi1 ssi1_rx0_fifo dma_req[11] ssi2 ssi2_tx1_fifo dma_req[10] ssi2 ssi2_rx1_fifo dma_req[9] ssi2 ssi2_tx0_fifo dma_req[8] ssi2 ssi2_rx0_fifo dma_req[7] sdhc1 sdhc1 dma_req[6] sdhc2 sdhc2 dma_req[5] reserved reserved dma_req[4] mshc mshc table 37-1. dma request mapping (continued) dma request number module assigned channel name direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-5 37.4 memory map and register definition the dmac module contains 158 32-bit re gisters. the registers are divide d into four groups according to the register functions as follows: ? general registers for all functional blocks (see section 37.4.3, ?general registers ?). ? 2d memory registers to control display width and x and y of the window (see section 37.4.4, ?2d memory registers (a and b) ?). ? channel registers to control and configure channels 0?15 (see section 37.4.5, ?channel registers ?). ? test registers. the base address of dma controller for i.mx27 is 0x10001000. table 37-4 summarizes the registers and offset addresses. section 37.4, ?memory map and register definition ? provides detailed descriptions of the dmac registers. 37.4.1 dmac memory map table 37-2 shows the dmac memory map. dma_req[3] external dma request ? dma_req[2] cspi3 cspi3_tx_fifo dma_req[1] cspi3 cspi3_rx_fifo dma_req[0] reserved ? table 37-2. dmac memory map address use access reset value section/page 0x1000_1000 (dcr) dma control register r/w 0x0000_0000 37.4.3.1/37-10 0x1000_1004 (disr) dma interrupt status register r/w 0x0000_0000 37.4.3.2/37-11 0x1000_1008 (dimr) dma interrupt mask register r/w 0x0000_0000 37.4.3.3/37-12 0x1000_100c (dbtosr) dma burst time-out status register r/w 0x0000_0000 37.4.3.4/37-13 0x1000_1010 (drtosr) dma request time-out status register r/w 0x0000_0000 37.4.3.5/37-13 0x1000_1014 (dsesr) dma transfer error status register r/w 0x0000_0000 37.4.3.6/37-14 0x1000_1018 (dbosr) dma buffer overflow status register r/w 0x0000_0000 37.4.3.7/37-15 0x1000_101c (dbtocr) dma burst time-out control register r/w 0x0000_0000 37.4.3.8/37-15 0x1000_1040 (wsra) 0x1000_104c (wsrb) w-size register a w-size register b r/w 0x0000_0000 37.4.4.1/37-17 0x1000_1044 (xsra) 0x1000_1050 (xsrb) x-size register a x-size register b r/w 0x0000_0000 37.4.4.2/37-18 table 37-1. dma request mapping (continued) dma request number module assigned channel name direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-6 freescale semiconductor 37.4.2 register summary figure 37-4 shows the key to the register fields, and table 37-3 shows the register figure conventions. figure 37-4. key to register fields 0x1000_1048 (ysra) 0x1000_1054 (ysrb) y-size register a y-size register b r/w 0x0000_0000 37.4.4.3/37-19 0x1000_1080 (sar0) ? 0x1000_1440 (sar15) channel 0 source address register ? channel 15 source address register r/w 0x0000_0000 37.4.5.1/37-20 0x1000_1084 (dar0) ? 0x1000_1444 (dar15) channel 0 destination address register ? channel 15destination address register r/w 0x0000_0000 37.4.5.2/37-20 0x1000_1088 (cntr0) ? 0x1000_1448 (cntr15) channel 0 count register ? channel 15 count register r/w 0x0000_0000 37.4.5.3/37-21 0x1000_108c (ccr0) ? 0x1000_144c (ccr15) channel 0 control register ? channel 15 control register r/w 0x0000_0000 37.4.5.4/37-22 0x1000_1090 (rssr0) ? 0x1000_1450 (rssr15) channel 0 request source select register ? channel 15 request source select register r/w 0x0000_0000 37.4.5.5/37-25 0x1000_1094 (blr0) ? 0x1000_1454 (blr15) channel 0 burst length register ? channel 15burst length register r/w 0x0000_0000 37.4.5.6/37-26 0x1000_1098 (rtor0) ? 0x1000_1458 (rtor15) 1 channel 0 request time-out register/ ? channel 15 request time-out register/ r/w 0x0000_0000 37.4.5.7/37-26 0x0000_0000 0x1000_1098 (bucr0) ? 0x1000_1458 (bucr15) 2 channel 0 bus utilization control register ? channel 15 bus utilization control register r/w 0x0000_0000 37.4.5.8/37-27 0x0000_0000 0x1000_109c (ccnr0) ? 0x1000_145c (ccnr15) channel 0 channel counter register ? channel 15channel counter register r/w 0x0000_0000 37.4.5.9/37-28 1 the rtor registers use the same memory addresses as the bucr registers. 2 he bucr registers use the same memory addresses as the rtor registers. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 37-2. dmac memory map (continued) address use access reset value section/page direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-7 table 37-4 shows the dmac register summary. table 37-3. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 37-4. dmac register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x1000_1000 (dcr) r0000000000000000 w r0000000000000 da m 0 den w drs t 0x1000_1004 (disr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-8 freescale semiconductor 0x1000_1008 (dimr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w 0x1000_100c (dbtosr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c 0x1000_1010 (drtosr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c 0x1000_1014 (dsesr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c 0x1000_1018 (dbosr) r0000000000000000 w r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c w1 c 0x1000_101c (dbtocr) r0000000000000000 w ren cnt [14: 0] w table 37-4. dmac register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-9 0x1000_1040 (wsra) 0x1000_104c (wsrb) r0000000000000000 w r ws [15: 0] w 0x1000_1044 (xsra) 0x1000_1050 (xsrb) r0000000000000000 w r xs [15: 0] w 0x1000_1048 (ysra) 0x1000_1054 (ysrb) r0000000000000000 w r ys [15: 0] w 0x1000_1080 (sar0) ? 0x1000_1440 (sar15) r sa [31: 16] w r sa [15: 0] w 0x1000_1084 (dar0) ? 0x1000_1444 (dar15) r da [31: 16] w r da [15: 0] w 0x1000_1088 (cntr0) ? 0x1000_1448 (cntr15) r00000000 cnt [23: 16] w r cnt [15: 0] w 0x1000_108c (ccr0) ? 0x1000_144c (ccr15) r0000000000000000 w r0 acr pt dmod smod mdi r ms el dsiz ssiz ren rpt 0cen w frc table 37-4. dmac register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-10 freescale semiconductor 37.4.3 general registers 37.4.3.1 dma control register (dcr) the dma control register (dcr) controls the i nput of the system clock, enabling, disabling, and resetting of the dma module. 0x1000_1090 (rssr0) ? 0x1000_1450 (rssr15) r0000000000000000 w r 0000000000 0 rss [5: 0] w 0x1000_1094 (blr0) ? 0x1000_1454 (blr15)) r0000000000000000 w r0000000000 bl [5: 0] w 0x1000_1098 (rtor0) ? 0x1000_1458 (rtor15)) r0000000000000000 w r en clk psc cnt [12: 0] w 0x1000_1098 (bucr0) ? 0x1000_1458 (bucr15)) r0000000000000000 w r bu_cnt [15: 0] w 0x1000_109c (ccnr0) ? 0x1000_145c (ccnr15) r00000000 ccnr[23:16] w r ccnr [15: 0] w table 37-4. dmac register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-11 37.4.3.2 dma interrupt status register (disr) the disr contains interrupt status of each channel in the dmac. the status bit is set whenever the corresponding dma channel data transfer is complete. when any bit in disr is set and the corresponding bit in the interrupt mask register is cleared, dma_int is asserted to the interrupt controller (aitc). when an interrupt occurs, an interrupt service routine must check disr to determine the interrupting channel. clear each bit by writing a value 1 to it. 0x1000_1000 (dcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0000000000000 dam 0 den w drst reset0000000000000000 figure 37-5. dma control register (dcr) table 37-5. dma control register field descriptions field description 31?3 reserved. these bits are reserved and should read 0. 2 dam dma access mode. specifies user or privileged access to be performed by dma. 0 privileged access 1 user access 1 drst dma soft reset. generates a 3-cycle reset pulse that resets the entire dma module, bringing the module to its reset condition. drst always reads 0. 0no effect 1 generates a 3-cycle reset pulse 0 den dma enable. enables/disables the system clock to the dma module. however the bit is not used for clock gating in i.mx27 as the clock is controlled from crm in the i.mx27 processor. 0dma disable 1 dma enable direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-12 freescale semiconductor 37.4.3.3 dma interrupt mask register (dimr) dimr masks both normal interrupts and error interrupt s generated by the corresponding channel. there is one control bit for each channel. when an interrupt is masked, the interrupt c ontroller does not generate an interrupt request to the aitc, however the status of the interrupt can be observed from the interrupt status register, burst time-out status register, request ti me-out status register, or the transfer error status register. at reset, all the interrupts are masked and all the bits in this register are set to 1. 0x1000_1004 (disr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 37-6. dma interrupt status register table 37-6. dma interrupt status register field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0 interrupt status. indicates interrupt status for each dma channel. 0 no interrupt 1 interrupt is pending 0x1000_1008 (dimr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset0000000000000000 figure 37-7. dma interrupt status register (dimr) direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-13 table 37-7. dma interrupt mask register field descriptions 37.4.3.4 dma burst time-out status register (dbtosr) a burst time-out is set when a dma burst cannot be co mpleted within the number of clock cycles specified in the dma burst time-out control register (dbtocr) of the channel. when any bit is set in this register and the corresponding bit in the interrupt ma sk register is cleared, a dma error interrupt is asserted to the interrupt controller (aitc). dbtosr indi cates the channel, if any, that is currently being serviced and whether a burst time-out was det ected. each bit is cleared by writing 1 to it. table 37-8. dma burst time-out status register description 37.4.3.5 dma request time-out status register (drtosr) a dma request time-out is set when there is no dm a burst started on the channel (when ren =1, either due to no dma request or dma channel not acquiring the bus) within the pre-assigned number of clock cycles specified in the request time-out control regist er (rtor) for the channel. when any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a dma error interrupt is asserted to the interrupt controller (aitc). drtosr indi cates the enabled channel, if any, that detected a dma request time-out. clear each bit by writing 1 to it. field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0 interrupt mask. controls the interrupts for each dma channel. 0 enables interrupts 1 disables interrupts 0x1000_100c (dbtosr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 37-8. dma burst time-out status register (dbtosr) field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0. indicates the burst time-out status of each dma channel. 0 no burst time-out 1 burst time-out direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-14 freescale semiconductor 37.4.3.6 dma transfer error status register (dsesr) a dma transfer error is set when dma data transfer results in an error. when any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a dma error interrupt is asserted to the interrupt controller (aitc). dsesr indicates the channel, if any, the detected transfer error during a dma burst. clear each bit by writing 1 to it. 0x1000_1010 (drtosr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 37-9. dma request time-out status register (drtosr) table 37-9. dma request time-out status register field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0. indicates the request time-out status of each dma channel. 0 no dma request time-out 1 dma request time-out 0x1000_1014 (dsesr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 37-10. dma transfer error status register (dsesr) direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-15 table 37-10. dma transfer error status register field descriptions 37.4.3.7 dma buffer overflow status register (dbosr) the dbosr indicates whether dma controller?s intern al fifo buffer overflowed during a data transfer. before a channel can be enabled for dma, the corresponding bit in this register must be cleared. when any bit in this register is set and the corresponding bit in the interrupt mask register is cleared, a dma error interrupt is asserted to the interrupt controller (aitc). table 37-11. dma buffer overflow status register field descriptions 37.4.3.8 dma burst time-out control register (dbtocr) this register sets the dma burst time-out (common fo r all dma channels), so that dmac can release the ahb and ip buses in the event of an error. an inte rnal counter starts counting when a dma burst starts, and resets to zero when the burst is completed. when the counter reaches the count value set in the register, it asserts an interrupt and sets the corresponding e rror bit in the dma burst time-out status register (dbtosr). the system clock is used as the input clock to the counter. field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0. indicates the dma transfer error status of each dma channel. 0 no transfer error 1 transfer error 0x1000_1018 (dbosr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 37-11. dma buffer overflow status register (dbosr) field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ch15?ch0 channel 15 to 0. indicates the buffer overflow error status of each dma channel. 0 no buffer overflow occurred 1 buffer overflow occurred direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-16 freescale semiconductor 37.4.4 2d memory registers (a and b) there are two sets of 2d memory registers that allow every channel to select any register set to define the respective 2d memory size. each data transfer perfor med by dma is strictly as per source and destination sizes specified in channel control register (this is valid for linear memory, 2d memory, and fifo mode). in the case of a transfer to/from 2d memory, the ch annel count register value is ignored and number of bytes transferred is equal to 2d memory size. 2d memory size is computed as follows. size (in number of bytes) = no of bytes per row (value in x register) * no. of rows (value in y register) at a time any number of channels ca n be programmed for 2d memory (e ven all 16 channels). 2d memory can be selected for a channel as source or destinati on or even both. in the last condition, only selected set of 2d registers (selected as per msel bit setting in th e channel control register) is used for both source and destination. the advantage of havi ng 2 sets of registers, which are us able by all dma channels, is that this allows the developer to have two different window size settings for 2d memory. each channel can be programmed to use any one of the 2 settings. in figure 37-13 , shaded portion shows the data transfer zone in the 2d memory for x= 4, y = 4, and w (display size) = 6 with memory increment option and starting address 0x001. in figure 37-14 , shaded portion shows the data transfer zone in 2d memory for x= 4, y = 5, and w = 6 with memory decrement option and starting address as 0x11c. 0x1000_101c (dbtocr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r en cnt w reset0000000000000000 figure 37-12. dma burst time-out control register (dbtocr) table 37-12. dma burst time-out control register field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15 en enable. enables/disables the burst time-out. 0 disables burst time-out 1 enables burst time-out 14?0 cnt count. this count is the number of system clock cycles to be used for the time-out value direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-17 figure 37-13. 2d memory increment diagram figure 37-14. 2d memory decrement diagram 37.4.4.1 w-size registers (wsra, wsrb) the w-size registers (wsra, wsrb) define the number of bytes that make up the display width. this allows the dmac to calculate the next starting a ddress of another row by adding the source/destination address to the w-size register content. starting address (ssa) y x w 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 y x w 11c 11b 11a 119 118 115 117 116 114 113 112 111 110 10f 10e 10d 10c 10b 10a 109 108 107 106 105 104 0fe 103 102 101 100 0ff starting address direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-18 freescale semiconductor 37.4.4.2 x-size registers (xsra, xsrb) x-size registers (xsra, xsrb) contain the number of bytes per row of the window. the value of this register is used by the dma controller to determine when to jump to the next row. 0x1000_1040 (wsra) 0x1000_104c (wsrb) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ws w reset0000000000000000 figure 37-15. w-size registers (wsra, wsrb) table 37-13. w-size registers field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ws w-size. contains the number of bytes that makes up the display width. w and x must follow the relation: w x w and access size must follow the relation: w access size. wsize needs to be a multiple of source or destination access size whichever is a 2d memory. 0x1000_1044 (xsra) 0x1000_1050 (xsrb) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r xs w reset0000000000000000 figure 37-16. x-size registers (xsra, xsrb) direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-19 table 37-14. x-size registers field descriptions 37.4.4.3 y-size registers (ysra, ysrb) the y-size registers (ysra, ysrb) contain the numbe r of rows in the 2d memory window. this setting is used by the dma controller to calc ulate the total size of transfer. 37.4.5 channel registers channels 0 to 15 supports linear memory, 2d me mory, fifo transfer. the dma request (dma_req [63:0]) signals do not have any configurable pr iority. the only priority available is the priority that is defined for each channel: channel 15 has the highest priority and channel 0 has the lowest priority. the channel priority is used only when more than one request occurs at the same time. otherwise, channels are serviced on a first come, first serve basis. each channel genera tes a normal interrupt to the interrupt handler when the data count reaches the selected value. each channe l generates an error interrupt to the interrupt handler when any of the following conditions exist: field description 31?16 reserved. these bits are reserved and should read 0. 15?0 xs x-size. contains the number of bytes per row that defines the x-size of 2d memory. the value in the x register should follow the following 2 rules: x burst length (bl) x/ bl = whole number. 0x1000_1048 (ysra) 0x1000_1054 (ysrb) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r ys w reset0000000000000000 figure 37-17. y size registers (ysra, ysrb) table 37-15. y-size registers field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?0 ys y-size. contains the number of rows that makes up the 2d memory window. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-20 freescale semiconductor ? a dma request time-out is true ? a dma burst time-out is true during a burst cycle ? the internal buffer overflows during a burst cycle ? a transfer error acknowledge is asserted during a burst cycle 37.4.5.1 channel source address registers (sar0?sar15) each of the sar contains the dma cycle source address. the implementation must ensure that sar?s value is stored internally before use, to allow softwa re to modify the register value for dma chaining (see section 37.5, ?dma chaining ). the value should be stored when cen bit is set or at the end of the transfer when rpt bit is found set (before initiating the new tran sfer). if the memory direction bit (mdir) in the channel control register (ccr) is clear (indicating a memory address increment), then sar contains memory block start address. if mdir is set (indica ting a memory address decrement), then sar contains the memory block end address. 37.4.5.2 destination address registers (dar0?dar15) each of the dar contains the dma cycle destination address. the implementation needs to ensure that dar?s value is stored internally before use, to a llow software to modify th e register value for dma chaining (see section 37.5, ?dma chaining ?). the value should be stored when cen bit is set or at the end of the transfer when rpt bit is found set (befor e initiating the new transfer). if the memory direction bit (mdir) in the channel control register (ccr) is clear (indicating a memory address increment), then 0x1000_1080 (sar0) ? 0x1000_1440 (sar15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sa w reset0000000000000000 1514131211109876543210 r sa w reset0000000000000000 figure 37-18. channel source address register (sar0?sar15) table 37-16. channel source address register field description field description 31?0 sa source address. contains source address from where data is read during a dma transfer. dma will not perform misaligned accesses. that is to say, for 32-bit transfers, the lower two bits of this address are ignored. 8-bit accesses begins from the address in this register. software must take care if the system does not support non-word aligned accesses in this case. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-21 dar contains memory block start address. if mdir is set (indicating a memory address decrement), then dar contains the memory block end address. 37.4.5.3 channel count registers (cntr0?cntr15) the den bit in dcr should be set to enable writes to this register. the implementation needs to ensure that cntr?s value is stored internally before use, to allow software to modify the register value for dma chaining (see section 37.5, ?dma chaining ?). the value should be stored in an internal count register when cen bit is set or at the end of the transfer when rpt bit is found set (before initiating new transfer). each of the cntr contain the number of bytes of data to be transferred. there is an internal counter that counts up (number of bytes: 4 for word, 2 for hal f-word and 1 for byte) for every dma transfer. the internal counter is compared with the internal count register after every transfer. when the counter value matches with the register value, the channel is disabl ed until the cen bit is cleared and set again, or the rpt bit in the corresponding channel control register is se t to 1. the internal counter is reset to 0 when the channel is enabled again. the length of the last dma burst can be shorter than the regular burst length specified in the burst length register. however, when data is transferred out from an i/o fifo and the last burst is less than bl, the i/o device must generate a dma request for the last transf er. when data is transferred to an i/o fifo and the last burst is less than bl, only the re maining number of data is transferred. 0x1000_1084 (dar0) ? 0x1000_1444 (dar15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r da w reset0000000000000000 1514131211109876543210 r da w reset0000000000000000 figure 37-19. channel destination address registers (dar0?dar15) table 37-17. channel destination address registers field descriptions field description 31?0 da destination address. contains destination address to which data is written to during a dma transfer. dmac will not perform misaligned accesses. that is, for a 32-bit transfers, the lower two bits of this address are ignored. 8-bit accesses begin from the address in this register. software must take care if the system does not support non-word aligned accesses in this case. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-22 freescale semiconductor 37.4.5.4 channel control registers (ccr0?ccr15) each of the ccr controls and displays the status of that dma channel operation. dmac has the capability to perform burst transfers of byte and half word data types while sdram c ontroller and eim support is restricted to burst transfers of word (32-bit) data types. therefore, while using the dma in conjunction with sdram controller and eim, ensure that all bur st transfers to/from sdram controller and eim are of word data types. this is configured in th e dma channel control register. while choosing sdram memory as the source or destination addr ess, set sdramc and eim as a 32-bit port. 0x1000_1088 (cntr0) ? 0x1000_1448 (cntr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 cnt w reset0000000000000000 1514131211109876543210 r cnt w reset0000000000000000 figure 37-20. channel count registers (cntr0?cntr15) table 37-18. channel count registers field descriptions field description 31?24 reserved. these bits are reserved and should read 0. 23?0 cnt count. contains the number of bytes of data to be transferred during a dma cycle. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-23 0x1000_108c (ccr0) ? 0x1000_144c (ccr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00000000 w reset0000000 0 00000000 1514131211109 8 76543210 r0 acr pt dmod smod mdir msel dsiz ssiz ren rpt frc cen w reset0000000 0 00000000 figure 37-21. channel control registers (ccr0?ccr15) table 37-19. channel control registers field descriptions field description 31?15 reserved. these bits are reserved and should read 0. 14 acrpt auto clear rpt. this bit is to be sampled at the end of the transfer along with the rpt bit. when this bit and rpt are set, a new transfer is initiated and rpt is reset before issuing any interrupts. 0 do not modify rpt 1 reset rpt at end of current transfer. 13?12 dmod destination mode. selects the destination transfer mode. 00 linear memory 01 2d memory 10 fifo 11 reserved 11?10 smod source mode. selects the source transfer mode. 00 linear memory 01 2d memory 10 fifo 11 reserved 9 mdir memory direction. selects the memory address direction. note: when address increment is chosen, data transfer starts from the values in sar and dar. when address decrement is chosen, data transfer will be done till the addresses mentioned in sar and dar, that is, no data read or write will be done at the address mentioned in sar and dar. 0 memory address increment 1 memory address decrement 8 msel memory select. selects 2d memory register set when source and/or destination is programmed to 2d memory mode. 0 2d memory register set a selected 1 2d memory register set b selected direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-24 freescale semiconductor 7?6 dsiz destination size. selects the destination size of a data transfer. if number of bytes to be written is less than the dsiz setting, then only that many bytes will be valid in the dma write cycle to ahb. however all dma write cycles to the destination will be of dsiz size. dma always writes data as per dsiz in all modes, that is, linear memory, 2d memory and fifo mode. 00 32-bit destination port 01 8-bit destination port 10 16-bit destination port 11 reserved 5?4 ssiz source size. selects the source size of data transfer. 1. ssiz1:ssiz0 always reads/writes 00 when source mode is programmed as end-of-burst enable fifo, because end of burst operation only works for 32-bit fifo. 21. if the number of bytes to be read is less than the ssiz setting, then only that many bytes will be used by the dma. however, all dma read cycles to the source will be of ?ssiz? size. 32. dma always reads data as per ssiz in all modes, that is, eobe mode, linear memory, 2d memory and fifo mode. 00 32-bit source port 01 8-bit source port 10 16-bit source port 11 reserved 3 ren request enable. enables/disables the dma request signal. when ren bit is set, dma burst is initiated by the dma_req signal from the i/o fifo. when ren is cleared, dma transfer is initiated by cen. 0 disables the dma request signal (when the peripheral asserts a dma request, no dma transfer is triggered); dma transfer is initiated by cen only 1 enables the dma request signal (when the peripheral asserts a dma request, a dma transfer is triggered) 2 rpt repeat. this is a status/control bit. software has a priority and can write to this bit at any time. this bit enables/ disables the data transfer repeat function. when enabled and when the counter reaches the value set in internal count register: a. source address, destination address and count register values are stored (reloaded) for the next dma burst. b. if acrpt bit is set, rpt bit is cleared. c. next dma cycle is enabled. after this an interrupt is asserted, if the corresponding channel bit in the interrupt mask register is cleared. data transfer is carried out continuously until the channel is disabled or it completes the last dma burst after rpt is cleared. the status information in this bit is that it gets cleared when acrpt is set as described above. note: implementation must ensure that rpt bit is sampled only at the time the counter reaches the value in the internal count register before asserting the interrupt. rpt bit should be allowed to be modified at all other times by the software (for example in the interrupt subroutine). 0 disables repeat function 1 enables repeat function table 37-19. channel control registers field descriptions field description direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-25 37.4.5.5 channel request source select registers (rssr0?rssr15) each of the 64-bit rssr selects one of the 64 dma request signals (dma_req [63:0]) to initiate a dma transfer for the corresponding channel. 1 frc force a dma cycle. forces a dma burst to occur when dma cycle is software enabled or dma request is enabled. when frc bit is set, it will remain set till a dma burst for this channel starts as per channel priority, and will get cleared after the dma burst for the channel starts. when set, software will read this bit as?1? till it gets cleared automatically or cleared by software. 0 no effect 1 force dma cycle 0 cen dma channel enable. enables/disables the dma channel. note: to re-program a particular channel after completion of a dma cycle refer section 37.8, ?application note .? note: disabling cen during an ongoing burst on the ahb will stop the burst in between the transfer 0 disables the dma channel 1 enables the dma channel 0x1000_1090 (rssr0) ? 0x1000_1450 (rssr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00000000 w reset0000000 0 00000000 1514131211109 8 76543210 r0000000 0 00 rss w reset0000000 0 00000000 figure 37-22. channel request source select registers (rssr0?rssr15) table 37-20. channel request source select registers field descriptions field description 31?6 reserved. these bits are reserved and should read 0. 5?0 rssr request source select. selects 1 of the 64 dma_req signals that initiates dma transfer cycle for the channel. 000000 select dma_req [0] 000001 select dma_req [1] ... 011111 select dma_req [31] .... 111111 select dma_req [ 63] table 37-19. channel control registers field descriptions field description direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-26 freescale semiconductor 37.4.5.6 channel burst length registers (blr0?blr15) the blr controls burst length of a dma cycle. for a fifo channel setting, burst length is normally assigned according to fifo size of the selected i/ o device, or by fifo level at which its dma_req signal is asserted. for example, when uart rxd fifo is 12x8, and it asserts dma_req when it receives more than 8 bytes of data, bl is 8. when memory port size also is 8-bit, dma burst is 8-byte read followed by 8-byte write. when memory port access size is smalle r than i/o port access size, burst length of the byte write is doubled. for example, if i/o port is 32-bit a nd memory port is 16-bit, then burst length is set to 32. in this configuration, dma performs 8 word burst reads and 16 half-word burst writes for i/o to memory transfer. when burst length is not programmed as a multiple of access sizes of source and destination, refer section 37.9, ?dma burst termination ? for behavior of dma. 37.4.5.7 channel request time-out registers (rtor0?rtor15) rtor set the time-out for dma request from the ch annel?s selected request source, which detects any discontinuity of data transfer. the request time-out takes effect only when the corresponding request enable (ren) bit in the channel control register ( ccr) is set. an internal request time-out counter starts counting when dma channel is enabled and burst on that channel ends. internal request time-out counter is reset to zero when another burst for that channel starts. when counter reaches the count value set in this register, it asserts an interrupt (if it is not masked) and set its error bit in the dma request 0x1000_1094 (blr0) ? 0x1000_1454 (blr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00000000 w reset0000000 0 00000000 1514131211109 8 76543210 r0000000 0 00 bl w reset0000000 0 00000000 figure 37-23. channel burst length registers (blr0?blr15) table 37-21. channel burst length registers field descriptions field description 31?6 reserved. these bits are reserved and should read 0. 5?0 bl burst length. contains the number of data bytes that are transferred in a dma burst. 000000 64 bytes read follow 64 bytes write 000001 1byte read follow 1 byte write 000010 2 bytes read follow 2 bytes write .... 111111 63 bytes read follow 63 bytes write direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-27 time-out status register (rtosr). the input clock of the counter is selectable either from the system clock (hclk) or input crystal (clk32k). internal request time-out counter wi ll not generate an error status (or count) for the first burst of a dma cycle. it can be programmed to count (and can generate an error status as described above) for all other bursts in the dma cycle. note this register shares the same address as the bus utilization control register. 37.4.5.8 channel bus utilization control registers (bucr0?bucr15) bucr controls the bus utilization of an enabled channel when ren bit in channel control register (ccr) is cleared. the channel does not request a dma tran sfer until the internal bus_untilization_counter reaches 0x1000_1098 (rtor0) ? 0x1000_1458 (rtor15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00000000 w reset0000000 0 00000000 1514131211109 8 76543210 r en clk psc cnt w reset0000000 0 00000000 figure 37-24. channel request time-out registers (rtor0?rtor15) table 37-22. channel request time-out registers field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15 en enable. enables/disables the dma request time-out. 0 disables dma request time-out 1 enables dma request time-out 14 clk clock source. selects the counter of input clock source. 0 hclk 1 32.768 khz 13 psc prescaler count. sets the prescaler of input clock. 0divide by 1 1 divide by 256 12?0 cnt request time-out count. contains time-out count down value for internal counter in number of clocks. this value remains unchanged through out the dma cycle. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-28 freescale semiconductor the count value set in this register except for the very first burst. this counter is cleared when the channel burst is started. when this count value is set to zer o, dma carries on burst transfers one after another until it reaches the value set in channel count register (cntr) . in this case, user must be careful not to violate the maximum bus request latency of other devices. note the bucr0?bucr15 registers share the same address as the channel request time-out (rtor0?rtor15) registers. 37.4.5.9 channel counter registers (ccnr0?ccnr15) the ccnr indicates the number of bytes transferred for th e channel. it is reset to zero after channel is enabled and keeps incrementing for each transfer duri ng the dma burst. this counter will retain its value after the channel is disabled, till it is enabled again. if rpt bit is found set at the end of last burst of the dma cycle, this counter retains its value and will be reset to zero only at the start of another dma burst, that is, the first burst of new dma cycle. if a dma channel is disabled before completion of dma cycle, this counter will retain the value of the number of da ta transferred in that dma cycle. when the peripheral responds with a error response during a dma data transfer, ccnr value will not be increment for that ahb cycle as no data was transferred in that cycle. 0x1000_1098 (bucr0) ? 0x1000_1458 (bucr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00000000 w reset0000000 0 00000000 1514131211109 8 76543210 r bu_cnt w reset0000000 0 00000000 figure 37-25. channel bus utilizati on control register (bucr0?bucr15) table 37-23. channel bus utilization control register field descriptions field description 31?16 reserved. these bits are reserved and should read 0. 15?0 bu_cnt bus utilization clock count. sets the number of system clocks that must occur before the channel starts the next burst. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-29 37.5 dma chaining dma chaining refers to using the same dma channe l to automatically transfer a second data buffer (possibly of a different length) between another two se ts of source and destina tion addresses, with an increase in the allowable value of interrupt service time. this is possible because the isr execution (that is, the setup for next transfer) can occur in parallel to the next buffer transfer from the dma (when rpt bit is set). to achieve dma chaining: the sar, dar and cntr for each channel are double buffered internally. with this, the host can update these thre e register values during an ongoing dma transfer for the same channel in preparation for the next dma transfer. with the use of rpt and acrpt bits, the second transfer can occur for different source, de stination addresses and different amount of data. as an example, consider a data transfer of 14 k bytes from memory to a fifo using 4 kbyte buffers. ? driver writes 4 kbyte of data into buffer 1, sets source register to buffer 1 and count to 4 kbyte, sets acrpt, then enables the transfer. dma hardware will immediately latch the registers and start the transfer. ? driver immediately writes 4 kbyte of data into buffer 2, sets the same source register to buffer 2, count to 4 kbyte, and sets the rpt bit. ? transfer of buffer 1 completes, dma hardware samples the rpt bit, finds it set, latches the register (now set for buffer 2), clears the rpt bit because acrpt is set, and starts the next transfer. ? it then generates the 1st interrupt. 0x1000_109c (ccnr0) ? 0x1000_145c (ccnr15) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 ccnr[23:16] w reset0000000 0 00000000 1514131211109 8 76543210 r ccnr[15:0] w reset0000000 0 00000000 figure 37-26. channel counter register (ccnr0?ccnr15) table 37-24. channel counter register field descriptions field description 31?24 reserved. these bits are reserved and should read 0. 23?0 ccnr channel counter. indicates the number of bytes transferred for the channel. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-30 freescale semiconductor ? driver isr writes 4 kbyte of new data to buffer 1, sets the source register to buffer 1 and count to 4 kbyte, and sets the rpt bit again. ? transfer of buffer 2 completes, dma hardware samp les rpt bit, finds it se t, latches the registers (now set for buffer 1), clears the rpt bit because ac rpt is still set, and starts the next transfer. ? it then generates the 2nd interrupt. ? driver isr writes 2 kbyte of new data to buffer 2, sets the source register to buffer 2 and count to 2 kbyte, and sets the rpt bit again. ? transfer of buffer 1 completes, dma hardware samples the rpt bit, finds it set, latches the register (now set for buffer 2), clears the rpt bit because ac rpt is still set, and starts the next transfer. ? it then generates the 3rd interrupt. ? driver isr has no more da ta to send so does nothing. ? transfer of buffer 2 completes, dma hardware samples the rpt bit, finds it clear so it stops the transfer. ? it then generates the 4th interrupt. ? driver isr disables the dma and the transfer is complete. 37.6 special cases of burst length and access size settings dma burst length should normally be programmed as a multiple of source and destination access sizes. the following sections discuss the behavior that occurs when burst length is not a multiple of access size. 37.6.1 memory increment the following are the possible adverse effects: 1. unknown data can be written at some locations, however, there is no data loss. 2. number of bytes transferred can be more than the count value set. these effects are explained in the examples below: example 1: source is linear memory with access size of 1 byte. destination is linear memory with access size of 2 bytes. burst length is programmed as 3 bytes with memory increment. source address register: 0x0000_1000. destination address reg: 0x0000_2000. for the first burst, dma would read 3 bytes from addresses: 1000, 1001, and 1002. during the write cycle of first burst, dma would write 2 bytes each at addresses 2000 and 2002. one extra memory location (0x2003) is written with unknown data from the dma internal fifo (8?h00 after hardware reset). example 2: source is linear memory with access size of 2 bytes. destination is linear memory with access size of 2 bytes. burst length is programmed as 3 bytes with memory increment. source address register: 0x0000_1000. destination address reg: 0x0000_2000. for the first burst, dma would read 2 bytes each from addresses 1000 and 1002. during the writ e cycle of first burst, dma would write 2 bytes each at addresses 2000 and 2002. one extra data byte is transferred per burst. when programmed with a count of say 9 bytes, dma would perform data transfer of 12 bytes. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-31 37.6.2 memory decrement possible adverse effects: 1. unknown data can be written at some locati ons. in certain cases there can be data loss. example: source is linear memory with access size of 1 byte. destination is linear memory with access size of 2 bytes. burst length is programmed as 3 bytes with memory decrement. source address register: 0x0000_1000. destination address reg: 0x0000_2000. for the first burst, dma would read 3 bytes from addresses: 0ffd, 0ffe, and 0fff. du ring write cycle of the first burst, dma would write 2 bytes each at addresses 1ffc and 1ffe. an extra byte is written at the address 1fff with unknown data from the dma internal fifo (8?h00 after hardware reset). for the second burst, dma would read 3 bytes from the addresses: 0ffa, 0ffb, and 0ffc. during write cycle of the second burst, dma would write 2 bytes each at addresses 1ffa and 1f fc. in this case data written at 1ffc and 1ffd in the first burst have been overwritten. data wr itten at 1ffd will be unknown data from the dma internal fifo (8?h00 after hardware reset). note in the case of 2d memory writing extra bytes would mean writing beyond the limits of x-size programmed in a row. similarly for linear memory, this can lead data overflowing the allocated buffer for dma. 37.7 special cases when ccnr and cntr values differ there are two combinations of events that can cause the values of ccnr and cntr to differ. this situations are discussed in detail in the following sections. 37.7.1 cntr not a multiple of destination access size if cntr register value is not a multiple of destination access size, then ccnr value will not match the value programmed in cntr after completion of the dma cycle for the channel. table 37-25 illustrates the values of ccnr with different combinations of source and destination access sizes when cntr = 5 bytes. this table holds good when bl = 3 bytes or bl = 4 bytes. table 37-25. cnnr value combinations source size (bytes) destination size (bytes) no. of bytes read by dma no. of bytes written by dma ccnr (bytes) memory increment memory decrement memory increment memory decrement 22 6 6 6 6 6 44 8 8 8 8 8 24 6 6 8 8 8 42 8 8 6 6 6 12 5 5 6 6 6 14 5 5 8 8 8 direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-32 freescale semiconductor 37.7.2 bl is not a multiple of destination access size, cntr is if bl register value is not a multiple of destination acc ess size but cntr is, then the value of ccnr will not match the value programmed in cntr afte r completion of dma cycle for the channel. table 37-26 illustrates the values of ccnr with different combin ations of source and destination access sizes when bl = 3 bytes and cntr = 4 bytes. note in case of memory decrement there might be some cases where dma overwrites data written by itself so the number of bytes seen by the user can be different than those mentioned in the tables above. 37.8 application note following is the sequence to re-progr am a channel for data transfer: 1. clear the status register bit corresponding to that channel (disr, dbtosr, dsesr, drtosr, dbosr) after the dma cycle is completed. 2. change smod (source mode) to 2?b00 and clear cen. 3. re-program all registers corresponding to that particular channel, except ccr. 4. program ccr and set cen bit to 1. note this sequence applies to all 16 channels in all modes: linear memory, 2d memory, and fifo. 37.9 dma burst termination dma controller needs to terminate its burst in case of: ? transfer error response from slave ? burst time-out error. ? buffer overflow error. table 37-26. ccnr value combinations source size (bytes) destination size (bytes) no. of bytes read by dma no. of bytes written by dma ccnr (bytes) memory increment memory decrement memory increment memory decrement 22 6 6 6 66 44 8 8 8 88 24 6 6 8 88 42 8 8 6 66 12 4 4 6 66 14 4 4 8 88 direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 37-33 ? channel disable (by software using cen bit). caution dma burst termination may not occur immediately. burst termination occurs immediately in dmac only on occurrence of transfer error response from the slave. in other cases, burst time-out, buffer overf low and channel disable (by software using cen bit) takes about 2 more ahb transfers to terminate the bur st after these are sensed. the burst termination is not done immediately to avoid ahb protocol violation. in case the burst hangs and hready is not asserted for a large number of cycles, then this must be handled by the watchdog timer in the abcd module in i.mx27 device or by the system software. 37.10 glossary of terms used dma burst this refers to the burst cycles on the ahb bus performed by the dma. dma cycle dma cycle can consists of a number of dma bursts depending on the channel burst length and channel count register settings. for example, if bl = 4 and cntr = 8, then dma cycle will consist of 2 dma bursts. direct memory access controller (dmac) MCIMX27 multimedia applications processor reference manual, rev. 0.2 37-34 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 1 book ii, part 7: multimedia peripherals introduction chapter 38, ?digital audio mux (audmux) ,? on page 38-1 chapter 39, ?cmos sensor interface (csi) ?, on page 39-1 chapter 40, ?video codec (video_codec) ,? on page 40-1 chapter 41, ?enhanced multimedia accelerator light (emma_lt) ,? on page 41-1 chapter 42, ?synchronous serial interface (ssi) ,? on page 42-1 chapter 43, ?liquid crystal display controller (lcdc) ,? on page 43-1 chapter 44, ?smart liquid crystal display controller (slcdc) ,? on page 44-1 cmos sensor interface (csi) this section presents the cmos sensor interface (csi) on the architecture, operation principles, and programming model. the csi is a logic interface which enables the i.mx27 to directly connect to external cmos sensors and ccir656 video source. digital audio mux (audmux) the digital audio mux (audmux) provides a programma ble interconnect fabric for voice, audio, and synchronous data routing between host serial interfaces (for example, ssi or sap) and peripheral serial interfaces (for example, audio and voice codecs). the audmux allows the audio system connectivity to be modified through programming (as opposed to altering the pcb schematics of the system). the digital audio mux is configured by software. with the audmux, resources do not need to be hard-w ired and can be effectively shared in different configurations. the audmux interconnections allow mu ltiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. the audmux includes two types of interfaces. internal ports connect to the processor serial interfaces and external ports connect to off-chip audio devices and serial interfaces of other processors. a desired connectivity is achieved by configuring the appropriate internal and external ports. enhanced multimedia accelerator light (emma_lt) the enhanced multimedia accelerator light (emma_lt) cons ists of the video pre-processor (prp) and post-processor (pp), similar functionalities with original emma which also includes mpeg4 encoder MCIMX27 multimedia applications processor reference manual, rev. 0.2 2 freescale semiconductor (en) and decoder (de). these blocks work together to provide video acceleration and off-load the cpu from computation intensive tasks. the prp and pp ca n be used for generic video pre and post processing such as scaling, resizing, and color space conversions. synchronous serial interface (ssi) the ssi is a full-duplex, serial port that allows the ch ip to communicate with a va riety of serial devices. these serial devices can be standard codecs, di gital signal processors (dsps), microprocessors, peripherals, and popular industry audio codecs that implement the inter-ic sound bus standard (i2s) and intel ac97 standard. ssi is typically used to transfer samples in a period ic manner. the ssi consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. the ssi contains independent (asynchronous) or shar ed (synchronous) transmit and receive sections with separate or shared internal/external clocks and fram e syncs, operating in master or slave mode. the ssi can work in normal mode operation using frame sync and in network mode operation allowing multiple devices to share the port with as many as thirty-two time slots. the ssi provides 2 sets of transmit and receive fifos. each of the four fifos is 8x24 bits. th e two sets of tx/rx fifos can be used in network mode to provide 2 independent channels for trans mission and reception. it also has programmable data interface modes such like i2s, lsb, msb aligned a nd programmable word lengths . other program options include frame sync and clock generation and prog rammable i2s modes (master, slave or normal). oversampling clock, ccm_ssi_clk available as output from srck in i2s master mode. in addition to ac97 support the ssi has completely se parate clock and frame sync selections for the receive and transmit sections. in ac97 standard, the cloc k is taken from an external source and frame sync is generated internally. the ssi also has a progra mmable internal clock divider and time slot mask. liquid crystal display controller (lcdc) the liquid crystal display controller (lcdc) provides di splay data for external gray-scale or color lcd panels. the lcdc is capable of supporting black-and- white, gray-scale, passive -matrix color (passive color or cstn), and active-matrix color (active color or tft) lcd panels. smart liquid crystal display controller (sldc) the smart liquid crystal display controller module transfers data from the display memory buffer to the external display device. direct memory access (dma) transfers the data transparently with minimal software intervention. bus utilization of th e dma is controllable and deterministic. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-1 chapter 38 digital audio mux (audmux) the digital audio mux (audmux) provides a programma ble interconnect fabric for voice, audio, and synchronous data routing between the i.mx27 device ssi modules and an external ssi, or between audio and voice codecs. with the audmux, resources do not need to be hard-wired and can be effectively shared in different configurations. the audmux inte rconnections allow multiple simultaneous separate audio/voice/data flows between the ports in a point -to-point or point-to-mu ltipoint configuration. 38.1 features the digital audio mux offers the following features: ? three host interfaces (two internal and one external) ? three peripheral interfaces (all external) ? full 6-wire ssi interfaces for asynchronous receive and transmit ? configurable 4-wire, synchronous or 6-wire asyn chronous rx and tx external host and peripheral interfaces ? independent frame sync and clock direction sel ection for host or peripheral. clock direction selection to function as master of the flow ? each host interface can be connected to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode) ? transmit and receive data switchi ng to support external network mode 38.2 overview figure 38-1 shows the block diagram of the audmux. on the left of the illustration are the internal interfaces and on the right, the external interfaces. port 1 and port 2 are internally connected to ssi-1 and ssi-2, respectively, and port 3 has special muxes allowing connection to an external ssi, such as a synchronous audio port (sap) commonly found on a base band modem. ports 4?6 are identical and can be connected to any 4-wire or 6-wire ssi, voice, i 2 s or ac97 codec. ports 1?3 are also known as host ports, and ports 4?6 as peripheral ports. port 1?port 6 have configurable 4-wire or 6-wire in terfaces. when configured as a 6-wire interface, the additional rfs and rclk signals of the interface enable the ssis to be used in asynchronous mode with separate receive and transmit clocks. in this mode, a device at one port can be connected to two ports (internal or external) configured as input only (simp lex) and output only (simplex). ports 1?3 have muxing arrangements to support internal network mode. po rts 3?6 have a tx/rx switch to support external network mode. the tx/rx switch enables the da and db lines to be swapped so that more than one master connected to any of ports 1?3 can communicate to more than one slave externally attached at the external ports. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-2 freescale semiconductor bit clock selection direction enables each port to be configured as a master or slave in the flow. possible scenarios are as follows: 1. ssi1 (internal host port) drives voice codec and bt (on external peripheral port 6) and the bottom connector (on external peripheral port 5) simultan eously using network mode. ssi1 is the master. 2. sap (external audio port from ba seband) drives voice codec and bt (on port 6) and the bottom connector (on port 5) simultaneously using network mode. sap is the master. note the first scenario supports external network mode when ssi1 provides the corresponding output enables for txdata , and the slave devices receiving the data must be configured to only receive in their corresponding time slot. in the second case, any slave devices a ttached locally to the sap in network mode must be disabled to access slave devices on the other ports (for example, ssi, voice codec, and/or bt). frame sync and bit clock selections enable each port to be configured as a master or slave in the flow. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-3 figure 38-1. audmux block diagram rxdsel[3:0] inmen 0 1 1 txd_obe to tx/rx switch txd_obe1 txd_obe 5 port 1 port 2 x txdn_obe txrxen3 txdn_in rxd_in rxdsel3[3:0] x txdn_obe txrxen4 txdn_in rxd_in rxdsel4[3:0] txd_out rfcsel4[3:0] rfcsel3[3:0] rfcsel5[3:0] rfcsel6[3:0] x txdn_obe txrxen5 txdn_in rxd_in rxdsel5[3:0] x txdn_obe txrxen6 txdn_in rxd_in rxdsel6[3:0] rfcsel2[3:0] tfcsel2[3:0] tfs2, tclk2 txd2 inmen rxdsel2[3:0] rfcsel2[3:0] tfcsel2[3:0] inmen rxdsel2[3:0] fsns, clkns txdn, rxdn fs6, clk6 da4 db4 fs5, clk5 fs4, clk4 da3 db3 fs3, clk3 da5 db5 da6 db6 rfs2, rclk2 rxd2 tfs1, tclk1 txd1 rfs1, rclk1 rxd1 port 3 port 4 port 5 port 6 txd_obe mux for port3 digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-4 freescale semiconductor 38.3 internal network mode figure 38-2 shows the internal network mode selection l ogic. network mode is where a master ssi is connected to more than one slave ssi device a nd communication occurs on a time-slotted frame. though network mode allows communication between master-sla ve and slave-slave, the internal network mode supports only master-slave network mode. in internal network mode (inmen=1), the output of th e and gate is routed to the output of the port and to the rxd signal of the ssi. the inmmask bit vector selects the transmit signals of the ports that are to be connected in network mode. th e transmit signals (txd_in from ssi and rxd_in from external ports) are anded together to form the output. in network mode, only one device can be transmitting in its predesignated timeslot and all other transmit signals will remain high (tri-s tated and pulled-up), hence non-active signals in the selection will be high and do not influence the output of the and gate. in normal mode (inmen=0), the ssi is connected in point to point (as a master or slave) and the rxdsel[2:0] settings select the transmit signal from the other ports. internal network mode can be used with external network as long as slave-only devices are attached in external netw ork mode at a port or in. internal network mode can also be used with extern al network mode if all slave devices connected to a master in external network mode are disabled. figure 38-2 shows the connections for port 1. figure 38-2. internal network mode 38.4 tx/rx switch and external network mode external network mode is the traditional network mode connection. it is called ex ternal network mode to differentiate from the internal network mode. in ex ternal network mode, devices are connected to the external ports in a star or multidrop configuration. txd2_in rxd3_in rxd4_in rxd5_in rxd6_in audmux boundary inmmask[4:0] inmen 1 0 rxdsel1[2:0] 0 1 1 inmmask[n] txd2_in/rxdn_in rxd internal network mode selection matrix (port1) digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-5 in network mode, there can be only one master (fram e sync and clock source) and the other devices are configured in normal slave mode or network slave mode. unlike internal network mode, in external network mode both master-slave and slave-slave comm unication can take place. codec devices transmit on a single timeslot and ssis in network master (for example sap) or slave mode (ssi-2) can process more than one timeslot of data. figure 38-3 shows the tx/rx switch. txd_obe is the output buffer enable signal and txd_out is the data transmit signal from the internal ssi. the rxd_in signal is the receive data signal going towards the rxdsel and txdsel muxes of the ssi ports and external ports. in normal mode and network slave mode, txrxen is disabled (txrxe n=0) and txd_out is routed to da (da_out) and db (db_in) is routed to rxd_in. in normal mode, the output buffer enable, da_obe is always enabled (asserted) and txd_out is routed to da_out. in network mode, the txd_obe signal is enabled during the ssi?s timeslot(s) and the da output is tri-stated in other timeslots. in network mode (ssix as master), the tx/rx switch is enabled (txrxen=1) and txd_out is routed to db_out and da_in is routed to rxd_in. the txd_obe signal is enabled during the ssi?s timeslot(s) and the db output is tristated in other timeslots. figure 38-3. tx/rx switch 38.5 frame sync and clocks the routing of frame syncs and interface clocks are shown in figure 38-4 . da db pin interface boundary 0 1 0 1 0 1 txrxen iopad txrx switch iopad da_out da_in db_out db_in da_obe db_obe txd_obe txd_out rxd_in audmux boundary digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-6 freescale semiconductor figure 38-4. frame sync and clock routing when peripheral port is 4-wire 38.6 synchronous mode (4-wire interface) in synchronous mode the port will have a 4-wire interface?that is, rxd,txd,txclk,txfs.the receive clock and the receive frame sync will be the same as transmit clock (txclk) and transmit frame sync (txfs), respectively. rfcselx[3:0] rfcselx[3:0] tfs_in tfs_out rfs_in rfs_out rfs_obe tfs_obe tfcsely[3:0] fs_obe fs_out fs_in iopad tfsn_obe, tfsn_in, rfsn_obe, to/from other ports rfcselx[3:0] rfcselx[3:0] tclk_in tclk_out rclk_in rclk_out rclk_obe tclk_obe tfcsely[3:0] clk_obe clk_out clk_in iopad tclkn_obe, tclkn_in, rclkn_obe to/from other ports rclkn_in and clkn_in rfsn_in and fsn_in txfs txclk audmux boundary audmux boundary pin boundary porty portx digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-7 as shown in figure 38-4 , portx signals can be routed to porty, showing a 6-wire to 4-wire port connectivity. tfs_in, rfs_in, tclk_in, and rclk_in are input fram e sync and bit clocks from the ssi with their corresponding output buffer enable signals (_obe). tfs_out, rfs_out, tclk_out, and rclk_out are the frame sync and bit clocks that are transmitted to the ssi from the other ports. tfs_out and tclk_out are selected by the tfcs el mux settings and rfs_out and rclk_out are selected by the rfcsel mux settings. similarly, in the external direction, the tfcsel selects the fs_obe and fs_out signals. in this mode rfcsel is not used. 38.7 asynchronous mode (6-wire interface) in asynchronous mode the port will have a 6-wire interface?that is, rxd, txd, txclk, txfs, rxclk, rxfs. there will be additional receive clock (rxclk) and the frame sync (rxfs) pins as compared to the synchronous or 4-wire interface. refer to figure 38-5 and figure 38-6 , portx signals can be routed to porty, depicting a 6-wire to 6-wire port connectivity. tfs_in, rfs_in, tclk_in and rclk_in are input frame sync and bit clocks from the ssi (portx) with their corresponding output buffer enable signals (_obe). tfs_out, rfs_out, tclk_out, and rclk_out are the frame sync and bit clocks that are transmitted to the ssi from the other ports. tfs_out and tclk_out are selected by the tfcs el mux settings and rfs_out and rclk_out are selected by the rfcsel mux settings. similarly, in the external direction, the tfcsel selects the txfs_obe, txfs_out and txclk_obe, txclk_out signals. the rfcsel selects the rxfs_obe and rxfs_out and rxclk_obe, rxclk_out. note noticed that because fs_in and clk_in from external interfaces are also routed to the tfcsel muxes of the external ports, these signals do not have corresponding buffer enable signals. consequently, their corresponding inputs to the tfcsel mux of the external ports must be tied high. 38.8 ssi to peripheral connection the figure 38-7 shows the data path interconne ctions between an internal ssi port and a peripheral port. txd_obe is the buffer enable signal from the ssi, txd_in, the input transmit data from the ssi and rxd_out, the receive data output from the audmxux to the ssi. txdsel[2:0] of the peripheral port, selects the buffe r enable signal (txd_obe) and transmit data output (txd_out) signal from the txd_obe and txd_in and rxd_in signals. txdsel[2:0] is a common signal to both selection muxes. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-8 freescale semiconductor note because rxd_in signals from external interfaces do not have their buffer enable signals, their corresponding buffer enable signals into the selection mux should be tied to high. this will ensure that selection of rxd_in as txd_out will also drive the txd_obe output high. transmit data from the ssi goes into the txdsel data mux and comes out as txd_out and is routed to da_out when txrxen is disabled and to db_out when txrxen is enabled. similarly, db_in is routed to rxd_in when txrxen is disabled and da_in is routed to rxd_in when txrxen is enabled. if the routing of frame syncs are shown in figure 38-5 and the routing of interface clocks are shown in figure 38-6 . digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-9 figure 38-5. frame sync routing when peripheral port is 6-wired tfcselx[3:0] rfcselx[3:0] tfs_in tfs_out rfs_in rfs_out rfs_obe tfs_obe tfcsely[3:0] tfs_obe tfs_out tfs_in iopad tfsn_obe, tfsn_in, rfsn_obe, to/from other ports tfcselx[3:0] rfcselx[3:0] tfs_in tfs_out rfs_in rfs_out rfs_obe tfs_obe rfcsely[3:0] rfs_obe rfs_out rfs_in iopad tfsn_obe, tfsn_in, rfsn_obe to/from other ports rfsn_in and fsn_in rfsn_in and fsn_in txfs rxfs audmux boundary audmux boundary pin boundary porty portx digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-10 freescale semiconductor figure 38-6. clock routing when peripheral port is 6-wired if internal network mode is disabl ed, then rxdsel selects the rxd_in which is then output from the audmux to the ssi. when internal network mode is selected, the rxd_in is anded with other txd_in and rxd_in signals from other ports before output as rxd_out to the ssi. tfcselx[3:0] rfcselx[3:0] tclk_in tclk_out rclk_in rclk_out rclk_obe tclk_obe tfcsely[3:0] tclk_obe tclk_out tclk_in iopad tclkn_obe, tclkn_in, rclkn_obe, to/from other ports tfcselx[3:0] rfcselx[3:0] tclk_in tclk_out rclk_in rclk_out rclk_obe tclk_obe rfcsely[3:0] rclk_obe rclk_out rclk_in iopad tclkn_obe, tclkn_in, rclkn_obe to/from other ports rclkn_in and clkn_in rclkn_in and clkn_in txclk rxclk audmux boundary audmux boundary pin boundary porty portx digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-11 if there are more than one device attached to the ex ternal port at da and db interfaces and one of the devices is a network master, then two conditions have to be noted: a) when the external master is enabled in network mode, then the ssi must be configured as slave (normal or network mode). no tx/rx switching is required. b) when the external master is disabled and the ssi and other slave devices require to communicate, then the ssi must be configured as network mode master and the tx/rx switch must be enabled (txrxen=1). this ensures that the transmit and receive paths are connected appropriately. to communicate with more than one port, internal network mode must be enabled at the ssi port. in internal network mode, it is possible to communicate with any device attached to the other ports. internal network mode must be enabled at the por t that is the ssi network mode master. 38.9 ssi to sap the figure 38-8 shows the detailed interconnection of a ssi port to a sap port. the ssi and sap port can act as masters or slaves and be configured in normal or network mode. the sap port can communicate with more than one external device attached to its own interface in external network mode and additionally with one device attached to another audmux port. if the sap must communicate with more than one port, then the internal network mode must be enabled. 38.10 peripheral port to peripheral port peripherals attached to the audmux can communicate with each other in 2 ways: a) one peripheral acts is configured as master a nd which sources the clock and/or the frame sync and the other peripheral is configured as slave. b) both peripherals are configured as slaves but with data routing established from external port to external port with one additi onal port configured as master (ssi or sap), which sources the frame sync and clock to the two ports. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-12 freescale semiconductor figure 38-7. ssi to peripheral port interconnection da db pin boundary 0 1 0 1 0 1 txd_obe txd_out rxd_in txrxeny iopad txrx switch iopad audmux boundary txd_obe txd_in rxd_out inmenx 0 1 rxdselx[3:0] rxdsely[2:0] inmmaskx[7:0] da_out da_obe da_in db_obe db_out db_in txdn_in, rxdn_in, txdn_obe to/from other ports audmux boundary porty portx digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-13 figure 38-8. ssi to sap interconnection da db pin boundary 0 1 0 1 txd_obe txd_out rxd_in txrxeny iopad txrx switch iopad audmux boundary txd_obe txd_in rxd_out inmenx 0 1 rxdselx[3:0] rxdsely[2:0] inmmaskx[7:0] da_out da_obe da_in db_obe db_out db_in txdn_in, rxdn_in, txdn_obe to/from other ports audmux boundary 0 1 inmeny inmmasky[7:0] porty portx 0 1 digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-14 freescale semiconductor 38.11 memory map and register definition there is one configuration register per host port and per peripheral port. the audmux has a total of 6 registers. table 38-3 shows the control register summary and address mapping for audmux. the base address is 0x1001 6000. 38.11.1 audmux memory map table 38-1 shows the audmux memory map. 38.11.2 register summary figure 38-9 shows the key to the register fields, and table 38-2 shows the register figure conventions. figure 38-9. key to register fields table 38-1. audmux memory map address use access reset value section/page 0x1001_6000 (hpcr1) host port configuration register 1 r/w 0x0000_0000 38.11.3/38-16 0x1001_6004 (hpcr2) host port configuration register 2 r/w 0x0000_0000 38.11.3/38-16 0x1001_6008 (hpcr3) host port configuration register 3 r/w 0x0000_0000 38.11.3/38-16 0x1001_6010 (ppcr1) peripheral port configuration register 1 r/w 0x0000_1000 38.11.4/38-18 0x1001_6014 (ppcr2) peripheral port configuration register 2 r/w 0x0000_1000 38.11.4/38-18 0x1001_601c (ppcr3) peripheral port configuration register 3 r/w 0x0000_1000 38.11.4/38-18 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 38-2. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-15 table 38-3 shows the audmux register summary. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 38-3. audmux register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1001_6000 (hpcr1) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 00 0 inmen inmmask[7:0] w 0x1001_6004 (hpcr2) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 00 0 inmen inmmask[7:0] w 0x1001_6008 (hpcr3) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 0 txr xen 0 inmen inmmask[7:0] w 0x1001_6010 (ppcr1) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 0 txr xen 0000000000 w 0x1001_6014 (ppcr2) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 0 txr xen 0000000000 w table 38-2. register figure conventions (continued) convention description digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-16 freescale semiconductor 38.11.3 host port configuration register (hpcr1?2) there is one host port configuration register (hpcr) for each host port. 0x1001_601c (ppcr3) r tfs dir tc lk dir tfcsel[3:0] rfs dir rclkdi r rfcsel[3:0] 0000 w r rxdsel[2:0] sy n 0 txr xen 0000000000 w 0x1001_6000 (hpcr1) 0x1001_6004 (hpcr2) 0x1001_6008 (hpcr3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tfs dir tclk dir tfcsel rfs dir rclk dir rfcsel 0 000 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rxdsel syn 0 txrx en 0 inme n inmmask w reset00000000000000 00 figure 38-10. host port configuration register (hpcr1?2) table 38-4. host port configuration register field descriptions field description 31 tfsdir transmit frame sync direction control. this bit sets the direction of the txfs pin of the interface as output or input.when set as input, the tfcsel settings are ignored.when set as output, the tfcsel settings determine the source port of the frame sync. 0 txfs is input pin. 1 txfs is output. 30 tclkdir transmit clock direction control. this bit sets the direction of the txclk pin of the interface as output or input.when set as input, the tfcsel settings are ignored.when set as output, the tfcsel settings determine the source port of the clock. 0 txclk is input pin. 1 txclk is output. table 38-3. audmux register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-17 29?26 tfcsel transmit frame sync and clock select. selects the source port from which txfs and txclk are sourced. 0xxx selects txfs and txclk from port 1xxx selects rxfs and rxclk from port 000 101 port 1?port 6 110 reserved 111 reserved 25 rsfdir receive frame sync direction control. this bit sets the direction of the rxfs pin of the interface as output or input.when set as input, the rfcsel settings are ignored.when set as output, the rfcsel settings determine the source port of the frame sync. 0 rxfs is input pin. 1 rxfs is output. 24 rclkdir receive clock direction control. this bit sets the direction of the rxclk pin of the interface as output or input.when set as input, the rfcsel settings are ignored.when set as output, the rfcsel settings determine the source port of the clock. 0 rxclk is input pin. 1 rxclk is output. 23?20 rfcsel receive frame sync and clock select. selects the source port from which rxfs and rxclk are sourced. rxfs and rxclk can be sourced from txfs and txclk, respectively, from other ports. 0xxx selects txfs and txclk from port 1xxx selects rxfs and rxclk from port 000?101 port 1?port 6 110 reserved 111 reserved 19?16 reserved. these bits are reserved and should read 0. 15?13 rxdsel receive data select. selects the source port for the rxd data. rxdsel is ignored if inmen is enabled. xxx port number for rxd, ignored if equal to self port number 000?101 port 1?port 6 110 reserved 111 reserved 12 syn synchronous/asynchronous select. when syn is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. that is, the port is a 4-wire interface. when syn is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections. that is, the port is a 6-wire interface. 0 asynchronous mode 1 synchronous mode (default) 11 reserved. this bit is reserved and should read 0. 10 txrxen transmit/receive switch enable. swaps the transmit and receive signals from (da-txd, db-rxd) to (da-rxd, db-txd) note: present only in port 3 0no switch 1switch 9 reserved. this bit is reserved and should be read as 0. table 38-4. host port configuration register field descriptions (continued) field description digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-18 freescale semiconductor 38.11.4 peripheral port configuration registers (ppcr1?2) there is one peripheral port configuration register (ppcr) for each peripheral port. 8 inmen internal network mode enable. rxd from ports in internal network mode are anded together. rxdsel is ignored. inmmask determines which rxd signals are anded together. when internal network mode is enabled at port 3, then rxdsel3[3:0] for txdn_obe selection is ignored and txd_obe is always driven high. that is, asserted for all timeslots. this places a restriction on slave devices connected in external network mode such that these slave devices have all to be disabled. see figure 38-16 . 0 disable 1 enable internal network mode 7?0 inmmask internal network mode mask. bit mask that selects which of the rxd signals from ports are to be anded together for internal network mode. bit 7 represents rxd from port 8 and bit 0 represents rxd from port 1. note: bit in self port position should be set as 1. 0 include rxdn for anding. 1 excludes the rxdn from anding. 0x1001_6010 (ppcr1) 0x1001_6014 (ppcr2) 0x1001_601c (ppcr3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tfs dir tclk dir tfcsel rfs dir rclk dir rfcsel 00 00 w reset00000 0 00 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rxdsel syn txrxen 00 0 0 000000 w reset00010 0 00 0 0 000000 figure 38-11. peripheral port configuration registers (ppcr1?2) table 38-4. host port configuration register field descriptions (continued) field description digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-19 table 38-5. peripheral port configuration register field descriptions field description 31 tfsdir transmit frame sync direction control. this bit sets the direction of the txfs pin of the interface as output or input.when set as input, the tfcsel settings are ignored.when set as output, the tfcsel settings determine the source port of the frame sync. 0 txfs is input pin. 1 txfs is output. 30 tclkdir transmit clock direction control. this bit sets the direction of the txclk pin of the interface as output or input.when set as input, the tfcsel settings are ignored.when set as output, the tfcsel settings determine the source port of the clock. 0 txclk is input pin. 1 txclk is output. 29?26 tfcsel transmit frame sync and clock select. selects the source port from which fs_obe, fs_out, clk_obe, and clk_out are sourced. 0xxx selects txfs and txclk from port 1xxx selects rxfs and rxclk from port xxx selection ignored if self-port number 110 reserved 111 reserved 25 rsfdir receive frame sync direction control. this bit sets the direction of the rxfs pin of the interface as output or input.when set as input, the rfcsel settings are ignored.when set as output, the rfcsel settings determine the source port of the frame sync. 0 rxfs is input pin. 1 rxfs is output. 24 rclkdir receive clock direction control. this bit sets the direction of the waxlike pin of the interface as output or input.when set as input, the rfcsel settings are ignored.when set as output, the rfcsel settings determine the source port of the clock. 0 rxclk is input pin. 1 rxclk is output. 23?20 rfcsel receive frame sync and clock select. selects the source port from which rxfs and rxclk are sourced. rxfs and rxclk can be sourced from txfs and txclk, respectively, from other ports. 0xxx selects txfs and txclk from port 1xxx selects rxfs and rxclk from port 000?101 port 1?port 6 110 reserved 111 reserved 19?16 reserved 15?13 rxdsel receive data select. selects the source port for the rxd data (txd_in or rxd_in). rxdsel is ignored if inmen is enabled. xxx port number for txd_in or rxd_in, ignored if equal to self port number 110 reserved 111 reserved 12 syn synchronous/asynchronous select. syn controls whether the receive and transmit functions of the port occur synchronously or asynchronously with respect to each other. when syn is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. that is, the port is a 4-wire interface.when syn is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections; that is, the port is a 6-wire interface. 0 asynchronous mode 1 synchronous mode (default) digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-20 freescale semiconductor 38.12 peripheral connectivity through audmux configuration this section describes some of the peripheral connectivity scenario s through audmux configuration and some limitations. 38.12.1 generic configuration figure 38-12 shows a general configuration of the audmux. it does not show what paths are enabled or possible. 11 reserved. these bits are reserved and should read 0. 10 txrxen transmit/receive switch enable. swaps the transmit and receive signals from (da-txd, db-rxd) to (da-rxd, db-txd). 0no switch 1switch 9?0 reserved. these bits are reserved and should read 0. table 38-5. peripheral port configuration register field descriptions (continued) field description digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-21 figure 38-12. sap as master to ssi2 as slave interconnection only ports 1, 2, 3 are capable of internal network m ode. only ports 3, 4, 5, 6 are capable of tx/rx switch. where internal network mode is enabled, for example at port 1, then port 1 is referred to as the egress port. therefore, ports 1, 2, and 3 become egress ports when internal network mode is enabled at that port. ? config1: only slave devices are connected in network mode. ? config2: one master/slave capable device with slave only devices. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-22 freescale semiconductor figure 38-13. configuration overview 38.12.2 audmux configuration with ssi1 and sap as master figure 38-14 shows two possible audio paths that can be configured simultaneously. ssi-1 slave slave slave slave slave slave sap audmux module ssi-2 (slave) port 1 port 2 port 3 port 4 port 5, 6 master/ slave device capable of master or slave mode slave slave only device internal network mode tx/rx switch digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-23 figure 38-14. ssi1 as master in internal network mode audio path 1: ? the above configuration shows, ss1-1 configured as master communicating to slaves on ports 4, 5, and 6. ? port 1 internal network mode is enabled hence it is the egress port. audio path 2: ? the sap (audio port from the base band) is connected to slave por ts and ssi-2. tx/rx switch is not enabled, neither is internal network mode. ? ssi-2 (internal to the i.mx27 device) is connected as slave. 38.12.3 tx-rx switch enabled figure 38-15 audmux configuration with ssi-1 as the master of the flow. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-24 freescale semiconductor figure 38-15. tx-rx switch restriction flow: ? ssi-1 is the master that is connected to all peripheral ports. ? internal network mode is enabled at po rt 1 to receive data from ports 3, 4, 5, 6. ? tx/rx switch is enabled only at port 3 to maintain signal directions to be consistent for slaves on port 3. ? the sap (audio port from the baseba nd) master must be disabled because its tx and rx signals will not be consistent. ? though disabling the sap master, apparently, make s config2 into config1, signal directions are not the same as config1, hence the requirement for the tx/rx switch. 38.12.4 internal/external network mode figure 38-16 shows the limitation posed by internal network mode. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 38-25 figure 38-16. internal and external mode restriction ? in this flow, the sap (audio port from the baseband) is now the master and internal network mode is enabled at port 3. ? port 3 is now an egress port for receive data coming from the other ports. ? the locally attached slave devices have to be disabled because the internal network mode will always drive the output at the egress port regardless of timeslots that will cause a multiple driver conflict with slave transmi ssion at port 3, otherwise. ? disabling of slave devices in config2 effectively re moves external network mode at port 3. this is what is meant by internal network mode cannot be used with external network mode. digital audio mux (audmux) MCIMX27 multimedia applications processor reference manual, rev. 0.2 38-26 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-1 chapter 39 cmos sensor interface (csi) this chapter presents the cmos sensor interf ace (csi) architecture, operation principles, and programming model. the csi enables the i.mx21 to conne ct directly to external cmos image sensors. cmos image sensors are separated in to two classes, dumb and smart. dumb sensors are those that support only traditional sensor timing (vertical sync and horizontal sync) and output only bayer and statistics data, while smart sensors support ccir656 video dec oder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats). the capabilities of the csi include: ? configurable interface logic to support most commonly available cmos sensors. ? support for ccir656 video interface as we ll as traditional sensor interface. ? 8-bit data port for ycc, yuv, bayer, or rgb data input. ? full control of 8-bit and 16-bi t data to 32-bit fifo packing. ?32 32 fifo to store received image pixel data that can be read through programmed io or dma. ? direct interface to emma preprocessing block (prp). ? single interrupt source to interrupt controller fro m maskable sensor interr upt sources: start of frame, end of frame, change of field, fifo full. ? configurable master clock frequency output to sensor. ? statistic data generation for auto exposure (ae) and auto white balance (awb) control of the camera (for bayer data only). 39.1 csi architecture figure 39-5 shows the block diagram of the cmos sensor interface. it consists of 2 control registers (control register 1 and 3) to set up the interface timi ng and interrupt generation, a control register (control register 2) for statistic data generation, a status re gister, interface logic, data packing logic, ccir timing decoder, interrupt controller, master clock generator, st atistical data generator, 32 32 image data receive fifo (rxfifo), and a 16 32 statistic data fifo (statfifo). cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-2 freescale semiconductor figure 39-1. csi block diagram 39.2 csi interface signal description table 39-1 provides a listing of the input and output signals between the csi module of the i.mx27 device and an external cmos sensor. control reg 1 csi status reg 8-bit to 32-bit ahb bus csi_mclk csi_d[7:0] interface signal master clock generator interrupt control data sampling logic data packing control timing logic csi_pixclk csi_vsync csi_hsync ahb interface gasket rxfifo(32x32) control reg 2 statfifo(16x32) statistic data generation 16-bit to 32-bit data packing statfifo_dmareq_b csi_int_b ccir656 timing decoder csi_line_strobe csi_sof csi_rxfull to emma pre-processor csi_rxdata[31:0] rxfifo_dmareq_b csi_rxff_level[1:0] 16-bit swap dummy zero packing control reg 3 debug reg cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-3 39.2.1 signals from csi to emma pre-processor block (prp) there is a dedicated bus from csi rxfifo to the emma pre-processor block (prp) for fast data transfer. the bus can be enabled or disabled. when it is en abled, the rxfifo is detached from the ahb bus and connected to the prp. any cpu read or dma access to the rxfifo register is ignored. all csi interrupts are also masked to prevent software access to the fifo and status registers. users select the rxfifo full level according to the data format and line width, each of the burst from csi rxfifo to prp must use a size that equal to the rxfi fo full level. to ensure complete transfer of the whole frame, the size of the image (in words) must be integer multiples of the rxfifo full level. a simple calculation is shown in table 39-2 . note fifo full level of 24 words is not supported in the csi-prp interface. if a 24-word full setting is used the internal logic will regard it as 8 words. 39.3 principles of operation this section describes the modes of operation of the sensor interface. the csi is designed to support gene ric sensor interface timing as we ll as ccir656 video interface timing. traditional cmos sensors typically use sof, hsync (blank), and pixclk signals to output bayer or yuv data. smart cmos sensors, that come wi th on-chip imaging processing, usually support video table 39-1. signals between csi and sensor csi signals direction description csi_vsync input vertical sync (start of frame) csi_hsync input horizontal sync (blank signal) csi_d[7:0] input 8-bit sensor data bus (bayer, yuv, ycrcb, rgb) csi_mclk output sensor master clock csi_pixclk input pixel clock table 39-2. integer multiples of rxfifo full levels data format byte per pixel pixel per word options for rxfifo full level (words) requirement on line width (pixels) yuv422 2 2 4 / 8 / 16 multiple of 8 / 16 / 32 ycc422 2 2 multiple of 8 / 16 / 32 rgb565 2 2 multiple of 8 / 16 / 32 rgb888 4 1 multiples of 4 / 8 / 16 bayer 1 4 multiple of 16 / 32 / 64 cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-4 freescale semiconductor mode transfer. they use an embedded timing codec to replace the sof and blank signal. the timing codec is defined by the ccir656 standard. 39.3.1 gated clock mode vsync, hsync, and pixclk signals are used in gated clock mode. a frame starts with a rising edge on vsync, then hsync goes to high and holds for the entire line. the pixel clock is valid as long as hsync is high. data is latched at the rising edge of the valid pixel clocks. hsync goes to low at the end of line. pixel clocks then become invalid and csi stops receiving data from the stream. for the next line the hsync timing repeats. for the next frame the vsync timing repeats. 39.3.2 non-gated clock mode in non-gated clock mode, only the vsync and pixclk signals are used; the hsync signal is ignored. figure 39-2. non-gated clock mode timing diagram the overall timing of non-gated mode is the same as the gated-clock mode, except for the hsync signal. hsync signal is ignored by the csi. all incoming pixel cl ocks are valid and cause data to be latched into rxfifo. the pixclk signal is inactive (states low) until valid data is ready to be transmitted over the bus. figure 39-2 shows the timing using a typical sensor, other sensors may have the slightly different timing from that shown. the csi should be programed to support rising/falling-edge triggered vsync; active-high/low hsync; and rising/ falling-edge triggered pixclk. 39.3.3 ccir656 interlace mode in ccir656 mode, only the pixclk and data[7:0] signals are used. the start of frame and blank signals are replaced by a timing codec which is embedded in the data stream. each active line starts with a sav code and ends with a eav code. in some cases, digital blanking is inserted in between eav and sav code. the csi decodes and filters out the timing-coding fr om the data stream, thus recovering vsync and hsync signals for internal use, such as statistica l block control and csi-to-pr p interconnection. data is forwarded to the data receive and packing block in a sequential manner without re-ordering?that is, field 1 followed by field 2. the fields must be re-ordered in software to get back the original image. vsync pixclk d(7:0) invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-5 change of field interrupt (cof) is triggered upon ever y field change. the interrupt service routine reads the status register to check for the current field. according to the ccir656 specification, the image must be in 625/50 pal or 525/60 ntsc format. in addition, the image is interlaced into odd and even fi elds, with vertical and hor izontal blank data being filled into certain lines. data must be in ycc422 form at, each pixel contains 2 bytes, either y + cr or y + cb. these requirements are set for tv systems. the csi module supports pal and ntsc format only. figure 39-3 shows the frame structure in pal system, show ing vertical blanking and horizontal blanking. figure 39-3. ccir656 interlace mode (pal) figure 39-4 shows the general timing for a single line, showing sav and eav. figure 39-4. ccir656 general line timing the coding tables recommended by the ccir656 specification are shown in table 39-3 , table 39-4 and table 39-5 . it is used in the ccir656 mode to decode the video stream. an interrupt is generated for sof, which is decoded from the embedded timing codec. (1,1,1) blanking (0,1,1) (1,1,0) (0,1,0) (1,0,0) (0,0,0) (1,1,0) (0,1,0) (1,1,1) (0,1,1) (1,0,1) (0,0,1) active video 1 active video 2 (h,v,f) (h,v,f) sav eav sof sov1 sov2 field 2 field 1 field 2 (f = 0) (f = 1) (f = 1) 1440 bytes 268 4 4 start of line eav sav start of active pixel next line h-blanking pixel data f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r y c b y c r y cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-6 freescale semiconductor . 39.3.4 ccir656 progressive mode for a cmos camera system of vga or cif resolution, st rict adherence to the inte rlace requirements stated in the cir standard is not required. the image is cons idered to have only 1 active field which is scanned in a progressive manner. this active field is regarded as field 1 and the f-bit in the timing codec is ignored by the decoder. most sensor s support ccir timing in this mode (progressive) by default. figure 39-5 shows the typical flow of progressive mode. table 39-3. coding for sav and eav data bit number 1st byte 0xff 2nd byte 0x00 3rd byte 0x00 4th byte 0xxy 7 (msb)1001 6100f 5100v 4100h 3100p3 2100p2 1100p1 0100p0 table 39-4. coding for protection bits f v h p3p2p1p0 0000000 0011101 0101011 0110110 1000111 1011010 1101100 1110001 table 39-5. representations by f-bit f-bit representations 0 odd field (field 1) 1 even field (field 2) cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-7 figure 39-5. ccir656 progressive mode (general case) an interrupt is generated for sof but not for cof. in the general case, when sof information is retrieved from the embedded coding, it is known as internal vsync mode. in other cases, when the vsync signal is provided by the sensor, it is known as external vs ync mode. the csi can be operated in internal or external vsync mode. 39.3.5 error correction for ccir656 coding according to the algorithm for ccir coding, protecti on bits in the sav and eav are encoded in the way that allows a 1-bit error to be corrected, or a 2-bit e rror to be detected by the decoder. this feature is supported by the ccir decoder in csi, for interlace mode only. for the 1-bit error case, users can select the error to be corrected automatically, or simply shown as a status flag instead. for the 2-bit error case, because the d ecoder is unable to make a correction, the error would be shown as a status flag only. an interrupt can be generated upon the detection of an error. this signal can be enabled or disabled without affecting the operation of the status bit. 39.4 interrupt generation this section describes csi events that generate interrupts. 39.4.1 start of frame interrupt (sof_int) the source of an sof interrupt is dependent on the mode of operation. blanking eav_b sav_b eav_a sav_a data sav eav field 1 (f = 0) configurable undefined 4 4 blanking blanking eav_b sav_b blanking blanking blanking eav_a sav_a data blanking eav_a sav_a data eav_b sav_b blanking blanking sof single line cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-8 freescale semiconductor in traditional mode, vsync signal is taken from sens or and sof_int is generated at the rising or falling edge (programmable) of vsync. in ccir interlace mode, the sof interrupt info rmation is retrieved from the embedded coding and sof_int is generated. in ccir progressive mode, there are two sources of an sof interrupt: ?in internal vsync mode, sof is retrieved from the embedded coding. ?in external vsync mode, vsync is taken from the se nsor and sof is generated at the rising edge of vsync. 39.4.2 end of frame interrupt (eof_int) an eof interrupt is generated when the frame ends a nd the complete frame data in rxfifo is read. the eof interrupt does not work in csi preprocessing mode. the eof event triggering works with the rx count re gister (csirxcnt). softwa re sets the rx count register to the frame size (in bytes). the csi rx l ogic then counts the number of pixel data being received and compares it with the rx count. if the preset valu e is reached, then an eof interrupt is generated and the data in the rxfifo are read. if an sof event is detected before this happens, then the eof interrupt is not generated. 39.4.3 change of field interrupt (cof_int) the change of field interrupt is only valid in ccir interlace mode. the cof interrupt is generated when the field toggles, either from field 1 to field 2, or field 2 to field 1. software should first check on cof_int bit in the csi status register (csistat), before checking that f1_int or f2_int is turned on. in pal systems, the field changes at the beginning of the frame and coincides with sof. for the first field, a cof interrupt is not generated, only an sof is gene rated. the cof interrupt is generated for the second field. 39.4.4 ccir error interrupt (ecc_int) the ccir error interrupt is only valid for ccir interl ace mode. an ecc interrupt is generated when an error is found on the sav or eav codes in the incoming stream. when this happens, the ecc_int status bit is set. 39.4.5 data packing style owing to different port sizes at different stages of the image capture path, the endianess of data is important. to enable flexible packing of image data, the csi module provides data swapping through the pack_dir and the swap16_en bits in csi control re gister 1 (csicr1) which enables data swapping before it is presented to the fifos. cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-9 data is packed from 8-bit to 32-bit according to the setting of pack_dir bit, and then put into the rx fifo according to the setting of the swap16_en bit. 39.4.6 rx fifo path bayer data is a type of raw data from the image sens or. this byte-wide data must be converted to the rgb space or yuv space by software. the data path for bayer data is from the csi to memory. if the system is in little endian, then the pack_dir bit should be se t to 0. doing so results in the data being packed to 32-bit as p3p2p1p0, where p0 is the pixel coming in time slot 0 (first data), while p3 is the pixel coming in time slot 3 (last data). when the data is addre ssed as bytes by software, p0 goes out first, and ends up with p3. 39.4.6.1 rgb565 data rgb565 data is processed data from the image sensor, which can be put directly into the display buffer. the data is 16 bits wide. the data path is from csi to memory, memory to lcdc. on the sensor side, data must be output as p0 first, followed by p1, and so on. within each pixel, either msb or lsb will come out first. this is controlled by the endian style of the se nsor. data is 16 bits wide with the msb labeled rg, and the lsb labeled gb. so for p0, it is represented as rg0, gb0, and so on for p1. csi receives data in one of the following sequence: ? rg0, gb0, rg1, gb1, while rg0 comes out at time slot 0 (first data), and gb1 comes out at time slot 3 (last data), or ? gb0, rg0, gb1, rg1. using the first sequence as an example, and assuming the system is running in little endian the data is presented as: ? 8-bit data from sensor: rg0, gb0, rg1, gb1, ? ? 32-bit data before csi rx fifo (pack_dir bit = 1): rg0gb0rg1gb1 ? 32-bit data in csi rx fifo (swa p16_en bit enabled): rg1gb1rg0gb0 ? 32-bit transfer to system memory: rg1gb1rg0gb0 ? 16-bit read by lcdc: rg0gb0, rg1gb1 39.4.6.2 rgb888 data this is another kind of processed data from image sensor, which can be used for further image processing directly. each of the data consist of 8-bit red, 8-bit green, and 8-bit bl ue data. an example of a possible timing scheme is shown in figure 39-6 . cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-10 freescale semiconductor figure 39-6. sample timing diagram for rgb888 data the 3-byte per pixel structure is not an optimum choice for a csi to prp path. to improve the data transfer from csi to prp, an optional dummy byte packing sche me is provided. for every group of 3 bytes data, a dummy zero is packed to form a 32-bit word as shown in figure 39-7 . the dummy zero is always packed at the lsb position. this byte will be ignored by the prp figure 39-7. optional dummy byte packing scheme 39.4.7 stat fifo path statistics only works for bayer data. it generates 16-bit statistical output from the 8-bit bayer input. the outputs are sum of green (g), sum of red (r), sum of blue (b), and auto focus (f). each output is 16-bits wide. the settings of pack_dir and swap16_en bits in the csicr1 register have no effect on the input path. the pack_dir only controls how the 16-bit stat output is packed into the 32-bit stat fifo. when the pack_dir bit = 1, the stat data is packed as: first 32-bit: rg second 32-bit: bf ? when the pack_dir bit = 0, the stat data is packed as: first 32-bit gr second 32-bit: fb ? input data timing pixclk data[7:0] r0 g0 r1 b0 g1 b1 data[7:0] b0 g0 b1 r0 g1 r1 format 1 format 2 format 2 with pack direction = ?0? (lsb first) format 1 with pack direction = ?1? (msb first) r0 g0 b0 zero r1 g1 b1 zero output data format cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-11 39.5 memory map and register definition the csi module contains six 32-bit re gisters which are summarized in table 39-6 . the base address of the csi module for i.mx27 is 0x1000 8000. table 39-8 summarizes the registers and offset addresses. section 39.5, ?memory map and register definition ? provides detailed descriptions of the dmac register. 39.5.1 csi memory map table 39-6 shows the csi memory map. 39.5.2 register summary figure 39-8 shows the key to the register fields, and table 39-7 shows the register figure conventions. figure 39-8. key to register fields table 39-6. csi memory map address use access reset value section/page 0x8000_00000 (csicr1) csi control register 1 r/w 0x4000_0800 39.5.3/39-14 0x8000_00004 (csicr2) csi control register 2 r/w 0x0000_0000 39.5.4/39-17 0x8000_0001c (csicr3) csi control register 3 r/w 0x0000_0000 39.5.5/39-19 0x8000_00008 (csisr) csi status register r/w 0x0000_4000 39.5.6/39-20 0x8000_0000c (csistatfifo) csi statistic fifo register r 0x0000_0000 39.5.7/39-22 0x8000_00010 (csirfifo) csi rx fifo register r 0x0000_0000 39.5.8/39-22 0x8000_00014 (csirxcnt) csi rx count register r/w 0x0000_0000 39.5.9/39-23 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit table 39-7. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-12 freescale semiconductor table 39-8 shows the csi register summary. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 39-8. csi register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x8000_00000 (csicr1) r swap16_en ext_vsync eof_int_en prp_if_en ccir_mode cof_int_en sf_or_inten rf_or_inten statff_level statff_inten rxff_level rxff_inten sof_pol sof_inten w r mclkdiv hsync_pol ccir_en mclken fcc pac k _ d i r clr_statfifo clr_rxfifo gclk_mode inv_data inv_pclk redge 0 w 0x8000_00004 (csicr2) r00000 dr m afs sce 00 bts lv r m w r vsc hsc w 0x8000_0001c (csicr3) r frmcnt w r frmcnt_rst 00000000000 csi_sup zero_pack_en ecc_int_en ecc_auto_en w table 39-7. register figure conventions (continued) convention description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-13 0x8000_00008 (csisr) r000000 sff_or_int rff_or_int 00 statff_int 00 rxff_int eof_int sof_int w r f2_int f1_int cof_int 00000000000 ecc_ int drdy w 0x8000_0000c (csistatfifo) rstat w rstat w 0x8000_00010 (csirfifo) rimage w rimage w 0x8000_00014 (csirxcnt) r0000000 0 00 rxcnt w r rxcnt w table 39-8. csi register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-14 freescale semiconductor 39.5.3 csi control register 1 (csicr1) this register controls the sensor interface timing, cs i-to-prp bus interface and interrupt generation. the csi module is enabled through the peripheral clock contro l register 0 (pccr0). the interrupt enable bits in this register control the interrupt signals and the status bits. that means status bits will only function when the corresponding interrupt bits are enabled. 0x8000_00000 (csicr1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r swap16_en ext_vsync eof_int_en prp_if_en ccir_mode cof_int_en sf_or_inten rf_or_inten statff_level statff_inten rxff_level rxff_inten sof_pol sof_inten w reset01000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r mclkdiv hsync_pol ccir_en mclken fcc pa c k _ d i r clr_statfifo clr_rxfifo gclk_mode inv_data inv_pclk redge 0 w reset00001000 0 0 000000 figure 39-9. cspi control register 1 (csicr1) table 39-9. csi control register 1 field descriptions field description 31 swap16_en swap 16-bit enable. this bit enables the swapping of 16-bit data. data is packed from 8-bit to 32-bit first (according to the setting of pack_dir and then swapped as 16-bit words before putting into the rx fifo. the action of the bit only affects the rx fifo and has no affect on the stat fifo. note: example of swapping enabled: data input to fifo = 0x11223344 data in rx fifo = 0x 33441122 note: example of swapping disabled: data input to fifo = 0x11223344 data in rx fifo = 0x11223344 0 disable swapping 1 enable swapping 30 ext_vsync external vsync enable. this bit controls the operational vsync mode. note: this only works when the cis is in ccir progressive mode. 0 internal vsync mode 1 external vsync mode 29 eof_int_en end-of-frame interrupt enable. this bit enables and disables the eof interrupt. 0 eof interrupt is disabled. 1 eof interrupt is generated when rx count value is reached. cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-15 28 prp_if_en csi?prp interface enable. this bit controls the csi to prp bus. when enabled the rxfifo is detached from the ahb bus and connected to prp. all cpu reads or dma accesses to the rxfifo register are ignored. all csi interrupts are also masked. 0 csi to prp bus is disabled 1 csi to prp bus is enabled 27 ccir_mode ccir mode select. this bit controls the ccir mode of operation. this bit only works in ccir interface mode. 0 progressive mode is selected 1 interlace mode is selected 26 cof_int_e change of image field (cof) interrupt enable. this bit enables the cof interrupt. this bit works only in ccir interlace mode which is when ccir_en = 1 and ccir_mode = 1. 0 cof interrupt is disabled 1 cof interrupt is enabled 25 sf_or_inten stat fifo overrun interrupt enable. this bit enables the statfifo overrun interrupt. 0 statfifo overrun interrupt is disabled 1 statfifo overrun interrupt is enabled 24 rf_or_inten rxfifo overrun interrupt enable. this bit enables the rx fifo overrun interrupt. 0 rxfifo overrun interrupt is disabled 1 rxfifo overrun interrupt is enabled 23?22 statff_level statfifo full level. when the number of data in statfifo reach this level, statfifo full interrupt is generated, or statfifo dma request is sent. 00 4 words 01 8 words 10 12 words 11 16 words 21 statff_inten statfifo full interrupt enable. this bit enables the stat fifo interrupt. 0 statfifo full interrupt disable 1 statfifo full interrupt enable 20?19 rxff_level rxfifo full level. when the number of data in rxfifo reach this level, a rxfifo full interrupt is generated, or an rxfifo dma request is sent, or csi-prp burst cycle is issued. 00 4 words 01 8 words 10 16 words 11 24 words note: in the case when prp i/f is enabled, 24-words option is not supported, internal logic will regard it as 8-word. this is not reflected in the register value. 18 rxff_inten rxfifo full interrupt enable. this bit enables the rxfifo full interrupt. 0 rxfifo full interrupt disable 1 rxfifo full interrupt enable 17 sof_pol sof interrupt polarity. this bit controls the condition that generates an sof interrupt. 0 sof interrupt is generated on sof falling edge 1 sof interrupt is generated on sof rising edge 16 sof_inten start of frame (sof) interrupt enable. this bit enables the sof interrupt. 0 sof interrupt disable 1 sof interrupt enable table 39-9. csi control register 1 field descriptions (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-16 freescale semiconductor 15?12 mclkdiv sensor master clock (mclk) divider. this field contains the divisor mclk. the mclk is derived from the perclk4. 0000 divided by 2 0001 divided by 4 0010 divided by 6 ... 1111 divided by 32 11 hsync_pol hsync polarity select. this bit controls the polarity of hsync. note: this bit only works in gated-clock?that is, gclk_mode = 1 and ccir_en = 0. 0 hsync is active low 1 hsync is active high 10 ccir_en ccir656 interface enable. this bit selects the type of interface used. when the ccir656 timing decoder is enabled, it replaces the function of timing interface logic. 0 traditional interface is selected. timing interface logic is used to latch data. 1 ccir656 interface is selected. 9 mclken sensor master clock (mclk) enable. this bit enables or disables the mclk input to the sensor. 0mclk disable 1 mclk enable 8 fcc fifo clear control. this bit determines how the rxfifo and statfifo are cleared. when synchronous fifo clear is selected the rxfifo and statfifo are cleared, and stat block is reset, on every sof. fifos and stat block restarts immediately after reset. for information on the operation when asynchronous fifo clear is selected, refer to the descriptions for the clr_rxfifo and clr_statfifo bits. 0 asynchronous fifo clear is selected. 1 synchronous fifo clear is selected. 7 pac k _ d i r data packing direction. this bit controls how 8-bit image data is packed into 32-bit rx fifo, and how 16-bit statistical data is packed into 32-bit stat fifo. 0 pack from lsb first. for image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in rx fifo. for stat data, 0xaaaa, 0xbbbb, it will appear as 0xbbbbaaaa in stat fifo. 1 pack from msb first. for image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in rx fifo. for stat data, 0xaaaa, 0xbbbb, it will appear as 0xaaaabbbb in stat fifo. 6 clr_statfifo asynchronous statfifo clear. this bit clears the statfifo and reset stat block. note: this bit works only in async fifo clear mode?that is, fcc = 0. otherwise this bit is ignored. writing 1 will clear statfifo and reset stat block immediately, statfifo and stat block then wait and restart after the arrival of next sof. the bit is restored to 0 automatically after finish. normally reads 0.fffffffff 5 clr_rxfifo asynchronous rxfifo clear. this bit clears the rxfifo. this bit works only in async fifo clear mode?that is, fcc = 0. otherwise this bit is ignored. writing 1 clears the rxfifo immediately, rxfifo restarts immediately after that. the bit is restore to 0 automatically after finish. normally reads 0. 4 gclk_mode gated clock mode enable. controls if csi is working in gated or non-gated mode. note: this bit works only in traditional mode?that is, ccir_mode = 0. otherwise this bit is ignored. 0 non-gated clock mode. all incoming pixel clocks are valid. hsync is ignored. 1 gated clock mode. pixel clock signal is valid only when hsync is high. table 39-9. csi control register 1 field descriptions (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-17 39.5.4 csi control register 2 (csicr2) this register provides the statistic block with data about which live vi ew resolution is being used, and the starting sensor pixel of the bayer pattern. it also contains the horiz ontal and vertical count used to determine the number of pixels to skip between the 64 64 blocks of statistics when generating statistics on live view image that are greater than 512 384. 3 inv_data invert data input. this bit enables or disables internal inverters on the data lines. 0 csi_d[7:0] data lines are directly applied to internal circuitry 1 csi_d[7:0] data lines are inverted before applied to internal circuitry 2 inv_pclk invert pixel clock input. this bit determines if the pixel clock (csi_pixclk) is inverted before it is applied to the csi module. 0 csi_pixclk is directly applied to internal circuitry 1 csi_pixclk is inverted before applied to internal circuitry 1 redge valid pixel clock edge select. selects which edge of the csi_pixclk is used to latch the pixel data. 0 pixel data is latched at the falling edge of csi_pixclk 1 pixel data is latched at the rising edge of csi_pixclk 0 reserved. this bit is reserved and should read 0. 0x8000_00004 (csicr2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000 drm afs sce 00 bts lv r m w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r vsc hsc w reset00000000 0 0 000000 figure 39-10. csi control register 2 (csicr2) table 39-10. csi control register 2 description field description 31?27 reserved. these bits are reserved and should read 0. 26 drm double resolution mode. controls size of statistics grid. 0 stats grid of 8 6 1 stats grid of 8 12 table 39-9. csi control register 1 field descriptions (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-18 freescale semiconductor 25?24 afs auto focus spread. selects which green pixels are used for auto-focus. 00 abs diff on consecutive green pixels 01 abs diff on every third green pixels 1x abs diff on every four green pixels 23 sce skip count enable. enables or disables the skip count feature. 0 skip count disable 1 skip count enable 22?21 reserved. these bits are reserved and should read 0. 20?19 bts bayer tile start. controls the bayer pattern starting point. 00 gr 01 rg 10 bg 11 gb 18?16 lv r m live view resolution mode. selects the grid size used for live view resolution. 0512 384 1448 336 2384 288 3384 256 4320 240 5288 216 6400 300 15?8 vsc vertical skip count. contains the number of rows to skip. sce must be 1, otherwise vsc is ignored. 0?255 number of rows to skip minus 1 7?0 hsc horizontal skip count. contains the number of pixels to skip. sce must be 1, otherwise hsc is ignored. 0?255 number of pixels to skip minus 1 table 39-10. csi control register 2 description (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-19 39.5.5 csi control register 3 (csicr3) this read/write register acts as an extension of the functionality of the csi control register 1 adding additional control and features. 0x8000_0001c (csicr3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r frmcnt w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r frmcnt_rst 0000000 0 0 00 csi_sup zero_pack_en ecc_int_en ecc_auto_en w reset00000000 0 0 000000 figure 39-11. csi control register 3 (csicr3) table 39-11. csi control register 3 field descriptions field description 31?16 frmcnt frame counter. this is a 16-bit frame counter (wrap around automatically after reaching the maximum) 15 frmcnt_rst frame count reset. resets the frame counter. 0do not reset 1 reset frame counter immediately 14?4 reserved. these bits are reserved and should read 0. 3 csi_svr supervisor mode access control. this bit enables and disables arm9 supervisor mode access. 0 module can be accessed in any arm9 mode 1 module can only be accessed in arm9 supervisor mode. accessing the module in non-supervisor mode will cause a data abort exception. 2 zero_pack_en dummy zero packing enable. this bit causes a dummy zero to be packed with every 3 incoming bytes, forming a 32-bit word. the dummy zero is always packed to the lsb position. 0 zero packing disabled 1 zero packing enabled cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-20 freescale semiconductor 39.5.6 csi status register (csisr) this read/write register shows sensor interface status , and which kind of interrupt is being generated. the corresponding interrupt bits must be set for the status bit to function. status bits should function normally even if the corresponding interrupt enable bits are not enabled. 1 ecc_int_en error detection interrupt enable. this bit enables and disables the error detection interrupt. this feature only works in ccir interlace mode. 0 no interrupt is generated when error is detected. only the status bit ecc_int is set. 1 interrupt is generated when error is detected. 0 ecc_auto_en automatic error correction enable. this bit enables and disables the automatic error correction. if an error occurs and error correction is disabled only the ecc_int status bit is set. this feature only works in ccir interlace mode. 0 auto error correction is disabled. 1 auto error correction is enabled. 0x8000_00008 (csisr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 sff_or_int rff_or_int 00 statff_int 00 rxff_int eof_int sof_int w reset000000 0 0 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r f2_int f1_int cof_int 000 0 0 0 0 0000 ecc_ int drdy w reset010000 0 0 0 0 000000 figure 39-12. csi status register (csisr) table 39-12. csi status register field descriptions field description 31?26 reserved. these bits are reserved and should read 0. 25 sf_or_int statfifo overrun interrupt status. indicates the overflow status of the statfifo register. 0 statfifo has not overflowed. 1 statfifo has overflowed. (cleared by writing 1) table 39-11. csi control register 3 field descriptions field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-21 24 rf_or_int rxfifo overrun interrupt status. indicates the overflow status of the rxfifo register. 0 rxfifo has not overflowed. 1 rxfifo has overflowed. (cleared by writing 1) 23?22 reserved. these bits are reserved and should read 0. 21 statff_int statfifo full interrupt status. indicates whether the statfifo condition is either full or not full /overflowed. 0 statfifo is not full, or has overflowed. 1 statfifo is full. (this bit is cleared automatically by reading the statfifo) 20?19 reserved. these bits are reserved and should read 0. 18 rxff_int rxfifo full interrupt status. indicates whether the rxfifo condition is either full or not full /overflowed. 0 rxfifo is not full, or has overflowed. 1 rxfifo is full. (this bit is cleared automatically by reading the rxfifo) 17 eof_int end of frame (eof) interrupt status. indicates when eof is detected. 0 eof is not detected. 1 eof is detected. (cleared by writing 1) 16 sof_int start of frame interrupt status. indicates when sof is detected. 0 sof is not detected. 1 sof is detected. (cleared by writing 1) 15 f2_int ccir field 2 interrupt status. indicates the presence of field 2 of video in ccir mode. note: only works in ccir interlace mode. 0 field 2 of video is not detected 1 field 2 of video is about to start (cleared automatically when current field does not match) 14 f1_int ccir field 1 interrupt status. indicates the presence of field 1 of video in ccir mode. note: only works in ccir interlace mode. 0 field 1 of video is not detected. 1 field 1 of video is about to start. (cleared automatically when current field does not match) 13 cof_int change of field interrupt status. indicates that a change of the video field has been detected. only works in ccir interlace mode. software should read this bit first and then dispatch the new field from f1_int and f2_int. 1 change of video field is detected. 0 video field has no change. (cleared by writing 1) 12? 2 reserved. these bits are reserved and should read 0. table 39-12. csi status register field descriptions (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-22 freescale semiconductor 39.5.7 csi statfifo register (csistatfifo) the statfifo is a read-only register containing statisti c data from the sensor. writing to this register has no effect. 39.5.8 csi rxfifo register (csirfifo) this read-only register contains received image data. writing to this register has no effect. 1 ecc_int ccir error interrupt. this bit indicates an error has occurred. this only works in ccir interlace mode. 0 no error detected (cleared by writing 1) 1 error is detected in ccir coding 0 drdy rxfifo data ready. indicates the presence of data that is ready for transfer in the rxfifo. 0 no data (word) is ready 1 at least 1 data (word) is ready in rxfifo. (cleared automatically by reading fifo) 0x8000_0000c (csistatfifo) access: user read-0nly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rstat w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rstat w reset00000000 0 0 000000 figure 39-13. csi statfifo register (csistatfifo) table 39-12. csi status register field descriptions (continued) field description cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 39-23 because the incoming image data is 8-bit while the fifo size is 32-bit, the incoming byte size data will be packed into 32-bit in the following sequence. 39.5.9 csi rx count register (csirxcnt) this register works for eof interrupt generation. it s hould be set to the number of words to receive that would generate an eof interrupt. there is an internal counter that counts the number of words read from the rx fifo. whenever the rx fifo is being read, by either the cpu or dma, th e counter value is updated and compared with this register. if the values match, then an eof interrupt is triggered. 0x8000_00010 (csirfifo) access: user read-0nly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rimage w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rimage w reset00000000 0 0 000000 figure 39-14. csi rxfifo register (csirfifo) 0x8000_00014 (csirxcnt) access: user read-0nly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000 0 00 rxcnt w reset00000000 0 0 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rxcnt w reset00000000 0 0 000000 figure 39-15. csi rx count register (csirxcnt) cmos sensor interface (csi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 39-24 freescale semiconductor table 39-13. csi rx count register field descriptions field description 31?22 reserved. these bits are reserved and should read 0. 21?0 rxcnt rxfifo count. this 22-bit counter for rxfifo is updated each time the rxfifo is read by cpu or dma.this counter should be set to the expected number of words to receive that would generate an eof interrupt. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-1 chapter 40 video codec (video_codec) the video codec module is the multimedia vi deo processing module in the i.mx27 device. figure 40-1 shows the top-level diagram for video codec. figure 40-1. video codec block architecture diagram 40.1 features video codec module support following multimedi a video stream processing features: ? multi-standard video codec ? mpeg-4 part-ii simple profile encoding/decoding ? h.264/avc baseline profile encoding/decoding ? h.263 p3 encoding/decoding ? multi-party call: max processing 4 image/bitstr eam encoding and/or decoding simultaneously. apb3 i/f host i/f bit processor core internal per bus interface h/w accelerator for bitstream packing/unpacking program mem data mem axi bus i/f reset controller main controller (macroblock sequencer) motion estimation cur mem reconstruction internal peripheral bus internal axi bus apb bus ip bus video codec processor residual avc tra n s fo r m / quant mpeg tra n s fo r m / quant coefficient buffer inter prediction intra prediction dmac deblock filter and rotation (decoded image) ac/dc prediction dmac rotation (source image) ahb bus for search ram video codec gasket ahb bus video codec gasket axi bus ahb bus ahb bus mpeg4 h.263p3 h.264 shared video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-2 freescale semiconductor ? multi-format: encodes mpeg4 bitstream, a nd decodes h.264 bitstream simultaneously. ? coding tools ? high-performance motion estimation. ? single reference frame for both mpeg4 and h.264 encoding. ? support 16 reference frame for h264 decoding ? quarter-pel and half-pel accuracy motion estimation ? [+/?16, +/?16] search range ? unrestricted motion vector ? mpeg-4 ac/dc prediction and h.264 intra prediction. ? all variable block sizes are s upported (in case of encoding, 8 x 4, 4 x 8, and 4 x 4 block sizes are not supported). ? h.263 annex i, j, k (rs = 0 and aso =0), and t are supported. in case of encoding, annex i and k (rs=1 or aso=1) are not supported. ? cir (cyclic intra refresh)/air (adaptive intra refresh) ? error resilience tools. ? mpeg-4 re-synchronize marker and data-partitioning with rvlc (fixed number of bits/macroblocks between macroblocks) ? h.264/avc fmo and aso ? h.263 slice structured mode ? bit-rate control (cbr and vbr) ? pre/post rotation/mirroring ? 8 rotation/mirroring modes for image to be encoded ? 8 rotation/mirroring modes fo r image to be displayed ? programmability ? embeds 16-bit dsp processor that is dedicated to process bitstream a nd drive codec hardware ? general purpose registers and interrupt genera tion for communication between the system and the video codec module 40.2 overview the video codec module in i.mx27 device supports fu ll duplex video codec processing and multi-party calls. it integrates multiple video processing sta ndard together, including h264 bp, mpeg4 sp, and h263 p3 (including annex i, j, k, and t). the video codec uses two bus interface protocols: th e ip bus for register acce ss control and the ahb bus for data throughput. the video codec module uses th ree memory components: embedded memory, system internal memory and system external memory. em bedded memories include dua l-port register files, single-port register file, dual-port sram, and single- port sram. system internal memory is used by motion estimation to increase codec perf ormance. system external memory is used to store input/output image pixel data and bit-stream data. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-3 video codec module mainly includes two hardware components: ? video codec processor: it is the heart of vi deo codec processing. it supports multiple video processing standard, and integr ates encoding and decoding function together with 32-bit axi interface. ? video codec interface: composed of two parts, one responds to bus protocol transfers between 32-bit axi bus interface and three 32-bit ahb-lite master bus interfaces (two read channels and one write channel). the other responds to bus protocol transfers between 32-bit apb bus and ip bus. encoder and decoder processing share data-paths in the video codec module. there is an embedded bit processor which is used to control the hardware se quence and as well as bitstream processing. the whole encoding or decoding is controlled by the firmware running on bit processor in video codec. the host processor only need to access the video codec registers for initializing the video codec or setting frame parameters during the en coding/decoding frame gap. the video codec module has 3 clock domains: ip bus clock, video codec core clock, and the ahb bus clock. the video codec processing ip core clock is asynchronous to ahb clock and ip clock. all sequential logic use only rising edge of clocks. 40.3 clock domain and reset 40.3.1 clocks there are three clock domains in video codec: ? ahb bus clock domain (hclk): controls all ahb or axi bus related functions. maximum frequency is 133 mhz. the hclk is de rived from pll clock reset module. ? codec core clock domain (cclk): this is the master clock for the video codec. it controls all video codec encoding/decoding functionality, at a maxi mum frequency of 133 mhz. the actual value of core clock is dependent upon application use case. ? ip bus clock domain (ipg_clk_s): controls vide o codec registers read/write function, with a maximum frequency of 66.5 mhz. ipg_clk_s is a gated clock of ip clock (ipg_clk) with ips_module_en, it is turned off when there is no registers read/write for power saving. only positive edge clocks is used in video codec design. all clock domains are asynchronous to the others. the video codec processor uses all the three cloc k domains because it is needed for axi signal generation, functional calculation, and apb bus confi guration. the video codec interface clock belongs to ahb clock domain and ip bus cl ock domain, because they are rela ted to ahb and axi, ip and apb bus protocol transfers. 40.3.2 reset corresponding to the three clock domains, there are three reset signals in video codec module, active low. ? ahb bus reset: used in ahb bus interface. corresponding clock is hclk. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-4 freescale semiconductor ? codec core reset: used in codec accelerating hardware. corresponding clock is cclk. ? ip bus reset: used in ip bus interface. corresponding clock is ipg_clk. the number of cycles for each reset signal must be at least 8 cycles. the video codec uses an internal reset controller for fe ature software reset from the bit processor. if any of the video codec blocks, with the exception of bit pr ocessor is needed to reset (software reset), the host processor can enable this software reset by setting the software reset register through video codec api. the bit processor cannot be reset by this software re set scheme, because the rese t signal of bit processor is connected directly to an external reset signal. if reset occurs when the video codec is processing a transaction through ahb bus, there is no guarantee that ahb bus will complete the transaction normally, since the video codec will be reset. if there are any corrupted data in memory, it can be discarded by soft ware. basically, if the host processor needs to issue a reset, it must check to ensure that there is no transaction on ahb bus between video codec and external ahb bus interface. in general, the ahb bus is fr ee of video codec transactions after one frame of decoding/encoding is completed. the start of next frame processing requires software initiation. note both ahb read channels only allows read access, its corresponding ahb master bus has no hwdata signal, and hwr ite is connected to ?0?. similarly, ahb write channel only allow write access, its corresponding ahb master bus has no hrdata signal, and hwrite is connected to ?1?. 40.4 memory map and register definition the video codec registers are all 32-bit wide and on ly support 32-bit aligned read/write operations. video codec registers are grouped into several regions co rresponding to different codec processing stages. the registers are used for codec processing configurati on and control. they can only be accessed through ip bus interface. 40.4.1 memory map video codec module includes several internal register address map space, as shown in table 40-1 . the video codec module uses 0x10023000?0x10023fff memory space as register mapping in i.mx27 system. the video codec module registers are divided into two categories. ? address 0x1002_3000?0x1002_30fc (64 registers address spac e) are hardware registers. these registers have reset values and their func tions are fixed (can not be configurable). ? address 0x1002_3100?0x1002_31fc (64 registers address space) are software registers. they have no reset values and are conf igurable by internal bit processor. so their definitions are not provided here. they can be used as general pa rameter registers between host and bit processor. ? the first 32 parameter registers (address 0x1002_3100?0x1002_317c) are used as static parameters. the meaning and functions of these registers are not changed regardless of the run commands used. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-5 ? the second 32 parameter registers (address 0x1002_3180?0x1002_31fc) are used as temporal parameters. the meaning and functions of th ese registers may be changed for each run commands. the memory map for the hardware registers of video codec is shown in table 40-1 . 40.4.2 register summary the conventions in figure 40-2 and figure 40-2 serve as a key for the register summary and individual register diagrams. table 40-2 provides a key for register figures and tables and the register summary. table 40-1. video codec hardware register memory map address register access reset value section/page 0xbase_3000 (coderun) bit processor run start w 0x0000_0000 40.4.3.1/40-7 0xbase_3004 (codedown) bit boot code download data register w 0x0000_0000 40.4.3.2/40-8 0xbase_3008 (hostintreq) host interrupt request to bit w 0x0000_0000 40.4.3.3/40-8 0xbase_300c (bitintclear) bit interrupt clear w 0x0000_0000 40.4.3.4/40-9 0xbase_3010 (bitintsts) bit interrupt status r 0x0000_0000 40.4.3.5/40-10 0xbase_3014 (bitcodereset) bit code reset w 0x0000_0000 40.4.3.6/40-10 0xbase_3018 (bitcurpc) bit current pc r 0x0000_0000 40.4.3.7/40-11 0xbase_301c?0xbase_30fc reserved ? ? ? always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 40-2. key to register fields table 40-2. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. (previously designated slfclr) video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-6 freescale semiconductor the brief video codec hardware register summary is shown in table 40-3 . reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 40-3. video codec hardware register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xbase_3000 (coderun) r w000000 000000000 0 r w000000 000000000coderun 0xbase_3004 (codedown) r w 0 0 0 codeaddr r w codedata 0xbase_3008 (hostintreq) r w000000 000000000 0 r w000000 000000000 intreq 0xbase_300c (bitintclear) r w000000 000000000 0 r w000000 000000000 intclear 0xbase_3010 (bitintsts) r000000 000000000 0 w r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 intsts w table 40-2. register conventions (continued) convention description video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-7 40.4.3 register descriptions this section consists of video codec hardware regist er descriptions in address order. each description includes a standard register diagram with an associat ed figure number. details of register bit and field function follow the register diagrams, in bit order. 40.4.3.1 video codec code run register (coderun) see figure 40-3 for an illustration of valid bits in video codec code run register and table 40-4 for descriptions of the bit fields in the register. 0xbase_3014 (bitcodereset) r w000000 000000000 0 r w000000 000000000codereset 0xbase_3018 (bitcurpc) r000000 000000000 0 w r0 0 curpc w 0xbase_3000 (coderun) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w0000000000000 000 reset0000000000000 000 151413121110987654 3 21 0 r w 0000000000000 00 code run reset0000000000000 000 figure 40-3. video codec code run register table 40-3. video codec hardware register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-8 freescale semiconductor 40.4.3.2 video codec bit boot code download data register (codedown) see figure 40-4 for an illustration of valid bits in video codec bit boot code download data register and table 40-5 for descriptions of the bit fields in the register. 40.4.3.3 video codec host interrupt request register (hostintreq) see figure 40-5 for an illustration of valid bits in video codec host interrupt request register and table 40-6 for descriptions of the bit fields in the register. table 40-4. video codec code run register field descriptions field description 31?1 reserved 0 coderun. bit processor run start bit. 0 bit processor stop execution 1 bit processor start execution 0xbase_3004 (codedown) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w 0 0 0 codeaddr reset000000000000 0000 151413121110987654 3 210 r w codedata reset000000000000 0000 figure 40-4. video codec bit boot code download data register table 40-5. video codec bit boot code download data register field descriptions field description 31?29 reserved 28?16 codeaddr[12:0]. download address of video codec bit boot code, which is video codec internal address of bit processor. 15?0 codedata[15:0]. download data of video codec bit boot code. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-9 40.4.3.4 video codec bit interrupt clear register (bitintclear) see figure 40-6 for an illustration of valid bits in vi deo codec bit interrupt clear register and table 40-7 for descriptions of the bit fields in the register. 0xbase_3008 (hostintreq) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w000000000000 000 0 reset000000000000 000 0 151413121110987654 3 21 0 r w000000000000 000intreq reset000000000000 000 0 figure 40-5. video codec host interrupt request register table 40-6. video codec host interrupt request register field descriptions field description 31?1 reserved 0 intreq. the host interrupt request bit. 0 no host interrupt is requested. 1 the host processor request interrupt to the bit processor. 0xbase_300c (bitintclear) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w0000000000000 00 0 reset0000000000000 00 0 151413121110987654 3 21 0 r w0000000000000 00intclear reset0000000000000 00 0 figure 40-6. video codec bit interrupt clear register video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-10 freescale semiconductor 40.4.3.5 video codec bit interrupt status register (bitintsts) see figure 40-7 for an illustration of valid bits in video codec bit interrupt status register and table 40-8 for descriptions of the bit fields in the register. 40.4.3.6 video codec bit code reset register (bitcodereset) see figure 40-8 for an illustration of valid bits in video codec bit code reset register and table 40-9 for descriptions of the bit fields in the register. table 40-7. video codec bit interrupt clear register field descriptions field description 31?1 reserved 0 intclear. bit interrupt clear bit. 0 no operation is issued. 1 clear the bit interrupt to the host. 0xbase_3010 (bitintsts) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 0 00 0 w reset000000000000 0 00 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r000000000000 0 00intsts w reset000000000000 0 00 0 figure 40-7. video codec bit interrupt status register table 40-8. video codec bit interrupt status register field descriptions field description 31?1 reserved 0 intsts. bit interrupt status bit. 0 no bit interrupt is asserted. 1 the bit interrupt is asserted to the host. it is cleared when the host processor write ?1? to bitintclear register. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-11 40.4.3.7 video codec bit current pc register (bitcurpc) see figure 40-9 for an illustration of valid bits in video codec bit current pc register and table 40-10 for descriptions of the bit fields in the register. 0xbase_3014 (bitcodereset) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w000000000000 0 00 0 reset000000000000 0 00 0 151413121110987654 3 21 0 r w 000000000000 0 00 code reset reset000000000000 0 00 0 figure 40-8. video codec bit code reset register table 40-9. video codec bit code reset register field descriptions field description 31?1 reserved 0 codereset. bit code reset bit. 0 no operation is issued. 1 the program counter of bit processor is set to ?0?, bit processor restart at initial routine. 0xbase_3018 (bitcurpc) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 0 00 0 w reset000000000000 0 00 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 curpc w reset000000000000 0 00 0 figure 40-9. video codec bit current pc register video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-12 freescale semiconductor 40.5 functional description the video codec module is a high-performance multi-sta ndard video processing unit in the system which supports h.263p3, mpeg-4 sp, and h.264 bp. 40.5.1 video codec architecture the video codec module mainly includes two ha rdware components: video codec processing ip and vide codec gasket. video codec proc essing ip is optimized to reduce l ogic gate count with many sharing parts of sub-modules for multi-standard. it is respons ible for bitstream parsing and frame data coding. it mainly consists an embedded 16bit bit processor , codec hardware accelerator , and bus arbiter/interface. bit processor is in charge of parsing/coding th e bitstream/image, controlling video codec process. hardware accelerators are designed to speed up bitstream/image processing. video codec gasket converts amba apb3 bus to ip sky blue bus and axi bus to ahb bus. refer to figure 40-1 for the block diagram of video codec. below sections describe the main function of vi deo codec processing ip components. 40.5.1.1 embedded bit processor the embedded bit processor is 16- bit programmable processor which is highly optimized to handle bitstream data. it is used for parsing or forming bits tream. it includes some hardware accelerators to speed up the bitstream processing. in addition to handling bi tstream, the bit processor controls video codec hardware and communicates with host processor through ip sky blue bus and axi bus interface. before running codec, bit firmware common rou tine should be downloaded into embedded program memory through system level control. for codec programing data, bit processor read it from a specified region of system external memory through ahb bus interface. the region is specified by application settings. 40.5.1.2 codec hardware accelerator all video codec processing, except handling coefficien ts for vlc and vld, are implemented in hardware accelerator. codec hardware acceler ator is designed to reduce logi c gate count by sharing parts of sub-modules for multi-standard video encoding and decoding. codec hardware accelerator supports rotation/mirror ing function. in case of rotating/mirroring source image during encoding, rotated image is encoded direc tly without writing it to any memory space. so no additional bandwidth is needed for the processing. ho wever, the rotation/mirrori ng process in decoding process requires additional bandwidth because decodi ng has to re-use the un-rotated image for decoding the next image. so the rotated image is written to other memory space. in this scheme, the display i/f has table 40-10. video codec bit current pc register field descriptions field description 31?14 reserved 13?0 curpc[13:0]. bit current pc value. returns the current program counter of bit processor by reading this register. video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-13 not to change memory space for displaying the decode d image because subsequent rotated image is written to the same space. the rotator modules support 8-types mode of 90 x n degree (n=0, 1, 2, 3) rotating and mirroring. table 40-11 shows the supported rotating/mirroring lists a nd some possible combinations of rotating and mirroring. figure 40-10 gives architecture diagram of pre/post rotation/mirroring module. table 40-11. rotation and mirroring mode image description original image (no rotating/mirroring) example image size: 720x480 rotate left 90 (rotate right 270) example image size: 480x720 rotate left 180 (rotate right180) example image size: 720x480 rotate left 270 (rotate right 90) example image size: 480x720 horizontal mirroring example image size: 720x480 vertical mirroring example image size: 720x480 horizontal mirroring and rotate right 90 example image size: 480x720 horizontal mirroring and rotate left 90 example image size: 480x720 video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-14 freescale semiconductor figure 40-10. rotation and mirroring data flow 40.5.2 interrupts there is one interrupt signal output from video codec. basically, this interrupt is used to indicate encoding/decoding processing state. it is generated when video codec interrupt is enabled and as well as the interrupt condition is met. the interrupt signal is ac tive high and retains till the host processor clears it by writing ?1? to the interrupt clear register. this signal is synchronized to the positive edge of hclk. when getting frame completion interrupt, the software needs to set the parameters for the processing of the next frame and start the bit processor again. the parameters mainly include source/destination frame rotate right 90 and horizontal mirroring example image size: 480x720 rotate left 90 and horizontal mirroring example image size: 480x720 table 40-11. rotation and mirroring mode image description video codec external memory video codec post-rotation/ mirroring external memory frame buffer reconstruction frame buffer reconstruction source frame buffer external pre-processor pre-rotation/ mirroring display frame buffer external pre-processor reference frame buffer video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-15 buffer base address. it can be different from previous frame buffer since the previous completed frame of data may be needed for other image block like di splay module or post-processing module in system. basically, operation responding to interrupt is depende nt upon the application. for example, software can send the decoded frame to emma for post-processing, or transfer the encoded bitstream for storage, at the same time software could store the next bitstream to be processed to the external memory before starting a new encoding processing. 40.6 initialization information video codec module embedded bit processor is 16- bit programmable processor, which is highly optimized to handle bitstream/image data. in addition to processing b itstream/pixel data, bit processor also controls the communicates betw een video codec module and system. 40.7 application information figure 40-11 shows roles of bit processor and codec hard ware accelerator, and how to interface with application software. at the frame level, a hos t processor communicates with video codec through provided apis. to give video codec more flexibility and debugging capability, all processes related to the bitstream are assigned to the bit processor. figure 40-11. video codec interface with application software diagram 40.7.1 video codec processing control this section describes how bit pr ocessor controls video codec proc essing and communicates with the host. host processor external memory through video codec apis receiving parameters and command from host processor. sending status to host processor. parsing/forming bitstream (vld/vlc)/w hardware acceleration. bit-rate control, video codec control bit processor codec except bitstream parsing processing codec hardware accelerator ahb bus host interface (ip bus) video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-16 freescale semiconductor 40.7.1.1 video codec processing flow the video codec can handle a maximum of 4 processes simultaneously. each process can have a different format?mpeg-4, h.263p3, h.264, and differen t codec process?encoding or decoding. figure 40-12 shows a simplified state diagra m for running the codec process. figure 40-12. codec process state diagram each codec process consists of three categories: ? create processes: software cr eates and configures processes. ? running processes: at a proper time instance, softwa re will begin a specific process. the proper time instance means when the codec is in idle st ate and image to be encoded or bitstream to be decoded is ready in the external memory. ? quit processes: software can quit a specific process wait till the process[j] for 1 frame is finished create and initialize n if process[j] is available? where j=0...n-1 processes, process[0?n-1] idle users want to quit process[j]? all processes are closed? run process[j] quit process[j] ye s ye s ye s no no ye s video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-17 if more than one process are ready to run, each process must be assigned to different process id?runindex, which is range from 0 to 3. basically, the id is assigned based on the order of creation. for example, when 1 mpeg-4 decoding + 1 h.264 decoding + 1 h.263 decoding + 1 h.264 encoding are running simultaneously, mpeg-4 decoding is a ssigned to process index ?0?, h.264 decoding is assigned to process index ?1?, h.263 decoding is a ssigned to index ?2?, and h.264 encoding is assigned to process index ?3?. there is no priority rules for executing processes, after creating all processes at the initialization step, host enables bit processor to execute process specified with the runindex. all processes are executed in time-division like mechanism, after one process fi nishes encoding or decoding a frame, another process then can be executed. in conjunction with the process id, runcodstd needs to be set, to define which coding standard is used with the created process and whether the created proc ess will encode an image or decode a bitstream. table 40-12 shows the dedicated runcodstd value for each coding standard. all this can be done through video codec api. 40.7.1.2 video codec processing finish detection the video codec module raises interrupt signal or bus y state when frame processing command is finished. so there are three ways of detecting whethe r decoding/encoding of a frame is finished: ? polling video codec interrupt status register. in terrupt status register indicates interrupt is generated. ? polling video codec busy status register. during decoding/encoding process, as soon as the busy status becomes 0, decoding/encoding processing is finished. ? capture interrupt signal from system level, respond to interrupt request within the system interrupt service routine. note interrupt status can be cleared by writi ng 1 to interrupt clear register. busy state is self cleared after read out. 40.7.1.3 video codec processing flow example figure 40-13 shows a process flow example for decoding an h.264 bitstream and encoding images as h.264 format simultaneously. at first both decoding a nd encoding process are cr eated and initialized, then each process is executed with picture_run command alternately. more details are described as below. table 40-12. runcodstd register value for coding standard coding standard runcodstd mpeg-4/h.263 p3 decoding 0 mpeg-4/h.263 p3 encoding 1 h.264 decoding 2 h.264 encoding 3 video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-18 freescale semiconductor figure 40-13. h.264 codec process flow example *runcommand = 1 (seq_init); runcommand = 2 (seq_end); runcommand = 3 (picture_run) 1. initialize the video codec ? bit code download: load bit processor firmware to memory. ? set initial parameters: general configuration for bit processor, setting working buffer base address, bit code memory address, bitstream buffer control and so on. ? bit run start: run bit processor to initialize video codec. 2. create and initialize an h.264 decoding process ? set seq_init parameters: confi gure base address and size of bitstream buffer, base address of frame buffers and so on. ? run seq_init command: initiate an h.264 decoding process. ? wait busyflag=0: wait bit processor completes seq_init command execution. start seq_init command runindex = 1 runcodstd = 3(avc_enc) runcommand = 1 wait busyflag = 0 set picture_run parameters picture_run command runindex = 0 runcodstd = 2 runcommand = 3 check return status set seq_init parameters bit code download set initial parameters bit run start wait busyflag = 0 set seq_init parameters seq_init command runindex = 0 runcodstd = 2(avc_dec) runcommand = 1 wait busyflag = 0 read return parameters wait busyflag = 0 set picture_run parameters picture_run command runindex = 1 runcodstd = 3 runcommand = 3 wait busyflag = 0 seq_end command runindex = 0 runcodstd = 2 runcommand = 2 wait busyflag = 0 seq_end command runindex = 1 runcodstd = 3 runcommand = 2 wait busyflag = 0 end video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-19 ? read return parameters: read the features of de coded bitstream, such as the picture resolution and number of reference frames through the video codec api. in this way, the host can prepare the required frame buffers. 3. create and initialize an h.264 encoding process ? the flow is similar to the h.264 decoding proce ss except the stage of read return parameters, the encoding frame buffer size can be configur ed according to the feature of video clips. 4. run the h.264 decoding process ? set picture_run parameters: configure the frame destination address. ? run picture_run command: start the h.264 decoding process. ? wait busyflag=0: wait the bit processor co mpletes picture_run command execution. it also means one frame process is finished. the decoded frame can be sent to the emma for post-processing. the actual operation is dependant on the application. 5. run the h.264 encoding process ? the flow is similar to the h.264 decoding pr ocess. the encoding pr ocess should configure frame source address in addition to destination address. 6. execute step 4 and step 5 alternately. ? before running decoding process, the host should lo ad new bitstream to the bitstream buffer if it is empty, and update the frame destinati on address according to the application. as for encoding, the next frame should be ready in ex ternal memory before the process is run. 7. stop the codec process ? run seq_end command to each process to terminate it. basically, the process flow for encoding and decodi ng is similar, though it may have minor change for different firmware version. 40.7.1.4 frame buffer this section describes the memory map of the frame buffer and size requirement. frame buffer is specified with the ba se address and stride line. a complete image consists of y, u and v component. therefore, an image frame has 3 component buffers for each component. stride line is the width of the luminance component buffer in pixel unit and must be multiple of 8. stride line for chrominance component buffer is a half of the luminance component. video codec module supports 11-bit stride line configuration which can be larg er or equal to the width of image frame. the relationship between image size and stride line is shown in figure 40-14 . yuv components are stored line-by-line. u component in one image frame is st ored adjoining y component of the same frame. v component follows u component. next frame data follows previous frame yuv component data. the relationship between image size and stride line also decides the memory map distribution of codec image data in external memory space. between every yuv component line data, there is some optional unused memory space which size is (stride_line - image_width) byte. it is greater than or equal to zero byte, and can not be larger than (2^11 - image_width) (because stride_line is 11bit width). video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-20 freescale semiconductor figure 40-14. frame buffer configuration figure 40-15 shows the memory map of frame buffer. for v frame buffer, memory map is the same as u frame buffer except the base address. video codec supports both little and big endian system. it means y(0,0) in figure 40-15 could be located in the bit[31:24]. user can specify the endianness through video codec api. frame width - fw stride line - sl bytes frame height - fh unused memory space y fw/2 sl/2 fh/2 u fw/2 sl/2 fh/2 v base address for y frame base address for u frame base address for v frame video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-21 figure 40-15. frame buffer address map in little endian table 40-13 also shows the memory requirement in case of qcif/cif/vga resolution image. in the case of h.264, the required size for the reference frame is dependent on the level be ing supported. video codec supports up to h.264 level 3.0, which the maximum decoded picture buffer size is defined as 3037.5 y frame buffer base address: eba_y fh: frame height fw: frame width y(0,3) y(0,2) y(0,1) y(0,0) y(0,7) y(0,6) y(0,5) y(0,4) 31 24 16 23 15 8 7 0 start of y frame row 0 y(0,fw-1) y(0,fw-2) y(0,fw-3) y(0,fw-4) end of valid data in y frame row 0 other y data in the current row y(1,3) y(1,2) y(1,1) y(1,0) start of y frame row 1 optional unused memory other y data in the current frame y(fh-1,fw-1) y(fh-1,fw-2) y(fh-1,fw-3) y(fh-1,fw-4) eba_y+sl end of valid data in y frame row fh sl: stride line optional unused memory u(0,3) u(0,2) u(0,1) u(0,0) start of u frame, start of row 0 u(0,fw/2-1) u(0,fw/2-2) u(0,fw/2-3) u(0,fw/2-4) end of valid data in u frame row 0 other u data in the current row start of u frame row 1 optional unused memory end of valid data in u frame row fh/2 u(1,3) u(1,2) u(1,1) u(1,0) u(fh/2-1, other u data in the current frame optional unused memory eba_u+sl/2*(fh/2-1)+(fw/2-4) eba_y+sl*(fh-1)+(fw-4) fw/2-1) u(fh/2-1, fw/2-2) u(fh/2-1, fw/2-3) u(fh/2-1, fw/2-4) u frame buffer base address: eba_u eba_u+sl/2 video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-22 freescale semiconductor kbytes in the standard. to support h.264 cif at leve l 3.0, 2524 kbyte is needed if 16 reference frames are used. 40.7.1.5 bit processor program memory at the initialization stage of video codec, hos t processor must download common routine to bit processor. after initialization, bit processor loads a program corresponding to the activated standard. table 40-13. frame buffer requirement mpeg-4 encoder mepg-4 decoder h.264 encoder h.264 decoder qcif reference frames 1 1 1 16 current frames 1 0 1 0 reconstruction frames 11 2 1 display frame 0 1 0 1 total frames 3 3 4 18 picture size 1 1 the picture size is the minimum size of one frame buffer with assumption that the picture is yuv 4:2:0 format and the stride line is equal to frame width. 37 kbyte 37 kbyte 37 kbyte 37 kbyte total frame size 111 kbyte 111 kbyte 148 kbyte 666 kbyte cif reference frames 1 1 1 2376 kbyte current frames 1 0 1 0 reconstruction frames 11 2 1 display frame 0 1 0 1 total frames 3 3 4 2 picture size 148 kbyte 148 kbyte 148 kbyte 148 kbyte total frame size 444 kbytes 444 kbytes 592 kbytes 2672 kbytes vga reference frames 1 1 1 3037.5 kbytes current frames 1 0 1 0 reconstruction frames 11 2 1 display frame 0 1 0 1 total frames 3 3 4 2 picture size 450 kbytes 450 kbytes 450 kbytes 450 kbytes total frame size 1350 kbytes 1350 kbytes 1800 kbytes 3937.5 kbytes video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-23 there are total 65 kbyte size for current version of bit firmware to support three standards (mpeg-4, h.263 p3 and h.264), including 1 kbyte common routine. 40.7.1.6 working buffer besides buffers for frames and firmware, additiona l working buffer for intermediate data from bit processor and codec processing is needed. the buffers are such as the reconstructed pixel row buffer for mpeg-4 ac/dc prediction or h.264 intra prediction, context saving buffer for running multiple processes, bitstream re-ordering buffer for mp eg-4 data partition or h.264 fmo/aso and so on. the required working buffer size varies according to codec size, standard and capability. for example, ac/dc prediction buffer size is determined by picture width and the maximum bitstream re-ordering buffer for data partition is determined by the maximum bitstream size of one picture. working buffer size may change for different firmware version. the cu rrent version of firmware requires 256 kbytes for working buffer when decodes/encodes 720 x 576 (d1 size) up to 10 mbps. its size can be set through video codec api. the detailed working buffer is organized as table 40-14 . 40.7.1.7 bitstream buffer host processor has to assign buffers for bitstream on a per instance basis. if video codec handles n-bitstreams simultaneously in an application, the hos t should assign n bitstream buffers, and specify the base address and size. the external bitstream buffer is ?ring buffer? type. start address of ring buffer and buffer size must be written by host to bit processor. the current read or write address of ring buffer is automatically wrapped-around by firmware. in decoding case, host writes bitstream to be decoded then bit processor re ads the bitstream. in this case, the bitstream overwriting or underflow may occur and if it occurs, decoding will fail. to prevent overwriting or underflow, current bitstream read/write pointer must be exchanged between the host and bit processor. bit processor writes current read pointer of ring buffe r to internal register and host must write current write pointer of ring buffer to internal register . bit processor checks the bit buffer empty (underflow) status by comparing current read pointer and write pointer. if no more bitstream data is available to be decoded (buffer empty status), bit processor stops bitstream decoding to prevent mis-reading the table 40-14. working buffer organization working buffer description size static buffer used commonly in whole processes/codecs 48 kbytes temp_pic for mpeg4 decoding ac/dc prediction buffer and bitstream reordering buffer for data partition. 16 kbytes temp_pic for mpeg4 encoding ac/dc prediction buffer and bitstream reordering buffer for data partition. 16 kbytes temp_pic for avc decoding intra-prediction buffer, fmo grout status buffer, and slice information buffer 208 kbytes temp_pic for avc encoding intra-prediction buffer 72 kbytes video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-24 freescale semiconductor bitstream and waits until host writes more bitstream data and updates write pointer. host must check the current read pointer and write pointer before writi ng more bitstream data to ring buffer to prevent overwriting bitstream data. bitstream data is read fr om the external bitstream buffer by 512 bytes. the read pointer or write pointer is increased by 512 bytes. 40.7.1.8 buffer requirement summary table 40-15 shows a summary of buffer requirement for each decoding instance, where bitstream buffer size is not considered because the size is not limited. the total size may change for different firmware version. except bit processor program memory, other ki nds of buffer has to be assigned on a per instance basis. the overall buffer size for a multi-party call application is nearly the sum of each instanced decoding. except the bit processor program memory, other kinds of buffer has to be assigned on a per instance basis. therefore the overall buffer size for a multi-part y call application is nearly the sum of each instanced codec. 40.7.2 application using cases video codec module allows 4 channels to encode/d ecode simultaneously. that extends i.mx27 video processing application fields, and make it possibl e for multi-channel bits tream/image processing. for example, it can encode captured image in one channel, and decode other 3 channels bitstream at the same time, as shown in figure 40-16 . in figure 40-16 , gray rectangle represents the bitstream data. all codec channels image/bitstream can be encoded/decoded by di fferent codec standard, li ke one image is encoded table 40-15. summary of buffer requirement mpeg-4 encoder mepg-4 decoder h.264 encoder h.264 decoder qcif frames size 111 kbytes 111 kbytes 148 kbytes 666 kbytes program size 65 kbytes working buffer 64 kbytes 64 kbytes 120 kbytes 256 kbytes total 240 kbytes 240 kbytes 333 kbytes 987 kbytes cif frames size 444 kbytes 444 kbytes 592 kbytes 2672 kbytes program size 65 kbytes working buffer 64 kbytes 64 kbytes 120 kbytes 256 kbytes total 573 kbytes 573 kbytes 777 kbytes 2993 kbytes vga frames size 1350 kbytes 1350 kbytes 1800 kbytes 3937.5 kbytes program size 65 kbytes working buffer 64 kbytes 64 kbytes 120 kbytes 256 kbytes total 1479 kbytes 1479 kbytes 1985 kbytes 4258.5 kbytes video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 40-25 to h264/avc bitstream, and one channel h264/avc bitstream, one channel mpeg4 bitstream, one channel h263 bitstream ar e decoded separately. figure 40-16. one of application using case: one channel encoding and three channels decoding external memory rotate left 90 encode external memory for transfer external memory external memory image before pp decode mirror hori. bitstream1 external memory external memory image before pp decode rotate bitstream2 external memory external memory image before pp decode mirror veri. bitstream3 right 90 can be combined video codec module for display during display image after prp degree degree video codec (video_codec) MCIMX27 multimedia applications processor reference manual, rev. 0.2 40-26 freescale semiconductor MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-1 chapter 41 enhanced multimedia acceler ator light (emma_lt) 41.1 introduction the enhanced multimedia accelerator light (emma_lt) cons ists of the video pre-processor (prp) and post-processor (pp), which provide video acceleration and off-load th e cpu from computation intensive tasks. the prp and pp can be used for generic video pre- and post-processing, such as scaling, resizing, and color space conversions. 41.1.1 features ? pre-processor: ? data input: ? system memory ? private dma between cmos sensor interface module and pre-processor ? data input formats: ? arbitrarily formatted rgb pixels (16 or 32 bits) ? yuv 4:2:2 (pixel interleaved) ? yuv 4:2:0 (iyuv, yv12) ? input image size: 32 32 to 2044 2044 ? image scaling: ? programmable independent ch-1 and ch-2 re sizer. can program to be in cascade or parallel. ? each resizer supports downscaling ratios from 1:1 to 8:1 in fractional steps. ? channel-1 output data format ? channel 1 ? rgb 16 and 32 bpp ? yuv 4:2:2 (yuyv, yvyu, uyvy, vyuy) ? channel-2 output data format ? yuv 4:2:2 (yuyv) ? yuv 4:4:4 ? yuv 4:2:0 (iyuv, yv12) ? rgb data and yuv data format can be generated concurrently ? 32/64-bit ahb bus ? post-processor enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-2 freescale semiconductor ? input data: ? from system memory ? input format: ? yuv 4:2:0 (iyuv, yv12) ? image size: 32 32 to 2044 2044 ? output format: ? yuv 4:2:2 (yuyv) ? rgb16 and rgb32 bpp ? image resize ? upscaling ratios ranging from 1:1 to 1:4 in fractional steps ? downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 ? ratios provide scaling between qcif, cif, qvga (320 240, 240 320) 41.2 emma_lt architecture figure 41-1 shows the block diagram of emma_lt. the emma_lt consists of the pre-processor and post-processor modules. each module has individual control and configuration registers wh ich are accessed via the ip interface and are capable of bus mastering the amba bus to independently access system memo ry without any cpu intervention. this allows each module to be used independently of each other a nd enables the pre-processor and post-processor modules to provide acceleration features fo r other software codec implementati ons and image processing software. a 32 bit to 64 bit ahb gasket is used to convert ahb bus from 32-bit to 64-bit protocol. a bypass function is implemented to bypass this 64 b it gasket if it is not needed. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-3 figure 41-1. emma_lt block diagram 41.2.1 pre-processor (prp) the pre-processor (prp) module ac cepts input from main memory via a 64-bit ahb port directly from emi or from the dedicated link that connects it to camera input via the cmos sensor interface (csi) module. the prp can be operated in two modes; sing le or continuous frame (loop) mode. in single frame mode, a single frame is processed either from memory or from the dedicated csi-prp link. in this mode, the prp must be re-enabled each time a frame is to be processed. this mode is suitable for still image capture, processing and display and for very low fr ame rate operation. in continuous frame or loop mode, the prp processes input frames from the dedicated csi-prp link continuously until it is disabled or an error occurs. the prp has two output channels (channel-1 and channe l-2) and both channels store processed frames to main memory. the output from channel-1 is dedicate d for display purposes and the output from channel-2 for input to a hardware encoder (mpeg-4 encoder m odule) or a software encoder or image compressor. the prp resizes input frames from memory of from the csi and performs color space conversion. 41.2.2 post-processor (pp) the post-processor module takes decoded frames fr om memory and performs additional processing to de-block, de-ring, resize, and color space convert the decoded frames for display. the decoded input can be either from the decoder module or a software decoder module. i p b u s i n t e r f a c e csi register and control configuration image access memory csi-prp link dedicated pre-processor post-processor 64bit_gasket 32 32 32 32 32 32 or 64 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-4 freescale semiconductor 41.2.3 64-bit gasket in order to connect prp to a 64-bit ahb port of emi, a 32-bit to 64-bit ahb protocol gasket is used to manage ahb signals between 32-bit master (prp) and 64-bit ahb bus. in the event where 64 bit transfer is not required, a bypass function is implemented in the ga sket to allow the prp to ignore this 64 bit gasket and work as the original 32 bit ahb protocol. figur e 1-2 shows the basic structure of the emma-lt ahb 64-bit gasket with a bypass function. when the a hb64_sel signal is low the gasket is avoided. figure 41-2. emma ahb 64-bit gasket with bypass to 32 bit master from 32 bit master to 32/64 bit bus from 32/64 bit bus ahb64_sel ahb64_sel emma_ahb64_gasket 1 0 0 1 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-5 41.3 post-processor (pp) the post-processor (pp) performs postp rocessing functions after video decoding. the key modules in the pp are: de-block?removes blocking artifacts while preserving natural edges in the ima ges. deblock processing is bypassed if not selected. de-ring?removes ringing artifacts from decoded im ages caused by the truncation of high spatial frequencies. subjective tests have shown that pe rforming both de-ringing and de-blocking improves slightly the visual quality than performing de-b locking alone. de-ring proc essing is bypassed if not selected. y buffer (116x32) uv buffer (68x32) data from memory csc data to memory yuv to rgb programmable from 2:1 to 1:4, fixed 4:1. resize buffer (64 x 24) resize buffer (64 24) rgb buffer (128 32) rgb buffer (128 32) de-ring de-block quantizer image resize resize coefficients figure 41-3. post-processor (pp) block diagram enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-6 freescale semiconductor image resize?scales input image to a diff erent size?for example, from qcif (176 144) to qvga (320 240) to match the size of the display or to scale fr om one aspect ratio to another ratio?for example, from 1:1 to 4:3. it supports programmable resize ratios from 2:1 to 1:4, and a fixe d 4:1. horizontal resizing and vertical resizing are independent and can be set to different resizing ratios. bilinear interpolation algorithm is implemented a nd used for both upscaling and downscaling?that is, two adjacent pixels are loaded and multiplied by respective weighting coefficients to produce an output pixel. the weighting coefficients for a particular resize ra tio are calculated by software and preloaded into the resize coefficient table of the pp from which the resize block reads the coefficients to use. for example, the output samples for 3:5 bilinear interpolation can be calculated as follows: out[0] = in[0] out[1] = 2/5 * in[0] + 3/5 * in[1] out[2] = 4/5 * in[1] + 1/5 * in[2] out[3] = 1/5 * in[1] + 4/5 * in[2] out[4] = 3/5 * in[2] + 2/5 * in[3] the output samples for the 5:3 bilinear interpolation can be calculated as follows: out[0] = 2/3 * in[0] + 1/3 * in[1] out[1] = 0/3 * in[1] + 3/3 * in[2] out[2] = 1/3 * in[3] + 2/3 * in[4] a programmable resize engine is implemented in ha rdware, which reads instructions from the resize coefficient table (register emma pp resize coef table). an output pixel will be generated with the value (w1 * in1 + w2 * in2)/32 and the resize engine will then read in n new input pixels, where in1 and in2 are two adjacent pixels. if n is zero, then no new pixels are read and the in1 and in2 pixel values are reused. each instruction in the table is in the form of (w1, n,o) where each coefficient (w1) is represented with 5 bits and n with 2 bits and ?o? in 1-bit. w2 is calculated as 32-w1. note coefficient value of 31 (5?b11111) is treated as 32 (6?b100000), consequently, coefficient values of 1 and 31 are not possible. the table 41-1 and table 41-2 show some example resize coefficients. table 41-1. resize coefficients for 3:5 w1 w2 n right coefficient left coefficient in1 in2 out 1 0 0 5?b11111 (32) 5?b00000 (0) in[0] ? in[0] 2/5 3/5 1 5?b01101 (13) 5?b10011 (19) in[0] in[1] 13/32 * in[0] + 19/32 * in[1] 4/5 1/5 1 5?b11010 (26) 5?b00110 (6) in[1] in[2] 26/32 * in[1] + 6/32 * in[2] enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-7 41.3.1 color space conversion (csc) the color space conversion block converts input images from yuv to rgb color space needed for display. the csc block is fully programmable. equation used for ycbcr to rgb calculation: r = c0*(y - x0) + c1*(cr-128) g = c0*(y - x0) - c2*(cb-128) - c3*(cr-128) b = c0*(y - x0) + c4*(cb-128) equation used for yuv to rgb calculation: r = c0*(y - x0) + c1*(u-128) g = c0*(y - x0) - c2*(u-128) - c3*(v-128) b = c0*(y - x0) + c4*(u-128) 1/5 4/5 0 5?b00110 (6) 5?b11010 (26) in[1] in[2] 6/32 * in[1] + 26/32 * in[2] 3/5 2/5 1 5?b10011 (19) 5?b01101 (13) in[2] in[3] 19/32 * in[2] + 13/32 * in[3] table 41-2. resize coefficients for 5:3 w1 w2 n left coefficient right coefficient in1 in2 out 2/3 1/3 1 5?b10101 (21) 5?b01011 (11) in[0] in[1] 21/32 * in[0] + 11/32 * in[1] 0 1 2 5?b00000 (0) 5?b11111 (32) in[1] in[2] 0 * in[0] + 1 * in[1] 1/3 2/3 2 5?b01011 (11) 5?b10101 (21) in[3] in[4] 11/32 * in[0] + 21/32 * in[1] table 41-3. resize coefficients for 4:1 w1 w2 n left coefficient right coefficient in1 in2 out 1/2 1/2 1 5?b10000 (16) 5?b10000 (16) in[0] in[1] 1/2 * in[0]+ 1/2 * in[1] 0 0 1 5?b00000 (0) 5?b00000 (0) in[1] in[2] ? 0 0 1 5?b00000 (0) 5?b00000 (0) in[2] in[3] ? 0 0 1 5?b00000 (0) 5?b00000 (0) in[3] in[4] ? table 41-1. resize coefficients for 3:5 (continued) w1 w2 n right coefficient left coefficient in1 in2 out enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-8 freescale semiconductor x0, c0, c1, c2, c3 and c4 are coefficients that can be programmed through registers pp_csc_coef_0123 and pp_csc_coef_4x. c0[7:0] range from 0 to 1.9921875 in steps of (1/128). c1[7:0] range from 0 to 1.9921875 in steps of (1/128). c2[7:0] range from 0 to 1.9921875 in steps of (1/128). c3[7:0] range from 0 to 1.9921875 in steps of (1/128). c4[8:0] range from 0 to 3.9921875 in steps of (1/128). x0 1 - 16, 0 - 0. all the 10 formats defined by mpeg-4, including yuv to rgb, ycbcr to rgb and itu-r bt 709 to rgb are supported through this programmable csc bloc k. the mpeg-4 standard allows for a number of conversion scenarios. the particular type of color sp ace used by an mpeg-4 encoder is signaled in the bit stream syntax and is determined by two fields, matrix_coefficients and vi deo_range. 5 color space conversion equations (matrix coefficients) and 2 vide o ranges for each equation (matrix) are defined in mpeg-4. this gives a total of 10 (5x2) color space conversion possibilities. the 5 matrix coefficients can be categorized into tw o sets. the matrices repres ented by matrix_coefficients field values of 4, 5, and 6 are similar and can be groupe d together into one set (set a). the two remaining matrices, represented by matr ix_coefficients field values of 1 and 7, are similar and hence can be grouped together into a second set (set b). set a and set b represent csc matrices in accordance with recommendation itu-r bt.470 and recommendation itu-r bt.709, respectively. for each csc matrix, there are two possible video ranges, indicated by the video_range field which is set to either 1 or 0. therefore there are now two video ranges x 2 sets = 4 csc scenarios and each of these are summarized in table 41-4 . table 41-4. yuv to rgb csc equations eqn matrix co- efficient video range input to csc and notation matrix register values a1 4,5 or 6 (set a) 1yuv y ranges from 0-255 u ranges from 0-255 v ranges from 0-255 r = y + 1.4026 * (v-128) g = y ? 0.3444 * (u-128) ? 0.7144 * (v-128) b = y + 1.7730 * (u-128) c0 = 8?b1000 0000 c1 = 8?b1011 0011 c2 = 8?b0010 1100 c3 = 8?b0101 1011 c4 = 9?b0 1110 0010 x0 = 1?b0 a0 4,5 or 6 (set a) 0 ycrcb y ranges from 16-235 cr ranges from 16-240 cb ranges from 16-240 r = 1.164*(y ? 16) + 1.596*(cr-128) g = 1.164*(y ? 16) ? 0.813*(cr-128) ? 0.391*(cb-128) b = 1.164*(y ? 16) + 2.018*(cb-128) c0 = 8?b1001 0100 c1 = 8?b1100 1100 c2 = 8?b0011 0010 c3 = 8?b0110 1000 c4 = 9?b1 0000 0010 x0 = 1?b1 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-9 the correct matrix has to be sele cted based on the video_range and ma trix_coefficient for color space conversion. 41.3.2 input interface the pp reads iyuv or yv12 data from external memory. quantization parameter (qp) data is required if deblock and/or de-ring operations are selected. figure 41-4 shows an example layout for qcif frames to be processed by the pp. the input y, u, v, and qp data are expected in 4 s ections of memory. the first data in every row starts with a new word. when the row size is not a multiple of 4 bytes, the last few pixels in a row will not occupy a full word and the extra bytes, if any, in the last word are ignored. the pp expects one qp byte per macroblock (mb). only the lower 5 bits of a qp byte are used and the 3 most significant bits must be set to 0. the first qp in every row starts with a new word and four qp bytes from 4 adjacent mbs in a row are packed into one word. when the number of mbs in a row is not a multiple of 4, then the extra qp bytes in the last word of a qp row are ignored. data is stored in the memory in the order of natural scan lines. for y, u, and v data, it is permitted that the distance between the start of two neighboring lines (l ine stride) is greater than the number of pixels in a line?that is, there could be fixed number of unused words between the end and the beginning of every two neighboring lines. however, unused words are not permitted for qp data. each row in figure 41-4 represents a word in memory. y(j,i) denotes y data of pixel row j and column i. layout of u and v data is similar to that of y data. the figure shows there can be unused space in memory between rows. this parameter is cont rolled by the input line stride parameter and applies only to y, u, and v data in the frame. the start of y, u, and v data can be anywhere in addressable memory. b1 1 or 7 (set b) 1y?u?v? y? ranges from 0-255 u? ranges from 0-255 v? ranges from 0-255 r = y? + 1.5749 * (v?-128) g = y? ? 0.1875 * (u?-128) ? 0.4682 * (v?-128) b = y? + 1.8554 * (u?-128) c0 = 8?b1000 0000 c1 = 8?b1100 1001 c2 = 8?b0001 1000 c3 = 8?b0011 1100 c4 = 9?b0 1110 1101 x0 = 1?b0 b0 1 or 7 (set b) 0y?cr?cb? y? ranges from 16-235 cr? ranges from 16-240 cb? ranges from 16-240 r = 1.164(y?-16) + 1.793 * (cr?-128) g = 1.164(y?-16) ? 0.533 * (cr?-128) ? 0.213 * (cb?-128) b = 1.164(y?-16) + 2.112 * (cb?-128) c0 = 8?b1001 0100 c1 = 8?b1110 0110 c2 = 8?b0001 1011 c3 = 8?b0100 0100 c4 = 9?b1 0000 1110 x0 = 1?b1 table 41-4. yuv to rgb csc equations (continued) eqn matrix co- efficient video range input to csc and notation matrix register values enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-10 freescale semiconductor in a qcif image, there are 11 9 = 99 mbs, representing all the qps for a qcif image. however, due to the packing constraints specified above, the 11 qps of a row are packed into 3 words with one unused byte in the last word. this is repeated for each row and there can be no optional space between qp rows. 41.3.3 output interface the output of the pp is selectable between rgb and yuv 4:2:2 (yuyv). rgb data is internally represented with 24 bits resolution (8 bits per color component) and color bits are truncated according to the programmed color widths. this truncation is done at the last stage of color space y(0,0) y(0,2) y(0,1) y(0,3) y(0,4) y(0,6) y(0,5) y(0,7) y(0,172) y(0,174) y(0,173) y(0,175) y(1,172) y(1,174) y(1,173) y(1,175) other y data in current row optional unused memory y(143,172) y(143,174) y(143,173) y(143,175) other y data in current frame optional unused memory optional gap u frame buffer optional gap v frame buffer optional gap qp0 qp5 qp6 qp7 qp1 qp2 qp3 qp4 qp8 qp12 qp13 qp14 qp9 qp10 unused qp11 qp96 qp97 qp98 unused other qp data in current frame lsb msb start of frame, start of line 0 end of valid data in line 0 start of line 1 end of valid data in line 143 end of y frame buffer start of qp frame; start of row 0 of mb end of row 0 of mb start of row 1 of mb end of qp frame buffer figure 41-4. pp input data layout (qcif) enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-11 conversion by discarding the least significant bits. for 8 bpp output only 1:1 resize ratio is supported. table 41-5 shows some examples for 16 bpp and unpacked 24 bpp settings. 41.3.4 data flow the post-processing block reads yuv 4:2:0 data from external memory and writes processed rgb or yuyv 4:2:2 data into external memory. a typical use case of the pp in i.mx27 device is as follows: 1. software or hardware decoder decodes one frame 2. pp is programmed with frame buffer a ddress and other ancillary information 3. software enables pp 4. for every mb read from memory, pp performs deblock, dering, resize, and csc and writes to output buffer for display 5. when all mbs of the current frame are pro cessed, pp signals frame completion to the core 6. when pp completes frame processing, it sets the frame completion status and interrupts the cpu. 41.3.5 relationship of register fields related to the input frame figure 41-5 shows how the input line stride affects the ar ea of frame that is processed by the pp. there are two rectangular areas in the diagram. the inner r ectangle shows the frame area to be processed and the outer rectangle indicates the actual memory allocated for the total frame. pp_y_source, pp_cr_source, and pp_cb_source are pointers to the start addresses of frame data. the input line stride, width, and height parameters are automatically divided by 2 when processing the cr and cb frame components. table 41-5. rgb color width and offsets pixel format bpp rgb width rgb offset packed 16-bit rgb565 16 redwidth = 5 greenwidth = 6 bluewidth = 5 redoffset = 11 greenoffset = 5 blueoffset = 0 unpacked 32-bit rgb888 32 redwidth = 8 greenwidth = 8 bluewidth = 8 redoffset = 16 greenoffset = 8 blueoffset = 0 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-12 freescale semiconductor figure 41-5. input line stride 41.3.6 relationship of register fields related to output frame figure 41-6 shows the effect of the output line stride parameter on the output frame. the output line stride can be used to select a smaller area of the processed and resized frame. the figure shows two rectangular areas. the outer rectangle shows the memo ry allocated for display. the inner rectangle shows the size of the final output image. the output image size is defined by the output line stride, image_width, and image_height parameters. process_frame_para.width y_input_line_stride process_frame_para.height pp_y_source pp_cb_source process_frame_width/2 y_input_line_stride/2 process_frame_height/2 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-13 figure 41-6. output line stride note output line stride is specified in bytes while image_width and image_height are specified in pixels. 41.4 post processor (pp) programming model only 32-bit accesses (read/write) is supported. all reserv ed bits should always be written with 0 and all registers are r/w unless specified. table 41-6 shows the memory map. table 41-6. pp register memory map address description access reset value section/page 0x1002_6000 (pp_cntl) pp control register r/w 0x0000_0876 41.4.1/41-14 0x1002_6004 (pp_intrcntl) pp interrupt control r/w 0x0000_0000 41.4.2/41-15 0x1002_6008 (pp_intrstatus) pp interrupt status r/w 0x0000_0?0? 41.4.3/41-16 0x1002_600c (pp_source_y_ptr) pp source y frame data pointer r/w 0x0000_0000 41.4.4/41-17 0x1002_6010 (pp_source_cb_ptr) pp source cb frame data pointer r/w 0x0000_0000 41.4.5/41-18 0x1002_6014 (pp_source_cr_ptr) pp source cr frame data pointer r/w 0x0000_0000 41.4.6/41-19 0x1002_6018 (pp_dest_rgb_ptr) pp destination rgb frame start address r/w 0x0000_0000 41.4.7/41-19 0x1002_601c (pp_quantizer_ptr) pp quantizer start address r/w 0x0000_0000 41.4.8/41-20 0x1002_6020 (pp_process_para) pp process frame parameter, width and height r/w 0x0000_0000 41.4.9/41-21 dest_start_address output_line_stride image_width image_height enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-14 freescale semiconductor 41.4.1 pp control register figure 41-7 shows the register; table 41-7 provides its field descriptions. 0x1002_6024 (pp_frame_width) pp source frame width r/w 0x0000_0000 41.4.10/41-21 0x1002_6028 (pp_display_width) pp destination display width r/w 0x0000_0000 41.4.11/41-22 0x1002_602c (pp_image_size) pp destination image size r/w 0x0000_0000 41.4.12/41-23 0x1002_6030 (pp_dest_frame_format_cntl) pp destination frame format control r/w 0x0000_0000 41.4.13/41-24 0x1002_6034 (pp_resize_index) pp resize table index r/w 0x0000_0000 41.4.14/41-25 0x1002_6038 (pp_csc_coef_123) pp csc coefficients r/w 0x0000_0000 41.4.15/41-26 0x1002_603c (pp_csc_coef_4) pp csc coefficients r/w 0x0000_0000 41.4.16/41-27 0x1002_6000?0x1002_607c (pp_resize_coef_tbl) pp resize coefficient table w 0x0000_0000 41.4.17/41-28 0x1002_6000 (pp_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0 0 0 bsdi csc_out mb_ mod e swr st 0 csc table sel csce n 0 de ring en de bloc k en pp_e n w reset0000100001110110 figure 41-7. pp control register table 41-7. pp control register field descriptions name description 31?13 reserved?these bits are reserved and should read 0. 12 bsdi byte swap input data. the input data word from memory is byte swapped (32-bit little endian to big endian or vice versa) before use. 0 swap disabled 1 swap enabled table 41-6. pp register memory map (continued) address description access reset value section/page enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-15 41.4.2 pp interrupt control register figure 41-8 shows the register; table 41-8 provides its field descriptions. 11?10 csc_out csc output. sets rgb output resolution. 00 32-bit (unpacked rgb888) 01 reserved 10 16-bit 11 32-bit (unpacked rgb888) 9 reserved?this bit should always read 0 8 swrst software reset. resets entire module, all registers return to their reset default values. 0 no reset 1 reset 7 reserved reserved. this bit is reserved and should read 0. 6?5 csc_table_sel csc table select. selects one of the 4 csc matrices. refer to table 41-4 for more information. 00 a1 01 a0 10 b1 11 b0 4 cscen csc enable. enables csc to output rgb data else yuv 4:2:2 data when disabled. yuv 4:2:2 output is in yuyv interleaved format. 0 yuv 4:2:2 1 rgb 3 reserved. this bit is reserved and should read 0. 2 deringen de-ring enable. enable or disable dering operation. 0 no dering 1 enable dering 1 deblocken de-block enable. enable or disable deblock operation. 0 no deblock 1 enable deblock 0 pp_en pp enable. start frame processing. bit has no effect if the lock_bit was not previously read successfully with idle status. once enabled, this bit cannot be reset unless one of the following has occurred; frame is completely processed or swrst is set or data abort error. 0 not enabled 1 enabled (self-clearing) table 41-7. pp control register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-16 freescale semiconductor 41.4.3 pp interrupt status register figure 41-9 shows the register; table 41-9 provides its field descriptions. 0x1002_6004 (pp_intrcntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0000000000000 err intr _en 0fra me com p intr en w reset0000000000000000 figure 41-8. pp interrupt control register table 41-8. pp interrupt control register description name description 31?3 reserved. this bit is reserved and should read 0. 2 err_intr_en error interrupt enable. if set, enables interrupt on error. 0 interrupt disabled 1 interrupt enabled 1 reserved. this bit is reserved and should read 0 0 frame_comp_intr_en frame complete interrupt enable. if set and in frame mode (mb_mode=0), enables interrupt on completion of frame processing. 0 interrupt disabled 1 interrupt enabled enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-17 41.4.4 pp source y address register figure 41-10 shows the register; table 41-10 provides its field descriptions. 0x1002_6008 (pp_intrstatus) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0000000000000 err intr _en 0fra me com p intr en w reset0000000000000w1c0w1c figure 41-9. pp interrupt status register table 41-9. pp interrupt status register field descriptions name description 31?3 reserved. these bits are reserved and should be set to 0. 2 err_intr error interrupt status. if set an error has occurred. the pp has to be reset (swrst = 1) before further operations can be initiated. 1 reserved. 0 frame_comp_intr frame complete interrupt status. if set, a frame has been processed. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-18 freescale semiconductor 41.4.5 pp source cb address register figure 41-11 shows the register; table 41-11 provides its field descriptions. 0x1002_600c (pp_source_y_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r pp_y_source w reset0000000000000000 1514131211109876543210 r pp_y_source w reset0000000000000000 figure 41-10. pp source y address register table 41-10. pp source y address register field descriptions name description 31?0 pp_y_source pp_source_y_ptr. 32-bit frame start address of y data (luminance). bits 1?0 are always set to 0 (word aligned) 0x1002_6010 (pp_source_cb_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r pp_cb_source w reset0000000000000000 1514131211109876543210 r pp_cb_source w reset0000000000000000 figure 41-11. pp source cb address register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-19 41.4.6 pp source cr address register figure 41-12 shows the register; table 41-12 provides its field descriptions. 41.4.7 pp destination rgb frame start address register figure 41-13 shows the register; table 41-13 provides its field descriptions. table 41-11. pp source cb address register field descriptions name description 31?0 pp_cb_source pp_source_cb_ptr. 32-bit frame start address of cb data (u or chrominance). bit 1?0 are always set to 0 (word aligned) 0x1002_6014 (pp_source_cr_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r pp_cr_source w reset0000000000000000 1514131211109876543210 r pp_cr_source w reset0000000000000000 figure 41-12. pp source cr address register table 41-12. pp source cr address register field descriptions name description 31?0 pp_cr_source pp_source_cr_ptr. 32-bit frame start address of cr data (v or chrominance). bits 1?0 are always set to 0 (word aligned) enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-20 freescale semiconductor 41.4.8 pp quantizer start address register figure 41-14 shows the register; table 41-14 provides its field descriptions. 0x1002_6018 (pp_dest_rgb_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rgb_start_addr w reset0000000000000000 1514131211109876543210 r rgb_start_addr w reset0000000000000000 figure 41-13. pp destination rgb frame start address register table 41-13. pp destination rgb frame start address register description name description 31?0 rgb_start_addr rgb start address. sets the destination frame start address. if cscen = 0, then these bits point to the start of yuv 4:2:2 (yuyv interleaved) data, else it points to rgb data. bit 1?0 are always set to 0 (word aligned). 0x1002_601c (pp_quantizer_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r quantizer_ptr w reset0000000000000000 1514131211109876543210 r quantizer_ptr w reset0000000000000000 figure 41-14. pp quantizer start address register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-21 41.4.9 pp process frame parameter register figure 41-15 shows the register; table 41-15 provides its field descriptions. 41.4.10 pp source frame width register figure 41-16 shows the register; table 41-16 provides its field descriptions. table 41-14. pp quantizer start address register description name description 31?0 quantizer_ptr quantizer_ptr. sets the start address of the quantization parameter in memory. this register is ignored if deblock and de-ring are both disabled. bits 1?0 are always set to 0 (word aligned) 0x1002_6020 (pp_process_para) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 process_frame_width[9:0] w reset0000000000000000 1514131211109876543210 r000000 process_frame_height[9:0] w reset0000000000000000 figure 41-15. pp process parameter register table 41-15. pp process parameter register description name description 31?26 reserved. these bits are reserved and should read 0. 25?16 process_frame_width process frame width. sets the input window width to be processed based on y frame pixel count. process_frame_width/2 is used for cb and cr window width. process_frame_width must always be less than or equal to input_line_stride. this value should be a multiple of 8 pixels. 15?10 reserved. these bits are reserved and should read 0. 9?0 process_frame_height process frame height. sets the input window height to be processed based on y frame line count. process_frame_height/2 is used for cb and cr window height. this value should be a multiple of 8 lines. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-22 freescale semiconductor 41.4.11 pp destination display width register figure 41-17 shows the register; table 41-17 provides its field descriptions. 0x1002_6024 (pp_frame_width) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 quantizer_frame_width w reset0000000000000000 1514131211109876543210 r0 0 0 0 y_input_line_stride w reset0000000000000000 figure 41-16. pp source frame width register table 41-16. pp source frame width register field descriptions name description 31?24 reserved. these bits are reserved and should read 0. 23?16 quantizer_frame_width quantizer frame width. these bits set the number of bytes used to represent quantizers from all the mb in a row. qp data is packed into words with possibly unused bytes in the last word when the number of mb in a row in not a multiple of 4. in such cases, quantizer_frame_width is rounded up to the nearest 4-byte multiple (word) that represents all the qp data for one row of mbs. for example, if there are 7 mbs in a row, then 2 words are required to represent the 7 qp data bytes with one unoccupied byte. the quantizer_frame_width in this example is set as 8 (7 bytes rounded up to the nearest multiple of 4). this value should be a multiple of 4 bytes. 15?12 reserved. these bits are reserved and should read 0. 11?0 y_input_line_stride y input line stride. these bits set the number of pixels between adjacent rows of pixels for y input data. y_input_line_stride/2 is used for cb and cr input data. this value must be a multiple of 8 pixels. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-23 41.4.12 pp destination image size register figure 41-18 shows the register; table 41-18 provides its field descriptions. 0x1002_6028 (pp_display_width) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0 0 0 output_line_stride w reset0000000000000000 figure 41-17. pp destination display width register table 41-17. pp destination display width register description name description 31?13 reserved. these bits are reserved and should read 0. 12?0 output_line_stride output line stride. these bits set the distance in bytes between the start addresses of adjacent lines in the output frame. if the stride is equal to the out_image_width, then the stride should be calculated as: out_image_width * bytes per pixel. this value should be a multiple of 4 bytes. 0x1002_602c (pp_image_size) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 0 out_image_width w reset0000000000000000 1514131211109876543210 r0 0 0 0 out_image_height w reset0000000000000000 figure 41-18. pp destination image size register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-24 freescale semiconductor 41.4.13 pp destination frame format control register figure 41-19 shows the register; table 41-19 provides its field descriptions. note this register is used only when the output is in rgb format. table 41-18. pp destination image size register description name description 31?28 reserved. these bits are reserved and should read 0. 27?16 out_image_width out image width. these bits set the width of the output in pixels (not bytes). this value must always be a multiple of 2. out_image_width[0] is read-only and always 0. 15?12 reserved. these bits are reserved and should read 0. 11?10 out_image_height out image height. these bits set the number of lines in the output. this value must always be a multiple of 2. out_image_height[0] is read-only and always 0. 0x1002_6030 (pp_dest_frame_format_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 red_offset green_offset blue_offset w reset0 0 0 000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 0 red_width green_width blue_width w reset0 0 0 000000000000 0 figure 41-19. pp destination frame format control register table 41-19. pp destination frame format control register description name description 31 reserved. these bits are reserved and should read 0. 30?26 red_offset red offset. specifies the bit offset of the red color or luminance component in the output pixel the offset is specified with respect to bit 0. 25?21 green_offset green offset. specifies the bit offset of the green color or chrominance (u) component in the output pixel. the offset is specified with respect to bit 0. 20?16 blue_offset blue offset. specifies the bit offset of the blue color or chrominance (v) component in the output pixel. the offset is specified with respect to bit 0. 15?12 reserved. these bits are reserved and should read 0. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-25 the following table shows some example conf igurations for the yuv 4:2:2 combinations. 41.4.14 pp resize table index register this register sets the start and end indices of horizont al and vertical resize tables. the two resize tables share a memory of 40 locations. the minimum start index is 0 and the maximum end index is 39. if the horizontal and vertical resize ratios are the same, then one resize table can be used and the horizontal and vertical start and end indices can be set to the same va lue. however, if the resize ratios are different, the horizontal and vertical resize tables need to be pr ogrammed differently. either the horizontal resize table or the vertical resize table can start from address 0. figure 41-20 shows the register; table 41-21 provides its field descriptions. 11?8 red_width red width. specifies the number of bits in the red color component in the output pixel. the width of the luminance component is fixed at 8 bits, always. allowed values are 0 to 8. any value greater than 8 is fixed to 8 internally. 7?4 green_width green width. specifies the number of bits in the green color component in the output pixel. the width of the chrominance (cb or u) component is fixed at 8 bits, always. allowed values are 0 to 8. any value greater than 8 is fixed to 8 internally. 3?0 blue_width blue width. specifies the number of bits in the blue color component in the output pixel.the width of the chrominance (cr or v) component is fixed at 8 bits, always. allowed values are 0 to 8. any value greater than 8 is fixed to 8 internally. table 41-20. yuv 4:2:2 configuration settings yuv format offsets width settings yuyv red_offset=24 green_offset=16 blue_offset=0 red_width=8 green_width=8 blue_width=8 0x6200_0888 yvyu red_offset=24 green_offset=0 blue_offset=16 0x6010_0888 uyvy red_offset=16 green_offset=24 blue_offset=8 0x4308_0888 vyuy red_offset=16 green_offset=8 blue_offset=24 0x4118_0888 table 41-19. pp destination frame format control register description (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-26 freescale semiconductor 41.4.15 pp csc coef 123 register figure 41-21 shows the register; table 41-22 provides its field descriptions. 0x1002_6034 (pp_resize_index) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 hori_tbl_start_index 00 hori_tbl_end_index w reset0 0 0 000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 vert_tbl_start_index 00 vert_tbl_end_index w reset0 0 0 000000000000 0 figure 41-20. pp resize table index register table 41-21. pp resize table index register field descriptions name description settings 31?30 reserved. these bits are reserved and should read 0. 29?24 hori_tbl_start_index horizontal table start index. start index of horizontal resize table. valid values: 0?39 23?22 reserved. these bits are reserved and should read 0. 21?16 hori_tbl_end_index horizontal table end index. end index of horizontal resize table. valid values: 0?39 15?14 reserved. these bits are reserved and should read 0. 13?8 vert_tbl_start_index vertical table start index. start index of vertical resize table. valid values: 0?39 7?6 reserved. these bits are reserved and should read 0. 5?0 vert_tbl_end_index vertical table end index. end index of vertical resize table. valid values: 0?39 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-27 41.4.16 pp csc coef_4 register figure 41-22 shows the register; table 41-23 provides its field descriptions. 0x1002_6038 (pp_csc_coef_123) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r c0 c1 w reset0 0 0 000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r c2 c3 w reset0 0 0 000000000000 0 figure 41-21. pp csc coefficient_123 register table 41-22. pp lock bit register field descriptions name description 31?24 c0[7:0] csc coefficient 0 range from 0 to 1.9921875 in steps of (1/128) 23?16 c1[7:0] csc coefficient 1 range from 0 to 1.9921875 in steps of (1/128) 15?8 c2[7:0] csc coefficient 2 range from 0 to 1.9921875 in steps of (1/128) 7?0 c3[7:0] csc coefficient 3 range from 0 to 1.9921875 in steps of (1/128) 0x1002_603c (pp_csc_coef_4) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 000000000000 0 w reset0 0 0 000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0 0 0 0 0 x0 c4 w reset0 0 0 000000000000 0 figure 41-22. pp csc coefficient_4 register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-28 freescale semiconductor 41.4.17 pp resize coefficient table figure 41-23 shows the register; table 41-25 provides its field descriptions. note this is a write-only register. table 41-23. pp csc coef_4 register field descriptions name description 31?10 reserved. these bits are reserved and should read 0 9 x0 x0. luminance component offset 1 = 16 0 = 0 8?0 c4 csc coefficient 4. range from 0 to 3.9921875 in steps of 1/128 table 41-24. csc coefficient usage yuv format yuv/rgb conversions ycbcr r = c0*(y ? x0) + c1*(cr-128) g = c0*(y ? x0) ? c2*(cb-128) ? c3*(cr-128) b = c0*(y ? x0) + c4*(cb-128) yuv r = c0*(y ? x0) + c1*(v-128) g = c0*(y ? x0) ? c2*(u-128) ? c3*(v-128) b = c0*(y ? x0) + c4*(u-128) 0x1002_6000?0x1002_607c (pp_resize_coef_tbl) access: user write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w0 0 0 000000000000 0 reset0 0 0 000000000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r w[4:0] n[1:0] op w0 0 0 00000 reset0 0 0 000000000000 0 figure 41-23. pp resize coefficient table (array of 32 resize coefficients) enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-29 table 41-25. pp resize coefficient table register field descriptions name description 31?8 reserved. these bits are reserved and should read 0. 7?4 w weighting coefficient. these bits set the weighting coefficient applied to the older of the two pixels used in the resize equation. valid values for weight are 0, 2 to 30, and 31. a value of 31 is treated as 32 and therefore 31 is an invalid co-efficient. the resizing algorithm uses w as the weighting coefficient 1, w1. w1 = w weighting coefficient 2, w2, is calculated as: w2 = 32?w1 2?1 n number of pixels to read. these bits set the number of new pixels to read. 00 no pixels are read. 01 1 new pixel is read. 10 2 new pixels are read. 11 3 new pixels are read. 0 op output pixels. this bit controls if pixels are output 1 pixels are output. 0 no pixels are output. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-30 freescale semiconductor 41.5 pre-processor table 41-26. pre-processing block diagram the pre-processor receives input from main memory or from the camera sensor via the cmos sensor interface (csi) module and outputs two channels of data, one for video encoding and another for video display. input data undergoes resize in a cha nnel-1 and channel-2 resi ze block which provides programmable downscaling. the channel-1 resize can be connected in cascade or parallel to channel-2 resize. this is followed by programmable color sp ace conversion. the csc block provides conversion from yuv to rgb and rgb to yuv for ch-1 and rgb to yuv for channel-2. after csc, the data is channelled into memory. ch annel-1 output is meant for display and both rgb and yuv 4:2:2 (interleaved) form ats are supported. data output on channe l-2 is meant for video encoding and various yuv formats are supported in this path. name ly, the yuv 4:2:0 (planar) format matches most mpeg-4 video encoder inputs and is required by the on-chip mpeg-4 encoder. note: channel-1 meant for display channel-2 meant for video encoder supports: rgb to yuv yuv to rgb line buffer (128x48) line buffer (128x48) csc_ch1 buffer (64 x 32) csc_ch1 buffer (64 x32) csc_ch2 buffer (64 x 32) ch-1 resize channel-1 yuv-acc buff (400 x 33) csc_ch 2 buffer (64 x 32) channel-2 csc csc ch-2 resize yuv-acc buff (400 x 33) supports: rgb to yuv to m e m o r y y u v 4:2:0 yuv 4:2:2 (yuyv) yuv 4:4:4 from csi or memory yuv4:2:2 yuv4:2:0 rgb16/32 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-31 41.5.1 features 41.5.2 input data formats table 41-27 shows the input data formats for the pre-processor. 41.5.2.1 input size the pre-processor can accept frames as small as 32 32 pixels to as large as 2044 2044 pixels. for yuv 4:2:0, the maximum frame size is limited to 2040 2040 pixels. 41.5.2.2 resize ratios there are two independent and identica l resize blocks in the pre-proce ssor, called the channel-1 resize block and the channel-2 resize block. the channel-1 re size block can either work in parallel to the channel-2 resize block, that is, both blocks connect to the input, or in cascade to the output of the channel-2 resize. each resize block supports two resize algorithms: bili near and averaging. for each resize block, a user needs select one of the algorithms through register bit before starting resizing. table 41-27. input data formats source format resolution csi rgb 16 bpp rgb 32 bpp (unpacked rgb888) yuv 4:2:2 pixel interleaved yuv 4:4:4 32 bpp?pixel interleaved memory rgb 16 bpp rgb 32 bpp (unpacked rgb888) yuv 4:2:2 pixel interleaved yuv 4:2:0 band interleaved (iyuv and yv12) yuv 4:4:4 32 bpp?pixel interleaved table 41-28. resize ratios resize block resize ratio description channel-1 resize 1:1 data is copied from input to output. no resize is effected. programmable from 1:1 to 8:1 or when cascaded, from 8:1 to 64:1 downscaling channel-2 resize 1:1 data is copied from input to output. no resize is effected. programmable from 1:1 to 8:1 downscaling enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-32 freescale semiconductor 41.5.2.3 output formats table 41-29 shows the output formats suppor ted on channel-1 and channel-2. 41.5.2.4 output data output data is always written to memory pointed to by the destination pointers of channel-1 and channel-2. 41.5.2.5 output size minimum output size on channel-1 and channel-2 is 32 32 pixels and resize ratios must be calculated accordingly to prevent data truncation at the output. 41.5.3 resize the channel-1 resize and cha nnel-2 resize modules are primarily used to resize captured sensor images and suitably format them to match the viewfinder display and video encoder input requirements. for example, an image or live video input from a 640 x 480 camera sensor can be resized to fit an lcd display of 240 x 320 or 320 x 320. the resizer can also prepare data for video encoding (channel-2). each resize module implements two resize algorithms: bilinear and averaging, and one of the algorithms can be enabled at any single time. 41.5.3.1 bilinear resize in prp bilinear interpolation algorithm is implemented and recommended for resize ratios between 1:1 and 2:1. here two adjacent pixels are loaded and multiplied by respective weighting coefficients to produce an output pixel. the weighting coefficients for a particular resize ra tio are calculated by software and preloaded into the resize coefficient registers (eg. register emma prp_ch1_rz_hori_coef1) of the prp from which the resize block reads the coefficients to use. table 41-29. output formats channel output format resolution description channel-1 rgb 8 bpp 4 pixels in an output word 16 bpp 2 pixels in an output word 32 bpp unpacked rgb888?1 pixel in an output word yuv 4:2:2 yuyv,yvyu,uyvy, vyuy pixel interleaved?2 pixels in an output word channel-2 yuv 4:2:2 yuyv pixel interleaved?2 pixels in an output word yuv 4:2:0 iyuv, yv12 band interleaved yuv 4:4:4 yuv0 pixel interleaved?1 pixel in an output word enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-33 for example, the output samples for the 5:3 bilinear interpolation can be calculated as follows: out[0] = 5/8 * in[0] + 3/8 * in[1] out[1] = 0/8 * in[1] + 8/8 * in[2] out[2] = 3/8 * in[3] + 5/8 * in[4] the entries should be (5 ,1),(0,1),(x,0),(3,1),(x,0). a programmable resize engine has been implemented in hardware, which reads instructions from the prp resize coefficient registers (register emma prp_ch1_rz_hori_coef1, prp_ch1_rz_hori_coef2, prp_ch1_rz_vert_coef1, prp_ch1_rz_vert_coef2, prp_ch2_rz_hori_coef1, prp_ch2_rz_hori_coef2, prp_ch2_rz_vert_coef1, prp_ch2_rz_vert_coef2). an output pixel will be ge nerated with the value (w1 * in1 + w2 * in2)/8 where in1 and in2 are two adjacent pixels. the resize e ngine will then read in one new input pixel, if the corresponding von bit in the corresponding register s (register emma prp_ch1_rz_hori_valid, prp_ch1_rz_vert_valid, prp_ch2_rz_hori_valid, or prp_ch2_rz_vert_valid) is true ?1?. therefore, each resize instruction is in the form of (w1, n) where each coefficient (w1) is represented with 3 bits and n with 1-bit, and stored in 2 register s, one for w1 coefficient, and one for n valid. w2 is calculated as 8-w1. ? allowed values of w1 are 0,1,2,3,4,5,6 and 7. w1 coefficient value of 7 (3?b111) is treated as 8 (4?b1000), consequently, w1 coefficient value of 7 is not possible. ? prp resize weighting coefficients only have 3 bits, not 5 bits as in pp resize. 41.5.3.2 averaging resize in prp this is a special convolution filter where a weighted average of every n input pixels will produce an output pixel, when the resize ratio is n:1. suppose in[0], in [1], ... in[n] are input pixels, w[i] are weighting coefficients, and out[0] is the corresponding output pixel, then out[0] = w[0] * in[0] + w[1] * in[1] +... + w[n] * in[n]. the resize instruction for prp averaging is also in the form of (w, n) where each coefficient (w) is represented with 3 bits and n with 1-bit. the aver aging resizer is also impl emented as a programmable resize engine. one pixel is loaded every cycle to the resize engine and a multiplication and accumulate operation is applied. a temporary register, t is used to store the interim result. on reset or at the beginning of a line (for horizontal re size) or a row (for vertical resize), t is reset to 0. then the process is as follows in every cycle: 1. load a new input pixel value into the ?in? register 2. t=t+ w*in; where 0 <= w <= 7. 3. if n bit is true ?1?, then an output pixel is produced as: out = t/8. after that t is reset to 0. the sum of all w coefficients (w[0]+w[1]+...+w[n]) fo r an output pixel will be 8. the resize instructions (w, n) are stored in 2 registers, one for w coeffi cient (for example, prp_ch1_rz_hori_coef1), and one for n (for example, prp_ch1_rz_hori_valid). enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-34 freescale semiconductor ? w coefficient value of 7 (3?b111) is treated as 8 (4?b1000), consequently, w coefficient value of 7 is not possible. following are some example resize tables: 3:1: (2, 0) (4, 0) (2, 1) 4:1: (1, 0) (3, 0) (3, 0) (1, 1) 7:1: (1, 0) (1, 0) (1, 0) (2, 0) (1, 0) (1, 0) (1, 1) non n:1 resize ratios - m:n - (greater than 2:1) can be supported in averaging resize algorithm by converting into n x[i]:1 resizing ratios, where the su m of x[i], i=1..n will be m. for example, 5:2 resize can be converted into 3:1 + 2:1 resize and the resize ta ble could be 5:2 (2, 0) (4, 0) (2, 1) (4, 0) (4, 1) 41.5.3.3 combined bilinear and averaging can choose bi-linear and averaging at same time for two different direction. that is horizontal can be averaging and vertical be using bi-linear. 41.5.3.4 resize output image size for m:n resize ratio the output image width is rzoutwidth = [rzinwidth * (n/m)] where [] integer operation. for example if input image width is 176 and resize ratio of 5:3 then rzwidthout = [176*3/5] = 105 pixels. it should be noted that the height calculation will be updated. 41.5.3.5 channel-1 output table 41-30 summarizes the channel-1 output requirements and limits. all channel-1 output must be word aligned. the final output on channel-1 is cont rolled by the ch1_out_image_width and ch1_out_image_height settings and the maximum values for these cannot exceed those of ch1_width and rzheightout. table 41-30. channel-1 output formats and sizes output resolution ch1_width description example output format 8 bpp rzwidthout and ~0x03 rounded down to a multiple of 4 rgb 332 16 bpp rzwidthout and ~0x01 rounded down to a multiple of 2 rgb 565 or yuv 4:2:2 32 bpp rzwidthout output is word aligned unpacked rgb888 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-35 41.5.3.6 channel-2 output table 41-31 summarizes the channel-2 output requirement s and limits. the inputs are from ch2 resize. 41.5.4 color space conversion (csc) if an image sensor produces rgb output then color space conversion (csc) is required to convert from rgb to a yuv color space format used for mpeg-4 encoding. the mpeg-4 standard allows for a number of colo r space conversion (csc) scenarios. the particular type of csc used by an mpeg-4 en coder is signaled in the bit stream syntax and is determined by two fields, these being matrix_coefficients and video_range . to allow total flexibility, programmable csc matrices are implemented. calculation of each coefficient depend upon precision or steps it need to represent. support a coefficient is specified in steps of (1/128) and user want to re present 0.345 in that then they need to calculate as int(128*0.345) = 44. 41.5.5 rgb to yuv the mpeg-4 encoder only operates in yuv (or also referred to as ycbcr) color space and therefore if an image sensor produces rgb output, there is a need to perform rgb to yuv color space conversion. the mpeg-4 standard allows a number of yuv formats and these can be summarized by four color space conversion equations. the conversion from rgb to yuv 4:2:0 (and yuv 4:2:2) can be decomposed into two steps. the first step is the conversion from rgb to yuv 4:4:4 and the second step is the down sampling from yuv 4:4:4 to yuv 4:2:0 (or yuv 4:2:2). down sampling from yuv 4:4:4 to yuv 4:2:0 is done by skipping alternate pixel and lines. similarl y down sampling from yuv 4:4:4: to yuv 4:2:2 is done by skipping alternate pixels. the conversion matrices for color space conversion (csc) and the downsampling procedure is discussed below. the mpeg-4 standard allows four csc matrices to be employed for rgb to yuv conversion. the actual matrix that is used needs to be indicated in the b it stream to allow the decode r to choose the appropriate inverse matrix for yuv to rgb conversion. see table 41-32 . table 41-31. channel-2 output formats and sizes output format y_width y_height u, v width, and height yuv 4:2:0 rzwidthout and ~0x07 (multiple of 8) rzheightout and ~0x01 band interleaved: u_width = y_width/2 v_width = y_width/2 u_height = y_height/2 v_height = y_height/2 yuv 4:2:2 rzwidthout and ~0x01 rzheightout pixel interleaved yuv 4:4:4 rzwidthout rzheightout pixel interleaved enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-36 freescale semiconductor 41.5.5.1 yuv to rgb for yuv to rgb conversion matrices, refer to table 41-4 . 41.5.5.2 clipping of rgb and yuv outputs the output rgb or yuv values are clipped to the range of 0 to 255. 41.5.6 frame skip frame skipping is done to reduce the output frame rate . it can be done at three stages. firstly at input, secondly at channel-1 output and thirdly at channel-2 output by usi ng in_skip,ch1_skip and ch2_skip bits of prp_cntl register, respectively. frame skip is valid only when input is from csi (csien = 1). input frames are skipped by using in_skip then pass ed to channel-1 and channel-2. each skip is controlled independently. example 1: channel-1 and channel-2 are configured in parallel 1. in_skip = 3?b010 2. ch1_skip = 3?b001 3. ch2_skip = 3?b100 4. let the input frame sequence be: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 5. after applying in_skip, the reduced sequence is: 0, 2, 3, 5, 6, 8, 9, 11, 12. these frames are sent to channel-1 and channel-2 (since th ese are configured in parallel). 6. output from channel-1 after applying ch1_skip is: 0, 3, 6, 9, 12 table 41-32. yuv to rgb csc equations equation name matrix coefficient video range input to csc and notation matrix a1 4, 5 or 6 (set a) 1yuv y ranges from 0?255 u ranges from 0?255 v ranges from 0?255 y = 0.299*r + 0.587*g + 0.114*b u = -0.169*r ? 0.331*g + 0.5*b + 128 v = 0.5*r - 0.419*g - 0.081*b + 128 a0 4, 5 or 6 (set a) 0 ycrcb y ranges from 16?235 cr ranges from 16?240 cb ranges from 16?240 y = 0.2568*r + 0.5041*g + 0.0979*b + 16 cb = -0.1484*r - 0.2907*g + 0.4392*b + 128 cr = 0.4392*r - 0.3680*g - 0.0711*b + 128 b1 1 or 7 (set b) 1y?u?v? y? ranges from 0?255 u? ranges from 0?255 v? ranges from 0?255 y = 0.2126*r + 0.7152*g + 0.0722*b u = -0.115*r - 0.386*g + 0.5*b + 128 v = 0.5*r - 0.454*g - 0.046*b + 128 b0 1 or 7 (set b) 0y?cr?cb? y? ranges from 16?235 cr? ranges from 16?240 cb? ranges from 16?240 y = 0.1826*r + 0.6142*g + 0.0620*b + 16 cb = -0.1010*r - 0.3390*g + 0.4392*b + 128 cr = 0.4392*r - 0.3988*g - 0.0404*b + 128 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-37 7. output from channel-2 after applying ch2_skip is: 0, 2, 3, 6, 8, 9, 12 example 2: channel-1 cascaded with channel-2 1. in_skip = 3?b010 2. ch1_skip = 3?b001 3. ch2_skip = 3?b100 4. let the input frame sequence be: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 5. after applying in_skip, the reduced sequence is: 0, 2, 3, 5, 6, 8, 9, 11, 12. these frames are sent to channel-2 6. output from channel-2 after applying ch2_skip: 0, 2, 3, 6, 8, 9, 12. these frames are sent to channel-1 7. output from channel-1 after applying ch1_skip: 0, 3, 8, 12 41.5.7 loop mode (len) loop mode is effective when the csi-prp link is enabled and has no effect when input frames are processed from memory. loop mode is enabled by setting len bit in prp_cntl. when this bit is enabled, output data is written into output buffers in ping-pong fashion for each enabled channel. two memory buffers are used for each channel output. for example, the current frame is written to buffer 1 and the next frame to buffer 2 followed by buffer 1, again. while in loop mode, if channel-1 or channel-2 is disabled, the prp continues to output data for that channel until the frame is completed. when the channel is re-enabled again, output al ways starts at the next alternate buffer. 41.5.8 channel-1 and channel-2 enable ch1en and ch2en bits of prp_cntl are used to enable channel-1 and channel-2 processing. if a frame is to be processed by both channels then both bi ts should be enabled at the same time. if data input is from memory and the two channels are enabled sepa rately one after the other, then the second channel will receive partial frame data. for example, if the input frame size is 320x240 and channel-1 is enabled table 41-33. loop mode ping pong registers channel buffer 1 registers buffer 2 registers channel-1 prp_dest_rgb1_ptr prp_dest_rgb2_ptr channel-2 prp_dest_y_ptr 1 prp_dest_cb_ptr 2 prp_dest_cr_ptr 1 prp_dest_y_ptr and prp_source_y_ptr are used in yuv 4:2:0, yuv 4:2:2 and yuv 4:4:4 modes. 2 prp_dest_cb_ptr, prp_dest_ cr_ptr and prp_dest_cb_ptr, prp_dest_cr_ptr are only used when output is in yuv 4:2:0 mode. prp_source_y_ptr 3 prp_source_cb_ptr prp_source_cr_ptr 3 these registers are re-used as output pointers in loop mode. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-38 freescale semiconductor first and channel-2 is enabled when 120 lines have al ready been processed, then lines 121 to 240 will be written to channel-2. line 121 will be treated as line 1 for channel-2. if data input is from csi then processing always begi ns with a new frame. for example, when channel-1 is enabled and processing of the first frame is in pr ogress when channel-2 is en abled then channel-2 will only begin to output frames from the second frame onwar ds and frame boundaries are maintained in this mode. if loop is not enabled then an enabled channel is automatically disabled after a single frame has been processed. if a channel is disabled in the midst of a frame, it will continue processing and stop when the full frame has been processed. 41.5.9 channel-2 flow control flow control is done to control channel-2 frame proc essing. flow control is valid when the csi input is enabled. flow control is enabled by setting ch2fen bit to ?1? in prp_cntl register. when flow control is enabled, ch2b1en and ch2b2en bits indicate if th e corresponding buffer is ready to accept new data. when flow control is disabled ch2b1en and ch2b 2en are not checked and channel-2 will write to buffer-1 and buffer-2, alternately. buffer-1 and buffer-2 are ping pong buffers whose memory address is configured as the channel-2 destination pointers. if flow control is enabled, then at the start of fra me processing the buffer enable bits (ch2b1en or ch2b2en) are checked to determine if the alternate buffer is enabled for writing. if the buffer is enabled then an input frame is processed and at the end of fram e, the buffer enable bit is reset. if the buffer is not enabled, then an overflow condition is signaled. th e c2fcfo bit is set in prp_intrstatus. if the c2fcie bit is enabled in prp_intrcntl, then an interrupt is also raised. when an overflow condition is encountered, input frame processing stops until the buffer is enabled and processing begins at the next start of frame. 41.5.10 line buffer overflow when prp processing speed is slower than input data arrival then line buffer overflow can happen. when a line buffer overflow occurs, the lb_ovi bit in prp_intrstatus is set. if lb_ovie bit in prp_intrcntl is enabled then an interrupt is raised. the frame_skip bit in the prp_cntl register determin es if processing re-starts at the next start of frame or continues when an overflow occurs. when an overflow occurs and frame_skip is ?1? then processing of that frame stops and continues at the ne xt start of frame. when frame_skip is ?0? and an overflow occurs, then processing continues but there will be some missing data in the output frame contributing to errors in the picture. 41.5.11 relationship of register fields related to the input frame figure 41-24 shows the relationship between prp_y_source, picture_x_size, picture_y_size and source_line_stride. there are two rectangles in the diagrams. the inner rectangle shows the processed frame, however a larger amount of memo ry may be allocated, as bounded by the outside rectangle. this windowing relationship applie s when prp takes input from main memory. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-39 stride information is not used when csi-prp link is enabled and instead cropping takes place. figure 41-24. memory image size and source line stride 41.5.12 relationship of register fields related to channel-1 output frame figure 41-25 shows the relationship between prp_dest_rgb1_ptr or prp_dest_rgb2_ptr, ch1_out_image_width, ch1_out_image_height and ch1_out_line_stride. there are two rectangles in the diagrams. the inner rectangle shows the channel-1 written frame in memory, however a larger amount of memory may be allocated as bounded by the outer rectangle or the input image may be larger than the out put image which is cropped. source_line_stride picture_x_size picture_y_size prp_y_source enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-40 freescale semiconductor figure 41-25. memory image and output stride 41.5.13 csi frame cropping the frame data from csi can be cropped using csi_line_skip and source_line_stride of prp_src_line_stride register and picture_x_size and picture_y_size of prp_src_frame_size register. when the input is 16-bit rgb or yuyv, source_line_stride should be a multiple of two. source_line _stride spec ifies the number of initial pixels to skip in a line and csi_line_skip specifies the number of lines to skip. the cropping parameter should be chosen such that this condition is always met. source_line_stride + picture_x_size <= csi_frame_x_size csi_line_skip + picture_y_size <= csi_frame_y_size cropping is enabled by setting wen bit to ?1? in prp_cntl register. figure 41-26 shows the effect of the cropping parameters. the figure shows two rectangular areas. the outer rectangle shows the actual frame from csi. th e inner rectangle shows the size of the image user selects. ch1_out_line_stride ch1_out_image_width ch1_out_image_height rgb1_start_address or rgb2_start_address enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-41 figure 41-26. csi frame cropping note source_line_stride and picture_x_skip are specified in pixels and csi_line_skip and picture_y_size are specified in lines. 41.5.14 csi-prp link figure 41-27 shows the timing diagram of the csi-prp dedicated link. the fifo data from csi is transferred to the pre-processor without any cpu intervention. csi_line_skip picture_x_size picture_y_size source_line_stride csi_frame_x_size csi_frame_y_size enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-42 freescale semiconductor figure 41-27. csi-prp link table 41-34. csi-prp link internal signals signal description hclk ahb hclk fifo_full asserted high when csi fifo has reached the high watermark fifo_data[31:0] 32-bit unidirectional data bus from csi to prp frame_start asserted for 2 hclks when the csi detects a start-of-frame (vsync) condition line_start asserted for 2 hclks when the csi detects a start-of-line (hsync) condition burst_length[1:0] 2-bit encoded to indicate to prp how many data words there are in a fifo_full burst. the fifo high watermark must be chosen such that the prp picture_x_size is a multiple of the burst length. yuv 4:2:2: burst_count = picture_x_size / (burst_length 2) rgb (16 bpp): burst_count = picture_x_size / (burst_length 2) rgb (32 bpp): burst_count = picture_x_size / (burst_length) burst_count should be exact integer value. 0 d0 d1 d2 d3 hclk fifo_full fifo_data[31:0] burst_length[1:0] burst_length[1:0] 00 = 4 words 01 = 8 words 10 = 16 words 11 = 24 words hclk frame_start line_start enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-43 41.6 pre-processor (prp) programming model all register reads and writes must be 32-bits access. write 0 to reserved bits. all registers are read or write unless specified. table 41-35. prp register memory map address register name access offset location 0x1002_6000 (prp_cntl) prp control register (prp_cntl) r/w 0x0000_f232 41.6.1/41-44 0x1002_6004 (prp_intr_cntl) prp interrupt control (prp_intrcntl) r/w 0x0000_0000 41.6.2/41-47 0x1002_6008 (prp_intrstatus) prp interrupt status r/w 0x0000_0000 41.6.3/41-49 0x1002_600c (prp_source_y_ptr) prp source y frame start address r/w 0x0000_0000 41.6.4/41-50 0x1002_6010 (prp_source_cb_ptr) prp source cb frame start address r/w 0x0000_0000 41.6.5/41-51 0x1002_6014 (prp_source_cr_ptr) prp source cr frame start address r/w 0x0000_0000 41.6.6/41-51 0x1002_6018 (prp_dest_rgb1_ptr) prp destination rgb frame-1 start address r/w 0x0000_0000 41.6.7/41-52 0x1002_601c (prp_dest_rgb2_ptr) prp destination rgb frame-2 start address r/w 0x0000_0000 41.6.8/41-53 0x1002_6020 (prp_dest_y_ptr) prp destination y frame start address r/w 0x0000_0000 41.6.9/41-53 0x1002_6024 (prp_dest_cb_ptr) prp destination cb frame start address r/w 0x0000_0000 41.6.10/41-54 0x1002_6028 (prp_dest_cr_ptr) prp destination cr frame start address r/w 0x0000_0000 41.6.11/41-55 0x1002_602c (prp_src_frame_size) prp source frame size r/w 0x0140_00f0 41.6.12/41-55 0x1002_6030 (prp_dest_ch1_line_stride) prp channel-1 line stride r/w 0x0000_0280 41.6.13/41-56 0x1002_6034 (prp_src_pixel_format_cntl) prp source pixel format control r/w 0x2200_0888 41.6.14/41-57 0x1002_6038 (prp_ch1_pixel_format_cntl) prp ch1 pixel format control r/w 0x2ca0_0565 41.6.15/41-59 0x1002_603c (prp_ch1_out_image_size) prp ch1 output image size r/w 0x0540_04f0 41.6.16/41-61 0x1002_6040 (prp_ch2_out_image_size) prp ch2 output image size r/w 0x0140_04f0 41.6.17/41-61 0x1002_6044 (prp_src_line_stride) prp source line stride r/w 0x0000_0000 41.6.18/41-62 0x1002_6048 (prp_csc_coef_012) prp csc coefficients c0, c1, c2 r/w 0x1005_a02c 41.6.19/41-63 0x1002_604c (prp_csc_coef_345) prp csc coefficients c3 to c5 r/w 0x0b67_1800 41.6.20/41-64 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-44 freescale semiconductor 41.6.1 prp control register figure 41-28 shows the register, and table 41-36 provides its field descriptions. 0x1002_6050 (prp_csc_coef_678) prp csc coefficients c6 to c8 r/w 0x0000_0000 41.6.21/41-65 0x1002_6054 (prp_ch1_rz_hori_coef1) prp channel 1 resize horizontal coefficients r/w 0x0000_0007 41.6.22/41-67 0x1002_6058 (prp_ch1_rz_hori_coef2) prp channel 1 resize horizontal coefficients r/w 0x0000_0000 41.6.23/41-68 0x1002_605c (prp_ch1_rz_hori_valid) prp channel 1 resize horizontal output data valid r/w 0x0100_0001 41.6.24/41-69 0x1002_6060 (prp_ch1_rz_vert_coef1) prp channel 1 resize vertical coefficients r/w 0x0000_0007 41.6.25/41-70 0x1002_6064 (prp_ch1_rz_vert_coef2) prp channel 1 resize vertical coefficients r/w 0x0000_0000 41.6.26/41-71 0x1002_6068 (prp_ch1_rz_vert_valid) prp channel 1 resize vertical output data valid r/w 0x0100_0001 41.6.27/41-72 0x1002_606c (prp_ch2_rz_hori_coef1) prp channel 2 resize horizontal coefficients r/w 0x0000_0007 41.6.28/41-73 0x1002_6070 (prp_ch2_rz_hori_coef2) prp channel 2 resize horizontal coefficients r/w 0x0000_0000 41.6.29/41-74 0x1002_6074 (prp_ch2_rz_hori_valid) prp channel 2 resize horizontal output data valid r/w 0x0100_0001 41.6.30/41-75 0x1002_6078 (prp_ch2_rz_vert_coef1) prp channel 2 resize vertical coefficients r/w 0x0000_0007 41.6.31/41-76 0x1002_607c (prp_ch2_rz_vert_coef2) prp channel 2 resize vertical coefficients r/w 0x0000_0000 41.6.32/41-78 0x1002_6080 (prp_ch2_rz_vert_valid) prp channel 2 resize vertical output data valid r/w 0x0100_0001 41.6.33/41-79 table 41-35. prp register memory map (continued) address register name access offset location enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-45 0x1002_6000 (prp_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ch2f en ch2b 2en ch2b 1en rz_fifo _level[1:0] input_fifo _level[1:0] ch2_tskip ch1_tskip in_tskip w reset0000000000000000 1514131211109876543210 r ch1 byp wen clke n sw rst skip fra me ch2_ l en ch1_ len ch2_out_ mode[1:0] ch1_out_ mode[1:0] datain mode [1:0] csi en ch2 en ch1 en w reset1111001000110010 figure 41-28. prp control register table 41-36. prp control register field descriptions name description 31 ch2fen channel 2 flow control enable. when this bit is set then output is controlled by ch2b1en and ch2b2en, else output is written alternately to output buffers. 0 disable flow control 1 enable flow control 30 ch2b2en channel 2 buffer 2 enable. this bit signals that buffer 2 is ready for writing 0 buffer is not ready for writing. 1 buffer is ready for writing. 29 ch2b1en channel 2 buffer 1 enable. this bit signals that buffer 1 is ready for writing 0 buffer is not ready for writing. 1 buffer is ready for writing. 27?28 rz_fifo_level[1:0] resize fifo level. selects the depth of resize buffers. the buffers are 24 bits wide. 00 64 words 01 48 words 10 32 words 11 16 words 25?26 input_fifo_level[1:0] input fifo level. selects the depth of input line buffers. the buffers are 48 bits wide. when data is sourced from csi (csien = 1) this bit should always set to ?00?. 00 128 words 01 96 words 10 64 words 11 32 words enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-46 freescale semiconductor 22?24 ch2_tskip[2:0] channel 2 skip control. selects frames to skip on channel 2 output. this bit is valid when csien=1. 000 no skip 001 skip 1 out of every 2 (1-0) 010 skip 1 out of every 3 (1-0-1) 011 skip 2 out of every 3 (1-0-0) 100 skip 1 out of every 4 (1-1-1-0) 101 skip 3 out of every 4 (1-0-0-0) 110 skip 2 out of every 5 (1-0-1-0-1) 111 skip 4 out of every 5 (1-0-0-0-0) 19?21 ch1_tskip[2:0] channel 1 skip control. selects frames to skip for channel 1 output. this bit is valid when csien=1. 000 no skip 001 skip 1 out of every 2 (1-0) 010 skip 1 out of every 3 (1-0-1) 011 skip 2 out of every 3 (1-0-0) 100 skip 1 out of every 4 (1-1-1-0) 101 skip 3 out of every 4 (1-0-0-0) 110 skip 2 out of every 5 (1-0-1-0-1) 111 skip 4 out of every 5 (1-0-0-0-0) 16?18 in_tskip[2:0] input frame skip. selects frames to skip from csi. this bit is valid when csien=1. 000 no skip 001 skip 1 out of every 2 (1-0) 010 skip 1 out of every 3 (1-0-1) 011 skip 2 out of every 3 (1-0-0) 100 skip 1 out of every 4 (1-1-1-0) 101 skip 3 out of every 4 (1-0-0-0) 110 skip 2 out of every 5 (1-0-1-0-1) 111 skip 4 out of every 5 (1-0-0-0-0) 15 ch1byp channel-1 bypass. cascade control of channel-1 resize 0 cascade channel-1 resize block 1 disable cascade of channel-1 resize 14 wen window enable. enables input windowing feature from main memory or cropping from csi. 0 disable 1 enable 13 clken clock gating enable. this bit controls clock gating to the prp. when clock gating is disabled, logic in the prp is always clocked. when clock gating is enabled, then clock is turned on when prp module is enabled. 1 clock gating off 0 clock gating on (power saving feature) 12 swrst software reset. writing ?1? to this bit resets entire prp module. all registers return to their default values. this bit is self-clearing. 11 skip_frame frame_skip. this bit selects whether to continue or stop when we get input fifo overflow error. 0 continue 1 stop table 41-36. prp control register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-47 41.6.2 prp interrupt control register figure 41-29 shows the register, and table 41-37 provides its field descriptions. 10 ch2_len channel-2 loop enable. this bit is valid only when input data is from csi (csien = 1). when enabled, output data is written in ping-pong fashion 0 disable 1 enable 9 ch1_len channel-1 loop enable. this bit is valid only when input data is from csi (csien = 1). when enabled, output data is written in ping-pong fashion. 0 disable 1 enable 7?8 ch2_out_mode[1:0] channel-2 output mode. these bits select channel-2 output format. 00 or 11 - yuv 4:2:0 (iyuv, yv12) 01 yuv 4:2:2 (yuyv) 10 yuv 4:4:4 (yuv0) 5?6 ch1_out_mode[1:0] channel-1 output mode. these bits select the channel-1 output format 00 8 bpp rgb 01 16 bpp rgb 10 32 bpp rgb 11 yuv 422 3?4 data_in_mode[1:0] data input mode. these bits set the input data format. 00 yuv 4:2:0 (not supported for csien=1) 01 yuv 4:2:2 10 16-bit rgb data 11 32-bit rgb data 2 csien csi enable. if set, enables the csi-prp link and input is sourced from the csi. when cleared, input is sourced from main memory. 0 input from main memory 1 input from csi 1 ch2en channel-2 enable. this bit enables or disables channel-2 output. 0 disable 1 enable when enabled, self clearing on success or error. does not self clear if in loop mode (ch2_len = 1) 0 ch1en channel-1 enable. this bit enables or disables channel-1 output. 0 disable 1 enable when enabled, self clearing on success or error. does not self clear if in loop mode (ch1_len = 1) table 41-36. prp control register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-48 freescale semiconductor 0x1002_6004 (prp_intr_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0000000 ch2 ovf ie lb ovf ie 0 ch2f c ie 0 ch1f c ie ch2 wer r ie ch1 wer r ie rd err ie w reset0000000000000000 figure 41-29. prp interrupt control register table 41-37. prp interrupt control register field descriptions name description 31?9 reserved. these bits are reserved and should read 0. 8 ch2ovfie channel-2 overflow interrupt enable. if set, an interrupt is generated when frame is missed due to flow control process. 0 disable 1 enable 7 lbovfie line buffer overflow interrupt enable. if set, an interrupt is generated when line buffer overflow occurs. 0 disable 1 enable 6 reserved. this bit is reserved and should read 0. 5 ch2fcie channel-2 frame complete interrupt enable. if set, an interrupt is generated when a frame is completely written out through channel-2. 0 disable 1 enable 4 reserved. this bit is reserved and should read 0. 3 ch1fcie channel-1 frame complete interrupt enable. if set, an interrupt is generated when a frame is completely written out through channel-1. 0 disable 1 enable 2 ch2werrie channel-2 write error interrupt enable. if set, an interrupt is generated when an ahb write error is encountered during channel-2 data output to memory 0 disable 1 enable enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-49 41.6.3 prp interrupt status register figure 41-30 shows the register, and table 41-38 provides its field descriptions. 1 ch1werrie channel-1 write error interrupt enable. if set, an interrupt is generated when an ahb write error is encountered during channel-1 data output to memory. 0 disable 1 enable 0 rderrie read error interrupt enable. if set, an interrupt is generated when an ahb read error is encountered during data input from memory. 0 disable 1 enable 0x1002_6008 (prp_intrstatus) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r0000000 ch2 ovf lb ovf ch1 b1ci ch1 b2ci ch2 b1ci ch2 b2ci ch2 wre rr ch1 wre rr rd err w reset0000000000000000 figure 41-30. prp interrupt status register table 41-38. prp interrupt status register field descriptions name description 31?9 reserved. these bits are reserved and should read 0. 8 ch2ovf channel-2 buffer overflow. when this bit is set, it indicates that a frame was missed because both ch2b1en and ch2b2en are disabled. 7 lbovf line buffer overflow. when this bit is set, it indicates that a line buffer overflow has occurred. 6 ch1b1ci channel-1 buffer-1 complete interrupt. if channel-1 is enabled and when this bit is set, it indicates that a frame has been completely written into buffer-1 of channel-1. this bit is set when input is either from csi or from memory. 5 ch1b2ci channel-1 buffer-2 complete interrupt. if channel-1 is enabled and when this bit is set, it indicates that a frame has been completely written into buffer-2 of channel-1. this bit is set only when csien=1 and len=1. table 41-37. prp interrupt control register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-50 freescale semiconductor 41.6.4 prp source y address register figure 41-31 shows the register, and table 41-39 provides its field descriptions. 4 ch2b1ci channel-2 buffer-1 complete interrupt. if channel-2 is enabled and when this bit is set, it indicates that a frame has been completely written into buffer-1 of channel-2. this bit is set when input is either from csi or from memory. 3 c2b2ci channel-2 buffer-2 complete interrupt. if channel-2 is enabled and when this bit is set, it indicates that a frame has been completely written into buffer-2 of channel-2. this bit is set only when csien=1 and len=1. 2 ch2wrerr channel-2 write error. if set, then an ahb write error to memory was encountered during channel-2 data output. prp has to be reset (swrst=1) and re-initialized. 1 ch1wrerr channel-1 write error. if set, then an ahb write error was encountered during channel-1 data output. prp has to be reset (swrst=1) and re-initialized. 0 readerr read error. if set, then an ahb read error was encountered during data input from memory. prp has to be reset (swrst=1) and re-initialized. 0x1002_600c (prp_source_y_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_y_source w reset0000000000000000 1514131211109876543210 r prp_y_source w reset0000000000000000 figure 41-31. prp source y address register table 41-39. prp source y address register field descriptions name description 31?0 prp_source_y_ptr prp_source_y_ptr. 32-bit pointer to memory. in rgb and yuv 4:2:2 modes, this register sets the frame start address. in yuv 4:2:0 mode (input or output), this register sets the luminance band start address of the frame. when csien=1 and len=1, this register is re-used as the channel-2 output buffer-2 destination address for the above formats. table 41-38. prp interrupt status register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-51 41.6.5 prp source cb address register figure 41-32 shows the register, and table 41-40 provides its field descriptions. 41.6.6 prp source cr address register figure 41-33 shows the register, and table 41-41 provides its field descriptions. 0x1002_6010 (prp_source_cb_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_cb_source w reset0000000000000000 1514131211109876543210 r prp_cb_source w reset0000000000000000 figure 41-32. prp source cb address register table 41-40. prp source cb address register field descriptions name description 31?0 prp_source_cb_ptr prp_source_cb_ptr. a 32-bit pointer to memory. this register sets the chrominance (u or cb) band start address when input is in yuv 4:2:0 band interleaved mode. it is not used for other input modes. when csien=1 and len=1, this register is re-used as the channel-2 u or cb output buffer-2 destination address for yuv 4:2:0. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-52 freescale semiconductor 41.6.7 prp destination rgb1 frame start address register figure 41-34 shows the register, and table 41-42 provides its field descriptions. 0x1002_6014 (prp_source_cr_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_cr_source w reset0000000000000000 1514131211109876543210 r prp_cr_source w reset0000000000000000 figure 41-33. prp source cr address register table 41-41. prp source cr address register field descriptions name description 31?0 prp_source_cr_ptr prp_source_cr_ptr. 32-bit pointer to memory. this register sets the chrominance (v or cr) band start address when input is in yuv 4:2:0 band interleaved mode. it is not used for other input modes. when csien=1 and len=1, this register is re-used as the channel-2 y or cr output buffer-2 destination address for yuv 4:2:0. 0x1002_6018 (prp_dest_rgb1_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rgb1_start_address w reset0000000000000000 1514131211109876543210 r rgb1_start_address w reset0000000000000000 figure 41-34. prp destination rgb1 start address register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-53 41.6.8 prp destination rgb2 frame start address register figure 41-35 shows the register, and table 41-43 provides its field descriptions. 41.6.9 prp destination y address register figure 41-36 shows the register, and table 41-44 provides its field descriptions. table 41-42. prp destination rgb1 start address register field descriptions name description 31?0 prp_dest_rgb1_ptr prp_dest_rgb1_ptr. 32-bit pointer to memory. this register sets the rgb or yuv 4:2:2 frame start address for channel-1 output. when csien=1 and len=1, this register becomes the output buffer-1 address for channel-1. 0x1002_601c (prp_dest_rgb2_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rgb2_start_address w reset0000000000000000 1514131211109876543210 r rgb2_start_address w reset0000000000000000 figure 41-35. prp destination rgb2 start address register table 41-43. prp destination rgb2 start address register field descriptions name description 31?0 prp_dest_rgb2_ptr prp_dest_rgb2_ptr. 32-bit pointer to memory. this register sets the output buffer-2 rgb or yuv 4:2:2 frame start address for channel-1 and is used only when csien=1 and len=1. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-54 freescale semiconductor 41.6.10 prp destination cb address register figure 41-37 shows the register, and table 41-45 provides its field descriptions. 0x1002_6020 (prp_dest_y_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_y_dest w reset0000000000000000 1514131211109876543210 r prp_y_dest w reset0000000000000000 figure 41-36. prp destination y address register table 41-44. prp destination y address register field descriptions name description 31?0 prp_y_dest prp_y_dest. 32-bit pointer to memory. this register sets the destination start address for channel-2 output. this register is the luminance band start address in yuv 4:2:0 mode and frame start address in yuv 4:2:2 and yuv 4:4:4 pixel interleaved modes. when csien=1 and len=1, this register is the buffer-1 output address. 0x1002_6024 (prp_dest_cb_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_cb_dest w reset0000000000000000 1514131211109876543210 r prp_cb_dest w reset0000000000000000 figure 41-37. prp destination cb address register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-55 41.6.11 prp destination cr address register figure 41-38 shows the register, and table 41-46 provides its field descriptions. 41.6.12 prp source frame size register figure 41-39 shows the register, and table 41-47 provides its field descriptions. table 41-45. prp destination cb address register field descriptions name description 31?0 prp_cb_dest prp_cb_dest. 32-bit pointer to memory. this register is used in yuv 4:2:0 band interleaved mode and sets the destination start address for channel-2 u or cb band data output. when csien=1 and len=1, this register is the chan nel-2 buffer-1 output address for u or cb band data in yuv 4:2:0 mode. 0x1002_6028 (prp_dest_cr_ptr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r prp_cr_dest w reset0000000000000000 1514131211109876543210 r prp_cr_dest w reset0000000000000000 figure 41-38. prp destination cr address register table 41-46. prp destination cr address register description name description 31?0 prp_cr_dest prp_cr_dest. 32-bit pointer to memory. this register is used in yuv 4:2:0 band interleaved mode and sets the destination start address for channel-2 v or cr band data output. when csien=1 and len=1, this register is the channel-2 buffer-1 output address for v or cr band data in yuv 4:2:0 mode. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-56 freescale semiconductor 41.6.13 prp destination cha nnel-1 line stride register figure 41-40 shows the register, and table 41-48 provides its field descriptions. 0x1002_602c (prp_src_frame_size) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000 picture_x_size w reset0000000101000000 1514131211109876543210 r00000 picture_y_size w reset0000000011110000 figure 41-39. prp source frame size register table 41-47. prp source frame size register field descriptions name description 31?27 reserved. these bits are reserved and should read 0. 26?16 picture_x_size picture_x_size. these bits set the frame width to be processed in number of pixels. in yuv 4:2:0 mode, cb and cr widths are taken as picture_x_size/2 pixels. in yuv 4:2:0 mode, this value should be a multiple of 8-pixels. in other modes (rgb, yuv 4:2:2 and yuv 4:4:4) it should be a multiple of 4 pixels. 15?11 reserved. these bits are reserved and should read 0. 10?0 picture_y_size picture_y_size. these bits set the frame height in number of lines to be processed. in yuv 4:2:0 mode, cb and cr lines to be processed are taken as picture_y_size/2. in yuv 4:2:0 mode, this value should be a multiple of 2. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-57 41.6.14 prp source pixel format control register figure 41-41 shows the register, and table 41-49 provides its field descriptions. 0x1002_6030 (prp_dest_ch1_line_stride) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000 000000 1514131211109876543210 r0 0 0 0 ch1_out_line_stride w reset0000001010000000 figure 41-40. prp destination channel-1 line stride register table 41-48. prp destination channel-1 line stride register field descriptions name description 31?12 reserved. these bits are reserved and should read 0. 11?0 ch1_out_line_stride ch1_out_line_stride. these bits sets the distance in bytes between the start addresses of adjacent lines in channel-1 output. the stride value should be a multiple of 4-bytes. 0x1002_6034 (prp_src_pixel_format_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 red_y_offset green_u_cb_ offset blue_v_cr_offset w reset0010001000 000000 1514131211109876543210 r0 0 0 0 red_width green_width blue_width w reset0000100010001000 figure 41-41. prp source pixel format control register enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-58 freescale semiconductor table 41-50 provides some examples of common input formats and the respective settings. table 41-49. prp source pixel format control register field descriptions name description 31 reserved. this bit is reserved and should read 0. 30?26 red_y_offset red_y_offset. these bits set the offset of the red color or y luminance component in the input pixel. the offset is calculated with respect to bit 0. 25?21 green_u_cb_offset green_u_cb_offset. these bits set the offset of the green color, u or cb chrominance component in the input pixel. the offset is calculated with respect to bit 0. 20?16 blue_v_cr_offset blue_v_cr_offset. these bits set the offset of the blue color, v or cr chrominance component in the input pixel. the offset is calculated with respect to bit 0. 15?12 reserved. these bits are reserved and should read 0. 11?8 red_width red width. these bits set the width in bits of the red color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. 7?4 green_width green width. these bits set the width in bits of the green color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. 3?0 blue_width blue width. these bits set the width in bits of the blue color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. table 41-50. example source input pixel formats input format pixel arrangement offset width prp_src_pixel_ format_cntl rgb 565 16 bpp red_y_offset=11 green_u_cb_offset=5 blue_v_cr_offset=0 red_width=5 green_width=6 blue_width=5 0x2ca0_0565 rgb 888 unpacked rgb888 red_y_offset=16 green_u_cb_offset=8 blue_v_cr_offset=0 red_width=8 green_width=8 blue_width=8 0x4100_0888 yuv 4:2:0 iyuv not applicable as input is band interleaved register is not used. yuv 4:2:0 yv12 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-59 41.6.15 prp channel-1 pixel format control register figure 41-42 shows the register, and table 41-51 provides its field descriptions. yuv 4:2:2 yuyv red_y_offset=8 green_u_cb_offset=16 blue_v_cr_offset=0 width is not used, set to 8 by default. 0x2200_0888 yuv 4:2:2 yvyu red_y_offset=8 green_u_cb_offset=0 blue_v_cr_offset=16 0x2010_0888 yuv 4:2:2 uyvy red_y_offset=0 green_u_cb_offset=24 blue_v_cr_offset=8 0x0308_0888 yuv 4:2:2 vyuy red_y_offset=0 green_u_cb_offset=8 blue_v_cr_offset=24 0x0118_0888 yuv 4:4:4 yuv0 red_y_offset=24 green_u_cb_offset=16 blue_v_cr_offset=8 0x6208_0888 0x1002_6038 (prp_ch1_pixel_format_cntl) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 red_offset green_offset blue_offset w reset0010110010 100000 1514131211109876543210 r0 0 0 0 red_width green_width blue_width w reset0000010101100101 figure 41-42. prp ch1 pixel format control register table 41-51. prp ch1 pixel format control register field descriptions name description 31 reserved. this bit is reserved and should read 0. 30?26 red_offset red_offset. these bits set the offset of the red color component in the output pixel. the offset is calculated with respect to bit 0. table 41-50. example source input pixel formats (continued) input format pixel arrangement offset width prp_src_pixel_ format_cntl enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-60 freescale semiconductor table 41-52 shows some example output rgb formats and encodings. 25?21 green_offset green_offset. these bits set the offset of the green color component in the output pixel. the offset is calculated with respect to bit 0. 20?16 blue_offset blue_offset. these bits set the offset of the blue color component in the output pixel. the offset is calculated with respect to bit 0. 15?12 reserved. these bits are reserved and should read 0. 11?8 red_width red_width. these bits set the width in bits of the red color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. 7?4 green_width green_width. these bits set the width in bits of the green color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. 3?0 blue_width blue_width. these bits set the width in bits of the blue color component in the input pixel. valid values are 0 to 8. any value greater than 8 is set to 8. table 41-52. example channel-1 rgb output pixel format input format pixel arrangement offset width prp_ch1_pixel_ format_cntl rgb 332 8 bpp red_offset=5 green_offset=2 blue_offset=0 red_width=3 green_width=3 blue_width=2 0x1440_0332 rgb 565 16 bpp red_offset=11 green_offset=5 blue_offset=0 red_width=5 green_width=6 blue_width=5 0x2ca0_0565 rgb 888 unpacked rgb888 red_offset=16 green_offset=8 blue_offset=0 red_width=8 green_width=8 blue_width=8 0x4100_0888 yuv 4:2:2 yuyv red_y_offset=24 green_u_cb_offset=16 blue_v_cr_offset=0 red_width=8 green_width=8 blue_width=8 0x6200_0888 yuv 4:2:2 yvyu red_y_offset=24 green_u_cb_offset=0 blue_v_cr_offset=16 0x6010_0888 yuv 4:2:2 uyvy red_y_offset=16 green_u_cb_offset=24 blue_v_cr_offset=8 0x4308_0888 yuv 4:2:2 vyuy red_y_offset=16 green_u_cb_offset=8 blue_v_cr_offset=24 0x4118_0888 table 41-51. prp ch1 pixel format control register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-61 41.6.16 prp destination channel-1 output image size register figure 41-43 shows the register, and table 41-53 provides its field descriptions. 41.6.17 prp destination channel-2 output image size register figure 41-44 shows the register, and table 41-54 provides its field descriptions. 0x1002_603c (prp_ch1_out_image_size) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000 ch1_out_image_width w reset0000010101000000 1514131211109876543210 r00000 ch1_out_image_height w reset0000010011110000 figure 41-43. prp destination channel-1 output image size register table 41-53. prp destination channel-1 output image size register field descriptions name description 31?27 reserved. these bits are reserved and should read 0. 26?16 ch1_out_image_width ch1_out_image_width. these bits sets the output width in number of pixels to display. see section 41.5.3, ?resize ? for more details. 8 bpp?this value should be a multiple of 4. 16 bpp or yuv 4:2:2?this value should be a multiple of 2 15?11 reserved. these bits are reserved and should read 0. 10?0 ch1_out_image_height ch1_out_image_height. these bits set the output height in number of lines to display. see section 41.5.3, ?resize ? for more details. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-62 freescale semiconductor 41.6.18 prp source line stride register figure 41-45 shows the register, and table 41-55 provides its field descriptions. 0x1002_6040 (prp_ch2_out_image_size) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000 ch2_out_image_width[10:0] w reset0000000101000000 1514131211109876543210 r00000 ch2_out_image_height w reset0000010011110000 figure 41-44. prp destination ch2 output image size register table 41-54. prp destination ch2 output image size register field description name description 31?27 reserved. these bits are reserved and should read 0. 26?16 ch2_out_image_width[10:0] channel-2 output image width. these bits sets the output width in number of pixels to display. yuv 422, yuv 444 - this value should be a multiple of 2. yuv 4:2:0 - this value should be a multiple of 8 16?11 reserved. these bits are reserved and should read 0. ch2_out_image_height 1 [10:0] 10?0 1 channel 2 output image height. these bits set the channel-2 output image height in number of lines in display. in yuv 4:2:0 mode, number of cr and cb lines are ch2_out_image_height/2. see section 41.5.3, ?resize ? for more details. in yuv 4:2:0 mode, this value should be in multiples of 2. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-63 41.6.19 prp csc coefficient 012 figure 41-46 shows the register, and table 41-56 provides its field descriptions. 0x1002_6044 (prp_src_line_stride) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 csi_line_skip[12:0] w reset0000000000000000 1514131211109876543210 r0 0 0 source_line_stride[12:0] w reset0000000000000000 figure 41-45. prp source line stride register table 41-55. prp source line stride register field descriptions name description 31?29 reserved. these bits are reserved and should read 0 28?16 csi_line_skip[12:0] csi_line_skip. these bits set the number lines to skip from start of a frame from csi. used only when winen=1 and csien=1. 15?13 reserved. these bits are reserved and should read 0 12?0 soucre_line_stride[12:0] source line stride. when csien = 0, these bits set the line stride for the source frame in bytes. in yuv 4:2:0 mode, source line stride for ?cb? and ?cr? are source_line_stride/2. when csien = 1, then these bits sets number of pixels to skip from start of a line. it should be multiple of 2. yuv 4:2:0?value should be a multiple of 8. yuv 4:2:2 or rgb?value should be a multiple of 4. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-64 freescale semiconductor 41.6.20 prp csc coefficient 345 figure 41-47 shows the register, and table 41-58 provides its field descriptions. 0x1002_6048 (prp_csc_coef_012) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 c0[7:0] 00 c1[7:5] w reset0001000000000101 1514131211109876543210 r c1[4:0] 000 c2[7:0] w reset1010000000101100 figure 41-46. prp csc coefficient 012 table 41-56. yuv to rgb name description 31?29 reserved. these bits are reserved and should read 0. 28?21 c0[7:0] coefficient 0. all 8 bits are significant range from 0 to 1.9921875 in steps of (1/128) 20?19 reserved. these bits are reserved and should read 0. 18?11 c1[7:0] coefficient 1. all 8 bits are significant. range from 0 to 1.9921875 in steps of (1/128) 10?8 reserved. these bits are reserved and should read 0. 7?0 c2[7:0] coefficient 2. all 8 bits are significant range from 0 to 1.9921875 in steps of (1/128) table 41-57. for rgb to yuv name description 31?29 reserved. these bits are reserved and should read 0 28?21 c0[7:0] coefficient 0. only c0[6:0], 7 bits are significant range from 0 to 0.49603750 in steps of (1/256) 20?19 reserved. these bits are reserved and should read 0 18?11 c1[7:0] coefficient 1. only c1[6:0], 7 bits are significant range from 0 to 0.9921875 in steps of (1/128) 10?8 reserved. these bits are reserved and should read 0 7?0 c2[7:0] coefficient 2. only c2[6:0], 7 bits are significant range from 0 to 0.248046875 in steps of (1/512) enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-65 41.6.21 prp csc coefficient 678 figure 41-48 shows the register, and table 41-60 provides its field descriptions. 0x1002_604c (prp_csc_coef_345) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 c3[7:0] 00 c4[8:5] w reset0000101101100111 1514131211109876543210 r c4[4:0] 0000 c5[6:0] w reset0001100000000000 figure 41-47. prp csc coefficient 345 table 41-58. for yuv to rgb name description 31?29 reserved. these bits are reserved and should read 0 28?21 c3[7:0] coefficient 3. all 8 bits are significant range from 0 to 1.9921875 in steps of (1/128) 20 reserved. this bit is reserved and should read 0 19?11 c4[8:0] coefficient 4. all 8 bits are significant range from 0 to 3.9921875 in steps of (1/128) 10?7 reserved. these bits are reserved and should read 0 6?0 c5[6:0] this coefficient is unused in yuv to rgb conversion. table 41-59. for rgb to yuv name description 31?29 reserved. these bits are reserved and should read 0 28?21 c3[7:0] coefficient 3. only c3[6:0], 7 bits are significant. range from 0.0 to 0.248046875 in steps of (1/512) 20 reserved. this bit is reserved and should read 0 19?11 c4[8:0] coefficient 4. only c4[6:0], 7 bits are significant. range from 0 to 0.49603750 in steps of (1/256) 10?7 reserved. these bits are reserved and should read 0 6?0 c5[6:0] coefficient 5. only c5[6:0], 7 bits are significant. range from 0 to 0.9921875in steps of (1/128) enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-66 freescale semiconductor 0x1002_6050 (prp_csc_coef_678) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r x0 000 c6[6:0] 000 c7[6:5] w reset0000000000000000 1514131211109876543210 r c7[4:0] 0000 c8[6:0] w reset0000000000000000 figure 41-48. prp csc coefficient 678 table 41-60. for rgb to yuv name description 31 x0 x0. luminance offset 1 x0 is equal to 16 in csc. 0 x0 is zero in csc. 30? 28 reserved. these bits are reserved and should read 0. 27?21 c6[7:0] coefficient 6. all 7 bits are significant. range from 0.0 to 0.9921875 in steps of (1/128) 20?18 reserved reserved. these bits are reserved and should read 0. 17?11 c7[8:0] coefficient 7. all 7 bits are significant. range from 0 to 0.49603750 in steps of (1/256) 10?7 reserved. these bits are reserved and should read 0. 6?0 c8[6:0] coefficient 8. all 7 bits are significant. range from 0 to 0.248046875 in steps of (1/512) table 41-61. csc equations conversion csc equation ycbcr to rgb r = c0*(y ? x0) + c1*(cr-128) g = c0*(y ? x0) ? c2*(cb-128) ? c3*(cr-128) b = c0*(y ? x0) + c4*(cb-128) yuv to rgb r = c0*(y ? x0) + c1*(u-128) g = c0*(y ? x0) ? c2*(u-128) ? c3*(v-128) b = c0*(y ? x0) + c4*(u-128) rgb to yuv y = c0 * r + c1 * g + c2 * b + x0 u = -c3 * r?c4 * g + c5 * b + 128 v = c6 * r?c7 * g ?c8 * b + 128 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-67 41.6.22 prp channel 1 horizontal resize coefficient-1 figure 41-49 shows the register, and table 41-62 provides its field descriptions. this register selects channel-1 horizontal resize co efficient values. the coefficient is 3-bits in width which represent value from 0 to 8. if hcx = 7 then it will treat as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 0x1002_6054 (prp_ch1_rz_hori_coef1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 hc9 hc8 hc7 hc6 hc5 w reset0000000000000000 1514131211109876543210 r0 hc4 hc3 hc2 hc1 hc0 w reset0000000000000111 figure 41-49. prp channel-1 horizontal resize coefficient 1 table 41-62. prp channel 1 horizontal resize coefficient-1 register field descriptions name description 31 reserved. this bit is reserved and should read 0. 30?28 hc9[2:0] horizontal resize coefficient 9. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 hc8[2:0] horizontal resize coefficient 8. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 hc7[2:0] horizontal resize coefficient 7. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 hc6[2:0] horizontal resize coefficient 6. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 hc5[2:0] horizontal resize coefficient 5. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0 14?12 hc4[2:0] horizontal resize coefficient 4. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 hc3[2:0] horizontal resize coefficient 3. alid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 hc2[2:0] horizontal resize coefficient 2. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-68 freescale semiconductor 41.6.23 prp channel1 horizontal resize coefficient-2 figure 41-50 shows the register, and table 41-63 provides its field descriptions. this register selects channel-1 horizontal resize co efficient values. the coefficient is 3-bits in width which represent value from 0 to 8. if hcx = 7 then it will treat as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 5?3 hc1[2:0] horizontal resize coefficient 1. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 hc0[2:0] horizontal resize coefficient 0. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_6058 (prp_ch1_rz_hori_coef2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 hc19 hc18 hc17 hc16 hc15 w reset0000000000000000 1514131211109876543210 r0 hc14 hc13 hc12 hc11 hc10 w reset0000000000000000 figure 41-50. prp channel-1 horizontal resize coefficient 2 table 41-63. prp channel1 horizontal resize coefficient-2 register field descriptions name description settings 31 reserved. this bit is reserved and should read 0. 30?28 hc10[2:0] horizontal resize coefficient 10. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 hc11[2:0] horizontal resize coefficient 11. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 hc12[2:0] horizontal resize coefficient 12. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 hc13[2:0] horizontal resize coefficient 13. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. table 41-62. prp channel 1 horizontal resize coefficient-1 register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-69 41.6.24 prp channel 1 horizontal resize valid figure 41-51 shows the register, and table 41-64 provides its field descriptions. 18?16 hc14[2:0] horizontal resize coefficient 14. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0. 14?12 hc15[2:0] horizontal resize coefficient 15. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 hc16[2:0] horizontal resize coefficient 16. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 hc17[2:0] horizontal resize coefficient 17. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 hc18[2:0] horizontal resize coefficient 18. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 hc19[2:0] horizontal resize coefficient 19. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_605c (prp_ch1_rz_hori_valid) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r avg_ bil 00 hori_tbl_len 0000 hov[19:16] w reset0000000100000000 1514131211109876543210 r hov[15:0] w reset0000000000000001 figure 41-51. prp channel-1 resize horizontal valid table 41-64. prp channel 1 horizontal resize valid register field descriptions name description 31 avg_bil averaging or bilinear mode select 0 averaging 1 bi-linear 30?29 reserved. these bits are reserved and should read 0. table 41-63. prp channel1 horizontal resize coefficient-2 register field descriptions (continued) name description settings enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-70 freescale semiconductor 41.6.25 prp channel1 vertical resize coefficient-1 figure 41-52 shows the register, and table 41-65 provides its field descriptions. this register selects channel-1 vertical resize coeffi cient values. the coefficient is 3-bits in width which represent values from 0 to 8. if vcx = 7 then it will treat it as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 28?24 hori_tbl_len horizontal resize table length. selects horizontal resize table length for m:n resize ratio for both bilinear and averaging mode table length should be set to ?m?. range from 1 to 20. 23?20 reserved. these bits are reserved and should read 0. 19?0 hov[19:0] horizontal output valid. bit vector that selects when to output pixel. skips output pixels when averaging and input pixels when bi-linear. 0 pixel is not output. 1 pixel is output. 0x1002_6060 (prp_ch1_rz_vert_coef1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 vc9 vc8 vc7 vc6 vc5 w reset0000000000000000 1514131211109876543210 r0 vc4 vc3 vc2 vc1 vc0 w reset0000000000000111 figure 41-52. prp channel 1 vertical resize coefficient 1 table 41-65. prp channel1 vertical resize coefficient-1 register field descriptions name description 31 reserved. this bit is reserved and should read 0. 30?28 vc9[2:0] vertical resize coefficient 9. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 vc8[2:0] vertical resize coefficient 8. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. table 41-64. prp channel 1 horizontal resize valid register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-71 41.6.26 prp channel 1 vertical resize coefficient 2 figure 41-53 shows the register, and table 41-66 provides its field descriptions. this register selects channel-1 vertical resize coefficient values. the coefficient is 3-bits in width which represent values from 0 to 8. if vcx = 7 then it is treated as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 24?22 vc7[2:0] vertical resize coefficient 7. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 vc6[2:0] vertical resize coefficient 6. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 vc5[2:0] vertical resize coefficient 5. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0. 14?12 vc4[2:0] vertical resize coefficient 4. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 vc3[2:0] vertical resize coefficient 3. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 vc2[2:0] vertical resize coefficient 2. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 vc1[2:0] vertical resize coefficient 1. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 vc0[2:0] vertical resize coefficient 0. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_6064 (prp_ch1_rz_vert_coef2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 vc19 vc18 vc17 vc16 vc15 w reset0000000000000000 1514131211109876543210 r0 vc14 vc13 vc12 vc11 vc10 w reset0000000000000000 figure 41-53. prp channel-1 vertical resize coefficient 2 table 41-65. prp channel1 vertical resize coefficient-1 register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-72 freescale semiconductor 41.6.27 prp channel 1 vertical resize valid figure 41-54 shows the register, and table 41-67 provides its field descriptions. table 41-66. prp channel 1 vertical resize coefficient 2 register field descriptions name description 31 reserved. this bit is reserved and should read 0. 30?28 vc10[2:0] vertical resize coefficient 10. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 vc11[2:0] vertical resize coefficient 11. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 vc12[2:0] vertical resize coefficient 12. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 vc13[2:0] vertical resize coefficient 13. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 vc14[2:0] vertical resize coefficient 14. valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0. 14?12 vc15[2:0] vertical resize coefficient 15 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 vc16[2:0] vertical resize coefficient 16 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 vc17[2:0] vertical resize coefficient 17 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 vc18[2:0] vertical resize coefficient 18 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 vc19[2:0] vertical resize coefficient 19 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_6068 (prp_ch1_rz_vert_valid) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r avg_ bil 00 vert_tbl_len 0000 vov[19:16] w reset0000000100000000 1514131211109876543210 r vov[15:0] w reset0000000000000001 figure 41-54. prp channel1 vertical resize valid enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-73 41.6.28 prp channel-2 horizontal resize coefficient-1 figure 41-55 shows the register, and table 41-68 provides its field descriptions. this register selects channel-2 horizontal resize co efficient values. the coefficient is 3-bits in width which represent value from 0 to 8. if hcx = 7 then it will treat as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. table 41-67. prp channel 1 vertical resize valid register field descriptions name description 31 avg_bil averaging or bilinear mode select 0 averaging 1 bi-linear 30?29 reserved. these bits are reserved and should read 0. 28?24 vert_tbl_len vertical resize table length. selects vertical resize table length. for m:n resize ratio for both bilinear and averaging mode table length should be set to ?m?. range from 1 to 20. 23?20 reserved. these bits are reserved and should read 0. 19?0 vov[19:0] vertical output valid. bit vector that selects when to output pixel. skips output pixels when averaging and input pixels when bi-linear. 0 pixel is not output. 1 pixel is output. 0x1002_606c (prp_ch2_rz_hori_coef1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 hc9 hc8 hc7 hc6 hc5 w reset0000000000000000 1514131211109876543210 r0 hc4 hc3 hc2 hc1 hc0 w reset0000000000000111 figure 41-55. prp channel-2 horizontal resize coefficient 1 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-74 freescale semiconductor 41.6.29 prp channel-2 horizontal resize coefficient-2 figure 41-56 shows the register, and table 41-69 provides its field descriptions. table 41-68. prp channel-2 horizontal resize coefficient-1 register field descriptions name description 31 reserved. this bit is reserved and should read 0 30?28 hc9[2:0] horizontal resize coefficient 9 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 hc8[2:0] horizontal resize coefficient 8 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 hc7[2:0] horizontal resize coefficient 7 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 hc6[2:0] horizontal resize coefficient 6 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 hc5[2:0] horizontal resize coefficient 5 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0 14?12 hc4[2:0] horizontal resize coefficient 4 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 hc3[2:0] horizontal resize coefficient 3 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 hc2[2:0] horizontal resize coefficient 2 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 hc1[2:0] horizontal resize coefficient 1 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 hc0[2:0] horizontal resize coefficient 0 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_6070 (prp_ch2_rz_hori_coef2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 hc19 hc18 hc17 hc16 hc15 w reset0000000000000000 1514131211109876543210 r0 hc14 hc13 hc12 hc11 hc10 w reset0000000000000000 figure 41-56. prp channel-2 horizontal resize coefficient 2 enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-75 this register selects channel-2 horizontal resize co efficient values. the coefficient is 3-bits in width which represent value from 0 to 8. if hcx = 7 then it will be treated as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 41.6.30 prp channel-2 horizontal resize valid figure 41-57 shows the register, and table 41-70 provides its field descriptions. table 41-69. prp channel-2 horizontal resize coefficient-2 field descriptions name description 31 reserved. this bit is reserved and should read 0 30?28 hc10[2:0] horizontal resize coefficient 10 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 hc11[2:0] horizontal resize coefficient 11 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 hc12[2:0] horizontal resize coefficient 12 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 hc13[2:0] horizontal resize coefficient 13 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 hc14[2:0] horizontal resize coefficient 14 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0 14?12 hc15[2:0] horizontal resize coefficient 15 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 hc16[2:0] horizontal resize coefficient 16 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 hc17[2:0] horizontal resize coefficient 17 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 hc18[2:0] horizontal resize coefficient 18 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 hc19[2:0] horizontal resize coefficient 19 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-76 freescale semiconductor 41.6.31 prp channel2 vertical resize coefficient-1 figure 41-58 shows the register, and table 41-71 provides its field descriptions. 0x1002_6074 (prp_ch2_rz_hori_valid) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r avg_ bil 00 hori_tbl_len 0000 hov[19:16] w reset0000000100000000 1514131211109876543210 r hov[15:0] w reset0000000000000001 figure 41-57. prp channel-2 resize horizontal valid table 41-70. prp channel-2 horizontal resize valid register field descriptions name description 31 avg_bil averaging or bilinear mode select 0 averaging 1 bi-linear 30?29 reserved. these bits are reserved and should read 0 28?24 hori_tbl_len horizontal resize table length. selects horizontal resize table length for m:n resize ratio for both bilinear and averaging mode table length should be set to ?m?. range from 1 to 20. 23?20 reserved. these bits are reserved and should read 0 19?0 hov[19:0] horizontal output valid. bit vector that selects when to output pixel. skips output pixels when averaging and input pixels when bi-linear. 0 pixel is not output 1 pixel is output enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-77 this register selects channel-2 vertical resize coeffi cient values. the coefficient is 3-bits in width which represent values from 0 to 8. if vcx = 7 then it will treat it as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 0x1002_6078 (prp_ch2_rz_vert_coef1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 vc9 vc8 vc7 vc6 vc5 w reset0000000000000000 1514131211109876543210 r0 vc4 vc3 vc2 vc1 vc0 w reset0000000000000111 figure 41-58. prp channel2 vertical resize coefficient 1 table 41-71. prp channel2 vertical resize coefficient-1 register field descriptions name description settings 31 reserved. this bit is reserved and should read 0 30?28 vc9[2:0] vertical resize coefficient 9 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 vc8[2:0] vertical resize coefficient 8 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 vc7[2:0] vertical resize coefficient 7 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 vc6[2:0] vertical resize coefficient 6 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 18?16 vc5[2:0] vertical resize coefficient 5 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0 14?12 vc4[2:0] vertical resize coefficient 4 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 vc3[2:0] vertical resize coefficient 3 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 vc2[2:0] vertical resize coefficient 2 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-78 freescale semiconductor 41.6.32 prp channel 2 vertical resize coefficient 2 figure 41-59 shows the register, and table 41-72 provides its field descriptions. this register selects channel-2 vertical resize coefficient values. the coefficient is 3-bits in width which represent values from 0 to 8. if vcx = 7 then it is treated as ?8?. ? for bi-linear mode (w0*a+ w1*b)/8. coefficient w0 is programmed. ? for m:n resize ratio number of coefficients will be ?m?. 5?3 vc1[2:0] vertical resize coefficient 1 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 vc0[2:0] vertical resize coefficient 0 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_607c (prp_ch2_rz_vert_coef2) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 vc19 vc18 vc17 vc16 vc15 w reset0000000000000000 1514131211109876543210 r0 vc14 vc13 vc12 vc11 vc10 w reset0000000000000000 figure 41-59. prp channel-2 vertical resize coefficient 2 table 41-72. prp channel 2 vertical resize coefficient 2 register field descriptions name description 31 reserved. this bit is reserved and should read 0 30?28 vc10[2:0] vertical resize coefficient 10 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 27?25 vc11[2:0] vertical resize coefficient 11 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 24?22 vc12[2:0] vertical resize coefficient 12 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 21?19 vc13[2:0] vertical resize coefficient 13 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. table 41-71. prp channel2 vertical resize coefficient-1 register field descriptions (continued) name description settings enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 41-79 41.6.33 prp channel 2 vertical resize valid figure 41-60 shows the register, and table 41-73 provides its field descriptions. 18?16 vc14[2:0] vertical resize coefficient 14 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 15 reserved. this bit is reserved and should read 0 14?12 vc15[2:0] vertical resize coefficient 15 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 11?9 vc16[2:0] vertical resize coefficient 16 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 8?6 vc17[2:0] vertical resize coefficient 17 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 5?3 vc18[2:0] vertical resize coefficient 18 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 2?0 vc19[2:0] vertical resize coefficient 19 valid values are 0?6 and 8. to set a value of 8, use 3?b111 instead. 0x1002_6080 (prp_ch2_rz_vert_valid) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r avg_ bil 00 vert_tbl_len 0000 vov[19:16] w reset0000000100000000 1514131211109876543210 r vov[15:0] w reset0000000000000001 figure 41-60. prp channel2 vertical resize valid table 41-73. prp channel 2 vertical resize valid register field descriptions name description 31 avg_bil averaging or bilinear mode select 0 averaging 1 bi-linear 30?29 reserved. these bits are reserved and should read 0 table 41-72. prp channel 2 vertical resize coefficient 2 register field descriptions (continued) name description enhanced multimedia accelerator light (emma_lt) MCIMX27 multimedia applications processor reference manual, rev. 0.2 41-80 freescale semiconductor 28?24 vert_tbl_len vertical resize table length. selects vertical resize table length for m:n resize ratio for both bilinear and averaging mode table length should be set to ?m?. range from 1 to 20. 23?20 reserved. these bits are reserved and should read 0 19?0 vov[19:0] vertical output valid. bit vector that selects when to output pixel. skips output pixels when averaging and input pixels when bi-linear. 0 pixel is not output. 1 pixel is output. table 41-73. prp channel 2 vertical resize valid register field descriptions (continued) name description MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-1 chapter 42 synchronous serial interface (ssi) this chapter presents the synchronous serial inte rface (ssi), and discusses the architecture, the programming model, the operating modes, and initialization of ssi. figure 42-1 shows a block diagram of the ssi. it consists of control registers to set up the port, status register, separate transmit and receive circuits with fifo registers, and separate serial clock and frame sync generation for the transmit and receive sections. the second set of tx and rx fifos, replicates the logic used for the first set of fifos. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-2 freescale semiconductor figure 42-1. ssi block diagram 42.1 overview the ssi is a full-duplex, serial port that allows the ch ip to communicate with a va riety of serial devices. these serial devices can be standard coder-de coder (codec), digital si gnal processors (dsps), microprocessors, peripherals, and popular industry audi o codecs that implement the inter-ic sound bus standard (i 2 s) and intel ac97 standard. transmit clock control reg receive clock control reg transmit config reg receive config reg transmit shift reg 32-bit srccr srcr txfifo0 (8x24) txsr ip bus rxfifo0 (8x24) receive shift reg srx0 rxsr stxd srxd stck stfs srck/sys_clk srfs tx clock generator tx sync generator tx control and state machines rx clock generator rx sync generator tx0 data reg stx0 rx0 data reg control reg stccr stcr scr rx control and state machines txfifo1 (8x24) tx1 data reg stx1 rxfifo1 (8x24) srx1 rx1 data reg tx shift reg load logic rx shift reg unload logic synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-3 ssi is typically used to transfer samples in a period ic manner. the ssi consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. 42.1.1 features the ssi includes the following features: ? independent (asynchronous) or shared (synchronous) transmit and receive sec tions with separate or shared internal/external clocks and frame syncs, operating in master or slave mode. ? normal mode operation using frame sync ? network mode operation allowing multiple devices to share the port with as many as thirty-two time slots ? gated clock mode opera tion requiring no frame sync ? 2 sets of transmit and receive fifos. each of the four fifos is 8x24 bits. the two sets of tx/rx fifos can be used in network mode to provide 2 independent channels for transmission and reception ? programmable data interface modes such like i 2 s, lsb, msb aligned ? programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits) ? program options for frame sync and clock generation ? programmable i 2 s modes (master, slave or normal). ov ersampling clock, ccm_ssi_clk available as output from srck in i 2 s master mode ? ac97 support ? completely separate clock and frame sync selections for the receive and transmit sections. in ac97 standard, the clock is taken from an external source and frame sync is generated internally. ? external ccm_ssi_clk input for use in i 2 s master mode. programmable oversampling clock (sys_clk/ccm_ssi_clk) of the sa mpling frequency available as out put in master mode at srck, when operated in sync mode. ? programmable internal clock divider ? time slot mask registers for reduced cpu overhead (for tx and rx both) ? ssi power-down feature ? programmable wait states for cpu accesses ? ip interface for register accesses, compliant to srs 3.0.2 standard 42.1.2 modes of operation ssi has the following basic operating modes. ? normal mode ? asynchronous protocol ? synchronous protocol ? network mode ? asynchronous protocol synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-4 freescale semiconductor ? synchronous protocol ? gated clock mode ? synchronous protocol only these modes can be programmed by several bits in the ssi control registers. table 42-1 lists these operating modes and some of the typical a pplications in which they can be used. the transmit and receive sections of the ssi can be synchronous or asynchronous. in synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. the rxbit0 and rshfd bits in srcr still affect shifting-in of rece ived data in synchronous mode. in asynchronous mode, the transmitter and receiver each has its own cl ock and frame synchronization signals. continuous or gated clock mode can be selecte d. in continuous mode, the clock runs continuously. in gated clock mode, the clock is only functioning during transmission. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, any number from two to thirty-two data words of i/o per frame can be used. network mode is typically used in star or ring time division multiplex networks with other processors or codecs, allowing interface to time divi sion multiplexed networks without additional logic. use of the gated clock is not allowed in network mo de. these distinctions result in the basic operating modes that allow the ssi to communicate with a wide variety of devices. the ssi supports both normal and network modes, and these can be selected independently of whether the transmitter and receiver are synchronous or as ynchronous. typically these protocols are used in a periodic manner, where data is transfe rred at regular intervals, such as at the sampling rate of an external codec. both modes use the concept of a frame. the beginning of the frame is marked with a frame sync when programmed with continuous clock. the frame sync occurs at a periodic interval. the length of the frame is determined by the dc[4:0] bits in either the srccr or stccr register, depending on whether data is being transmitted or received. the number of words transferred per frame depends on the mode of the ssi. in normal mode, one data word is transferred per frame. in network mode, the frame is divided into anywhere between two and thirty-two time slots, where in each time slot one data word can optionally be transferred. table 42-1. ssi operating modes tx, rx sections serial clock mode typical application asynchronous continuous normal multiple synchronous codecs asynchronous continuous network tdm codec or dsp networks synchronous continuous normal multiple synchronous codecs synchronous continuous network tdm codec or dsp network synchronous gated normal spi-type devices; dsp to mcu synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-5 apart from the above basic modes of operation, ssi supports the following modes which require some specific programming. ?i 2 s mode ? ac97 mode ? ac97 fixed mode ? ac97 variable mode in (non-i 2 s) slave modes (external frame sync), the ssi programmed word length setting should be equal to the word length setting of the master. in i 2 s slave mode, the ssi programmed word length setting can be lesser than or equal to th e word length setting of the i 2 s master (external codec). in slave modes, the ssi programmed frame length setting (dc bits) can be less than or equal to the frame length setting of the master (external codec). the following sections provide detailed descriptions of the above modes. 42.1.2.1 normal mode normal mode is the simplest mode of the ssi. it is used to transfer data in one time slot per frame. a time slot is a unit of data and the wl[3:0] bits define th e number of bits in a time slot. in continuous clock mode, a frame sync occurs at the beginning of each frame. the length of the frame is determined by the following factors: ? the period of the serial bit clock (div2, psr, pm[7 :0] bits for internal clock or the frequency of the external clock on the stck port) ? the number of bits per time slot (wl[3:0] bits) ? the number of time slots per frame (dc[4:0] bits) if normal mode is configured with more than one time slot per frame, data is transferred only in the first time slot. no data is transferred in subsequent time slots. in norm al mode, dc[4:0] values corresponding to more than a single time slot in a frame, only resu lt in lengthening the frame. data transfer only takes place during the first time slot of the frame. 42.1.2.1.1 normal mode transmit the conditions for data transmission from the ssi in normal mode are: 1. ssi enabled (ssien = 1) 2. enable fifo and configure transmit and receive watermark if fifo is used. 3. write data to transmit data register (stx) 4. transmitter enabled (te = 1) 5. frame sync active (for continuous clock case) 6. bit clock begins (for gated clock case) when the above conditions occur in normal mode, the next data word is transferred into the transmit shift register (txsr) from the transmit data register 0 (stx0), or from the transmit fifo 0 register, if transmit fifo 0 is enabled. the new data word is transmitted immediately. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-6 freescale semiconductor if transmit fifo 0 is not enabled and the transmit data register empty (tde0) bit is set, transmit interrupt 0 occurs if the transmit interrupt enable (tie) and tde0_en bits are set. the transmit fifo empty 0 (tfe0) bit is set if the transmit fifo 0 reaches the selected threshold. if transmit fifo 0 is enabled and the transmit fifo empt y (tfe0) bit is set, transmit interrupt 0 occurs if the transmit interrupt enable (tie) and tfe0_en bits ar e set. if transmit fifo 0 is enabled and filled with data, 8 data words can be transferred before the core must write new data to the stx0 register. the stxd port is disabled except during the data transmission period. for a continuous clock, the optional frame sync output and clock outputs are not disabled, even if both receiver and transmitter are disabled. 42.1.2.1.2 normal mode receive the conditions for data reception from the ssi are: 1. ssi enabled (ssien = 1) 2. receiver enabled (re = 1) 3. frame sync active (for continuous clock case) 4. bit clock begins (for gated clock case) with the above conditions in normal mode with a continuous clock, each time the frame sync signal is generated (or detected) a data word is clocked in. with the above c onditions and a gated clock, each time the clock begins, a data word is clocked in. if receive fifo 0 is not enabled, the received data word is transferred from the receive shift register (rxsr) to the receive data register 0 (srx0), the receive data ready 0 (rdr0) flag is set. receive interrupt 0 occurs if rie and rdr0_en bits are set. if receive fifo 0 is enabled, the received data word is transferred to the receive fifo 0. the receive fifo full 0 (rff0) flag is set if the receive data re gister (srx0) is full and receive fifo 0 reaches the selected threshold. receive interrupt 0 occurs if recei ve interrupt enable (rie) and rff0_en bits are set. the core program has to read the data from the rece ive data register 0 (srx0) before a new data word is transferred from the receive shift register (rxs r), otherwise the receive overrun error 0 (roe0) bit is set. if receive fifo 0 is enabled, the receive overrun error 0 (roe0) bit is set when the receive fifo 0 data level reaches the selected threshold and a new da ta word is ready to be transferred to the receive fifo 0. figure 42-2 shows transmitter and receiver timing for an 8-bit word in the first time slot in normal mode, continuous clock with a late word length frame sync. the tx data register is loaded with the data to be transmitted. on arrival of the frame sync, this data is transferred to the transmit shift register and transmitted on the stxd output. simultaneously, the receive shift register shifts in the received data available on the srxd input and at the end of the time slot , this data is transferred to the rx data register. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-7 figure 42-2. normal mode timing?continuous clock figure 42-3 shows a similar case for internal (ssi generates clock) gated clock mode and figure 42-4 shows a case for external (ssi receives clock) gated clock mode. note a pull-down resistor is required in th e gated clock case because the clock port is disabled between transmissions. the tx data register is loaded with the data to be transmitted. on arrival of the clock, this data is transferred to the transmit shift register and transmitted on the stxd output. simultaneously, the receive shift register shifts in the received data available on the srxd input and at the end of the time slot, this data is transferred to the rx data register . in case of internal gated clock mode, the tx data line and clock output port are put in the high-impedance state at the end of transmission of the last bit (at the completion of the complete clock cycle), whereas, in external gated clock mode, the tx data line is tri-stated at the last inactive edge of the incoming bit clock (during the last bit in a data word). clk fs tx data stxd srxd rx data continuous synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-8 freescale semiconductor figure 42-3. normal mode timing?internal gated clock figure 42-4. normal mode timing?external gated clock 42.1.2.2 network mode network mode is used for creating a time division multiplexed (tdm) network, such as a tdm codec network or a network of dsps. in continuous clock mode, a frame sync occurs at the beginning of each frame. in this mode, the frame is divided into more than one time slot. during each time slot, one data word can be transferred. each time slot is then assigne d to an appropriate codec or dsp on the network. the dsp can be a master device that controls its own privat e network, or a slave device that is connected to an existing tdm network and occupies a few time slots. clk tx data stxd srxd rx data gated clk tx data stxd srxd rx data gated synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-9 the frame sync signal indicates the beginning of a new data frame. each data frame is divided into time slots and transmission and/or reception of one data word can occur in each time slot (rather than in just the frame sync time slot as in normal mode). the frame rate dividers, controlled by the dc[4:0] bits, select two to thirty-two time slots per frame. the length of the frame is determined by the following factors: ? the period of the serial bit clock (psr, pm[7:0] bits for internal clock, or the frequency of the external clock on the stck port) ? the number of bits per sample (wl[3:0] bits) ? the number of time slots per frame (dc[4:0] bits) in network mode, data can be transmitted in any time slot. the distinction of the network mode is that each time slot is identified with respect to the fram e sync (data word time). this time slot identification allows the option of transmitting data during the time slot by writing to the stx registers or ignoring the time slot as determined by stmsk register bits. the receiver is treated in the same manner and received data is only transferred to the receive data regist er/fifo if the corresponding time slot is enabled (through srmsk). by utilizing the stmsk and srmsk registers, software only has to service the ssi during valid time slots. this eliminates any overhead associated with unused time slots. refer to section 42.3.3.20, ?ssi transmit time slot mask register (stmsk) ? and section 42.3.3.21, ?ssi receive time slot mask register (srmsk) ? for more information on stmsk and srmsk. in the two-channel mode of operation, the second set of transmit and receive fifos and data registers are used to create two separate channels. these channe ls are completely independent, with a their own set of core interrupts and dma requests, which are identical to the ones available for the default channel. in this mode, data is transmitted/received in enabled time slots alternately from/to fifo 0 and fifo 1, starting from fifo 0. the first data word is taken from fifo 0 and transmitted in the first enabled time slot and subsequently, data is loaded from fifo 1 and fifo 0 alternately and transmitted. similarly, the first received data is sent to fifo 0 and subsequent data is sent to fifo 1 and fifo 0 alternately. time slots can be selected through the transmit and receiv e time slot mask registers (stmsk and srmsk). for using this mode of operation, the tch_en bit (scr[8]) needs to be set. 42.1.2.2.1 network mode transmit the transmit portion of ssi is enabled when the ssien and the te bits in the scr are both set. however, for continuous clock, when the te bit is set, the tran smitter is enabled only after detection of a new frame sync (transmission starts from the next frame boundary). normal start-up sequence for transm ission is to perform the following: ? write the data to be transmitted to the stx register. this clears the tde flag. ? set the te bit to enable the transmitter on th e next word boundary (for continuous clock case). ? enable transmit interrupts. alternately, the programmer may decide not to transm it in a time slot by writing to the stmsk. the tde flag is not cleared, but the stxd port remains disabl ed during the time slot. when the frame sync is detected or generated (continuous clock), the first enab led data word is transferred from the stx register to the txsr and is shifted out (transmitted). when the stx register is empty, the tde bit is set, which causes a transmitter interrupt (in case fifo is disabled) to be sent if the tie bit is set. software can poll synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-10 freescale semiconductor the tde bit or use interrupts to reload the stx regist er with new data for the next time slot. failing to reload the stx register before the txsr is finished shifting (empty) causes a transmitter underrun, the tue error bit to be set. in case fifo is enabled, the tfe flag is set in accordance with the watermark setting and this flag causes the transmitter interrupt to occur. the operation of clearing the te bit disables the transmitter after completion of transmission of the current frame. setting the te bit enables transmission from the next frame. during that time the stxd port is disabled. the te bit should be cleared after the tde bit is set to ensure that all pending data is transmitted. to summarize, the network mode transmitter generate s interrupts every enabled time slot and requires the core program to respond to each enabled time slot. thes e responses from the core are one of the following: ? write data in data register to enab le transmission in the next time slot. ? configure the time slot register to disable trans mission in the next time slot (unless time slot is already masked by stmsk register bit). ? do nothing?transmit underrun occurs at the beginning of the next time slot and the previous data is re-transmitted. in the two-channel mode of operation, both the cha nnels (data registers, fifos, interrupts and dma requests) operate in the same manner, as describe d above. the only difference in case of the second channel is that the interrupts related to this channel are generated only in case this mode of operation is selected (tde1 is low by default). 42.1.2.2.2 network mode receive the receiver portion of the ssi is enabled when both the ssien and the re bits in the scr are set. however, the receive enable only takes place during that time slot if re is enabled before the second to last bit of the word. if the re bit is cleared, the receiver is disabled at the end of the current frame. ssi is capable of finding the start of the next frame automati cally. when the word is completely received, it is transferred to the srx register, which sets the rdr bit (receive data ready). setting the rdr bit causes a receive interrupt to occur if the receiver interrupt is enabled (the rie bit is set). the second data word (second time slot in the frame), begins shifting in immed iately after the transfer of the first data word to the srx register. the dsp program has to read the da ta from the receive data register (which clears rdr) before the second data word is completely rece ived (ready to transfer to rx data register) or a receive overrun error occurs (the roe bit is set). an interrupt can occur after the reception of each enabled data word or the programmer can poll the rdr flag. the core program response can be one of the following: ? read rx and use the data. ? read rx and ignore the data. ? do nothing?the receiver overrun exception occurs at the end of current time slot. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-11 note for a continuous clock, the optional frame sync output and clock output signals are not affected, even if the transmitter or receiver is disabled. te and re do not disable the bit clock or the frame sync generation. to disable the bit clock and the frame sync generation, the ssien bit in the scr can be cleared, or the port control logic external to the ssi (for example, in the iomux) can be reconfigured. in the two-channel mode of operation, both the cha nnels (data registers, fifos, interrupts and dma requests) operate in the same manner, as describe d above. the only difference in case of the second channel is that the interrupts related to this channel are generated only in case this mode of operation is selected. the transmitter and receiver timing for an 8-bit word with continuous clock, fifo disabled, three words per frame sync in network mode is shown in figure 42-5 . note the transmitter repeats the value 0x5e because of an underrun condition for the transmit section, the stmsk value is updated in the last time slot of frame 1, to mask the first two time slots (0x3). this value takes effect from the next time slot and consequently, the next frame transmits data in the third time slot only. for the receive section, data received on the srxd pin gets transferred to the rx data register at the end of each time slot. if fifo is disabled, the rdr flag gets set and causes a receiv er interrupt if re, rie and rdr_en bits are set. if fifo is enabled, then the rff flag is used for interrupt generation (this flag is set in accordance with the watermark settings). here all time slots are enabled. the receive data ready flag is set after reception of the first data (0x55). since the flag is not cleared (rx data register not read by core), the receive overrun error (roe) flag is set on recepti on of the next data (0x5e). roe flag is cleared on reading the ssi status register followed by reading the rx data register. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-12 freescale semiconductor figure 42-5. network mode timing?continuous clock 42.1.2.3 gated clock mode gated clock mode is ofte n used to hook up to spi-type interfaces on microcontroller units (mcus) or external peripheral chips. in gated clock mode, the presence of the clock indicates that valid data is on clk fs tx data stxd tde tue srxd rx data rdr roe $5e $5e $5e $d6 $d6 $55 $5e $55 $d6 $5e stmsk $3 $7b $7b zz zz $d6 zz $7b synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-13 the stxd or srxd ports. for this reason, no frame sync is needed in this mode. once transmission of data has completed, the clock is pulled to the inactive state. gated clocks are allowed for both the transmit and receive sections with either internal or extern al clock and in normal mode. gated clocks are not allowed in network mode. refer to table 42-5 for ssi configuration for gated-mode operation. the clock runs when the te bit and/or the re bit ar e appropriately enabled. for the case of internally generated clock, all internal bit clocks, word clocks, and frame clocks continue to operate. when a valid time slot occurs (such as the first time slot in no rmal mode), the internal bit clock is enabled onto the appropriate clock port. this allows data to be tran sferred out in periodic inte rvals in gated clock mode. with an external clock, the ssi waits for a clock signa l to be received. once the clock begins, valid data is shifted in. care should be taken to clear all dc bits (0x00000) when ssi is used in gated mode. for gated clock operated in external clock mode, a proper clock signalling must be apply to the ssi stck in order for it to function properly. if the ssi uses rising edge transition to clock data (tsckp=0) and falling edge transition to latch data (rsckp=0), the cloc k must be in an active low state when idle. if the ssi uses falling edge transition to clock data (t sckp=1) and rising edge tr ansition to latch data (rsckp=1), the clock must be in a active high state when idle. figure 42-6 through figure 42-9 illustrate the different edge clocking/latching. figure 42-6. internal gated mode timing?rising edge clocking/falling edge latching figure 42-7. internal gated mode timing?fa lling edge clocking/rising edge latching stxd srxd stck tsckp=0, rsckp=0 stxd srxd stck tsckp=1, rsckp=1 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-14 freescale semiconductor figure 42-8. external gated mode timing?rising edge clocking/falling edge latching figure 42-9. external gated mode timing?fa lling edge clocking/rising edge latching note ? the bit clock ports must be kept free of timing glitches. if a single glitch occurs, all ensuing transfers wi ll be out of synchronization. ? in case of external gated mode, even though the tx data line is put in the high-impedance state at the last non-active edge of the bit clock, the round trip delay should be sufficient to take care of hold time requirements at the external receiver. 42.1.2.4 i 2 s mode the ssi is compliant to i 2 s bus specification from philips semiconductors (february 1986, revised june 5, 1996). figure 42-10 depicts basic i 2 s protocol timing. figure 42-10. i 2 s mode timing?serial clock, frame sync, and serial data stxd srxd stck tsckp=0, rsckp=0 stxd srxd stck tsckp=1, rsckp=1 frame sync serial data serial clock msb msb lsb word (n-1) right channel word (n) left channel word (n+1) right channel synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-15 i 2 s mode can be selected in the following manner: in normal mode operation, all register bits are not forced to any pa rticular state internally and user can program the ssi to work in any operating condition. when i 2 s modes are selected (i 2 s master (01) or i 2 s slave (10)), the following settings are recommended: ? sync mode (scr[4] =1) ? tx shift direction: msb transmitted first (stcr[4]=0) ? rx shift direction: msb received first (srcr[4]=0) ? tx data clocked at falling edge of the clock (stcr[3]=1) ? rx data latched at rising e dge of the clock (srcr[3]=1) ? tx frame sync active low (stcr[2]=1) ? rx frame sync active low (srcr[2]=1) ? tx frame sync initiated one bit before data is transmitted (stcr[0]=1) ? rx frame sync initiated one bit before data is received (srcr[0]=1) in i 2 s master mode(scr[6:5]=01) , the following additional settings are recommended: ? txdir bit (stcr[5]) set to 1 to se lect internal generated bit clock ? tfdir bit (stcr[6]) set to 1 to select internal generated frame sync in i 2 s master mode(scr[6:5]= 01), the following settings are done automatically by the hardware internally: ? network mode is selected (scr[3]=1) ? tx frame sync length set to one-word-long-frame (stcr[1]=0) ? rx frame sync length set to one-word-long-frame (srcr[1]=0) ? tx shifting w.r.t. bit 0 of txsr (stcr[9]=1) ? rx shifting w.r.t. bit 0 of rxsr (srcr[9]=1) the user needs to set the following control bits to configure the bit clock and frame sync: ? pm (stccr[7:0]) ? psr (stccr[17]) ? div2(stccr[18] ? wl (stccr[16:13] ? dc (stccr[12:8]) table 42-2. i 2 s mode selection i 2 s_mode[1] i 2 s_mode[0] remark 0 0 normal mode 01 i 2 s master mode 10 i 2 s slave mode 1 1 normal mode synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-16 freescale semiconductor the word length is fixed to 32 in i 2 s master mode and the wl bits determine the number of bits that will contain valid data (out of the 32 transmitted/received bits in each channel). the fixing of word duration as 32 simplifies the relation between oversampling cloc k (ccm_ssi_clk) and frame sync (ccm_ssi_clk becomes an integer multiple of frame sync). in i 2 s slave mode(scr[6:5]=10), the follow ing additional settings are recommended: ? txdir bit(stcr[5]) set to 0 to select external generated bit clock ? tfdir bit(stcr[6]) set to 0 to select external generated frame sync in i 2 s slave mode(scr[6:5]=10), the following settings ar e done automatically by the hardware internally: ? normal mode is selected (scr[3]=0) ? tx frame sync length set to one-bit-long-frame (stcr[1]=1) ? rx frame sync length set to one-bit-long-frame (srcr[1]=1) ? tx shifting w.r.t. bit 0 of txsr (stcr[9]=1) ? rx shifting w.r.t. bit 0 of rxsr (srcr[9]=1) the user needs to set the following control bits to configure the data transmission: ? wl (stccr[16:13]) ? dc (stccr[12:8]) the word length is variable in i 2 s slave mode and the wl bits determine the number of bits that will contain valid data. the actual word length is de termined by the external codec. the external i 2 s master still sends frame sync according to the i 2 s protocol (early, word wide a nd active low), the ssi internally operates so that each frame sync transition is the star t of a new frame (the wl bits determine the number of bits to be transmitted/received) . after one data word has been tran sferred, the ssi waits for the next frame sync transition to start operation in the next time slot. transmit (stmsk) and receive (srmsk) mask bits should not be used in i 2 s slave mode of operation. 42.1.2.5 ac97 mode in ac97 mode of operation, the ssi transmits a 16-bit tag slot at the start of a frame and the rest of the slots (in that frame) are all 20-bits wide. the same se quence is followed while receiving data. refer to the ac97 specification for details regarding trans mit and receive sequences and data formats. note that the ssi only has one rxdata pin so th e ssi can only support one codec. secondary codecs are not supported. when ac97 mode is enabled, the following settings are internally overridden by the hardware. the programmed register values are not changed by en tering ac97 mode but they no longer apply to the module?s operation. writing to the programmed register fields will update their values; these updates can be seen by reading back the register fields. however, these settings will not take effect until ac97 mode is turned off. the register bits within the bracket are the equivalent settings: ? sync mode is entered (scr[4] =1) ? network mode is selected (scr[3]=1) synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-17 ? tx shift direction is msb transmitted first (stcr[4]=0) ? rx shift direction is msb received first (srcr[4]=0) ? tx data is clocked at rising edge of the clock (stcr[3]=0) ? rx data is latched at falling edge of the clock (srcr[3]=0) ? tx frame sync is active high (stcr[2]=0) ? rx frame sync is active high (srcr[2]=0) ? tx frame sync length is one-word-long-frame (stcr[1]=0) ? rx frame sync length is one-word-long-frame (srcr[1]=0) ? tx frame sync initiated one bit before data is transmitted (stcr[0]=1) ? rx frame sync initiated one bit before data is received (srcr[0]=1) ? tx shifting w.r.t. bit 0 of txsr (stcr[9]=1) ? rx shifting w.r.t. bit 0 of rxsr (srcr[9]=1) ? tx fifo is enabled (stcr[7]=1) ? rx fifo is enabled (srcr[7]=1) ? tfdir bit (stcr[6]) is forced to 1 internally to select internal generated frame sync ? txdir bit(stcr[5]) is forced to 0 internal ly to select external generated bit clock any alteration of these bits individually will not aff ect the operational conditions of the ssi unless ac97 mode is deselected. hence the only control bits needed to set by user to configure the data transmission/reception are the wl (stccr[16:13]) and dc (stccr[12:8]) bi ts. in ac97 mode, the wl bits can only legally take the values corresponding to 16-bit (truncated data) or 20-bit time slot s. in case wl bits are set to select 16-bit time slots, the ssi pads the transmit data (four least signi ficant bits) with zeros and while receiving, stores only the most significant 16 bits in the rx fifo. follow below sequence for programming the ssi to work in ac97 mode: ? program the wl bits to a value corresponding to either 16 or 20 bits. the wl bit setting is only for the data portion of the ac97 frame (slots #3 through #12). the tag slot (slot #0) is always 16 bits wide and the command addre ss and command data slots (slots #1 and #2) are always 20 bits wide. ? select the number of time slots through dc bits. for ac97 operation, dc bits should be set to a value of ?0xc?, resulting in 13 time slots per frame. ? write data to be transmitted, in tx fifo 0 (through tx data register 0) ? program the fv, tif, rd, wr and frdiv bits in sacnt register ? update the contents of sacadd, sacdat and satag (for fixed mode only) registers ? enable the ac97 mode of operation (ac97en bit in sacnt register) once the ssi starts transmitting and receiving data (after being configured in ac97 mode), the programmer needs to service the interrupts, as and when they are raised (updates to command address/data or tag registers, reading of received data and writing more data for transmission). further details regarding fixed and variable mode implementation are provided in the following sections. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-18 freescale semiconductor while using ac97 in two-channel mode (tch_en=1), it is recommended that the received tag is not stored in the rx fifo (tif=0). in case the progra mmer needs to update the satag register and also issue a rd/wr command (in a single frame), it is recommende d that the satag register be updated prior to issuing a rd/wr command. 42.1.2.5.1 ac97 fixed mode (sacnt[1]=0) in fixed mode of operation, ssi transmits in accordance with the frame rate divider bits which decides the number of frames for which the ssi should be idle, after operating for one frame. in a valid frame, tag value (written by core) will be transmitted in slot #0, command address will be transmitted in slot #1 in case of rd/wr command, a nd command data will be tran smitted in slot #2 in case of a wr command. the data from tx-fifo is transmitted in slot #3 to slot #12 depending on the valid slots indicated by the tag value. while receiving, bit 15 of the tag value (slot #0) is chec ked to see if the codec is ready. if this bit is set, the frame is received. the received tag provide s the information about sl ots containing valid data. the the corresponding tag bit is valid, the command address (slot #1) and command data (slot #2) values are stored in the corresponding registers. the rece ived data (slot #3 to slot #12) is then stored in the rx-fifo (for valid slots). 42.1.2.5.2 ac97 variable mode (sacnt[1]=1) in variable mode, the transmit slots which should c ontain data in the current frame are determined by slotreq bits received in the previous frame. while receiving, if the codec is ready, the frame is received and the slotreq bits (contained in slot #1) are stored for scheduling transmission in the next frame. the saccst, saccen and saccdis registers help to determine which transmit slots are active. this information is used to ensure that ssi does not transmit data for powered-down/inactive channels. 42.1.2.6 external frame and clock operation when applying external frame sync and clock signals to ssi, there should be at least 4 bit clock cycles between the enabling of the transmit or receive secti on and the rising edge of the corresponding frame sync signal. the transition of stfs or srfs should be sync hronized with the rising edge of external clock signal, stck or srck. 42.1.2.7 data alignment formats supported the ssi supports three data formats in order to provide flexibility with handling data. these formats dictate how data is written to (and read from) the data registers. therefore, data can appear in different places in stx0/1 and srx0/1 based on the data format and the number of bits pe r word. independent data formats are supported for both the transmitter and recei ver (that is, the transmitter and receiver can use different data formats). the supported data formats are: ? msb alignment synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-19 ? lsb alignment ? zero-extended (receive data only) ? sign-extended (receive data only) with msb alignment, the most significant byte is bits 31 through 24 of the data register if the word length is larger than or equal to 16 bits. if the word length is less than 16 bits and msb alignment is chosen, the most significant byte is bits 15 through 8. with lsb a lignment, the least significant byte is bits 7 through 0. data alignment is controlled by the txbit0 b it in the stcr and the rxbit0 bit in the srcr. table 42-3 shows the bit assignment for all the data formats supported by the ssi. table 42-3. data alignment format bit number 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 8-bit lsb aligned 76543210 8-bit msb aligned 76543210 10-bit lsb aligned 9876543210 10-bit msb aligned 9876543210 12-bit lsb aligned 1 1 1 0 9876543210 12-bit msb aligned 1 1 1 0 9876543210 16-bit lsb aligned 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 16-bit msb aligned 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 18-bit lsb aligned 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 18-bit msb aligned 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 20-bit lsb aligned 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 20-bit msb aligned 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 22-bit lsb aligned 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 22-bit msb aligned 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 24-bit lsb aligned 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 24-bit msb aligned 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-20 freescale semiconductor in addition, receive data can either be zero-extended or sign-extended if lsb ali gnment is selected. with zero-extension, all bits above the most significant bit are ?0?s. this format is useful when data is stored in a pure integer format. with sign-extension, all bits a bove the most significant bit are equal to the most significant bit. this format is useful when data is stored in a fixed-point integer format (which implies fractional values). receive data extension is controlle d by the rxext bit in the srcr. transmit data used with lsb alignment has no concept of sign/zero-extens ion. unused bits above the most significant bit are simply ignored. when configured in i 2 s or ac97 mode, the ssi forces the selection of lsb alignment. however, rxext still permits a choice between zero-extension and sign-extension. refer to section 42.3.3.10, ?ssi transmit c onfiguration register (stcr) ? and section 42.3.3.11, ?ssi receive configuration register (srcr) ? for more detail on the relevant bits in the stcr and srcr. 42.2 external signal description 42.2.1 overview the ssi has no external signals as its serial i/o signals are connected to digital audio mux (audmux) in the appropriate manner. the six ssi ports can be connected to various chip ports by programming the digital audio mux (audmux) in the appropriate manner. refer to chapter 38, ?digital audio mux (audmux) ? for details regarding this programming. 42.2.2 detailed signal descriptions 42.2.2.1 srck?serial receive clock the srck port can be used as either an input or an output. this clock signal is used by the receiver and is always continuous. during gated cl ock mode, the stck port is used instead for clocking in data. in ssi master modes, this port can be used as an output port for the oversampling clock, sys_clk (ccm_ssi_clk). in i 2 s master mode, this port can be used to output ccm_ssi_clk to external codec. table 42-4. signal properties name port function reset state pull up srck ? serial receive clock 0 passive srfs ? serial receive frame sync 0 passive srxd ? serial receive data ? ? stck ? serial transmit clock 0 passive stfs ? serial transmit frame sync 0 passive stxd ? serial transmit data 0 passive synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-21 42.2.2.2 srfs?serial receive frame sync the srfs port can be used as either an input or an output. the frame sync is used by the receiver to synchronize the transfer of data. the frame sync signa l can be one bit or one word in length and can occur one bit before the transfer of data or right at the transf er of data. if srfs is configured as input, the external device should drive srfs during rising edge of stck or srck. 42.2.2.3 srxd?serial receive data the srxd port is an input and is used to bring se rial data into the receive data shift register. 42.2.2.4 stck?serial transmit clock the stck port can be used as either an input or an output. this clock signal is used by the transmitter and can be either continuous or gate d. during gated clock mode, data on the stck port is valid only during the transmission of data, otherwise it is pulled to the inactive state. in synchronous mode, this port is used by both the transmit and receive sections. 42.2.2.5 stfs?serial transmit frame sync the stfs port can be used as either an input or an output. the frame sync is used by the transmitter to synchronize the transfer of data. the frame sync signa l can be one bit or one word in length and can occur one bit before the transfer of data or right at the tr ansfer of data. in synchronous mode, this port is used by both the transmit and receive sections. in gated clock mode, frame sync signals are not used. if stfs is configured as input, the external device should dr ive stfs during rising edge of stck or srck. 42.2.2.6 stxd?serial transmit data the stxd port is an output and transmits data from the serial transmit shift register. the stxd port is an output port when data is being transmitted and is disabled between data word transmissions and on the trailing edge of the bit cl ock after the last bit of a word is transmitted. figure 42-11 and figure 42-12 show the main ssi configurations. these ports support all transmit and receive functions with conti nuous or gated clock as shown. note gated clock implementations do not require the use of the frame sync ports (stfs and srfs). synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-22 freescale semiconductor figure 42-11. asynchronous (syn=0) ssi configurations?continuous clock stxd srxd stck stfs srck srfs ssi ssi internal continuous clock for tx/rx (rxdir=1,txdir=1,rfd ir=1,tfdir=1,syn=0) stxd srxd stck stfs srck srfs ssi ssi external continuous clock for tx/rx (rxdir=0,txdir=0,rfdir=0,tfdir=0,syn=0) stxd srxd stck stfs srck srfs ssi ssi internal continuous clock for rx (rxdir=1, txdir=0,rfdir=1,tfdir=0, syn=0) stxd srxd stck stfs srck srfs ssi ssi internal continuous clock for tx (rxdir=0, txdir=1, rfdir=0, tfdir=1, syn=0) ssi external continuous clock for tx ssi external continuous clock for rx synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-23 figure 42-12. synchronous ssi configurations?continuous and gated clock an example of the port signals for an 8-bit data transfer is shown in figure 42-13 . continuous and gated clock signals are shown, as well as the bit-length frame sync signal and the word-length frame sync signal. ssi internal continuous clock (rxdir=0, txdir=1, rfdir=x, tfdir=1, syn=1, sys_clk_en = 1) stxd srxd stck stfs ssi ssi external continuous clock (rxdir=0, txdir=0, rfdir=x, tfdir=0,syn=1) stxd srxd stck ssi ssi internal gated clock (rxdir=1, txdir=1, syn=1) stxd srxd stck ssi ssi external gated clock (rxdir=1, txdir=0, syn=1) stxd srxd stck stfs ssi ssi i2s master mode (i2s_mode=01, sys_clk_en) ssi i2s slave mode (i2s_mode=10) sys_clk synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-24 freescale semiconductor note the shift direction can be defined as ms b first or lsb first, and that there are other options on the clock and frame sync. figure 42-13. serial clock and frame sync timing continuous stck, srck gated stck, srck stfs, srfs stxd 7 6 54321 0 srxd 7 6 54321 0 8-bit data 7 6 7 6 bit length frame sync word length frame sync early stfs, srfs synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-25 42.2.3 internal i/o signal description table 42-6 provides a list of internal i/o signals. table 42-5. clock pin configuration syn rxdir txdir rfdir tfdir srck stck srfs stfs asynchronous mode 0 0 0 0 0 rck in tck in rfs in tfs in 0 0 0 0 1 rck in tck in rfs in tfs out 0 0 0 1 0 rck in tck in rfs out tfs in 0 0 0 1 1 rck in tck in rfs out tfs out 0 0 1 0 0 rck in tck out rfs in tfs in 0 0 1 0 1 rck in tck out rfs in tfs out 0 0 1 1 0 rck in tck out rfs out tfs in 0 0 1 1 1 rck in tck out rfs out tfs out 0 1 0 0 0 rck out tck in rfs in tfs in 0 1 0 0 1 rck out tck in rfs in tfs out 0 1 0 1 0 rck out tck in rfs out tfs in 0 1 0 1 1 rck out tck in rfs out tfs out 0 1 1 0 0 rck out tck out rfs in tfs in 0 1 1 0 1 rck out tck out rfs in tfs out 0 1 1 1 0 rck out tck out rfs out tfs in 0 1 1 1 1 rck out tck out rfs out tfs out synchronous mode 10 0 x 0 ?ck in?fs in 1 0 0 x 1 ? ck in ? fs out 10 1 x 0 ?ck out?fs in 1 0 1 x 1 ? ck out ? fs out 1 1 0 x x ? gated in ? ? 1 1 1 x x ? gated out ? ? table 42-6. internal i/o signal description name i/o function ipg_hard_async_reset_b input global hardware reset signal ipg_clk input ip interface working clock ipg_clk_s input ip interface register access clock synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-26 freescale semiconductor ips_module_en input ip bus module enable ips_addr[13:2] input ip bus address signal. address of the register being accessed ips_rwb input ip bus read/write signal ips_byte_31_24 input ip bus byte enable signal for the bits [31:24] ips_byte_23_16 input ip bus byte enable signal for the bits [23:16] ips_byte_15_8 input ip bus byte enable signal for the bits [15:8] ips_byte_7_0 input ip bus byte enable signal for the bits [7:0] ips_wdata[31:0] input ip write data bus. all register data writes occur through this bus. ipt_scan_mode input dft test mode signal ipt_test_reset_b input dft test mode reset signal ipt_se_async input dft test asynchronous select signal ipt_se_gatedclk input dft test clock select signal ccm_ssi_clk input ssi input clock for bit clock generation resp_sel input select behavior of ips_xfr_err signal (see note below) din_srxd input ssi receive data input din_stck input ssi transmit clock input din_stfs input ssi transmit frame sync input din_srck input ssi receive clock input din_srfs input ssi receive frame sync input ipg_enable_clk output this signal can be used to gate off the functional clocks when the module is not enabled. ipi_int_b output ssi interrupt request (active low) ipd_ssi_rx1_dmareq_b output ssi receive 1 dma request ipd_ssi_tx1_dmareq_b output ssi transmit 1 dma request ipd_ssi_rx0_dmareq_b output ssi receive 0 dma request ipd_ssi_tx0_dmareq_b output ssi transmit 0 dma request ips_rdata[31:0] output ip read data bus. all register data reads occur through this bus. ips_xfr_err output this signal indicates ip bus access errors. ips_xfr_wait output ip bus wait state signal ssi_stxd output ssi transmit data output ssi_stck output ssi transmit clock output ssi_stfs output ssi transmit frame sync output ssi_srck output ssi receive clock output table 42-6. internal i/o signal description (continued) name i/o function synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-27 note in case the resp_sel signal is low (0), the ips_xfr_err signal is used to generate an error response in case there is an access to the unused portion of ssi?s 16 kb address space. otherwise, an okay response is generated in case of such accesses. 42.3 memory map and register definition section 42.3.3, ?register descriptions ? provides the detailed descriptions for all of the ssi registers. 42.3.1 r/wssi memory map table 42-7 shows the ssi memory map. ssi_srfs output ssi receive frame sync output ssi_ddr_stxd output ssi transmit data (ssi_stxd) output enable ssi_ddr_stck output ssi transmit clock (ssi_stck) output enable ssi_ddr_stfs output ssi transmit frame sync (ssi_stfs) output enable ssi_ddr_srck output ssi receive clock (ssi_srck) output enable ssi_ddr_srfs output ssi receive frame sync (ssi_srfs) output enable table 42-7. ssi memory map address register access reset value 0x1001_1000 (stx0) 0x1001_1004 (stx1) ssi transmit data register 0 (stx0) ssi transmit data register 1 (stx1) r/w r/w 0x0000_0000 0x0000_0000 0x1001_1008 (srx0) 0x1001_100c (srx1) ssi receive data register 0 (srx0) ssi receive data register 1 (srx1) r 0x0000_0000 0x1001_1010 (scr) ssi control register (scr) r/w 0x0000_0000 0x1001_1014 (sisr) ssi interrupt status register (sisr) read only 0x0000_3003 0x1001_1018 (sier) ssi interrupt enable register (sier) r/w 0x0000_3003 0x1001_101c (stcr) ssi transmit configuration register (stcr) r/w 0x0000_0200 0x1001_1020 (srcr) ssi receive configuration register (srcr) r/w 0x0000_0200 0x1001_1024 (stccr) ssi transmit clock control register (stccr) r/w 0x0004_0000 0x1001_1028 (srccr) ssi receive clock control register (srccr) r/w 0x0004_0000 0x1001_102c (sfcsr) ssi fifo control/status register (sfcsr) r/w 0x0081_0081 0x1001_1030 (str) ssi test register (str) 1 r/w 0x0000_1111 table 42-6. internal i/o signal description (continued) name i/o function synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-28 freescale semiconductor 42.3.2 register summary figure 42-14 shows the key to the register fields and table 42-8 shows the register figure conventions. 0x1001_1034 (sor) ssi option register (sor) 2 r/w 0x0000_0000 0x1001_1038 (sacnt) ssi ac97 control register (sacnt) r/w 0x0000_0000 0x1001_103c (sacadd) ssi ac97 command address register (sacadd) r/w 0x0000_0000 0x1001_1040 (sacdat) ssi ac97 command data register (sacdat) r/w 0x0000_0000 0x1001_1044 (satag) ssi ac97 tag register (satag) r/w 0x0000_0000 0x1001_1048 (stmsk) ssi transmit time slot mask register (stmsk) r/w 0x0000_0000 0x1001_104c (srmsk) ssi receive time slot mask register (srmsk) r/w 0x0000_0000 0x1001_1050 (saccst) ssi ac97 channel status register r 0x0000_0000 0x1001_1054 (saccen) ssi ac97 channel enable register w 0x0000_0000 0x1001_1058 (saccen) ssi ac97 channel disable register w 0x0000_0000 1 ssi test register is intended for debugging purposes only and is not visible to the end user. 2 ssi option register intended for internal use only and is not visible to the end user. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 42-14. key to register fields table 42-8. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit. writing a one has some effect on the module, but it always reads as zero. table 42-7. ssi memory map (continued) address register access reset value synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-29 table 42-9 shows the ssi register summary. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 42-9. register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1001_1000 (stx0) r stx0[31:16] w r stx0[15:0] w 0x1001_1004 (stx1) r stx1[31:16] w r stx1[15:0] w 0x1001_1008 (srx0) r srx0[31:16] w r srx0[15:0] w 0x1001_100c (srx1) r srx1[31:16] w r srx1[15:0] w 0x1001_1010 (scr) r000000 0 0 0 0 0 00 0 0 0 w r000000 clk _is t tc h_e n sy s_ cl k_ en i 2 s mode[1:0] sy n ne t re te ss- ien w table 42-8. register figure conventions convention description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-30 freescale semiconductor 0x1001_1014 (sisr) r000000 0 0 0 0 0 00 cmd au cm dd u rx t w r rd r1 rd r0 td e1 td e0 ro e1 ro e0 tu e1 tu e0 tf s rfs tls rl s rf f1 rff 0 tf e1 tfe 0 w 0x1001_1018 (sier) r000000 0 0 0 rd mae rie td ma e tie cmd au_ en cm dd u_ en rx t_e n w rrd r1 _e n rd r0 _e n td e1 _e n td e0 _e n ro e1 _e n ro e0 _e n tu e1_ en tu e0_ en tf s_ en rfs _en tls _en rl s_ en rf f1 _e n rff 0_e n tf e1 _e n tfe 0_e n w 0x1001_101c (stcr) r000000 0 0 0 0 0 00 0 0 0 w r000000 txb it0 tfe n1 tf en 0 tfdi r txd ir ts hf d ts ck p tfsi tf sl tef s w 0x1001_1020 (srcr) r000000 0 0 0 0 0 00 0 0 0 w r00000rx ex t rx bit 0 rf en1 rf en 0 rfd ir rxd ir rs hf d rs ck p rfsi rf sl re fs w 0x1001_1024 (stccr) r000000 0 0 0 0 0 00 div2 ps r wl 3 w r wl 2 wl 1 wl 0 dc 4 dc 3 dc 2 dc 1 dc 0 pm 7 pm6 pm5 pm 4 pm 3 pm2 pm 1 pm 0 w 0x1001_1028 (srccr) r000000 0 0 0 0 0 00 div2 ps r wl 3 w r wl 2 wl 1 wl 0 dc 4 dc 3 dc 2 dc 1 dc 0 pm 7 pm6 pm5 pm 4 pm 3 pm2 pm 1 pm 0 w 0x1001_102c (sfcsr) r rfcnt1[3:0] tfcnt1[3:0] rfwm1[3:0] tfwm1[3:0] w r rfcnt0[3:0] tfcnt0[3:0] rfwm0[3:0] tfwm0[3:0] w table 42-9. register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-31 0x1001_1030 (str) r000000 0 0 0 0 0 00 0 0 0 w r te st rc k2 tc k rf s2 tf s rxstate[4:0] tx d2 rx d tck 2rc k tfs 2rf s txstate[4:0] w 0x1001_1034 (sor) r000000 0 0 0 0 0 00 0 0 0 w r000000 0 0 0 clk off rx_ clr tx _c lr ini t wait[1:0] sy nr st w 0x1001_1038 (sacnt) r000000 0 0 0 0 0 00 w r00000 frdiv[5:0] w r rd tif fv ac9 7e n w 0x1001_103c (sacadd) r000000 0 0 0 0 0 00 sacadd[18:16] w r sacadd[15:0] w 0x1001_1040 (sacdat) r000000 0 0 0 0 0 0 sacdat[19:16] w r sacdat[15:0] w 0x1001_1044 (satag) r000000 0 0 0 0 0 00 0 0 0 w r satag[15:0] w 0x1001_1048 (stmsk) r stmsk[31:0] w r w table 42-9. register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-32 freescale semiconductor 42.3.3 register descriptions this section consists of register descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 42.3.3.1 ssi transmit data registers 0 and 1 (stx0/1) see figure 42-15 for an illustration of valid bits in ssi transmit data register and table 42-10 for descriptions of the bit fields in the register. 0x1001_104c (srmsk) r srmsk[31:0] w r w 0x1001_1050 (saccst) r000000 0 0 0 0 0 00 0 0 0 w r 0 0 0 0 0 0 saccst[9:0] w 0x1001_1054 (saccen) r000000 0 0 0 0 0 00 0 0 0 w r000000 0 0 0 0 0 00 0 0 0 w saccen[9:0] 0x1001_1058 (saccen) r000000 0 0 0 0 0 00 0 0 0 w r000000 0 0 0 0 0 00 0 0 0 w saccdis[9:0] table 42-9. register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-33 note enable ssi (ssien=1) before writing to ssi transmit data registers. 42.3.3.2 ssi transmit fifo 0 and 1 registers the ssi transmit fifo registers are 8x24-bit registers. these registers are not directly accessible by the end user (except in ssi test mode). transmit shift register (txsr) receives its values from these fifo registers. transmitted data is first-in-first-out. when the transmit interrupt enable (tie) bit in the sier and either of the transmit fifo empty (tfe0 or 1) bits in the sisr are set, the core is interrupted whenever the data level in either of the ssi transmit fifos falls below the selected threshold. 42.3.3.3 ssi transmit shift register (txsr) the ssi transmit shift register (txsr) is a 24-bit shif t register that contains the data being transmitted. this register is not directly accessi ble by the end user. when a continuous clock is used, data is shifted out to the serial transmit data (stxd) port by the select ed (internal/external) bit clock when the associated (internal/external) frame sync is asserted. when a gate d clock is used, data is shifted out to the stxd port 0x1001_1000 (stx0) 0x1001_1004 (stx1) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r stx0/1[31:16] w reset0000000000000000 1514131211109876543210 r stx0/1[15:0] w reset0000000000000000 figure 42-15. ssi transmit data registers table 42-10. ssi transmit data register field descriptions field description 31?0 stx0 stx1 ssi transmit data. these bits store the data to be transmitted by the ssi. these are implemented as the first word of their respective tx fifos. data written to these registers is transferred to the transmit shift register (txsr), when shifting of the previous data is complete. if both fifos are in use, data is alternately transferred from stx0 and stx1, to txsr. multiple writes to the stx registers will not result in the previous data being over-written by the subsequent data. stx1 can only be used in two-channel mode of operation. protection from over-writing is present irrespective of whether the transmitter is enabled or not. example 1: if tx fifo0 is in use and user writes data1...data9 to stx0, data9 will not over-write data1. data1...data8 are stored in the fifo while data9 is discarded. example 2: if tx fifo0 is not in use and user writes data1, data2 to stx0, then data2 will not over-write data1 and will be discarded. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-34 freescale semiconductor by the selected (internal/external) gated clock. the word length control bits (wl[3:0]) in the stccr (described in ssi transmit and receive clock control registers) determine the number of bits to be shifted out of the txsr before it is considered empty and can be written to again. this word length can be 8, 10, 12, 16, 18, 20, 22 or 24 bits. the data to be tran smitted occupies the most significant portion of the shift register if txbit0 is ?0?, otherwise it occupies the least significant portion. the unused portion of the register is ignored. data is always shifted out of this register with the most significant bit (msb) first when the shfd bit of the stcr is cleared. if this bit is set, the least significant bit (lsb) is shifted out first. figure 42-16 through figure 42-19 show the transmitter loading and shifting operation. the figures show the working for some wl values , the same can be extended for other values. figure 42-16. transmit data path (txbit0=0, tshfd=0) (msb alignment) figure 42-17. transmit data path (txbit0=0, tshfd=1) (msb alignment) stx 31 0 24 bits stxd 20 bits 16 bits 31 0 txsr 15 11 7 12 bits 12 bits 16 bits stx 31 0 stxd 31 0 txsr 12 bits 20 bits 24 bits 24 bits 12 bits 20 bits 16 bits 15 11 7 15 11 7 16 bits synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-35 figure 42-18. transmit data path (t xbit0=1, tshfd=0) (lsb alignment) figure 42-19. transmit data path (t xbit0=1, tshfd=1) (lsb alignment) 42.3.3.4 ssi receive data registers 0 and 1 (srx0/1) see figure 42-20 for an illustration of valid bits in ssi receive data register and table 42-11 for descriptions of the bit fields in the register. stx 23 0 24 bits stxd 11 12 bits 20 bits 16 bits 23 0 txsr 11 15 19 15 19 31 stx 23 0 stxd 15 txsr 11 19 24 bits 12 bits 20 bits 16 bits 23 0 11 15 19 31 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-36 freescale semiconductor 42.3.3.5 ssi receive fifo 0 and 1 registers the ssi receive fifo registers are 8x24-bit registers. these registers are not directly accessible by the end user (except in ssi test mode). they always acce pts data from the receive shift register (rxsr). the core is interrupted when the data level in either of the ssi receive fifos reaches the selected threshold, if the associated interrupt is enabled. 42.3.3.6 ssi receive shift register (rxsr) the ssi receive shift register (rxsr) is a 24-bit, sh ift register that receives incoming data from the serial receive data srxd port. this register is not directly accessible by the end user. when a continuous clock is used, data is shifted in by the selected (internal/external) bit clock when the associated (internal/external) frame sync is as serted. when a gated clock is used, data is shifted in by the selected (internal/external) gated clock. data is assumed to be received msb first if the shfd bit of the srcr is cleared. if this bit is set, the data is received lsb first. data is transferred to the appropriate ssi receive data register (srx0/1) or receive fifos (if the r eceive fifo is enabled and the corresponding srx is full) after 8, 10, 12, 16, 18, 20, 22 or 24 bits have been shifted in depending on the wl[3:0] control bits. for receiving less than 24 bits of data, lsb bits ar e appended with zero. the following figures show the receiver loading and shifting operation. the figures s how the working for some wl values, the same can be extended for other values. 0x1001_1008 (srx0) 0x1001_100c (srx1) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r srx0/1[31:16] w reset0000000000000000 1514131211109876543210 r srx0/1[15:0] w reset0000000000000000 figure 42-20. ssi receive data registers table 42-11. ssi receive data register field descriptions field description 31?0 srx0 srx1 ssi receive data. these bits store the data received by the ssi. these are implemented as the first word of their respective rx fifos. these bits receive data from the rxsr depending on the mode of operation. in case both fifos are in use, data is transferred to each data register alternately. srx1 can only be used in two-channel mode of operation. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-37 figure 42-21. receive data path (rxbit0=0, rshfd=0) (msb alignment) figure 42-22. receive data path (rxbit0=0, rshfd=1) (msb alignment) srx 31 0 srxd 12 bits 24 bits 20 bits 31 0 rxsr 24 bits 12 bits 20 bits 16 bits 7 11 15 7 11 15 16 bits srx 31 0 srxd 31 0 24 bits 12 bits 20 bits 16 bits rxsr 7 11 15 7 11 15 16 bits 12 bits synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-38 freescale semiconductor figure 42-23. receive data path (rxbit0=1, rshfd=0) (lsb alignment) figure 42-24. receive data path (rxbit0=1, rshfd=1) (lsb alignment) 42.3.3.7 ssi control register (scr) the ssi control register (scr) is a 10-bit register used to set up the ssi. ssi reset is controlled by bit 0 in the scr. ssi operating modes are also selected in this register (except ac97 mode, which is selected in sacnt register). see figure 42-25 for an illustration of valid b its in ssi control register and table 42-12 for descriptions of the bit fields in the register. srx 0 24 bits srxd 11 rxsr 15 19 23 24 bits 12 bits 20 bits 16 bits 23 0 11 15 19 31 srx srx 23 0 24 bits srxd 12 bits 20 bits 16 bits 24 bits 12 bits 20 bits 16 bits rxsr 11 15 19 23 0 11 15 19 31 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-39 0x1001_1010 (scr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000 clk_i st tch_ en sys_ clk_ en i 2 s mode[1:0] syn net re te ss- ien w reset0000000000000000 figure 42-25. ssi control register table 42-12. ssi control register field descriptions field description 31?10 reserved 9 clk_ist clock idle state. this bit controls the idle state of the transmit clock port during ssi internal gated mode. 0 clock idle state is ?0?. 1 clock idle state is ?1?. 8 tch_en two-channel operation enable. this bit allows ssi to operate in the two-channel mode. in this mode, 2 time slots should be used out of the possible 32. any 2 time slots (from 0 to 31) can be selected. the data in the two time slots is alternately handled by the two data registers (0 and 1). while receiving, the rxsr transfers data to srx0 and srx1 alternately and while transmitting, data is alternately transferred from stx0 and stx1 to txsr. if more than 2 slots are to be enabled, then for odd number of slots two-channel operation is deprecated and tch_en should be cleared. this will ensure that all data is received and transmitted from one fifo, fifo0. for an even number of slots, two-channel operation can be enabled to optimize usage of both fifos or disabled as in the case of odd number of active slots. 0 two-channel mode is disabled. 1 two-channel mode is enabled. 7 sys_clk_en system clock enable. when set, this bit allows the ssi to output the sys_clk (ccm_ssi_clk) at the srck port, provided that network mode, synchronous mode, and transmit internal clock mode are set. the relationship between bit clock and sys_clk is determined by div2, psr, and pm bits. this bit can be used to output the oversampling clock on srck port in i2s master mode. 0 sys_clk is not output on the srck port. 1 sys_clk is output on the srck port. 6?5 i 2 s mode[1:0] i 2 s mode select. these bits allow the ssi to operate in normal, i 2 s master or i 2 s slave mode. refer to section 42.1.2.4, ?i2s mode ? for a detailed description of i 2 s mode of operation. refer to table 42-2 for details regarding settings. 4 syn synchronous mode. this bit controls whether ssi is in synchronous mode or not. in synchronous mode, the transmit and receive sections of ssi share a common clock port (stck) and frame sync port (stfs). 0 asynchronous mode is selected. 1 synchronous mode is selected. 3 net network mode. this bit controls whether ssi is in network mode or not. 0 network mode is not selected. 1 network mode is selected. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-40 freescale semiconductor 42.3.3.8 ssi interrupt status register (sisr) the ssi interrupt status register (sisr) is a 19-bit re gister used to monitor the ssi. this register is read-only and is used by the core to interrogate the stat us of the ssi. the status bits are described in the following table. refer to figure 42-26 for a list of ssi interrupt sources. all receiver related interrupts are generated only if the receiver is enabled (scr[2]=1) and all transmitter related interrupts are generated only if the transmitter is enabled (scr[1]=1). 2 re receive enable. this control bit enables the receive section of the ssi. when this bit is enabled, data reception starts with the arrival of the next frame sync. if data is being received when this bit is cleared, data reception continues until the end of the current frame and then stops. if this bit is set again before the second to last bit of the last time slot in the current frame, then reception continues without interruption. 0 receive section is disabled. 1 receive section is enabled. 1 te transmit enable. this control bit enables the transmit section of the ssi. it enables the transfer of the contents of the stx registers to the txsr and also enables the internal transmit clock. the transmit section is enabled when this bit is set and a frame boundary is detected. when this bit is cleared, the transmitter continues to send data until the end of the current frame and then stops. data can be written to the stx registers with the te bit cleared (the corresponding tde bit will be cleared). if the te bit is cleared and then set again before the second to last bit of the last time slot in the current frame, data transmission continues without interruption. the normal transmit enable sequence is to write data to the stx register(s) and then set the te bit. the normal disable sequence is to clear the te and tie bits after the tde bit is set. in gated clock mode, clearing the te bit results in the clock stopping after the data currently in txsr has shifted out. when the te bit is set, the clock starts immediately (for internal gated clock mode). 0 transmit section is disabled. 1 transmit section is enabled. 0 ssien ssien?ssi enable this bit is used to enable/disable the ssi. when disabled, all ssi status bits are preset to the same state produced by the power-on reset, all control bits are unaffected, the contents of tx and rx fifos are cleared. when ssi is disabled, all internal clocks are disabled (except register access clock). 0 ssi is disabled. 1 ssi is enabled. table 42-12. ssi control register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-41 figure 42-26. ssi interrupts note ssi status flags are updated when ssi is enabled. refer to section 42.4.3, ?receive interrupt enable bit description ? and section 42.4.4, ?transmit interrupt enable bit description ? for interrupt source mapping. all the flags in the sisr are updated after the first bit of the next ssi word has completed transmission or recepti on. some status bits (roe0/1 and tue0/1) are cleared by reading the sisr followed by a read or write to either the srx0/1 or stx0/1 registers. see figure 42-27 for an illustration of valid bits in ssi interrupt register and table 42-13 for descriptions of the bit fields in the register. 0x1001_1014 (sisr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0000000000000 cmd au cmd du rxt w reset0000000000000000 1514131211109876543210 r rdr1 rdr0 tde1 tde0 roe1 roe0 tue1 tue0 tfs rfs tls rls rff1 rff0 tfe1 tfe0 w reset0011000000000011 figure 42-27. ssi interrupt status register ssi interrupt sources ssi receive data with exception status 0/1 ssi receive data 0/1 ssi transmit data with exception status 0/1 ssi transmit data 0/1 ssi transmit last time slot ssi ac97 command address updated ssi ac97 receive tag updated ssi receive last time slot ssi ac97 command data updated ssi receive frame sync synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-42 freescale semiconductor table 42-13. ssi interrupt status register field descriptions field description 31?19 reserved 18 cmdau command address register updated. this bit causes the command address updated interrupt (when cmdau_en bit is set). this status bit is set each time there is a difference in the previous and current value of the received command address. this bit is cleared on reading the sacadd register. 0 no change in sacadd register. 1 sacadd register updated with different value. 17 cmddu command data register updated. this bit causes the command data updated interrupt (when cmddu_en bit is set). this status bit is set each time there is a difference in the previous and current value of the received command data. this bit is cleared on reading the sacdat register. 0 no change in sacdat register. 1 sacdat register is updated with different value. 16 rxt receive tag updated. this status bit is set each time there is a difference in the previous and current value of the received tag. it causes the receive tag interrupt (if rxt_en bit is set). this bit is cleared on reading the satag register. 0 no change in satag register. 1 satag register is updated with different value. 15 rdr1 receive data ready 1. this flag bit is set when srx1 or rx fifo 1 is loaded with a new value and two-channel mode is selected. rdr1 is cleared when the core reads the srx1 register. if rx fifo 1 is enabled, rdr1 is cleared when the fifo is empty. if rie and rdr1_en are set, a receive data 1 interrupt request is issued on setting of rdr1 bit in case rx fifo1 is disabled, if the fifo is enabled, the interrupt is issued on rff1 assertion. the rdr1 bit is cleared by por and ssi reset. 0 no new data for core to read. 1 new data for core to read. 14 rdr0 receive data ready 0. this flag bit is set when srx0 or rx fifo 0 is loaded with a new value. rdr0 is cleared when the core reads the srx0 register. if rx fifo 0 is enabled, rdr0 is cleared when the fifo is empty. if rie and rdr0_en are set, a receive data 0 interrupt request is issued on setting of rdr0 bit in case rx fifo0 is disabled, if the fifo is enabled, the interrupt is issued on rff0 assertion. the rdr0 bit is cleared by por and ssi reset. 0 no new data for core to read. 1 new data for core to read. 13 tde1 transmit data register empty 1. this flag is set whenever data is transferred to txsr from stx1 register and two-channel mode is selected. if tx fifo1 is enabled, this occurs when there is at least one empty slot in stx1 or tx fifo1. if tx fifo1 is not enabled, this occurs when the contents of stx1 are transferred to txsr. the tde1 bit is cleared when the core writes to stx1. if tie and tde1_en are set, an ssi transmit data 1 interrupt request is issued on setting of tde1 bit. the tde1 bit is cleared by por and ssi reset. 0 data is available for transmission. 1 data needs to be written by the core for transmission. 12 tde0 transmit data register empty 0. this flag is set whenever data is transferred to txsr from stx0 register. if tx fifo 0 is enabled, this occurs when there is at least one empty slot in stx0 or tx fifo 0. if tx fifo 0 is not enabled, this occurs when the contents of stx0 are transferred to txsr. the tde0 bit is cleared when the core writes to stx0. if tie and tde0_en are set, an ssi transmit data 0 interrupt request is issued on setting of tde0 bit. the tde0 bit is cleared by por and ssi reset. 0 data is available for transmission. 1 data needs to be written by the core for transmission. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-43 11 roe1 receiver overrun error 1. this flag is set when the rxsr is filled and ready to transfer to srx1 register or to rx fifo 1 (when enabled) and these are already full and two-channel mode is selected. if rx fifo 1 is enabled, this is indicated by rff1 flag, else this is indicated by the rdr1 flag. the rxsr is not transferred in this case. the roe1 flag causes an interrupt if rie and roe1_en are set. the roe1 bit is cleared by por and ssi reset. it is also cleared by reading the sisr with roe1 bit set, followed by reading the srx1 register. clearing the re bit does not affect the roe1 bit. 0 default interrupt is issued to the core. 1 exception interrupt is issued to the core. 10 roe0 receiver overrun error 0. this flag is set when the rxsr is filled and ready to transfer to srx0 register or to rx fifo 0 (when enabled) and these are already full. if rx fifo 0 is enabled, this is indicated by rff0 flag, else this is indicated by the rdr0 flag. the rxsr is not transferred in this case. the roe0 flag causes an interrupt if rie and roe0_en are set. the roe0 bit is cleared by por and ssi reset. it is also cleared by reading the sisr with roe0 bit set, followed by reading the srx0 register. clearing the re bit does not affect the roe0 bit. 0 default interrupt is issued to the core. 1 exception interrupt is issued to the core. 9 tue1 transmitter underrun error 1. this flag is set when the txsr is empty (no data to be transmitted), the tde1 flag is set, a transmit time slot occurs and the ssi is in two-channel mode. when a transmit underrun error occurs, the previous data is retransmitted. in network mode, each time slot requires data transmission (unless masked through stmsk register), when the transmitter is enabled (te is set). the tue1 flag causes an interrupt if tie and tue1_en are set. the tue1 bit is cleared by por and ssi reset. it is also cleared by reading the sisr with tue1 bit set, followed by writing to the stx1 register. 0 default interrupt is issued to the core. 1 exception interrupt is issued to the core. 8 tue0 transmitter underrun error 0. this flag is set when the txsr is empty (no data to be transmitted), the tde0 flag is set and a transmit time slot occurs. when a transmit underrun error occurs, the previous data is retransmitted. in network mode, each time slot requires data transmission (unless masked through stmsk register), when the transmitter is enabled (te is set). the tue0 flag causes an interrupt if tie and tue0_en are set. the tue0 bit is cleared by por and ssi reset. it is also cleared by reading the sisr with tue0 bit set, followed by writing to the stx0 register. 0 default interrupt is issued to the core. 1 exception interrupt is issued to the core. 7 tfs transmit frame sync. this flag indicates the occurrence of transmit frame sync. data written to the stx registers during the time slot when the tfs flag is set, is sent during the second time slot (in network mode) or in the next first time slot (in normal mode). in network mode, the tfs bit is set during transmission of the first time slot of the frame and is then cleared when starting transmission of the next time slot. in normal mode, this bit is always high. this flag causes an interrupt if tie and tfs_en are set. the tfs bit is cleared by por and ssi reset. 0 no occurrence of transmit frame sync. 1 transmit frame sync occurred during transmission of last word written to stx registers. 6 rfs receive frame sync. this flag indicates the occurrence of receive frame sync. in network mode, the rfs bit is set when the first slot of the frame is being received. it is cleared when the next slot begins to be received. in normal mode, this bit is always high. this flag causes an interrupt if rie and rfs_en are set. the rfs bit is cleared by por and ssi reset. 0 no occurrence of receive frame sync. 1 receive frame sync occurred during reception of next word in srx registers. table 42-13. ssi interrupt status register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-44 freescale semiconductor 5 tls transmit last time slot. this flag indicates the last time slot in a frame. when set, it indicates that the current time slot is the last time slot of the frame. tls is set at the start of the last transmit time slot and causes the ssi to issue an interrupt (if tie and tls_en are set). tls is cleared when the sisr is read with this bit set. the tls bit is cleared by por and ssi reset. 0 current time slot is not last time slot of frame. 1 current time slot is the last transmit time slot of frame. 4 rls receive last time slot. this flag indicates the last time slot in a frame. when set, it indicates that the current time slot is the last receive time slot of the frame. rls is set at the end of the last time slot and causes the ssi to issue an interrupt (if rie and rls_en are set). rls is cleared when the sisr is read with this bit set. the rls bit is cleared by por and ssi reset. 0 current time slot is not last time slot of frame. 1 current time slot is the last receive time slot of frame. 3 rff1 receive fifo full 1. this flag is set when rx fifo1 is enabled, the data level in rx fifo1 reaches the selected rx fifo watermark 1 (rfwm1) threshold and the ssi is in two-channel mode. the setting of rff1 only causes an interrupt when rie and rff1_en are set, rx fifo1 is enabled and the two-channel mode is selected. rff1 is automatically cleared when the amount of data in rx fifo1 falls below the threshold. the rff1 bit is cleared by por and ssi reset. when rx fifo1 contains 8 words, the maximum it can hold, all further data received (for storage in this fifo) is ignored until the fifo contents are read. 0 space is available in receive fifo1. 1 receive fifo1 is full. 2 rff0 receive fifo full 0. this flag is set when rx fifo0 is enabled and the data level in rx fifo0 reaches the selected rx fifo watermark 0 (rfwm0) threshold. the setting of rff0 only causes an interrupt when rie and rff0_en are set and rx fifo0 is enabled. rff0 is automatically cleared when the amount of data in rx fifo0 falls below the threshold. the rff0 bit is cleared by por and ssi reset. when rx fifo0 contains 8 words, the maximum it can hold, all further data received (for storage in this fifo) is ignored until the fifo contents are read. 0 space is available in receive fifo0. 1 receive fifo0 is full. 1 tfe1 transmit fifo empty 1. this flag is set when tx fifo1 is enabled, the data level in tx fifo1 falls below the selected tx fifo watermark 1 (tfwm1) threshold and the two-channel mode is selected. the setting of tfe1 only causes an interrupt when tie and tfe1_en are set, tx fifo1 is enabled and two-channel mode is selected. the tfe1 bit is automatically cleared when the data level in tx fifo1 becomes more than the amount specified by the watermark bits. the tfe1 bit is set by por and ssi reset. 0 transmit fifo1 has data for transmission. 1 transmit fifo1 is empty. 0 tfe0 transmit fifo empty 0. this flag is set when tx fifo0 is enabled and the data level in tx fifo0 falls below the selected tx fifo watermark 0 (tfwm0) threshold. the setting of tfe0 only causes an interrupt when tie and tfe0_en are set and tx fifo0 is enabled. the tfe0 bit is automatically cleared when the data level in tx fifo0 becomes more than the amount specified by the watermark bits. the tfe0 bit is set by por and ssi reset. 0 transmit fifo0 has data for transmission. 1 transmit fifo0 is empty. table 42-13. ssi interrupt status register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-45 42.3.3.9 ssi interrupt enable register (sier) the ssi interrupt enable register (sier) is a 23-bit register used to set up the ssi interrupts and dma requests. see figure 42-28 for an illustration of valid bits in ssi interrupt enable register and table 42-14 for descriptions of the bit fields in the register. 0x1001_1018 (sier) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000 rdm ae rie tdm ae tie cmd au_e n cmd du_e n rxt_ en w reset0000000000000000 1514131211109876543210 r rdr1 _en rdr0 _en tde1 _en tde0 _en roe1 _en roe0 _en tue1 _en tue0 _en tfs_ en rfs_ en tls_ en rls_ en rff1 _en rff0 _en tfe1 _en tfe0 _en w reset0011000000000011 figure 42-28. ssi interrupt enable register table 42-14. ssi interrupt enable register field descriptions field description 31?23 reserved 22 rdmae receive dma enable. this bit allows ssi to request for dma transfers. when enabled, dma requests are generated when any of the rff0/1 bits in the sisr are set and if the corresponding rfen bit is also set. if the corresponding fifo is disabled, a dma request is generated when the corresponding rdr bit is set. 0 ssi receiver dma requests are disabled. 1 ssi receiver dma requests are enabled. 21 rie receive interrupt enable. this control bit allows the ssi to issue receiver related interrupts to the core. refer to section 42.4.3, ?receive interrupt enable bit description ? for a detailed description of this bit. 0 ssi receiver interrupt requests are disabled. 1 ssi receiver interrupt requests are enabled. 20 tdmae transmit dma enable. this bit allows ssi to request for dma transfers. when enabled, dma requests are generated when any of the tfe0/1 bits in the sisr are set and if the corresponding tfen bit is also set. if the corresponding fifo is disabled, a dma request is generated when the corresponding tde bit is set. 0 ssi transmitter dma requests are disabled. 1 ssi transmitter dma requests are enabled. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-46 freescale semiconductor 42.3.3.10 ssi transmit configuration register (stcr) the ssi transmit configuration register (stcr) is a read/write control registers used to direct the transmit operation of the ssi. stcr controls the dire ction of the bit clock and frame sync ports, stck and stfs. interrupt enable bit for the transmit sections is provided in this control register. the power on reset clears all stcr bits. however, ssi reset does not affect the stcr bits. the stcr bits are described in the following paragraphs. see table 42-7 for the programming model of the ssi. the ssi control register (scr) must first be set to enable interrupts. next, the ssi interrupt bit in the interrupt enable register (sier) must be set to enable the interrupt. finally the interrupt can be enabled from within the ssi. see figure 42-29 for an illustration of valid bits in ssi transmit configuration register and table 42-15 for descriptions of the bit fields in the register. 19 tie transmit interrupt enable. this control bit allows the ssi to issue transmitter data related interrupts to the core. refer to section 42.4.4, ?transmit interrupt enable bit description ? for a detailed description of this bit. 0 ssi transmitter interrupt requests are disabled. 1 ssi transmitter interrupt requests are enabled. 18?0 enable bits enable bit. each bit controls whether the corresponding status bit in sisr can issue an interrupt to the core or not. 0 status bit cannot issue an interrupt. 1 status bit can issue an interrupt. 0x1001_101c (stcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000 txbi t0 tfen 1 tfen 0 tfdi r txdi r tshf d tsck p tfsi tfsl tefs w reset0000001000000000 figure 42-29. ssi transmit configuration register table 42-14. ssi interrupt enable register field descriptions field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-47 table 42-15. ssi transmit configuration register field descriptions field description 31?10 reserved 9 txbit0 transmit bit 0. this control bit allows ssi to transmit the data word from bit position 0 or 15/31 in the transmit shift register. the shifting data direction can be msb or lsb first, controlled by the tshfd bit. 0 shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (msb aligned). 1 shifting with respect to bit 0 of transmit shift register (lsb aligned). 8 tfen1 transmit fifo enable 1. this bit enables transmit fifo 1. when enabled, the fifo allows 8 samples to be transmitted by the ssi (per channel) (a 9th sample can be shifting out) before tde1 bit is set. when the fifo is disabled, an interrupt is generated when a single sample is transferred to the transmit shift register (provided the interrupt is enabled). 0 transmit fifo 1 disabled. 1 transmit fifo 1 enabled. 7 tfen0 transmit fifo enable 0. this bit enables transmit fifo 0. when enabled, the fifo allows eight samples to be transmitted by the ssi per channel (a 9th sample can be shifting out) before tde0 bit is set. when the fifo is disabled, an interrupt is generated when a single sample is transferred to the transmit shift register (provided the interrupt is enabled). 0 transmit fifo 0 disabled. 1 transmit fifo 0 enabled. 6 tfdir transmit frame direction. this bit controls the direction and source of the transmit frame sync signal. internally generated frame sync signal is sent out through the stfs port and external frame sync is taken from the same port. 0 frame sync is external. 1 frame sync generated internally. 5 txdir transmit clock direction. this bit controls the direction and source of the clock signal used to clock the txsr. internally generated clock is output through the stck port. external clock is taken from this port. refer to table 42-5 for details of clock pin configurations. 0 transmit clock is external. 1 transmit clock generated internally. 4 tshfd transmit shift direction. this bit controls whether the msb or lsb will be transmitted first in a sample. note: the codec device labels the msb as bit 0, whereas the core labels the lsb as bit 0. therefore, when using a standard codec, core msb (codec lsb) is shifted in first (tshfd cleared). 0 data transmitted msb first. 1 data transmitted lsb first. 3 tsckp transmit clock polarity. this bit controls which bit clock edge is used to clock out data for the transmit section. 0 data clocked out on rising edge of bit clock. 1 data clocked out on falling edge of bit clock. 2 tfsi transmit frame sync invert. this bit controls the active state of the frame sync i/o signal for the transmit section of ssi. 0 transmit frame sync is active high. 1 transmit frame sync is active low. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-48 freescale semiconductor 42.3.3.11 ssi receive configuration register (srcr) the ssi receive configuration register (srcr) is a read /write control registers used to direct the receive operation of the ssi. srcr controls the direction of the bit clock and frame sync ports, srck and srfs. interrupt enable bit for the transmit sections is provide d in this control register. the power on reset clears all srcr bits. however, ssi reset does not affect the srcr bits. see figure 42-30 for an illustration of valid bits in ssi receive configuration register and table 42-16 for descriptions of the bit fields in the register. 1 tfsl transmit frame sync length. this bit controls the length of the frame sync signal to be generated or recognized for the transmit section. the length of a word-long frame sync is same as the length of the data word selected by wl[3:0]. 0 transmit frame sync is one-word long. 1 transmit frame sync is one-clock-bit long. 0 tefs transmit early frame sync. this bit controls when the frame sync is initiated for the transmit section. the frame sync signal is deasserted after one bit-for-bit length frame sync and after one word-for-word length frame sync. in case of synchronous operation, the frame sync can also be initiated on receiving the first bit of data. 0 transmit frame sync initiated as the first bit of data is transmitted. 1 transmit frame sync is initiated one bit before the data is transmitted. 0x1001_1020 (srcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000 rxex t rxbi t0 rfen 1 rfen 0 rfdi r rxdi r rshf d rsck p rfsi rfsl refs w reset0000001000000000 figure 42-30. ssi receive configuration register table 42-16. ssi receive configuration register field descriptions field description 31?11 reserved 10 rxext receive data extension. this control bit allows ssi to store the received data word in sign extended form. this bit affects data storage only in case received data is lsb aligned (srcr[9]=1) 0 sign extension is turned off. 1 sign extension is turned on. table 42-15. ssi transmit configuration register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-49 9 rxbit0 receive bit 0. this control bit allows ssi to receive the data word at bit position 0 or 15/31 in the receive shift register. the shifting data direction can be msb or lsb first, controlled by the rshfd bit. 0 shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (msb aligned). 1 shifting with respect to bit 0 of receive shift register (lsb aligned). 8 rfen1 receive fifo enable 1. this bit enables receive fifo 1. when enabled, the fifo allows eight samples to be received by the ssi per channel (a 9th sample can be shifting in) before rdr1 bit is set. when the fifo is disabled, an interrupt is generated when a single sample is received by the ssi (provided the interrupt is enabled). 0 receive fifo 1 disabled. 1 receive fifo 1 enabled. 7 rfen0 receive fifo enable 0. this bit enables receive fifo 0. when enabled, the fifo allows 8 samples to be received by the ssi (per channel) (a 9th sample can be shifting in) before rdr0 bit is set. when the fifo is disabled, an interrupt is generated when a single sample is received by the ssi (provided the interrupt is enabled). 0 receive fifo0 is disabled. 1 receive fifo0 is enabled. 6 rfdir receive frame direction. this bit controls the direction and source of the receive frame sync signal. internally generated frame sync signal is sent out through the srfs port and external frame sync is taken from the same port. 0 frame sync is external. 1 frame sync is generated internally. 5 rxdir receive clock direction. this bit controls the direction and source of the clock signal used to clock the rxsr. internally generated clock is output through the srck port. external clock is taken from this port. refer to table 42-5 for details on clock pin configurations. 0 receive clock is external. 1 receive clock is generated internally. 4 rshfd receive shift direction. this bit controls whether the msb or lsb will be received first in a sample. note: the codec device labels the msb as bit 0, whereas the core labels the lsb as bit 0. therefore, when using a standard codec, core msb (codec lsb) is shifted in first (rshfd cleared). 0 data received is msb first. 1 data received is lsb first. 3 rsckp receive clock polarity. this bit controls which bit clock edge is used to latch in data for the receive section. 0 data latched on falling edge of bit clock. 1 data latched on rising edge of bit clock. 2 rfsi receive frame sync invert. this bit controls the active state of the frame sync i/o signal for the receive section of ssi. 0 receive frame sync is active high. 1 receive frame sync is active low. table 42-16. ssi receive configuration register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-50 freescale semiconductor 42.3.3.12 ssi transmit and receive clock control registers (stccr and srccr) the ssi transmit and receive control (stccr and s rccr) registers are 19-b it, read/write control registers used to direct the operation of the ssi. the clock and reset module (crm) can source the ssi clock (ccm_ssi_clk) from multiple sources and pe rform fractional division to support commonly used audio bit rates. the crm can maintain the ccm_ssi_clk frequency at a constant rate even in cases where the ipg_clk frequency changes. these registers control the ssi clock generator, bit and frame sync rates, word length, and number of words per frame for the seri al data. the stccr register is dedicated to the transmit section, and the srccr register is dedicated to the receive section except in synchronous mode, in which the stccr register controls both the receive and transmit sections. power-on reset clears all stccr and srccr bits. ssi reset does not affect the stccr and srccr bits. the control bits are described in the following paragraphs. although the bit patterns of the stccr and srccr registers are the same, the contents of these two registers can be programmed differently. see figure 42-31 for an illustration of valid bits in stccr and srccr, and refer to table 42-17 for descriptions of the bit fields for both ssi transmit and receive clock control registers. 1 rfsl receive frame sync length. this bit controls the length of the frame sync signal to be generated or recognized for the receive section. the length of a word-long frame sync is same as the length of the data word selected by wl[3:0]. 0 receive frame sync is one-word long. 1 receive frame sync is one-clock-bit long. 0 refs receive early frame sync. this bit controls when the frame sync is initiated for the receive section. the frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word length frame sync. 0 receive frame sync is initiated one bit before the data is received. 1 receive frame sync initiated as the first bit of data is received. 0x1001_1024 (stccr) 0x1001_1028 (srccr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000 div2 psr wl3 w reset0000000000000100 1514131211109876543210 r wl2 wl1 wl0 dc4 dc3 dc2 dc1 dc0 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 w reset0000000000000000 figure 42-31. ssi transmit and receive clock control registers table 42-16. ssi receive configuration register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-51 table 42-17. ssi transmit and receive clock control register field descriptions field description 31?19 reserved 18 div2 divide by 2. this bit controls a divide-by-two divider in series with the rest of the prescalers. 0 divider bypassed. 1 divider used to divide clock by 2. 17 psr prescaler range. this bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. it extends the range of the prescaler for those cases where a slower bit clock is required. 0 prescaler bypassed. 1 prescaler used to divide clock by 8. 16?13 wl3?wl0 word length control. these bits are used to control the length of the data words being transferred by the ssi. these bits control the word length divider in the clock generator. they also control the frame sync pulse length when the fsl bit is cleared. in i2s master mode, the ssi works with a fixed word length of 32, and the wl bits are used to control the amount of valid data in those 32 bits. refer to ta bl e 4 2 - 1 8 for details of data word lengths supported by ssi. in ac97 mode of operation, if word length is set to any value other than 16 bits, it will result in a word length of 20 bits. table 42-18. ssi data length wl3 wl2 wl1 wl0 number of bits/word supported in implementation 0000 2 no 0001 4 no 0010 6 no 0011 8 yes 0100 10 yes 0101 12 yes 0110 14 no 0111 16 yes 1000 18 yes 1001 20 yes 1010 22 yes 1011 24 yes 1100 26 no 1101 28 no 1110 30 no 1111 32 no synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-52 freescale semiconductor 42.3.3.13 ssi fifo control/status register (sfcsr) see figure 42-32 for an illustration of valid bits in ssi fifo control/status register and table 42-19 for descriptions of the bit fields in the register. 12?8 dc4?dc0 frame rate divider control. these bits are used to control the divide ratio for the programmable frame rate dividers. the divide ratio works on the word clock. in normal mode, this ratio determines the word transfer rate. in network mode, this ratio sets the number of words per frame. the divide ratio ranges from 1 to 32 in normal mode and from 2 to 32 in network mode. in normal mode, a divide ratio of 1 (dc=00000) provides continuous periodic data word transfer. a bit-length frame sync must be used in this case. these bits can be programmed with values ranging from ?00000? to ?11111? to control the number of words in a frame. 7?0 pm7?pm0 prescaler modulus select. these bits control the prescale divider in the clock generator. this prescaler is used only in internal clock mode to divide the internal clock (ccm_ssi_clk). the bit clock output is available at the clock port. a divide ratio from 1 to 256 (pm[7:0] = 0x00 to 0xff) can be selected. refer to section 42.4.2.2, ?div2, psr and pm bit description ? for details regarding settings. 0x1001_102c (sfcsr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rfcnt1[3:0] tfcnt1[3:0] rfwm1[3:0] tfwm1[3:0] w reset0000000010000001 1514131211109876543210 r rfcnt0[3:0] tfcnt0[3:0] rfwm0[3:0] tfwm0[3:0] w reset0000000010000001 figure 42-32. ssi fifo control/status register table 42-17. ssi transmit and receive clock control register field descriptions field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-53 table 42-19. ssi fifo control/status register field descriptions field description 31?28 rfcnt1[3:0] receive fifo counter1. these bits indicate the number of data words in receive fifo 1. settings for receive fifo counter bits: 0000 0 data word in receive fifo 0001 1 data word in receive fifo 0010 2 data word in receive fifo 0011 3 data word in receive fifo 0100 4 data word in receive fifo 0101 5 data word in receive fifo 0110 6 data word in receive fifo 0111 7 data word in receive fifo 1000 8 data word in receive fifo 27?24 tfcnt1[3:0] transmit fifo counter1. these bits indicate the number of data words in transmit fifo. settings for transmit fifo counter bits: 0000 0 data word in receive fifo 0001 1 data word in receive fifo 0010 2 data word in receive fifo 0011 3 data word in receive fifo 0100 4 data word in receive fifo 0101 5 data word in receive fifo 0110 6 data word in receive fifo 0111 7 data word in receive fifo 1000 8 data word in receive fifo 23?20 rfwm1[3:0] receive fifo full watermark 1. these bits control the threshold at which the rff1 flag will be set. the rff1 flag is set whenever the data level in rx fifo 1 reaches the selected threshold. settings for receive fifo watermark bits: 0000 reserved 0001 rff set when at least one data word have been written to the receive fifo. set when rxfifo = 1,2,3,4,5,6,7,8 data words 0010 rff set when more than or equal to 2 data word have been written to the receive fifo. set when rxfifo = 2,3,4,5,6,7,8 data words 0011 rff set when more than or equal to 3 data word have been written to the receive fifo. set when rxfifo = 3,4,5,6,7,8 data words 0100 rff set when more than or equal to 4 data word have been written to the receive fifo. set when rxfifo = 4,5,6,7,8 data words 0101 rff set when more than or equal to 5 data word have been written to the receive fifo. set when rxfifo = 5,6,7,8 data words 0110 rff set when more than or equal to 6 data word have been written to the receive. set when rxfifo = 6,7,8 data words 0111 rff set when more than or equal to 7 data word have been written to the receive fifo. set when rxfifo = 7,8 data words 1000 rff set when 8 data word have been written to the receive fifo (default). set when rxfifo = 8 data words synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-54 freescale semiconductor table 42-20 indicates the status of the transmit fifo empt y flag, with different settings of the transmit fifo watermark bits and varying amounts of data in the tx fifo. 19?16 tfwm1[3:0] transmit fifo empty watermark 1. these bits control the threshold at which the tfe1 flag will be set. the tfe1 flag is set whenever the data level in tx fifo 1 falls below the selected threshold. settings for transmit fifo watermark bits: 0000 reserved 0001 tfe set when there are more than or equal to 1 empty slots in transmit fifo. (default) transmit fifo empty is set when txfifo <= 7 data. 0010 tfe set when there are more than or equal to 2 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 6 data. 0011 tfe set when there are more than or equal to 3 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 5 data. 0100 tfe set when there are more than or equal to 4 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 4 data. 0101 tfe set when there are more than or equal to 5 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 3 data. 0110 tfe set when there are more than or equal to 6 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 2 data. 0111 tfe set when there are more than or equal to 7 empty slots in transmit fifo. transmit fifo empty is set when txfifo <= 1 data. 1000 tfe set when there are 8 empty slots in transmit fifo. transmit fifo empty is set when txfifo=0 data. 15?12 rfcnt0[3:0] receive fifo counter 0. these bits indicate the number of data words in receive fifo 0. 11?8 tfcnt0[3:0] transmit fifo counter 0. these bits indicate the number of data words in transmit fifo 0. 7?4 rfwm0[3:0] receive fifo full watermark 0. these bits control the threshold at which the rff0 flag will be set. the rff0 flag is set whenever the data level in rx fifo 0 reaches the selected threshold. 3?0 tfwm0[3:0] transmit fifo empty watermark 0. these bits control the threshold at which the tfe0 flag will be set. the tfe0 flag is set whenever the data level in tx fifo 0 falls below the selected threshold. table 42-20. status of transmit fifo empty flag transmit fifo watermark (tfwm) number of data in txfifo 012345678 1 111111110 2 111111100 3 111111000 4 111110000 5 111100000 6 111000000 7 111000000 8 100000000 table 42-19. ssi fifo control/status register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-55 42.3.3.14 ssi test register (str) note ssi test register is designed fo r debugging purpose only, and is not intended for general user access. see figure 42-33 for an illustration of valid bits in ssi test register and table 42-21 for descriptions of the bit fields for the register. 0x1001_1030 (str) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r test rck2 tck rfs2 tfs rxstate[4:0] txd2 rxd tck2 rck tfs2 rfs txstate[4:0] w reset0001000100010001 figure 42-33. ssi test register table 42-21. ssi test register field descriptions field description 31?16 reserved 15 test test mode. this bit enables the test features of ssi. when set, the rxstate and txstate bit values get transferred to the state machine. when in test mode, the user can read the contents of a specific fifo by writing an appropriate value to the rfcnt0/1 or tfcnt 0/1 bits (in sfcsr). 0 no effect on ssi operation. 1 ssi in test mode. 14 rck2tck receive clock to transmit clock loop back. this bit connects srck (used as output) to stck (used as input). 0 no effect on ssi operation. 1 srck to stck loop back enabled. 13 rfs2tfs receive frame to transmit frame loop back. this bit connects srfs (used as output) to stfs (used as input). 0 no effect on ssi operation. 1 srfs to stfs loop back enabled. 12?8 rxstate[4:0] receiver state machine status. these bits indicate the current status of the receive state machine. 7 txd2rxd transmit data to receive data loop back. this bit connects stxd to srxd. 0 no effect on ssi operation. 1 stxd to srxd loop back enabled. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-56 freescale semiconductor 42.3.3.15 ssi option register (sor) note ssi option register is designed for debugging purpose only, and is not intended for general user access. see figure 42-34 for an illustration of valid bits in ssi option register and table 42-22 for descriptions of the bit fields for the register. 6 tck2rck transmit clock to receive clock loop back. this bit connects stck (used as output) to srck (used as input). 0 no effect on ssi operation. 1 stck to srck loop back enabled. 5 tfs2rfs transmit frame to receive frame loop back. this bit connects stfs (used as output) to srfs (used as input). 0 no effect on ssi operation. 1 stfs to srfs loop back enabled. 4?0 txstate transmitter state machine status. these bits indicate the current status of the transmit state machine. 0x1001_1034 (sor) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000000 clko ff rx_c lr tx_c lr init wait[1:0] synr st w reset0000000000000000 figure 42-34. ssi option register table 42-22. ssi option register field descriptions field description 31?7 reserved 6 clkoff clock off. this bit is used to turn off the ipg_clk to further reduce power consumption. 0 no effect on ssi operation. 1 turn off ipg_clk. table 42-21. ssi test register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-57 42.3.3.16 ssi ac97 control register (sacnt) see figure 42-35 for an illustration of valid bits in ssi ac97 control register and table 42-23 for descriptions of the bit fields for the register. 5 rx_clr receiver clear. this bit flushes the contents of rx fifos. it is always read as cleared (?0?). 0 no effect on ssi operation. 1 flush rx fifos. 4 tx_clr tr a n s m i t t e r c l e a r this bit flushes the contents of tx fifos. it is always read as cleared (?0?). 0 no effect on ssi operation. 1 flush tx fifos. 3 init initialize. the setting of this bit causes the ssi state machine to reset. 0 no effect on ssi operation. 1 initialize ssi state machine. 2?1 wait[1:0] wait. these bits control the number wait states to be added to all transactions between the core and ssi. the value of these bits ranges from ?00? (no wait states) to ?11? (three wait states). 0 synrst frame sync reset. this bit automatically resets the accumulation of data in receive data registers (srx0/1) and receive fifos (rxfifo 0/1) on the next frame synchronization. 0 data accumulation not affected. 1 reset data accumulation on frame synchronization. 0x1001_1038 (sacnt) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000 frdiv[5:0] wr rd tif fv ac97 en w reset0000000000000000 figure 42-35. ssi ac97 control register table 42-22. ssi option register field descriptions (continued) field description synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-58 freescale semiconductor 42.3.3.17 ssi ac97 command address register (sacadd) see figure 42-36 for an illustration of valid bits in ssi ac97 command address register and table 42-24 for descriptions of the bit fields for the register. table 42-23. ssi ac97 control register field descriptions field description 31?11 reserved 10?5 frdiv[5:0] frame rate divider. these bits control the frequency of ac97 data transmission/reception. they are programmed with the number of frames for which the ssi should be idle, after operating in one frame. through these bits, ac97 frequency of operation, from 48 khz (000000) to 1 khz (101111) can be achieved. sample value: 001010 (10 decimal) = ssi will operate once every 11 frames. 4 wr write command. this bit specifies whether the next frame will carry an ac97 write command or not. the programmer should take care that only one of the bits (wr or rd) is set at a time. when this bit is set, the corresponding tag bits (corresponding to command address and command data slots of the next tx frame) are automatically set. this bit is automatically cleared by the ssi after completing transmission of a frame. 0 next frame will not have a write command. 1 next frame will have a write command. 3 rd read command. this bit specifies whether the next frame will carry an ac97 read command or not. the programmer should take care that only one of the bits (wr or rd) is set at a time. when this bit is set, the corresponding tag bit (corresponding to command address slot of the next tx frame) is automatically set. this bit is automatically cleared by the ssi after completing transmission of a frame. 0 next frame will not have a read command. 1 next frame will have a read command. 2 tif tag in fifo. this bit controls the destination of the information received in ac97 tag slot (slot #0). 0 tag info stored in satag register. 1 tag info stored in rx fifo 0. 1 fv fixed/variable operation. this bit selects whether the ssi is in ac97 fixed mode or ac97 variable mode. 0 ac97 fixed mode. 1 ac97 variable mode. 0 ac97en ac97 mode enable. this bit is used to enable ssi ac97 operation. refer to section 42.1.2.5 for details of ac97 operation. 0 ac97 mode disabled. 1 ssi in ac97 mode. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-59 42.3.3.18 ssi ac97 command data register (sacdat) see figure 42-37 for an illustration of valid bits in ssi ac97 command data register and table 42-25 for descriptions of the bit fields for the register. 0x1001_103c (sacadd) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000 sacadd[18:16] w reset0000000000000000 1514131211109876543210 r sacadd[15:0] w reset0000000000000000 figure 42-36. ssi ac97 command address register table 42-24. ssi ac97 command address register field descriptions field description 31?19 reserved 18?0 sacadd ac97 command address. these bits store the command address slot information (bit 19 of the slot is sent in accordance with the read and write command bits in sacnt register). these bits can be updated by a direct write from the core. they are also updated with the information received in the incoming command address slot. if the contents of these bits change due to an update, the cmdau bit in sisr is set. 0x1001_1040 (sacdat) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 sacdat[19:16] w reset0000000000000000 1514131211109876543210 r sacdat[15:0] w reset0000000000000000 figure 42-37. ssi ac97 command data register synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-60 freescale semiconductor 42.3.3.19 ssi ac97 tag register (satag) see figure 42-38 for an illustration of valid bits in ssi ac97 tag register and table 42-26 for descriptions of the bit fields for the register. (continued) 42.3.3.20 ssi transmit time slot mask register (stmsk) see figure 42-39 for an illustration of valid bits in ssi transmit time slot register and table 42-27 for descriptions of the bit fields for the register. table 42-25. ssi ac97 command data register field description 31?20 reserved 19?0 sacdat ac97 command data. the outgoing command data slot carries the information contained in these bits. these bits can be updated by a direct write from the core. they are also updated with the information received in the incoming command data slot. if the contents of these bits change due to an update, the cmddu bit in sisr is set. in case of an ac97 read command, these bits are cleared for transmission in time slot #2 of ac97 frame. 0x1001_1044 (satag) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r satag[15:0] w reset0000000000000000 figure 42-38. ssi ac97 tag register table 42-26. ssi ac97 tag register field descriptions field description 31?16 reserved 15?0 satag ac97 tag value. writing to this register (by the core) sets the value of the tx-tag in ac97 fixed mode of operation. on a read, the core gets the rx-tag value received (in the last frame) from the codec. if tif bit in sacnt register is set, the tag value is also stored in rx-fifo in addition to satag register. when the received tag value changes, the rxt bit in sisr register is set. bits satag[1:0] convey the codec-id. in current implementation only primary codecs are supported. thus writing value 2?b00 to this field is mandatory. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-61 42.3.3.21 ssi receive time slot mask register (srmsk) see figure 42-40 for an illustration of valid bits in ssi receive time slot mask register and table 42-28 for descriptions of the bit fields for the register. 0x1001_1048 (stmsk) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r stmsk[31:16] w reset0000000000000000 1514131211109876543210 r stmsk[15:0] w reset0000000000000000 figure 42-39. ssi transmit time slot mask register table 42-27. ssi transmit time slot mask register field descriptions field description 31?0 stmsk transmit mask. these bits indicate which slot has been masked in the current frame. the core can write to this register to control the time slots in which the ssi transmits data. each bit has info corresponding to the respective time slot in the frame. if a change is made to the register contents, the transmission pattern is updated from the next time slot. transmit mask bits should not be used in i2s slave mode of operation. 0 valid time slot. 1 time slot masked (no data transmitted in this time slot). 0x1001_104c (srmsk) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r srmsk[31:16] w reset0000000000000000 1514131211109876543210 r srmsk[15:0] w reset0000000000000000 figure 42-40. ssi receive time slot mask register synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-62 freescale semiconductor 42.3.3.22 ssi ac97 channel status register (saccst) see figure 42-41 for an illustration of valid bits in ssi ac97 channel status register and table 42-29 for descriptions of the bit fields for the register. figure 42-41. ssi ac97 channel status register 42.3.3.23 ssi ac97 channel enable register (saccen) see figure 42-42 for an illustration of valid bits in ssi ac97 channel enable register and table 42-30 for descriptions of the bit fields for the register. table 42-28. ssi receive time slot mask register field descriptions field description 31?0 srmsk receive mask. these bits indicate which slot has been masked in the current frame. the core can write to this register to control the time slots in which the ssi receives data. each bit has info corresponding to the respective time slot in the frame. if a change is made to the register contents, the reception pattern is updated from the next time slot. receive mask bits should not be used in i2s slave mode of operation. 0 valid time slot. 1 time slot masked (no data received in this time slot). 0x1001_1050 (saccst) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r000000 saccst[9:0] w reset00000000000000 00 table 42-29. ssi ac97 channel status register field descriptions field description 9?0 saccst ac97 channel status. these bits indicate which data slot has been enabled in ac97 variable mode operation. this register is updated in case the core enables/disables a channel through a write to saccen/saccdis register or the external codec enables a channel by sending a ?1? in the corresponding slotreq bit. bit [0] corresponds to the first data slot in an ac97 frame (slot #3) and bit [9] corresponds to the tenth data slot (slot #12). the contents of this register only have relevance while the ssi is operating in ac97 variable mode. writes to this register result in an error response on the ip interface. 0 data channel is disabled. 1 data channel is enabled. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-63 figure 42-42. ssi ac97 channel enable register 42.3.3.24 ssi ac97 channel disable register (saccdis) see figure 42-43 for an illustration of valid bits in ssi ac97 channel disable register and table 42-31 for descriptions of the bit fields for the register. figure 42-43. ssi ac97 channel disable register 0x1001_1054 (saccen) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000000000 00 w saccen[9:0] reset00000000000000 00 table 42-30. ssi ac97 channel enable register field descriptions field description 9?0 saccen ac97 channel enable register. the core writes a ?1? to these bits to enable an ac97 data channel. writing a ?0? has no effect. bit [0] corresponds to the first data slot in an ac97 frame (slot #3) and bit [9] corresponds to the tenth data slot (slot #12). writes to these bits only have effect in the ac97 variable mode of operation. these bits are always read as ?0? by the core. 0 write has no effect. 1 write enables the corresponding data channel. 0x1001_1058 (saccen) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 00 w reset00000000000000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000000000 00 w saccdis[9:0] reset00000000000000 00 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-64 freescale semiconductor 42.4 functional description 42.4.1 ssi architecture the synchronous serial interface (s si) is connected to chip pads through the digital audio mux (audmux) module. the audmux can be configured to connect the ssi module to the chip pads in various ways. refer to figure 42-1 for a block diagram of the ssi. 42.4.2 ssi clocking the ssi uses the following clocks: ? bit clock?used to serially clock the data bits in and out of the ssi port. this clock is either generated internally (from ccm_ssi_clk) or take n from external clock source (through the tx/rx clock ports). ? word clock?used to count the number of data b its per word (8, 10, 12, 16, 18, 20, 22 or 24 bits). this clock is generated internally from the bit clock. ? frame clock (frame sync)?used to count the number of words in a frame. this signal can be generated internally from the bit clock, or taken from external source (from the tx/rx frame sync ports). ? system clock?in master mode, this is an integer multiple of frame clock. this is ccm_ssi_clk. it is used in cases when ssi has to provide the clock. care should be taken to ensure that the bit clock frequency (either internally generated by dividing the ccm_ssi_clk or sourced from external device through tx/rx clock ports) is never greater than 1/4 of the ipg_clk frequency. in normal mode (scr[6:5]=00), the bit clock, used to serially clock the data, is visible on the serial transmit clock (stck) and serial receive clock (srck) ports. the word clock is an internal clock used to determine when transmission of an 8, 10, 12, 16, 18, 20, 22, or 24 bit word has completed. the word clock in turn then clocks the frame clock, which count s the number of words in the frame. the frame clock can be viewed on the stfs and srfs frame sync ports, because a frame sync is generated after the correct number of words in the frame have passed. in ma ster and synchronous mode, the unused port srck is used as serial system clock (s ys_clk) enabled by the scr register bit 15, sys_clk_en. this serial system clock is an oversampling clock of the frame sync clock (stfs). in this mode, the word length (wl), prescaler range (psr), prescaler modulus (pm) and frame rate (dc) sele cts the ratio of sys_clk to sampling clock stfs. in case of i 2 s mode, the oversampling clock ccm_ssi_clk can be made available table 42-31. ssi ac97 channel disable register field descriptions field description 9?0 saccdis ac97 channel disable register. the core writes a ?1? to these bits to disable an ac97 data channel. writing a ?0? has no effect. bit [0] corresponds to the first data slot in an ac97 frame (slot #3) and bit [9] corresponds to the tenth data slot (slot #12). writes to these bits only have effect in the ac97 variable mode of operation. these bits are always read as ?0? by the core. 0 write has no effect. 1 write disables the corresponding data channel. synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-65 on this port if the sys_clk_en bit is set. the relati onship between the clocks and the dividers is shown in figure 42-44 . the bit clock can be received from an ss i clock port or can be generated from the ccm_ssi_clk through a divider, as shown in figure 42-45 . figure 42-44. ssi clocking 42.4.2.1 ssi clock and frame sync generation data clock and frame sync signals can be generated in ternally, or can be obtained from external sources. if internally generated, the ssi clock generator is used to derive bit clock and frame sync signals from the ccm_ssi_clk clock. the ssi clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit rate clock generation. in gated clock m ode, the data clock is valid only when data is being transmitted. otherwise the clock port is pulled to the inactive state. a programmable frame rate divider and a word length divider are used for frame rate sync signal generation. figure 42-45 shows a block diagram of the clock generator for the transmit section. the serial bit clock can be internal or external, depending on the transmit direction (txdir) bit in the ssi transmit configuration register (stcr). the receive section contains an equivalent clock generator circuit. figure 42-45. ssi transmit clock generator block diagram figure 42-46 shows the frame sync generator block for the transmit section. when internally generated, both receive and transmit frame sync are generated fro m the word clock and are defined by the frame rate divider (dc[4:0]) bits and the word length (wl[3:0]) bits of the ssi transmit clock control register (stccr). the receive section contains an equi valent circuit for the frame sync generator. serial bit clock word divider (/8, /10, /12, /16, word clock frame divider (/1 to /32) frame clock /18, /20, /22, /24) prescaler (/1 or /8) divider (/1 to /256) txdir(1=output) txdir(0=input) serial bit clock txdir(1=output) word length divider word clock wl[3:0] psr pm[7:0] stck sys_clk sys_clk(srck) txdir sys_clk_en ccm_ssi_clk divider (/1 or /2) div2 divide by 2 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-66 freescale semiconductor figure 42-46. ssi transmit frame sync generator block diagram 42.4.2.2 div2, psr and pm bit description the bit clock frequency can be calculated from the ssi serial system clock (ccm_ssi_clk), using the equation in figure 42-47 . note you must ensure that the bit-clock frequency must be l4 times the ipg_clk period. the oversampling clock frequenc y can go up to ipg_clk frequency. bits div2, psr and pm should not be all set to zero at the same time. figure 42-47. ssi bit clock equation for example, if the ssi working clock sys_clk (ccm_ssi_clk) is 12.288mhz, in 8-bit word normal mode with dc[4:0] set to 1 (00001), pm[7:0] set to 47 (0010 1111), the psr bit cleared, div2 bit set to 1, a bit clock rate of 12.288 mhz /[1 x 4 x 48] = 64 khz is generated. since the 8-bit word rate is equal to one(that is, normal mode), the sampling rate (fs rate) would then be 64 khz / [1 * 8] = 8khz. in next example, the sys_clk (ccm_ssi_clk) cloc k is 11.2896mhz. a 16-bit word network mode with dc[4:0] set to 1 (00001), pm[7:0] se t to 3(0000 0011), the psr bit is set to 0, div2 bit set to 0, and a 11.2896mhz sys_clk clock, a bit clock rate of 11.2896 mhz 3/ [1 x 2x 4] = 1.4112mhz is generated. since the 16-bit word rate is equa l to two, the sampling rate (fs rate ) would be 1.4112 mhz / [2 * 16] = 44.1 khz. table 42-32 below shows programming examples for the clock dividers in crm and ssi to support various bit clock (stck) frequencies. frame rate dc[4:0] frame sync tfsl tx control tfsi stfs tfsi tx frame sync out tx frame sync in word clock tfdir(1=output) tfdir(0=input) f int_bit_clk = f sys_clk / [(div2 + 1) x (7 x psr + 1) x (pm + 1) x 2] where pm=pm[7:0] f frame_syn_clk = (f int_bit_clk ) / [(dc + 1) x wl] where dc = dc[4:0] and wl = 8, 10, 12, 16, 18, 20, 22, 24 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-67 table 42-32. ssi bit clock and frame rate as a function of psr, pm and div2 bits/ word words/ frame ideal frame rate (khz) pll freq (mhz) ssidiv (in crm) mclk/ ccm_ssi_clk freq (mhz) div2 psr pm wl dc actual bit_clk freq (khz) stck required bit_clk freq (khz) stck error (hz) 16 1 8 294.912 48 12.288 0 0 47 7 0 128 128 0 16 2 8 294.912 48 12.288 0 0 23 7 1 256 256 0 16 4 8 294.912 48 12.288 0 0 11 7 3 512 512 0 16 1 12 294.912 48 12.288 0 0 31 7 0 192 192 0 16 2 12 294.912 48 12.288 0 0 15 7 1 384 384 0 16 4 12 294.912 48 12.288 0 0 7 7 3 768 768 0 16 1 16 294.912 48 12.288 0 0 23 7 0 256 256 0 16 2 16 294.912 48 12.288 0 0 11 7 1 512 512 0 16 4 16 294.912 48 12.288 0 0 5 7 3 1024 1024 0 16 1 24 294.912 48 12.288 0 0 15 7 0 384 384 0 16 2 24 294.912 48 12.288 0 0 7 7 1 768 768 0 16 4 24 294.912 48 12.288 0 0 3 7 3 1536 1536 0 16 1 32 294.912 48 12.288 0 0 11 7 0 512 512 0 16 2 32 294.912 48 12.288 0 0 5 7 1 1024 1024 0 16 4 32 294.912 48 12.288 0 0 2 7 3 2048 2048 0 16 1 48 294.912 48 12.288 0 0 15 7 0 768 768 0 16 2 48 294.912 48 12.288 0 0 3 7 1 1536 1536 0 16 4 48 294.912 48 12.288 0 0 1 7 3 3072 3072 0 16 1 11.025 270.9504 48 11.2896 0 0 31 7 0 176.4 176.4 0 16 2 11.025 270.9504 48 11.2896 0 0 15 7 1 352.8 352.8 0 16 4 11.025 270.9504 48 11.2896 0 0 7 7 3 705.6 705.6 0 16 1 22.05 270.9504 48 11.2896 0 0 15 7 0 352.8 352.8 0 16 2 22.05 270.9504 48 11.2896 0 0 7 7 1 705.6 705.6 0 16 4 22.05 270.9504 48 11.2896 0 0 3 7 3 1411.2 1411.2 0 16 1 44.1 270.9504 48 11.2896 0 0 7 7 0 705.6 705.6 0 16 2 44.1 270.9504 48 11.2896 0 0 3 7 1 1411.2 1411.2 0 16 4 44.1 270.9504 48 11.2896 0 0 1 7 3 2822.4 2822.4 0 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-68 freescale semiconductor note the above table describes how various frame rates can be achieved with the pll 0/1 supplying a frequency of 294.912 mhz and 270.9504 mhz (with wl and dc settings as shown). using pll2 requires that these input frequencies be lowered by a factor of 2 (and the dividers be changed accordingly). using the mrcg allows the input frequency to be lowered by a factor of 4 (provided the dividers are changed accordingly). these clocks are recommended as convenient starting points but the system allows for other input clock frequencies as well. the table should be treated as an example and should be updated with the targeted and achievable values specific to the chip. table 42-34 below shows programming of the crm and ssi divi ders in order to gene rate the appropriate sys_clk and bit_clk frequencies for various sampli ng rates.in these examples, the master mode is selected either by setting i 2 s master bit (scr[6:5]=01) or indivi dually programming the ssi in network, synchronous, transmit internal mode (the table specifically illustrates the i 2 s mode frequencies/sample rates). the sys_clk clock is ccm_ssi_clk. the fixed i 2 s frame rate of 64 bits per frame (word length (wl) can be any value) and dc of 1 are assumed. note the above table describes how various frame rates can be achieved with the pll0/1 supplying a frequency of 294.912 mhz and 270.9504 mhz. using pll2 requires that these input frequenc ies be lowered by a factor of 2 (and the dividers be changed accordingly). using the mrcg allows the input frequency to be lowered by a factor of 4 (provided the dividers are changed accordingly). these cloc ks are recommended as convenient starting points but the system allows for other input clock frequencies as well. the above table should be treated as an exam ple and should be updated with the targeted and achievable values specific to the chip. table 42-33. ssi system clock, bit clock, frame clock in master mode bits/ word words/ frame ideal sampling rate (khz) over sampling rate pll freq (mhz) ssidiv (in crm) target mclk freq (mhz) actual mclk freq (mhz) bits/ word words/ frame actual sampling rate (khz) stfs error (hz) 32 2 22.05 512 270.9504 48 11.2896 11.2896 32 2 44.117 17.65 32 2 24 512 294.912 48 12.288 12.288 32 2 22.058 8.82 32 2 32 384 294.912 48 12.288 12.288 32 2 11.029 4.41 32 2 32 512 294.912 36 16.384 16.384 32 2 48.000 0 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-69 42.4.3 receive interrupt enable bit description when the rie and re bit are set the program controller is interrupted when either of the ssi receive fifo full (rff0/1) bits in sisr is set (if the correspondi ng receive fifo is enabled). if receive fifo is not enabled, interrupt is generated when the corresponding ssi receive data ready (rdr0/1) bit in the sisr is set. when the receive fifo is enabled, maximum 8 va lues are available to be read (8 values per channel in two channel mode). if not enabled, then one value ca n be read from the srx register (one each in case of two channel mode). if the rie bit is cleared, thes e interrupt are disabled. however, the rff0/1 and rdr0/1 bits still indicate the receive data regist er full condition. reading the srx registers clears the rdr bits, thus clearing the pending interrupt. two receiv e data interrupts (two per channel in case of two channel mode) are available: receive data with ex ception status, and receive data without exception. table 42-34 and table 42-35 show the conditions under which these interrupts are generated. 42.4.4 transmit interrupt enable bit description the ssi transmit interrupt enable (tie) control bit a llows interrupting the program controller for data transfer requirements of the ssi transmitter. when th e tie and te bits are set, the program controller is interrupted when either of the ssi transmit fifo empty (tfe0/1) flags in sisr are set (if corresponding transmit fifo is enabled). if the corresponding transmit fifo is not enabled, interrupt is generated when the corresponding ssi transmit data register empty (tde0/1) flag in the sisr is set and transmit enable (te) bit is set. when transmit fifo 0 is enabled, 8 values can be writ ten to the ssi (8 per channel in case of two channel mode, using tx fifo 1). if not enabled, then one va lue can be written to the stx0 register (one per channel in case of two channel mode, using stx1). when the tie bit is cleared, all transmit interrupts are disabled. however, the tde0/1 bits always i ndicate the corresponding stx register empty condition, even when the transmitter is disabled by the transmit enable (te) bit (in the scr). writing data to the stx clears the corresponding tde bit, thus clearing the interrupt. two transmit data interrupts are available (four in case of two channel mode, two per channel): transmit data with exception status and transmit data without exceptions. table 42-36 and table 42-37 show the conditions under which these interrupts are generated. table 42-34. ssi receive data 1 interrupts interrupt rie roe1 rff1/rdr1 receive data 1 (with exception status) 1 1 1 receive data 1 (without exception) 1 0 1 table 42-35. ssi receive data 0 interrupts interrupt rie roe0 rff0/rdr0 receive data 0 (with exception status) 1 1 1 receive data 0 (without exception) 1 0 1 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-70 freescale semiconductor 42.4.5 ip bus interface the ssi has an ip bus interface compliant with srs 3.0.2 in order to provide a cont rol and data interface. this interface is used by both the processor and dma controller. 42.4.5.1 transfer lengths supported the ip bus interface of the ssi only supports 32-bit transfers with all ssi registers other than stx0, stx1, srx0, and srx1 (that is, the data registers). w ith the exception of the data registers, using 8-bit and 16-bit transactions could result in undesired behavi or but will not result in a transfer bus error. the data registers (stx0, stx1, srx0, and srx1) support 8- bit, 16-bit, and 32-bit transfer lengths without restrictions. 42.4.5.2 transfer bus errors transfer bus errors are generated upon response to the following: ? write transfer to a read-only register. ? read or write access to a register space beyond the ssi?s last populated register in its memory map (up until the end of the ssi?s allocated memory address range). 42.4.5.3 clock rate the ip bus clock frequency must be at leas t four times the serial bit clock frequency. 42.5 initialization/app lication information the ssi is affected by the following types of reset: ? power-on reset?the power-on reset is genera ted by asserting the reset port. the power-on reset clears the ssien bit in scr, which disables the ssi. all other status and control bits in the ssi are affected as described in ssi programming model in section 42.3, ?memory map and register definition .? ? ssi reset?the ssi reset is generated when the ssien bit in the scr is cleared. the ssi status bits are preset to the same state produced by the power-on reset. the ssi control bits are table 42-36. ssi transmit data 1 interrupts interrupt tie tue1 tfe1/tde1 transmit data 1 (with exception status) 1 1 1 transmit data 1 (without exception) 1 0 1 table 42-37. ssi transmit data 0 interrupts interrupt tie tue0 tfe0/tde0 transmit data 0 (with exception status) 1 1 1 transmit data 0 (without exception) 1 0 1 synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 42-71 unaffected. the control bits in the scr are also unaffected. the ssi reset is useful for selective reset of the ssi without changing the present ss i control bits and without affecting the other peripherals. the correct sequence to initialize the ssi is as follows: 1. issue a power-on or ssi reset (scr[ssien]=0). 2. disable ssi clocks (ipg_clk, ccm_ssi_clk). 3. set all control bits for configuring the ssi (refer to table 42-38 ). 4. enable appropriate interr upts/dma requests through sier. 5. set the scr[ssien] bit (=1) to enable the ssi. 6. enable ssi clocks (ipg_clk, ccm_ssi_clk), as required. 7. in case of ac97 mode, set the sacnt[ac97en] bit after programming the satag register (if needed, for ac97 fixed mode). 8. set scr[te/re] bits. to ensure proper operation of the ssi, the program mer should use the power-on or ssi reset before changing any of the following control bits listed in table 42-38 . note these control bits should not be changed when ssi is enabled. table 42-38. ssi control bits requiring ssi to be disabled before change control register bit scr [9]=clk_ist [8]=tch_en [7]=sys_clk_en [6:5]=i 2 s_mode [4]=syn [3]=net sier [22]=rdmae [20]=tdmae synchronous serial interface (ssi) MCIMX27 multimedia applications processor reference manual, rev. 0.2 42-72 freescale semiconductor srcr stcr [9]=rxbit0 [9]=txbit0 [8]=rfen1 [8]=tfen1 [7]=rfen0 [7]=tfen0 [6]=rfdir [6]=tfdir [5]=rxdir [5]=txdir [4]=rshfd [4]=tshfd [3]=rsckp [3]=tsckp [2]=rfsi [2]=tfsi [1]=rfsl [1]=tfsl [0]=refs [0]=tefs srccr stccr [16]=wl3 [15]=wl2 [14]=wl1 [13]=wl0 sacnt [1]=fv [10:5]=frdiv table 42-38. ssi control bits requiring ssi to be disabled before change (continued) control register bit MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-1 chapter 43 liquid crystal display controller (lcdc) the liquid crystal display controller (lcdc) provides di splay data for external gray-scale or color lcd panels. the lcdc is capable of supporting black-and- white, gray-scale, passive -matrix color (passive color or cstn), and active-matrix color (active color or tft) lcd panels. 43.1 features the lcdc provides the following features: ? configurable ahb bus width (32-bit/64-bit). ? support for single (non-split) screen monochrome or color lcd panels and self-refresh type lcd panels ? 16 simultaneous gray-scale levels from a palette of 16 fo r monochrome display ? support for: ? maximum resolution of 800 600 ? passive color panel: ? 4 (mapped to rgb444) / 8 (mapped to rgb444) / 12 (rgb444) bits per pixel (bpp) ? tft panel: ? 4 (mapped to rgb666) / 8 (mapped to rgb666) / 12 (rgb444) / 16 (rgb565) / 18 (rgb666) bpp ? 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp cstn display respectively ? 16 and 256 colors out of a palette of 256k colors for 4 bpp and 8 bpp tft display respectively ? true 4096 colors for a 12 bpp display ? true 64k colors for 16 bpp ? true 256k colors for 18 bpp ? 16-bit auo tft lcd panel. ? 24-bit auo tft lcd panel. additional support details are shown in table 43-1 . table 43-1. supported panel characteristics panel type bit/pixel panel interface (bits) number of gray level/color monochrome 1 1, 2, 4, 8 black-and-white 2 1, 2, 4, 8 4 out of palette of 16 4 1, 2, 4, 8 16 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-2 freescale semiconductor ? standard panel interface for common lcd drivers ? panel interface of 1-, 2-, 4-, 8-bit for monochrome panels ? panel interface of 12-, 16-, 18-bit for color panels ? for 4 bpp and 8 bpp, a palette table is used for re-mapping of data from memory, independent of the type of panel used. for 1 bpp, 2 bpp, 12 bpp, 16 bpp and 18 bpp, the palette table is by-passed. ? interface to passive and active color panel (tft) ? supports timing requirements for sharp 240 320 hr-tft panel ? hardware-generated cursor with blink, color, and size programmability ? logical operation between color hardware cursor and background ? hardware panning (soft horizontal scrolling) ? 8-bit pulse-width modulator for software contrast control ? graphic window support for viewfinder function in color display ? graphic window color keying for graphical hardware cursor ? 256 transparency levels for alpha blendi ng between graphic window and background plane cstn 4, 8 12 16, 256 out of palette of 4096 12 12 4096 tft 4, 8 18 16, 256 out of palette of 256k 12, 16, 18 12, 16, 18 4096, 64k, 256k table 43-1. supported panel characteristics (continued) panel type bit/pixel panel interface (bits) number of gray level/color liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-3 figure 43-1. lcdc block diagram 43.2 overview the following sections describe the operation of lc dc with various industry standard lcd displays. 43.2.1 lcd screen format the number of pixels forming the screen width a nd screen height of the lcd panel are software programmable. figure 43-2 shows the relationship between the screen size and memory window. figure 43-2. lcd screen format fifo panning shifter 256x18 lut byte swap panning data shifter data 256x18 lut background plane graphic window alpha blending 4bpp gray interface frc gray non- color cursor color cursor frc color 4bpp gray color cstn buffer interface buffer interface logic cstn tft to panel 4/8bpp color 4/8bpp color 1/2bpp gray ahb interface 64x8 fifo 64 bit to 32 bit interface dma underrun protect fifo byte swap dma ahb interface 64x8 fifo 64 bit to 32 bit interface virtual page width (vpw) virtual page height (vph) screen starting address (ssa) screen height (ymax) screen width (xmax) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-4 freescale semiconductor screen width (xmax) and screen height (ymax) pa rameters specify the lcd panel size. lcdc begins scanning the display memory at the location pointed by the screen starting address (ssa) register, represented by the shaded area in figure 43-2 , for display on the lcd panel. maximum page width is specified by the virtual page width (vpw) parameter. virtual page height (vph) does not affect the lcdc and is limited only by memory size. by changing the ssa register, a screen-sized window can be vertically or horizontally scrolled (panned) a nywhere inside the virtual page boundaries. software must control the starting address in the ssa properly so that the sc anning logic?s system memory pointer (smp) stays within the vpw and vph limits to prevent display of strange artifacts on the screen. vph is used by the programmer only for boundary checks. there is no vph parameter internal to lcdc. vpw is used to calculate the ram starting address representing the begi nning of each displayed line. ssa sets the address of data for the first line of a frame. for each subse quent line, vpw is added to an accumulation initialized by the ssa to yield the starting address of that line. 43.2.2 graphic window on screen graphic window is supported in lcd color panel scr een for viewfinder and graphic hardware cursor functions. similar to screen, virtua l page width, graphic window start address and graphic window width and height are software programma ble. graphic window position on scre en is specified by the graphic window position register. figure 43-3 shows how the graphic window is configured and placed on the screen. graphic window and background plane can be alpha blended. the alpha value is window basis which means all the pixels in the graphic window have the same level of transpar ency. there are a total of 256 levels of transparency to be configured. in add ition, one of the pixel colors can be chosen for color keying in which the selected pixel color in the graphi cs window is made totally transparent. one of the applications can be a graphical hardware cursor. figure 43-3. graphic window on screen note graphic window and background images must have the same bpp setting. background image screen graphic window image graphic window graphic window virtual page width graphic window width graphic window height graphic window start address graphic window position liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-5 43.2.3 panning panning offset (pos) is expressed in bits, not pixels, so when operating in any mode other than 1 bpp, only even pixel boundaries are valid. in 12 bpp mode, pixels are aligned to 16-bit boundaries, and pos also must align to these boundaries. ssa and pos are located in isolated registers and are double buffered because they are dynamic parameters, likely to cha nge when lcdc is running. new values of ssa and pos do not take effect until the beginning of next frame. a typical panning algorithm includes an interrupt at the beginning of frame. in the interrupt service routine, pos and/or ssa are updated (old values are internally latched). the updates take effect on the next frame. 43.2.4 display data mapping lcdc supports 1/2/4 bpp in monochrome mode and 4/ 8/12/16/18 bpp in color mode. system memory data mapping in 2/4/8/12/16/18 bpp modes is shown in figure 43-4 . figure 43-4. pixel location on display screen note in 12 bpp mode, 16 bits of memory are used for each set of 12-bits, to leave 4-bits unused. in 18 bpp mode, 32 bits of memory are used for each pixel, leaving 14-bits unused. refer to figure 43-5 . lcd screen p0 p1 p2 p3 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-6 freescale semiconductor figure 43-5. display data mapping 1 bpp through 16 bpp mode 1 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 p24 p25 p26 p27 p28 p29 p30 p31 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 p16 p17 p18 p19 p20 p21 p22 p23 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p8 p9 p10 p11 p12 p13 p14 p15 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p1 p2 p3 p4 p5 p6 p7 2 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 p12 p13 p14 p15 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 p8 p9 p10 p11 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p4 p5 p6 p7 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p1 p2 p3 4 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 p6 p7 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 p4 p5 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p2 p3 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p1 8 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 p3 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 p2 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 12 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 red1 [3] red1 [2] red1 [1] red1 [0] 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 green1 [3] green1 [2] green1 [1] green1[0] blue1 [3] blue1 [2] blue1 [1] blue1 [0] 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 red0 [3] red0 [2] red0 [1] red0 [0] 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 green0 [3] green0 [2] green0 [1] green0 [0] blue0 [3] blue0 [2] blue0 [1] blue0 [0] 16 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 red1 [4] red1 [3] red1 [2] red1 [1] red1 [0] green1 [5] green1 [4] green1 [3] 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 green1 [2] green1 [1] green1 [0] blue1 [4] blue1 [3] blue1 [2] blue1 [1] blue1 [0] 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 red0 [4] red0 [3] red0 [2] red0 [1] red0 [0] green0 [5] green0 [4] green0 [3] 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 green0 [2] green0 [1] green0 [0] blue0 [4] blue0 [3] blue0 [2] blue0 [1] blue0 [0] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-7 figure 43-6. display data mapping for 18 bpp mode figure 43-7. display data mapping for 24 bpp mode 43.2.5 black-and-white operation the 1 bpp mode is also known as black-and-white mode because each pixel is always either fully on or fully off. 43.2.6 gray-scale operation the lcdc generates a maximum of 16 gray levels. these gray levels are defined by 2 or 4 bits of display data for each pixel. using 2 bpp, lcdc displays 4 shades of gray. using 4 bpp, lcdc displays all 16 shades. the shades of gray are obtained by controlling the number of frames in which the pixel is ?on? over a period of 16 frames. this method is known as fra me rate control (frc). for more information on frc, see section 43.2.8, ?frame rate modulation control (frc) .? mapping ram use is shown in normal 18bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 red [5] red [4] red [3] red [2] red [1] red [0] 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 green [5] green [4] green [3] green [2] green [1] green [0] 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blue [5] blue [4] blue [3] blue [2] blue [1] blue [0] microsoft pal_bgr 18bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 blue [5] blue [4] blue [3] blue [2] blue [1] blue [0] 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 green [5] green [4] green [3] green [2] green [1] green [0] 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 red [5] red [4] red [3] red [2] red [1] red [0] aus 24 bpp mode byte address sample bit-to-pixel mapping 3 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 2 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 blue[7] blue[6] blue [5] blue [4] blue [3] blue [2] blue [1] blue [0] 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 breen[7] green[6] green [5] green [4] green [3] green [2] green [1] green [0] 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 red[7] red[6] red [5] red [4] red [3] red [2] red [1] red [0] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-8 freescale semiconductor figure 43-8 . while using 2 bpp, 2-bit code is mapped to one of the four gray levels, and while using 4 bpp, 4-bit code is mapped to one of the 16 gray levels. because crystal form ulations and driving voltages vary, visual gray effect may or may not be linearly relate d to the frame rate. a logarithmic scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly sp aced scale such as 0, 5/16, 11/16 and 1 for certain graphics. figure 43-8 illustrates gray-scale pixel generation. the flexible mapping scheme allows user to optimize the visual effect for a specific panel or application. figure 43-8. gray-scale pixel generation 43.2.7 color generation figure 43-9 shows an overview of an active matrix color pixel generation. 10 1100 76543210 2 bpp data 4 bpp data 10 1 1 - - - - - - - - frc 1 to panel liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-9 figure 43-9. active matrix color pixel generation the value corresponding to each color pixel on the screen is represented by a 4-bit, 8-bit, 12-bit, 16-bit or 18-bit code in the display memory. for 4-bit and 8-bi t modes, lcdc?s color mapping ram is used to map the data to a 12-bit and 18-bit rgb c ode for passive and active matrix co lor displays respectively. for 4-bit and 8-bit passive matrix color di splays, 12-bit rgb code from mapping ram is output to the frc blocks that independently process the code corresponding to the red, green and blue components of each pixel to generate the required shade and intensity. for 4-bit and 8-bit active matrix display, 18-bit output from mapping ram is output to the panel. for 12-bit mode for passive matrix color display, mappi ng ram is by-passed and output directly to the frc block. for 12-bit, 16-bit and 18-bit active matrix color display, pixel data is simply moved from display memory to the lcdc output bus. figure 43-9 and figure 43-10 illustrates active matrix and passive matrix color pixel generation. 10 1100 76543210 4 bpp data 8 bpp data to panel 1 1 10 11 color ram inside lcdc 256 rows 0101 12/16/18 bpp data 10 10 11011101 r g b 0 0 0 0 000 0 0 11 1 1 111 1 1 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-10 freescale semiconductor figure 43-10. passive matrix color pixel generation 43.2.8 frame rate modulation control (frc) circuitry inside the lcdc generates intermediate gr ay-scale colors on the panel by adjusting the density of zeroes and ones that appear over the frames. lc dc can generate 16 simultaneous gray-scale levels. table 43-2. gray palette density gray code (hexadecimal) density density (decimal) 000 1 1/8 0.125 21/50.2 31/40.25 4 1/3 0.333 52/50.4 6 4/9 0.444 71/20.5 8 5/9 0.555 10 1100 76543210 4 bpp data 8 bpp data 10 1 1 1 1 10 11 color ram inside lcdc 256 rows rgb frc frc frc 0101 10 10 11011101 12 bpp data 1 0 1 to panel 0 0 00 1 1 1 11 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-11 43.2.9 panel interface signals and timing lcdc continuously provides pixel data to the lcd pa nel via lcd panel interface. panel interface signals are illustrated in figure 43-11 . format, timing and polarity of panel interface signals are programmable. there are two basic modes, passive and active, selected by the tft register bit. the user must also select either gray scale mode or color mode. figure 43-11. lcdc interface signals spl_spr, ps, cls and rev are other interface signals from lcdc. however, these signals are dedicated for sharp hr-tft 240 320 panels only. 43.2.9.1 pin configuration for lcdc figure 43-11 shows the signals used for the lcdc. these pins are multiplexed with other functions on the device, and must be configured for lc dc operation before they can be used. note the user must ensure that data directi on bits in gpio are set to the correct direction for proper operation. 93/50.6 a 2/3 0.666 b3/40.75 c4/50.8 d 7/8 0.875 e 14/15 0.933 f11 note: overbars indicate repeating decimal numbers. table 43-2. gray palette density (continued) gray code (hexadecimal) density density (decimal) ld [17:0] flm/vsync lp/hsync lsclk acd/oe ps cls rev spl_spr contrast lcd controller liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-12 freescale semiconductor 43.2.9.2 passive matrix panel interface signals figure 43-12 shows lcd interface timing for monochrome panels and figure 43-13 shows lcd interface timing for passive matrix color panels. signal polarities are shown positive, however it can be reversed by clearing the bits in panel configura tion register (pcr). data bus timi ng for passive panels is controlled by shift clock (lsclk), line pulse (lp), first line ma rker (flm), alternate crystal direction (acd) and line data (ld) signals. operati on of the panel interface is accomplished in the following steps: 1. lsclk clocks the pixel data into the di splay driver?s internal shift register. 2. lp signifies the end of current line of serial data and latches the shifted pixe l data into a wide latch. 3. flm marks the first line of the displayed page. ld (and the associated lp), enclosed by the flm signal, marks the first line of the current frame. 4. acd toggles after a pre-programmed number of fl m pulses. this signal refreshes the lcd panel. note ld bus width is programmable to 1, 2, 4, or 8 bits in monochrome mode (color bit in panel configuration register is set to 0). data is justified to the least significant bits of the ld [ 17:0] bus. passive color displays use a fixed 2-2/3 pixels of data pe r 8-bit vector as shown in figure 43-13 . table 43-3. pin configuration pin setting configuration procedure acd/oe primary function of gpio port a[31] 1. clear bit 31 of port a gpio in use register (gius_a) 2. clear bit 31 of port a general purpose register (gpr_a) contrast primary function of gpio port a[30] 1. clear bit 30 of port a gpio in use register (gius_a) 2. clear bit 30 of port a general purpose register (gpr_a) flm/vsync primary function of gpio port a[29] 1. clear bi t 29 of port a gpio in use register (gius_a) 2. clear bit 29 of port a general purpose register (gpr_a) lp/hsync primary function of gpio port a[28] 1. clear bit 28 of port a gpio in use register (gius_a) 2. clear bit 28 of port a general purpose register (gpr_a) spl_spr primary function of gpio port a[27] 1. clear bit 27 of port a gpio in use register (gius_a) 2. clear bit 27 of port a general purpose register (gpr_a) ps primary function of gpio port a[26] 1. clear bit 26 of port a gpio in use register (gius_a) 2. clear bit 26 of port a general purpose register (gpr_a) cls primary function of gpio port a[25] 1. clear bit 25 of port a gpio in use register (gius_a) 2. clear bit 25 of port a general purpose register (gpr_a) rev primary function of gpio port a[24] 1. clear bit 24 of port a gpio in use register (gius_a) 2. clear bit 24 of port a general purpose register (gpr_a) ld [17:0] primary function of gpio port a[23:6] 1. clear bits [23:6] of port a gpio in use register (gius_a) 2. clear bits [23:6] of port a general purpose register (gpr_a) lsclk primary function of gpio port a[5] 1. clear bit 5 of port a gpio in use register (gius_a) 2. clear bit 5 of port a general purpose register (gpr_a) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-13 figure 43-12. lcdc interface timing for 4-bit data width gray-scale panels figure 43-13. lcdc interface timing for 8-bit data passive matrix color panels 43.2.9.3 passive panel interface timing figure 43-14 shows horizontal timing (timing of one line), including both line pulse (lp) and data. lp width and delay, both before and after lp are progr ammable. the parameters used for panel interface timing are: ? xmax (x size) defines number of pixels per line . xmax is the total number of pixels per line. ? h_wait_1 defines the delay from end of data output to the beginning of lp. ? h_width (horizontal sync pulse width) defines width of flm pulse, and it must be at least 1. ? h_wait_2 defines the delay from end of lp to the beginning of data output. ld0 [0,0] [0,4] [0,8] ld1 [0,1] [0,5] [0,9] ld2 [0,2] [0,6] [0,10] ld3 [0,3] [0,7] [0,11] [0,m-8] [0,m-4] [0,m-7] [0,m-3] [0,m-6] [0,m-2] [0,m-5] [0,m-1] [0,232] [0,236] [0,233] [0,237] [0,234] [0,238] [0,235] [0,239] lsclk 123 m/4 m/4-1 59 60 lp flm lp line 1 line 2 line 3 line 4 line n line 1 ld7 r[0,0] b[0,2] g[0,5] ld6 g[0,0] r[0,3] b[0,5] ld5 b[0,0] g[0,3] r[0,6] ld4 r[0,1] b[0,3] g[0,6] b[0,m-6] g[0,m-3] r[0,m-5] b[0,m-3] g[0,m-5] r[0,m-2] b[0,m-5] g[0,m-2] b[0,234] g[0,237] r[0,235] b[0,237] g[0,235] r[0,238] b[0,235] g[0,238] lsclk 123 3*m/8 3*m/8-1 89 90 lp flm lp line 1 line 2 line 3 line 4 line n line 1 ld3 g[0,1] r[0,4] b[0,6] ld2 b[0,1] g[0,4] r[0,7] ld1 r[0,2] b[0,4] g[0,7] ld0 g[0,2] r[0,5] b[0,7] r[0,m-4] b[0,m-2] g[0,m-4] r[0,m-1] b[0,m-4] g[0,m-1] r[0,m-3] b[0,m-1] r[0,236] b[0,238] g[0,236] r[0,239] b[0,236] g[0,239] r[0,237] b[0,239] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-14 freescale semiconductor note all parameters are defined in unit of pixel clock period, unless otherwise stated. 43.2.10 8 bpp mode color stn panel figure 43-14. horizontal sync pulse timing in passive mode figure 43-15. vertical sync pulse timing in passive mode hwait2+2 hwidth+1 hwait1+1 t xmax flm lsclk lp ld[15:0] hwidth+1 hwait2+2 ts (last line) (first line ) when it is in cstn mode or monochrome m ode with bus width = 1, t = 1 sclk period. when it is in monochrome mode with bus width = 2, 4 and 8, t = 1, 2 and 4 sclk period respectively. flm lp lsclk pass_frame_wait ymax (lines) end of last line start of frame liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-15 43.2.10.1 active matrix panel interface signals figure 43-16. lcdc interface 16-bit timing for active matrix color panels figure 43-16 and figure 43-17 shows lcd interface timing for an active matrix color tft panel. in these figures, signals are shown with negative polarit y (flmpol=1, lppol=1, clkpol=0, oepol=1). in tft mode, lsclk is automatically inverted. the panel interface timing for active matrix panels is sometimes referred to as a ?digital crt? and is c ontrolled by shift clock (lsclk), horizontal sync pulse (hsync, lp pin in passive mode), vertical sync pulse (vsync, flm pin in passive mode), output enable (oe, acd pin in passive mode), and line data (ld) si gnals. sequence of events for active matrix interface timing is: 1. lsclk latches data into the panel on its negative edge (when positive polarity is selected). in active mode, lsclk runs continuously. 2. hsync causes the panel to start a new line. 3. vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. ld14 r1[0,0] r1[0,1] r1[0,2] ld13 r0[0,0] r0[0,1] r0[0,2] ld11 g5[0,0] g5[0,1] g5[0,2] ld10 g4[0,0] g4[0,1] g4[0,2] lsclk 123 m m-1 239 240 hsync vsync hsync line 1 line 2 line 3 line 4 line n line 1 ld9 g3[0,0] g3[0,1] g3[0,2] ld8 g2[0,0] g2[0,1] g2[0,2] ld7 g1[0,0] g1[0,1] g1[0,2] ld6 g0[0,0] g0[0,1] g0[0,2] ld5 b4[0,0] b4[0,1] b4[0,2] oe r1[0,m-1] r0[0,m-1] g5[0,m-1] g4[0,m-1] g3[0,m-1] g2[0,m-1] g1[0,m-1] g0[0,m-1] b4[0,m-1] r1[0,m-2] r0[0,m-2] g5[0,m-2] g4[0,m-2] g3[0,m-2] g2[0,m-2] g1[0,m-2] g0[0,m-2] b4[0,m-2] r1[0,239] r1[0,238] r0[0,239] r0[0,238] b4[0,239] b4[0,238] g0[0,239] g0[0,238] g1[0,239] g1[0,238] g2[0,239] g2[0,238] g3[0,239] g3[0,238] g4[0,239] g4[0,238] g5[0,239] g5[0,238] ld17 r4[0,0] r4[0,1] r4[0,2] ld16 r3[0,0] r3[0,1] r3[0,2] ld15 r2[0,0] r2[0,1] r2[0,2] r4[0,m-1] r3[0,m-1] r2[0,m-1] r4[0,m-2] r3[0,m-2] r2[0,m-2] r4[0,239] r4[0,238] r3[0,239] r3[0,238] r2[0,239] r2[0,238] ld4 b3[0,0] b3[0,1] b3[0,2] ld3 b2[0,0] b2[0,1] b2[0,2] ld2 b1[0,0] b1[0,1] b1[0,2] ld1 b0[0,0] b0[0,1] b0[0,2] b3[0,m-1] b2[0,m-1] b1[0,m-1] b0[0,m-1] b3[0,m-2] b2[0,m-2] b1[0,m-2] b0[0,m-2] b0[0,239] b0[0,238] b1[0,239] b1[0,238] b2[0,239] b2[0,238] b3[0,239] b3[0,238] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-16 freescale semiconductor 4. oe functions as an output enable signal to the crt. this output enable signal is similar to blanking output in a crt and enables the data to be shifte d onto the display. when disabled, data is invalid and the trace is off. figure 43-17. lcdc interface 18-bit timing for active matrix color panels in 4-bit and 8-bit mode, ld [17:12] bits define red, ld [11:6] bits define green and ld [5:0] bits define blue. in 12-bit mode, ld[17:14] bits define red, ld[11: 8] bits define green and ld[5:2] bits define blue. in 16-bit mode, ld [17:13] bits define red, ld [11:6] bits define green and ld [5:1] bits define blue. the actual tft color channel assignments are shown in table 43-4 . the unused bits are fixed at 0. lsclk 123 m m-1 239 240 vsync line 1 line 2 line 3 line 4 line n line 1 oe ld12 r0[0,0] r0[0,1] r0[0,2] ld11 g5[0,0] g5[0,1] g5[0,2] ld10 g4[0,0] g4[0,1] g4[0,2] ld9 g3[0,0] g3[0,1] g3[0,2] hsync ld8 g2[0,0] g2[0,1] g2[0,2] ld7 g1[0,0] g1[0,1] g1[0,2] ld6 g0[0,0] g0[0,1] g0[0,2] ld5 b5[0,0] b5[0,1] b5[0,2] ld4 b4[0,0] b4[0,1] b4[0,2] r0[0,m-1] g5[0,m-1] g4[0,m-1] g3[0,m-1] g2[0,m-1] g1[0,m-1] g0[0,m-1] b5[0,m-1] b4[0,m-1] r0[0,m-2] g5[0,m-2] g4[0,m-2] g3[0,m-2] g2[0,m-2] g1[0,m-2] g0[0,m-2] b5[0,m-2] b4[0,m-2] r0[0,239] r0[0,238] g5[0,239] g5[0,238] b4[0,239] b4[0,238] b5[0,239] b5[0,238] g0[0,239] g0[0,238] g1[0,239] g1[0,238] g2[0,239] g2[0,238] g3[0,239] g3[0,238] g4[0,239] g4[0,238] ld15 r3[0,0] r3[0,1] r3[0,2] ld14 r2[0,0] r2[0,1] r2[0,2] ld13 r1[0,0] r1[0,1] r1[0,2] r3[0,m-1] r2[0,m-1] r1[0,m-1] r3[0,m-2] r2[0,m-2] r1[0,m-2] r3[0,239] r3[0,238] r2[0,239] r2[0,238] r1[0,239] r1[0,238] ld3 b3[0,0] b3[0,1] b3[0,2] ld2 b2[0,0] b2[0,1] b2[0,2] ld1 b1[0,0] b1[0,1] b1[0,2] ld0 b0[0,0] b0[0,1] b0[0,2] b3[0,m-1] b2[0,m-1] b1[0,m-1] b0[0,m-1] b3[0,m-2] b2[0,m-2] b1[0,m-2] b0[0,m-2] b0[0,239] b0[0,238] b1[0,239] b1[0,238] b2[0,239] b2[0,238] b3[0,239] b3[0,238] ld17 r5[0,0] r5[0,1] r[50,2] ld16 r4[0,0] r4[0,1] r4[0,2] r5[0,m-1] r4[0,m-1] r5[0,m-2] r4[0,m-2] r5[0,239] r5[0,238] r4[0,239] r4[0,238] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-17 note1: data output at clock 3*n +1. note2: data output at clock 3*n + 2. note3: data output at clock 3*n +3. figure 43-18. lcdc interface 24-bpp timing for aus mode table 43-4. tft color channel assignments ld 17 ld 16 ld 15 ld 14 ld 13 ld 12 ld 11 ld 10 ld 9 ld 8 ld 7 ld 6 ld 5 ld 4 ld 3 ld 2 ld 1 ld 0 4 bpp r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 8 bpp r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 12 bpp r3 r2 r1 r0 ? ? g3 g2 g1 g0 ? ? b3 b2 b1 b0 ? ? 16 bpp r4 r3 r2 r1 r0 ? g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 ? 18 bpp r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 16 bpp (for aus mode only) ??????????r4r3r2r1r0r4r3 r2 1 ??????????g5g4g3g2g1g0g5 g4 2 ??????????b4b3b2b1b0b4b3 b2 3 24 bpp (for aus mode only) ??????????r7r6r5r4r3r2r1 r0 1 ??????????g7g6g5g4g3g2g1 g0 2 ??????????b7b6b5b4b3b2b1 b0 3 lsclk 1 2 3 960 959 239 240 hsync vsync hsync line 1 line 2 line 3 line 4 line n line 1 ld7 r7[0,0] g7[0,0] b7[0,0] ld6 r6[0,0] g6[0,0] b6[0,0] ld5 r5[0,0] g5[0,0] b5[0,0] ld4 r4[0,0] g4[0,0] b4[0,0] b7[0,239] b6[0,239] b5[0,239] b4[0,239] g7[0,239] g6[0,239] g5[0,239] g4[0,239] b4[0,79] g4[0,79] b5[0,79] g5[0,79] b6[0,79] g6[0,79] b7[0,79] g7[0,79] ld3 r3[0,0] g3[0,0] b3[0,0] ld2 r2[0,0] g2[0,0] b2[0,0] ld1 r1[0,0] g1[0,0] b1[0,0] ld0 r0[0,0] g0[0,0] b0[0,0] b3[0,239] b2[0,239] b1[0,239] b0[0,239] g3[0,239] g2[0,239] g1[0,239] g0[0,239] b0[0,79] g0[0,79] b1[0,79] g1[0,79] b2[0,79] g2[0,79] b3[0,79] g3[0,79] liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-18 freescale semiconductor figure 43-19. lcdc interface 16-bpp timing for aus mode 43.2.10.2 active panel interface timing figure 43-20 shows horizontal timing (timing of one line), including both horizontal sync pulse and data. the width of hsync and delays, both before and after hsync are programma ble. the timing signal parameters are defined as follows: ? h_width defines the width of hsync pulse and must be at least 1. ? h_wait_2 defines the delay from end of hsync to the beginning of the oe pulse. ? h_wait_1 defines the delay from end of oe to the beginning of the hsync pulse. ? xmax defines the (total) number of pixels per line. figure 43-20. horizontal sync pulse timing in tft mode note: all parameters are defined in pixel periods, not lsclk periods. lsclk 1 2 3 960 959 239 240 hsync vsync hsync line 1 line 2 line 3 line 4 line n line 1 ld7 r4[0,0] g5[0,0] b4[0,0] ld6 r3[0,0] g4[0,0] b3[0,0] ld5 r2[0,0] g3[0,0] b2[0,0] ld4 r1[0,0] g2[0,0] b1[0,0] b4[0,239] b3[0,239] b2[0,239] b1[0,239] g5[0,239] g4[0,239] g3[0,239] g2[0,239] b1[0,79] g2[0,79] b2[0,79] g3[0,79] b3[0,79] g4[0,79] b4[0,79] g5[0,79] ld3 r0[0,0] g1[0,0] b0[0,0] ld2 r4[0,0] g0[0,0] b4[0,0] ld1 r3[0,0] g5[0,0] b3[0,0] ld0 r2[0,0] g4[0,0] b2[0,0] b0[0,239] b4[0,239] b3[0,239] b2[0,239] g1[0,239] g0[0,239] g5[0,239] g4[0,239] b2[0,79] g4[0,79] b3[0,79] g5[0,79] b4[0,79] g0[0,79] b0[0,79] g1[0,79] hsync oe data lsclk h_width+1 h_wait_2+3 xmax vsync h_wait_1+1 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-19 figure 43-21 shows vertical timing (timing of one frame). the delay from end of one frame until the beginning of the next is programmable. the memory timing signal parameters are: ? v_wait_1 is a delay measured in lines. for v_wait_1 = 1 there is a delay of one hsync (time = one line period) before vsync. hsync pul se is output during the v_wait_1 delay. ? for v_width (vertical sync pulse width) = 0, vsync encloses one hsync pulse. for v_width = 2, vsync encloses two hsync pulses. ? v_wait_2 is a delay measured in lines. for v_wait_2 = 1, there is a delay of one hsync (time = one line period) after vsync . the hsync pulse is output during the v_wait_2 delay. figure 43-21. vertical sync pulse timing tft mode 43.3 memory map and register definitions the lcdc memory space contains 21 32-bit registers fo r display parameters, a read-only status register, and two 256 18 color mapping rams?one for the graphic window and the other for the background plane. the color mapping rams are physically located inside the palette lookup table module. table 43-5 summarizes these registers and their addresses. the lcdc only supports word access. byte and halfword access is undefined. table 43-5. lcdc memory map address register access reset value section/page 0x1002_1000 (lssar) lcdc screen start address register r/w 0x0000_0000 43.3.2/43-24 0x1002_1004 (lsr) lcdc size register r/w 0x0000_0000 43.3.3/43-24 0x1002_1008 (lvpwr) lcdc virtual page width register r/w 0x0000_0000 43.3.4/43-25 0x1002_100c (lcpr) lcdc cursor position register r/w 0x0000_0000 43.3.5/43-26 0x1002_1010 (lcwhb) lcdc cursor width height and blink register r/w 0x0101_ffff 43.3.6/43-27 0x1002_1014 (lccmr) lcdc color cursor mapping register r/w 0x0000_0000 43.3.7/43-28 0x1002_1018 (lpcr) lcdc panel configuration register r/w 0x0000_0000 43.3.8/43-29 0x1002_101c (lhcr) lcdc horizontal configuration register r/w 0x0000_0000 43.3.9/43-31 0x1002_1020 (lvcr) lcdc vertical configuration register r/w 0x0400_0000 43.3.10/43-32 0x1002_1024 (lpor) lcdc panning offset register r/w 0x0000_0000 43.3.11/43-33 0x1002_1028 (lscr) lcdc sharp configuration register r/w 0x400c_0373 43.3.12/43-34 v_wait_2 vsync hsync oe v_wait_1 v_width ymax (lines) end of frame beginning of frame liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-20 freescale semiconductor 43.3.1 register summary figure 43-22 shows the key to the register fields, and table 43-6 shows the register figure conventions. 0x1002_102c (lpccr) lcdc pwm contrast control register r/w 0x0000_0000 43.3.13/43-36 0x1002_1030 (ldcr) lcdc dma control register r/w 0x8004_0060 43.3.14/43-37 0x1002_1034 (lrmcr) lcdc refresh mode control register r/w 0x0000_0000 43.3.15/43-38 0x1002_1038 (licr) lcdc interrupt configuration register r/w 0x0000_0000 43.3.16/43-39 0x1002_103c (lier) lcdc interrupt enable register r/w 0x0000_0000 43.3.17/43-40 0x1002_1040 (lisr) lcdc interrupt status register read 0x0000_0000 43.3.18/43-41 0x1002_1050 (lgwsar) lcdc graphic window start address register r/w 0x0000_0000 43.3.19/43-43 0x1002_1058 (lgwvpwr) lcdc graphic window size register r/w 0x0000_0000 43.3.20/43-43 0x1002_1058 (lgwvpwr) lcdc graphic window virtual page width register r/w 0x0000_0000 43.3.21/43-44 0x1002_105c (lgwpor) lcdc graphic window panning offset register r/w 0x0000_0000 43.3.22/43-44 0x1002_1060 (lgwpr) lcdc graphic window position register r/w 0x0000_0000 43.3.23/43-45 0x1002_1064 (lgwcr) lcdc graphic window control register r/w 0x0000_0000 43.3.24/43-46 0x1002_1068 (lgwdcr) lcdc graphic window dma control register 0x8004_0060 43.3.25/43-47 0x1002_1080 (lauscr) lcdc aus mode control register r/w 0x0000_0000 43.3.26/43-48 0x1002_1084 (lausccr) lcdc aus mode cursor control register r/w 0x0000_0000 43.3.27/43-49 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 43-22. key to register fields table 43-6. register figure conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. table 43-5. lcdc memory map (continued) address register access reset value section/page liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-21 table 43-7 provides an overview of the fields for all of the registers. rw standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 43-7. lcdc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1002_1000 (lssar) screen start address high ? ssa h screen start address low ? ssa l 0x1002_1004 (lsr) 000 bus size 0 0 screen width ? xmax screen height ? ymax 0x1002_1008 (lvpwr) virtual page width ? vpw 0x1002_100c (lcpr) cc op cursor x position ? cxp cursor y position ? cyp 0x1002_1010 (lcwhb) bk_e n cursor width ? cw cursor height ? ch bd 0x1002_1014 (lccmr) cur_col_r[ 5:4] cursor red ? cur_col_r[3:0] cursor green ? cur_col_g cursor blue ? cur_col_b table 43-6. register figure conventions (continued) convention description liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-22 freescale semiconductor 0x1002_1018 (lpcr) tft colo r bus width pbsiz bits per pixel bpix pi x po l flm pol lp pol cl k po l oe po l scl k idl e end _se l end_ byte _sw ap rev _vs acd sel crystal direction toggle ? acd scl k sel shar p pixel clock divider ? pcd 0x1002_101c (lhcr) horizontal sync width ? h_width horizontal wait 1 ? h_wait_1 horizontal wait 2 ? h_wait_2 0x1002_1020 (lvcr) vertical sync width ? v_width vertical wait 1 ? v_wait_1 vertical wait 2 ? v_wait_2 0x1002_1024 (lpor) 0 0 0000000 0 0 panning offset ? pos 0x1002_1028 (lscr) ps_rise_delay cls_rise_delay rev_toggle_del ay gray 2 gray 1 0x1002_102c (lpccr) 0 000 cls high width ld msk scr cc _e n pulse width ? pw 0x1002_1030 (ldcr) burs t 0 0 0 0 0 0 0 0 dma high mark ? hm dma trigger mark ? tm 0x1002_1034 (lrmcr) 0 0 0 0 0 0 000 0 000 0 0 self _ref 0x1002_1038 (licr) 0 0 0000000 0 0 0 0 g w_ in t_ co n int syn int con 0x1002_103c (lier) 0 0 000000 gw _ud r_e rr_ en gw_e rr_r es_e n gw _e of _e n g w_ bo f_ en udr _er r_e n err _re s_e n eof_ en bof_e n table 43-7. lcdc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-23 0x1002_1040 (lisr) 0 0 000000 gw _ud r_e rr gw_e rr_r es gw _e of g w_ bo f udr _er r err _re s eof bof 0x1002_1050 (lgwsar) graphic window start address high ? gwsa h graphic window start address low ? gwsa l 0x1002_1054 (lgwsr) 0 0 0 0 0 0 graphic window width ? gww graphic window height ? gwh 0x1002_1058 (lgwvpwr) 0 0 0000 graphic window virtual page width ? gwvpw 0x1002_105c (lgwpor) 0 0 0000000 0 0 graphic window panning offset ? gwpo 0x1002_1060 (lgwpr) 0 0 0 0 0 0 graphic window x position ? gwxp graphic window y position ? gwyp 0x1002_1064 (lgwcr) graphic window alpha value ? gwav gw cke gwe gw _r vs graphic window color key red ? gwckr[5:4] graphic window color key red ? gwckr[3:0] graphic window color key green ? gwckg graphic window color key blue ? gwckb 0x1002_1068 (lgwdcr) gwbt 0 0 0 0 0 0 0 0 graphic window high mark ? gwhm graphic window low mark ? gwlm 0x1002_1080 (lauscr) aus mode graphic window color key red ? agwckr[7:0] (aus mode only) graphic window color key green ? agwckg[7:0] (aus mode only) graphic window color key blue ? agwckb[3:0] (aus mode only) 0x1002_1084 (lausccr) cursor red ? acur_col_r [7:0] (aus mode only) cursor green ? acur_col_g [7:0] (aus mode only) cursor blue? acur_col_b [7:0] (aus mode only) 0x1002 1800 ? 0x1002 1bfc (bplut) (r[5:4]) first ram location of background plane lut (r [3:0], g [5:0], b [5:0]) (r[5:4]) last ram location of background plane lut (r [3:0], g [5:0], b [5:0]) table 43-7. lcdc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-24 freescale semiconductor 43.3.2 lcdc screen start address register (lssar) the lssar specifies the lcd screen start address. see figure 43-23 for bit assignments and table 43-8 for field descriptions. 43.3.3 lcdc size register (lsr) the lsr defines the height and width of the lcd screen. see figure 43-24 for bit assignments and table 43-9 for field descriptions. 0x1002 1c00 ? 0x1002 1ffc (gwlut) first ram location of graphic window lut (r[3:0], g[5:0], b[5:0]) (r[5:4]) last ram location of graphic window lut (r[3:0], g[5:0], b[5:0]) 0x1002_1000 (lssar) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ssa[31:16] w reset0000000000000000 1514131211109876543210 r ssa[15:2] 00 w reset0000000000000000 figure 43-23. lcdc screen start address register (lssar) table 43-8. screen start address register field description field description 31?2 ssa screen start address of lcd panel. holds pixel data for a new frame from ssa address. this field must start at a location that enables a complete picture to be stored in a 4 mbyte memory boundary (a [21:0]). a [31:22] has a fixed value for a picture?s image. 1?0 reserved. these bits are reserved and should read 0. table 43-7. lcdc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-25 43.3.4 lcdc virtual page width register (lvpwr) the lvpwr defines virtual page width for lcd panel. see figure 43-25 for bit assignments and table 43-10 for field descriptions. 0x1002_1004 (lsr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 0 bus size 00 xmax 0000 w reset0000000000000000 1514131211109876543210 r000000 ymax w reset0000000000000000 figure 43-24. lcdc size register (lsr) table 43-9. lcdc size register field descriptions field description 31?29 reserved. these bits are reserved and should read 0. 28 bus size bus size. determine lcdc bus size. 0 ahb bus of lcdc is 64-bit 1 ahb bus of lcdc is 32-bit. 25?20 xmax screen width divided by 16. holds screen x-axis size, divided by 16. for black-and-white panels (1 bpp), xmax [20] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line. 19?10 reserved. these bits are reserved and should read 0. 9?0 ymax screen height. specifies the height of lcd panel in terms of pixels or lines. lines are numbered from 1 to ymax for a total of ymax lines. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-26 freescale semiconductor 43.3.5 lcdc cursor position register (lcpr) lcpr is used to determine the starting position of the cursor on the lcd panel. figure 43-26 shows the register; table 43-11 provides its field descriptions. 0x1002_1008 (lvpwr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000 vpw w reset0000000000000000 figure 43-25. lcdc virtual page width register (lvpwr) table 43-10. lcdc virtual page width register field descriptions field description 31?10 reserved. these bits are reserved and should read 0. 9?0 vpw virtual page width. defines virtual page width of lcd panel. vpw bits represent the number of 32-bit words required to hold the data for one virtual line. vpw is used in calculating the starting address representing the beginning of each displayed line. 0x1002_100c (lcpr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r cc 0 op 00 cxp w reset0000000000000000 1514131211109876543210 r000000 cyp w reset0000000000000000 figure 43-26. lcdc cursor position register (lcpr) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-27 43.3.6 lcdc cursor width height and blink register (lcwhb) lcwhb is used to determine the cursor?s width and height, and how it blinks. figure 43-27 shows the register; table 43-12 provides its field descriptions. table 43-11. lcdc cursor position register field descriptions field description 31?30 cc cursor control. controls the cursor format and the type of arithmetic operations. when op = 0 00 transparent, cursor is disabled 01 1 for non-color displays; color defined in lcdc color cursor mapping register for color displays 10 reversed, inv background for non-color displays; inv color defined in lcdc color cursor mapping register for color displays 11 0 for non-color displays; and between background and cursor for color displays when op = 1, for color mode only 00 transparent, cursor is disabled 01 or between background and cursor 10 xor between background and cursor 11 and between background and cursor 29 reserved. this bit is reserved and should read 0. 28 op arithmetic operation control. enables/disables arithmetic operations between the background and cursor. 0 = disable arithmetic operation 1 = enable arithmetic operation 27?26 reserved. these bits are reserved and should read 0. 25?16 cxp cursor x position. represents the cursor?s horizontal starting position x in pixel count (from 0 to xmax). 15?10 reserved. these bits are reserved and should read 0. 9?0 cyp cursor y position. represents the cursor?s vertical starting position y in pixel count (from 0 to ymax). 0x1002_1010 (lcwhb) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r bk_e n 00 cw 000 ch w reset0000000100000001 1514131211109876543210 r00000000 bd w reset0000000011111111 figure 43-27. lcdc cursor width height and blink register (lcwhb) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-28 freescale semiconductor 43.3.7 lcdc color cursor mapping register (lccmr) lccmr defines the cursor color in passive or tft color modes. if bpp mode setting is smaller than 18bpp, cursor color component bits should be put in the ms bs. for example, if color cursor of rgb=(0x1a, 0x26, 0x05) is wanted, cur_col_r, cur_col_g and cur_col_b should be set to 0x34, 0x26 and 0x0a. figure 43-28 shows the register; table 43-13 provides its field descriptions. table 43-12. lcdc cursor width height and blink register field descriptions field description 31 bk_en blink enable. determines whether the blink enable cursor will blink or remain steady. 0 blink is disabled 1 blink is enabled 30?29 reserved. these bits are reserved and should read 0. 28?24 cw cursor width. specifies the width of hardware cursor in pixels. this field can be any value between 1 and 31 (setting this field to zero disables the cursor) 23?21 reserved. these bits are reserved and should read 0. 20?16 ch cursor height. specifies the height of hardware cursor in pixels. this field can be any value between 1 and 31 (setting this field to zero disables the cursor) 15?8 reserved. these bits are reserved and should read 0. 7?0 bd blink divisor. sets the cursor blink rate. a 32 hz clock from rtc is used to clock the 8-bit up counter. when the counter value equals bd, the cursor toggles on/off. hence larger the bd, slower the cursor will blink. the faster cursor blinking rate is when bd is 0. 0x1002_1014 (lccmr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000000 cur_col_r w reset0000000000000000 1514131211109876543210 r cur_col_r cur_col_g cur_col_b w reset0000000000000000 figure 43-28. lcdc color cursor mapping register (lccmr) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-29 43.3.8 lcdc panel configuration register (lpcr) the lpcr defines all properties of the lcd screen. see figure 43-29 for bit assignments and table 43-14 for field descriptions. table 43-13. lcdc color cursor ma pping register field descriptions field description 31?18 reserved. these bits are reserved and should read 0. 17?12 cur_col_r cursor red field. defines the red component of the cursor color in color mode. 000000 = no red ? 111111 = full red 11?6 cur_col_g cursor green field. defines the green component of the cursor color in color mode. 000000 = no green ? 111111 = full green 5?0 cur_col_b cursor blue field. defines the blue component of the cursor color in color mode. 000000 = no blue ? 111111 = full blue 0x1002_1018 (lpcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tft col or pbsiz bpix pix pol flm pol lp pol clk pol oe pol sclk idle end_ sel swa p_ sel rev_ vs w reset0000000000000000 1514131211109876543210 r acd sel acd sclk sel shar p pcd w reset0000000000000000 figure 43-29. lcdc panel configuration register (lpcr) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-30 freescale semiconductor table 43-14. lcdc panel configuration register field descriptions field description 31 tft interfaces to tft display. controls the format and timing of output control signals. active and passive displays use different signal timing formats as described in section 43.2.9, ?panel interface signals and timing .? tft also controls the use of frc in color mode. 0 lcd panel is a passive display 1 lcd panel is an active display: ?digital crt? signal format, frc is bypassed. 0 0 monochrome 01 cstn 10 ? 1 1 tft 30 color interfaces to color display. activates 3 channels of frc in passive mode to allow the use of special 2 2/3 pixels per output vector format. 0 lcd panel is a monochrome display. 1 lcd panel is a color display. 0 0 monochrome 01 cstn 10 ? 1 1 tft 29?28 pbsiz panel bus width. specifies the panel bus width. applicable for monochrome monitors. for passive color panels, only 8-bit panel bus width is supported. 00 1-bit 10 4-bit 11 8-bit 27?25 bpix bits per pixel. indicates the number of bits per pixel in memory. 000 1 bpp, frc bypassed 001 2 bpp 010 4 bpp 011 8 bpp 100 12 bpp (16-bits of memory used) 101 16 bpp 110 18bpp (32-bits of memory used) 111 reserved note: to set normal 18bpp mode: bpix = 110, end_sel = 0 and swap_sel = x (don?t care) to set microsoft pal_bgr 18bpp mode: bpix = 110, end_sel = 1 and swap_sel = 1 24 pixpol pixel polarity. sets the pixels polarity. 0 active high 1 active low 23 flmpol first line marker polarity. sets the polarity of first line marker symbol. 0 active high 1 active low 22 lppol line pulse polarity. sets the polarity of line pulse signal. 0 active high 1 active low 21 clkpol lcd shift clock polarity. sets the polarity of active edge of lcd shift clock. 0 active negative edge of lsclk (in tft mode, active on positive edge of lsclk) 1 active positive edge of lsclk (in tft mode, active on negative edge of lsclk) 20 oepol output enable polarity. sets the output enable signal polarity. 0 active high 1 active low liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-31 43.3.9 lcdc horizontal configuration register (lhcr) lhcr defines the horizontal sync pulse timing. for detailed settings, refer to the i.mx27 multimedia applications processor data sheet . figure 43-30 shows the register; table 43-15 provides its field descriptions. 19 sclkidle lsclk idle enable. enables/disables lsclk when vsync is idle in tft mode. 0 disable lsclk 1 enable lsclk 18 end_sel endian select. selects the image download into memory as big or little endian format. 0 little endian 1 big endian 17 swap_sel swap select. lcdc operates in big endian mode internally. swap select controls the swap of data before operation in little endian mode. 0 16 bpp, 12 bpp mode 1 8 bpp, 4 bpp, 2 bpp, 1 bpp mode note: when swap_sel = 0, byte 3 (bits 31?24), byte 2 (bits 23?16), byte 1 (bits 15?8), byte 0 (bits 7?0) data swapped to byte 1, byte 0, byte 3 and byte 2 respectively. when swap_sel = 1, byte 3, byte 2, byte 1, byte 0 data swapped to byte 0, byte 1, byte 2 and byte 3 respectively. 16 rev_vs reverse vertical scan. selects the vertical scan direction as normal or reverse image flips along the x-axis). ssa register must be changed accordingly. 0 vertical scan in normal direction 1 vertical scan in reverse direction 15 acdsel acd clock source select. selects the clock source used by alternative crystal direction counter. 0 use frm as clock source for acd count 1 use lp/hsyn as clock source for acd count 14?8 acd alternate crystal direction. toggles acd signal once every 1?16 flm cycles based on the value specified in this field. the actual number of flm cycles between toggles is the programmed value plus one. for active mode (tft=1), this parameter is not used. 7 sclksel lsclk select. selects whether to enable or disable lsclk in tft mode when there is no data output. 0 disable oe and lsclk in tft mode when no data output 1 always enable lsclk in tft mode even if there is no data output 6 sharp sharp panel enable. enables/disables signals for sharp hr-tft 240 x 320 panels. 0 disable sharp signals 1 enable sharp signals 5?0 pcd pixel clock divider. holds clock divider value. lcdc_clk (perclk3) is divided by n (pcd plus one) to yield the pixel clock rate. values of 1 to 63 yield n=2 to 64. pixel clock rate is faster than lsclk by a factor equal to the data bus width for monochrome display. for all other displays, pixel clock rate is the same as lsclk. pcd value must be set such that lsclk frequency is at least one third or one fourth of hclk frequency in tft and cstn modes respectively, otherwise ld will be incorrect. table 43-14. lcdc panel configuration re gister field descriptions (continued) field description liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-32 freescale semiconductor 43.3.10 lcdc vertical configuration register (lvcr) lvcr defines the vertical sync pulse timing. for detailed settings, refer to the i.mx27 multimedia applications processor data sheet . figure 43-31 shows the register; table 43-16 provides its field descriptions. 0x1002_101c (lhcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r h_width 0000000000 w reset0000010000000000 1514131211109876543210 r h_wait_1 h_wait_2 w reset0000000000000000 figure 43-30. lcdc horizontal configuration register (lhcr) table 43-15. lcdc horizontal configur ation register field description field description 31?26 h_width horizontal sync pulse width. specifies number of sclk periods for which hsync is activated. the active time is equal to (h_width + 1) of the sclk periods. 25?16 reserved. these bits are reserved and should read 0. 15?8 h_wait_1 wait between oe and hsync. in tft mode, it specifies the number of sclk periods between the end of oe signal and the beginning of hsync. total delay time equals (h_wait_1 + 1) of sclk periods. in cstn mode, it specifies the number of sclk periods between the last display data and the beginning of hsync signal. total delay time equals (h_wait_1 + 1) of sclk periods. 7?0 h_wait_2 wait between hsync and start of next line. in tft mode, it specifies the number of sclk periods between the end of hsync and the beginning of oe signal. total delay time equals (h_wait_2 + 3). in cstn mode, it specifies the number of sclk periods between the end of hsync and the first display data in each line. total delay time equals (h_wait_2 + 2) of sclk periods. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-33 43.3.11 lcdc panning offset register (lpor) the lcdc panning offset register (lpor) sets up panning for the image. figure 43-32 shows the register; table 43-17 provides its field descriptions. 0x1002_1020 (lvcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r v_width 0000000000 w reset0000010000000000 1514131211109876543210 r v_wait_1 v_wait_2 w reset0000000000000000 figure 43-31. lcdc vertical c onfiguration register (lvcr) table 43-16. lcdc vertical configuration register field descriptions field description 31?26 v_width vertical sync pulse width. specifies the width, in lines, of vsync pulse for active mode (tft =1). for a value of ?000001?, vertical sync pulse encompasses one hsync pulse. for a value of ?000002?, vertical sync pulse encompasses two hsync pulses, and so on. for passive mode (tft=0) and non-color mode, see figure 43-14 . 25?16 reserved. these bits are reserved and should read 0. 15?8 v_wait_1 wait between frames 1. defines the delay, in lines, between the end of oe pulse and the beginning of vsync pulse for active mode (tft=1). this field has no meaning in passive non-color mode. the actual delay is (v_wait_1). in passive color mode, this field is the delay, measured in virtual clock periods, between the last line of the frame to the beginning of next frame. 7?0 v_wait_2 wait between frames 2. defines the delay, in lines, between the end of vsync pulse and the beginning of oe pulse of the first line in active mode (tft=1). the actual delay is v_wait_2 ) lines. set this field to zero for passive non-color mode. the minimum value of this field is 0x01. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-34 freescale semiconductor 43.3.12 lcdc sharp configuration register (lscr) for 2 bpp modes, full black and full white are th e two predefined display levels. the other two intermediate gray-scale shading densities can be adjusted within the lscr. lscr also controls the relative delay timing of cls, rev and ps. for detail sharp panel settings, refer to the i.mx27 multimedia applications processor data sheet . a tft timing diagram that shows the relationship between these signals is shown in the figure 43-34 . 0x1002_1024 (lpor) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000000000 pos w reset0000000000000000 figure 43-32. lcdc panning offset register (lpor) table 43-17. lcdc panning offset register field descriptions field description 31?5 reserved. these bits are reserved and should read 0. 4?0 pos panning offset. defines the number of bits that the data from memory is panned to the left before processing. pos is read by the lcdc once at the beginning of each frame. for example, in 4bpp mode, setting pos = 16 shifts 16-bits, which means panning the image by 4 pixels left. note: shifting data more than 32 bits should use lssar register setting. 18 bpp panning should use lssar register setting. to achieve panning of the final image by n bits: bits per pixel pos effective # of pixels panned on image 1n n 22n n 44n n 88n n 12/16 16n n liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-35 0x1002_1028 (lscr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ps_rise_delay 00 cls_rise_delay w reset0100000000001100 1514131211109876543210 r0 0 0 0 rev_toggle_delay gray 2 gray 1 w reset0000001101110011 figure 43-33. lcdc sharp confi guration register (lscr) table 43-18. lcdc sharp configuration register field descriptions field description ps_rise_delay 31?26 ps rise delay. controls the rising edge delay of ps relative to the falling edge of cls. total delay time equals to ps_rise_delay sclk periods. 00000 0 lsclk period 00001 1 lsclk period ? 11111 63 lsclk periods 25?24 reserved. these bits are reserved and should read 0. cls_rise_delay 23?16 cls rise delay. controls the rising edge delay of cls relative to the last ld of the line. total delay time equals to (cls_rise_delay + 1) sclk periods. 00000000 10 lsclk periods 00000001 2 lsclk period ? 11111111 256 lscclk periods 15?12 reserved. these bits are reserved and should read 0. rev_toggle_delay 11?8 rev toggle delay. controls the transition delay of rev relative to the last ld of the line. total delay time equals to (rev_toggle_delay + 1) sclk periods. 0000 1 lsclk period 0001 2 lsclk period ? 1111 16 lsclk periods gray 2 7?4 gray-scale 2. represents one of the two gray-scale shading densities. this field is programmable to any value between 0 and 16 (0 and 16 are already defined as two of the four colors) gray 1 3?0 gray-scale 1. represents the other gray-scale shading density. this field is programmable to any value between 0 and 16 (0 and 16 are already defined as two of the four colors) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-36 freescale semiconductor figure 43-34. horizontal timing in device_number 43.3.13 lcdc pwm contrast control register (lpccr) lpccr is used to control the signal output at the cont rast pin, which controls contrast of the lcd panel. 0x1002_102c (lpccr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 000000 cls_hi_width w reset0 000000 0 00000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ldmsk 0000 scr cc_en pw w reset0 000000 0 00000000 figure 43-35. lcdc pwm contrast control register (lpccr) d1 d2 lsclk r0?r5 g0?g5 b0?b5 spl spr lp cls ps rev hwait1 + 1 rev_tog_delay +1 hwait2+4 hwait1+1 cls_rise_delay + 1 xmax ps_rise_delay 1 sclk cls_hi_width + 1 rev_tog_delay +1 d320 d320 falling edge of ps aligns with rising edge of cls the rising edge delay of ps is programmed by ps_rise_delay cls_hi_width is equal to pwm_scr0 256 + pwm_width in units of lsclk. 256 + pwm_width in units of lsclk. spl/spr pulse width is fixed and aligned to the first data of the line. rev toggles every lp period. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-37 43.3.14 lcdc dma control register (ldcr) there is a 128 32 bit line buffer in the lcdc that stores dma data from system memory. ldcr controls dma burst length and when to trigger a dma burst in terms of number of data bytes left in the pixel buffer. table 43-19. lcdc pwm contrast control register field description field description 31?25 reserved. these bits are reserved and should read 0. 24?16 cls_hi_width cls high pulse width. controls the pulse width of cls in units of sclk. the actual pulse width = cls_hi_wdith +1. 15 ldmsk ld mask. enables/disables the ld output to zero for sharp tft panel power-off sequence. 0 ld [15:0] is normal 1 ld [15:0] always equals 0 14?11 reserved. these bits are reserved and should read 0. 10?9 scr source select. selects the input clock source for pwm counter. pwm output frequency is equal to the frequency of input clock divided by 256. 00 line pulse 01 pixel clock 10 lcd clock 11 reserved 8 cc_en contrast control enable. enables/disables the contrast control function. 0 contrast control is off 1 contrast control is on 7?0 pw pulse-width. controls the pulse-width of the built-in pwm, which controls the contrast of lcd screen. 0x1002_1030 (ldcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r burst 000000 0 0 hm w reset1 000000 0 0000010 0 1514131211109 8 7654321 0 r0 000000 0 0 tm w reset0 000000 0 0110000 0 figure 43-36. lcdc dma control register (ldcr) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-38 freescale semiconductor note the dynamic mode is recommend, and also the tm and hm reset value are recommend in the dynamic mode. the same recommendation is for the graphic dma control. 43.3.15 lcdc refresh mode control register (lrmcr) lrmcr is used to control the refresh characteristics. table 43-20. lcdc dma control register field descriptions field description 31 burst burst length. determines whether the burst length is fixed or dynamic. 0 burst length is dynamic 1 burst length is fixed 30?23 reserved. these bits are reserved and should read 0. 22?16 hm dma high mark. establishes the high mark for dma requests. for dynamic burst length, after dma request is made, data is loaded and pixel buffer continues to be filled until the number of empty words left in dma fifo is equal to the high mark minus 2. minimum hm setting in dynamic burst is 3. for fixed burst length, burst length (in words) of each request is equal to the dma high mark setting and its value must be larger than tm. 15?7 reserved. these bits are reserved and should read 0. 6?0 tm dma trigger mark. sets the low-level mark in the pixel buffer to trigger a dma request. the low-level mark equals the number of words left in the pixel buffer. 0x1002_1034 (lrmcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 000000 0 0000000 0 w reset0 000000 0 0000000 0 1514131211109 8 7654321 0 r0 000000 0 0000000 self_ref w reset0 000000 0 0000000 0 figure 43-37. lcdc refresh mode control register (lrmcr) table 43-21. lcdc refresh mode cont rol register field descriptions field description 31?1 reserved. these bits are reserved and should read 0. 0 self_ref self-refresh. enables/disables self-refresh mode. 0 disable self-refresh 1 enable self-refresh liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-39 note on entering self-refresh mode, lsclk and ld [17:0] signals stay low. hysn and vsyn operate normally. except for ssa, bglut and gwlut regi sters, all configurations must be performed before enabling the lcdc to avoid a malfunction. ssa must always match the address ra nge of the ram selected. if the user wants to switch between various type s of ram, lcdc must be disabled before switching. 43.3.16 lcdc interrupt configuration register (licr) licr is used to configure the interrupt conditions. 0x1002_1038 (licr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000 0 0000 w reset00000000000 0 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000000 gw_int_ con 0 int syn 0 int con w reset00000000000 0 0000 figure 43-38. lcdc interrupt conf iguration register (licr)) table 43-22. lcdc interrupt configuration register field descriptions field description 31?5 reserved. these bits are reserved and should read 0. 4 gw_int_con graphic window interrupt condition. determines if an interrupt condition is set at the beginning or end of graphic window condition. 0 interrupt flag is set when end of graphic window is reached 1 interrupt flag is set when beginning of graphic window is reached 3 reserved. this bit is reserved and should read 0. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-40 freescale semiconductor 43.3.17 lcdc interrupt enable register (lier) lier is used to enable the lcdc interrupt pin ge nerated to arm926ej-s interrupt controller (aitc). when interrupt is masked, lcdc will not generate the interrupt request to aitc, but its status can still be observed in the interrupt status register. 2 intsyn interrupt source. determines if an interrupt flag is set during last/first data of frame loading or on last/first data of frame output to the lcd panel. note: there is a latency between loading last/first data of the frame to output to the lcd panel. 0 interrupt flag is set on loading the last/first data of frame from memory 1 interrupt flag is set on output of the last/first data of frame to lcd panel 1 reserved. this bit is reserved and should read 0. 0 intcon interrupt condition. determines if an interrupt condition is set at the beginning or end of frame condition. 0 interrupt flag is set when the end of frame (eof) is reached. 1 interrupt flag is set when the beginning of frame (bof) is reached. 0x1002_103c (lier) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000000 gw_udr_err_en gw_err_res_en gw_eof_en gw_bof_en udr_ err_en err_ res_en eof_en bof_en w reset0000000000000000 figure 43-39. lcdc interrupt enable register (lier) table 43-22. lcdc interrupt configuration register field descriptions field description table 43-23. intsyn/intcon settings intsyn intcon description 0 0 interrupt flag is set on loading last data of frame from memory. 0 1 interrupt flag is set on loading first data of frame from memory. 1 0 interrupt flag is set on output of last data of frame to lcd panel. 1 1 interrupt flag is set on output of first data of frame to lcd panel. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-41 bit value meaning: 0 = mask interrupt, 1 = enable interrupt 43.3.18 lcdc interrupt status register (lisr) the read-only lisr indicates whether an interrupt has occurred or not. the status bit is set whenever the interrupt condition is met. if any bit in this register is set and the corresponding bit in lier is set, lcdc interrupt pin is asserted to aitc. the stat us bit is cleared by reading the register. table 43-24. lcdc interrupt enable register field description field description 31?8 reserved. these bits are reserved and should read 0. 7 gw_udr_err_en graphic window under run error interrupt enable. used to enable or mask the graphic window under-run error interrupt to aitc. 6 gw_err_res_en graphic window error response interrupt enable. used to enable or mask the graphic window error response interrupt to aitc. 5 gw_eof_en graphic window end of frame interrupt enable. used to enable or mask the graphic window end of frame interrupt to aitc. 4 gw_bof_en graphic window beginning of frame interrupt enable. used to enable or mask the graphic window beginning of frame interrupt to aitc. 3 udr_err_en under run error interrupt enable. used to enable or mask the background plane under-run error interrupt to aitc. 2 err_res_en error response interrupt enable. used to enable or mask the background plane error response interrupt to aitc. 1 eof_en end of frame interrupt enable. used to enable or mask the background plane end of frame interrupt to aitc. 0 bof_en beginning of frame interrupt enable. used to enable or mask the background plane beginning of frame interrupt to aitc. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-42 freescale semiconductor bit value meaning: 0 = interrupt has not occurred, 1 = interrupt has occurred 0x1002_1040 (lisr) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000 0 0000 w reset00000000000 0 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 00000000 gw_udr_err gw_err_res gw_eof gw_bof udr_ err err_ res eof bof w reset00000000000 0 0000 figure 43-40. lcdc interrupt status register (lisr) table 43-25. lcdc interrupt status register field descriptions field description 31?8 reserved. these bits are reserved and should read 0. 7 gw_udr_err graphic window under run error. indicates whether the lcdc fifo in graphic window plan has hit an under-run condition. this is when the data output rate is faster than the data input rate to the fifo of the graphic window plan. under-run can cause erroneous data output to ld. ld data output rate must be adjusted to prevent this error. 6 gw_err_res graphic window error response. indicates whether the lcdc has issued a read data request in graphic window and has received a response from the memory controller not equal to ?ok.? it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. 5 gw_eof graphic window end of frame. indicates whether the end of graphic window has reached. it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. 4 gw_bof graphic window beginning of frame. indicates whether the beginning of graphic window has reached. it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. 3 udr_err under run error. indicates whether the lcdc fifo has hit an under-run condition. this is when the data output rate is faster than the data input rate to the fifo. under-run can cause erroneous data output to ld. ld data output rate must be adjusted to prevent this error. 2 err_res error response. indicates whether the lcdc has issued a read data request and has received a response from the memory controller not equal to ?ok?. it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. 1 eof end of frame. indicates whether the end of frame has reached. it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. 0 bof beginning of frame. indicates whether the beginning of frame has reached. it is cleared by reading the status register, at power on reset, or when the lcdc is disabled. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-43 43.3.19 lcdc graphic window start address register (lgwsar) lgwsar defines the starting addre ss of the graphic window image. see figure 43-3 . 43.3.20 lcdc graphic window size register (lgwsr) lgwsr defines the height and width of the graphic window on the lcd screen. 0x1002_1050 (lgwsar) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gwsa w reset0000000000000000 1514131211109876543210 r gwsa 00 w reset0000000000000000 figure 43-41. lcdc graphic window start address register (lgwsar) table 43-26. lcdc graphic window start address register field descriptions field description 31?2 gwsa graphic window start address on lcd screen. holds the starting address of the graphic window picture. this field must start at a location that enables a complete graphic window picture to be stored in a 4mbyte memory boundary (a[21:0]). a[31:22] has a fixed value for the graphic window picture?s image. 1?0 reserved. these bits are reserved and should read 0. 0x1002_1054 (lgwsr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 gww 0000 w reset0000000000000000 1514131211109876543210 r000000 gwh w reset0000000000000000 figure 43-42. lcdc graphic window start address register (lgwsar) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-44 freescale semiconductor 43.3.21 lcdc graphic window virtual page width register (lgwvpwr) lgwvpwr defines the virtual page width for the graphic window picture on the lcd screen. see figure 43-3 . 43.3.22 lcdc graphic window panning offset register (lgwpor) lgwpor sets up panning for the image. table 43-27. lcdc graphic window size register field descriptions field description 31?26 reserved. these bits are reserved and should read 0. 25?20 gww graphic window width divided by 16. holds graphic window x-axis size divided by 16. for black-and-white panels (1 bpp), gw_xmax [20] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line. note: graphic window size cannot be set to 0. 19?10 reserved. these bits are reserved and should read 0. 9?0 gwh graphic window height. specifies height of the graphic window in terms of pixels or lines. the lines are numbered from 1 to gw_ymax for a total of gw_ymax lines. note: graphic window size cannot be set to 0. 0x1002_1058 (lgwvpwr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000 gwvpw w reset0000000000000000 figure 43-43. lcdc graphic window virtual page width register (lgwvpwr) table 43-28. lcdc graphic window virtual page width register field descriptions field description 31?10 reserved. these bits are reserved and should read 0. 9?0 gwvpw graphic window virtual page width. defines the virtual page width of the graphic window picture. vpw bits represent the number of 32-bit words required to hold the data for one virtual line. gwvpw is used in calculating the starting address representing the beginning of each line of the graphic window picture. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-45 43.3.23 lcdc graphic window position register (lgwpr) lgwpr is used to determine the starting pos ition of the graphic window on the lcd panel. 0x1002_105c (lgwpor) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000000000 gwpo w reset0000000000000000 figure 43-44. lcdc graphic window panning offset register (lgwpor) table 43-29. lcdc graphic window panning offset register field descriptions filed description 31?5 reserved. these bits are reserved and should read 0. 4?0 gwpo graphic window panning offset. defines the number of bits that the graphic window data from memory is panned to the left before processing. pos is read by the lcdc once at the beginning of each frame. for example, in 4 bpp mode, setting pos = 16 shifts 16 bits which means panning the image by 4 pixels left. note: shifting data more than 32 bits in graphic window should use lgwsar register setting. 18 bpp graphic window panning should use lgwsar register setting. to achieve panning of the final image by n bits: table 43-30. bits per pixel gwpo effective number of pixels panned 1n n 22n n 44n n 88n n 12/16 16n n liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-46 freescale semiconductor 43.3.24 lcdc graphic window control register (lgwcr) lgwcr defines the behavi ors of graphic window. 0x1002_1060 (lgwpr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000 gwxp w reset0000000000000000 1514131211109876543210 r000000 gwyp w reset0000000000000000 figure 43-45. lcdc graphic window position register (lgwpr) table 43-31. lcdc graphic window posi tion register field descriptions field description 31?26 reserved. these bits are reserved and should read 0. 25?16 gwxp graphic window x position. represents the graphic window?s horizontal starting position in pixel count (from 0 to xmax). 15?10 reserved. these bits are reserved and should read 0. 9?0 gwyp graphic window y position. represents the graphic window?s vertical starting position in line (from 0 to ymax). 0x1002_1064 (lgwcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gwav gwc ke gwe gw_ rvs 000 gwckr[5:4] w reset0000000000000000 1514131211109876543210 r gwckr[3:0] gwckg gwckb w reset0000000000000000 figure 43-46. lcdc graphic window control register (lgwcr) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-47 43.3.25 lcdc graphic window dma control register (lgwdcr) there is a 128 32 bit line buffer in the lcdc that stores graphic window data from system memory. lgwdce controls the dma burst length and when to tr igger a dma burst in terms of the number of data bytes left in the pixel buffer. table 43-32. lcdc graphic window control register field descriptions field description 31?24 gwav graphic window alpha value. defines the graphic window alpha value used for alpha blending between graphic window and background plane 0 graphic window totally transparent, that is, not displayed on lcd screen 1 graphic window totally opaque, that is, completely visible on lcd screen 23 gwcke graphic window color keying enable. enable/disable graphic window color keying. 0 disable color keying of graphic window 1 enable color keying of graphic window 22 gwe graphic window enable. enable/disable graphic window displayed on screen. 0 disable graphic window on screen 1 enable graphic window on screen 21 gw_rvs graphic window reverse vertical scan. selects the graphic window vertical scan direction as normal or reverse (graphic window image flips along the x-axis). lgwsar must be changed accordingly. 0 vertical scan in normal direction 1 vertical scan in reverse direction 20?18 reserved. these bits are reserved and should read 0. 17?12 gwckr graphic window color keying red component 000000 no red ? 111111 full red 11?6 gwckg graphic window color keying green component 000000 no green ? 111111 full green 5?0 gwckb graphic window color keying blue component 000000 no blue ? 111111 full blue liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-48 freescale semiconductor 43.3.26 lcdc aus mode control register (lauscr) lcdc aus mode control register is used to determine the behavior of lcdc in aus mode. 0x1002_1068 (lgwdcr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r gwbt 00000000 gwhm w reset1 000000000000100 1514131211109876543210 r0 00000000 gwtm w reset0 000000001100000 figure 43-47. lcdc graphic window dma control register (lgwdcr) table 43-33. lcdc dma control register field descriptions field description 31 gwbt graphic window dma burst type. determines whether burst length is fixed or dynamic in graphic window plane. 0 burst length is dynamic. 1 burst length is fixed. 30?23 reserved?these bits are reserved and should read 0. 22?16 gwhm graphic window dma high mark. establishes high mark for dma requests. for dynamic burst length, once dma request is made, data is loaded and the graphic window fifo continues to be filled until the number of empty words left in the graphic window fifo is equal to the high mark minus 2. minimum hm setting in dynamic burst is 3. for fixed burst length, burst length (in words) of each request is equal to the dma high mark setting and its value must be larger than tm. 15?7 reserved. these bits are reserved and should read 0. 6?0 gwtm graphic window dma low mark. sets low level mark in the graphic window fifo to trigger a dma request. low level mark equals the number of words left in the pixel buffer. liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-49 43.3.27 lcdc aus mode cursor control register (lausccr) lcdc aus mode cursor control register is used to determine the color map of cursor in aus mode. 0x1002_1080 (lauscr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r aus mode 0000000 graphic window color key red ? agwckr[7:0] (aus mode only) w reset0 000000000000000 1514131211109876543210 r graphic window color key green ? agwckg[7:0] (aus mode only) graphic window color key blue ? agwckb[7:0] (aus mode only) w reset0 000000000000000 figure 43-48. lcdc aus mode control register (lauscr) table 43-34. lcdc aus mode control register field descriptions field description 31 aus mode aus mode control. determines whether lcdc enters aus mode or not. when bpix = 101, supports 16bpp auo panel. when bpix = 110, supports 24bpp auo panel. 0 normal mode 1 aus mode 30?24 reserved. these bits are reserved and should read 0. 23?16 agwckr aus graphic window color keying red component. defines the red component of graphic window color keying. (aus mode only) 15?8 agwckg aus graphic window color keying green component. defines the green component of graphic window color keying. (aus mode only) 7?0 agwckb aus graphic window color keying blue component. defines the blue component of graphic window color keying.(aus mode only) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-50 freescale semiconductor 43.3.28 bglut and gwlut there are 2 separate mapping rams in lcdc: ba ckground lookup table (bglut) and graphic window lookup table (gwlut). bglut is for background pl ane and the mapping table is addressable from 0x10021800?0x10021bfc. gwlut is for graphic window and its mapping table is addressable from 0x10021c00?0x10021ffc. these mapping rams are used for mapping 4-bit codes for grayscale to 16 gray shades, and for mapping 4-bit color and 8-bit co lor to 16 colors and 256 colors, respectively, out of either a palette of 4096 (pa ssive panels) or a palette of 256k (active panels). mapping ram contains 256 entries and each entry is 18-bits wide. each ram entry uses 4 bytes of address space. ram is accessed with word transact ions only and the address must be word aligned. unimplemented bits are read as 0. byte or halfword access to the ram corrupts its contents. all read and write data use the least significant 12 or 18 bits. in 4 bpp mode, first sixteen ram entries are used. in 8 bpp mode, all 256 ram entries are used. the color ram is not initialized at reset. only the following settings use the mapping rams: ? 4 bpp gray-scale mode ? 4 bpp passive matrix color mode 0x1002_1084 (lausccr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0000000 gcursor red ? acur_col_r [7:0] (aus mode only) w reset0 000000000000000 1514131211109876543210 r cursor green ? acur_col_g [7:0] (aus mode only) c ursor blue ? acur_col_b [7:0] (aus mode only) w reset0 000000000000000 figure 43-49. lcdc aus mode cursor control register (lausccr) table 43-35. lcdc aus mode cursor control register field descriptions field description 31?24 reserved. these bits are reserved and should read 0. 23?16 acur_col_r aus cursor red field. defines the red component of cursor color in color mode.(aus mode only) 15?8 acur_col_g aus cursor red field. defines the green component of cursor color in color mode.(aus mode only) 7?0 acur_col_b aus cursor red field. defines the blue component of cursor color in color mode.(aus mode only) liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 43-51 ? 8 bpp passive matrix color mode ? 4 bpp active matrix color mode ? 8 bpp active matrix color mode 43.3.28.1 four bits per pixel gray-scale mode in 4bpp gray-scale mode, a 4-bit code represents a gray-scale level. the first 16 mapping ram entries must be written to define the codes for all 16 combinations. 43.3.28.2 four bits per pixel passive matrix color mode in 4bpp passive matrix color mode, a 4- bit code represents a 12-bit color. because just 4-bits are used to encode the color, a maximum of 16 colors can be selected out of a palette of 4096. the first 16 mapping ram entries must be written to define the codes for the 16 available combinations. 43.3.28.3 eight bits per pixel passive matrix color mode in 8bpp passive matrix color mode, an 8-bit code represents a 12-bit color. because 8-bits are used to encode the color, a maximum of 256 colors can be selected out of a palette of 4096. all 256 mapping ram entries must be written to define the codes for the 256 available combinations. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpm table 43-36. four bits per pixel gray-scale mode bits field description 11?4 reserved these bits are reserved and should read 0. 3?0 gpm gray palette map. represents the gray-scale level for a given pixel code. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r g b table 43-37. four bits per pixel passive matrix color mode bits field description 11?8 r red level (color display). represents the red component level in the color. 7?4 g green level (color display). represents the green component level in the color. 3?0 b blue level (color display). represents the blue component level in the color. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r g b liquid crystal display controller (lcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 43-52 freescale semiconductor 43.3.28.4 four bits per pixel active matrix color mode in 4bpp active color mode, a 4-bit code represents a 18-bit color. because just 4-bits are used to encode the color, a maximum of 16 colors can be selected out of a palette of 256k. the first 16 mapping ram entries must be written to define the codes for the 16 available combinations. 43.3.28.5 eight bits per pixel active matrix color mode in 8bpp active color mode, an 8-bit code represents an 18-bit color. because 8-bits are used to encode the color, a maximum of 256 colors can be selected out of a palette of 256k. all 256 mapping ram entries must be written to define the codes for the 256 available combinations. table 43-38. eight bits per pixel passive matrix color mode bits field description 11?8 r red level (color display). represents the red component level in the color. 7?4 g green level (color display). represents the green component level in the color. 3?0 b blue level (color display). represents the blue component level in the color. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r g b table 43-39. four bits per pixel active matrix color mode bits field description 17?12 r red level (color display). represents the red component level in the color. 11?6 g green level (color display). represents the green component level in the color. 5?0 b blue level (color display). represents the blue component level in the color. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r g b table 43-40. eight bits per pixel active matrix color mode bits field description 17?12 r red level (color display). represents the red component level in the color. 11?6 g green level (color display). represents the green component level in the color. 5?0 b blue level (color display). represents the blue component level in the color. MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-1 chapter 44 smart liquid crystal display controller (slcdc) the slcdc module transfers data from display memory buffer to external display device. dma transfers data transparently with minima l software intervention. dma bus utilization is controllable and deterministic. as cellular phone displays become larger and more colorful, demands on the processor increase. more cpu power is needed to render and manage the image. the role of the display controller is to reduce the cpu?s involvement in the data transfer from memory to the display device so that cpu can concentrate on image rendering. dma is used to optimize the transf er. embedded control information needed by the display device is automatically read from a second buf fer in system memory and inserted into the data stream at the proper time to completely eliminate the cpu?s role in the transfer. a typical scenario for a cellular phone display is to have display image rendered in main system memory. after the image is complete, cpu tr iggers the slcdc module to transfer the image to the display device. image transfer is accomplished by burst dma which st eals bus cycles from cpu. cycle stealing behavior is programmable and bus use can be kept within predef ined bounds. after transfer is complete, a maskable interrupt is generated indicating the status. for animat ed displays, it is suggested to implement a 2-buffer ping-pong scheme so that when dma is fetching data fr om 1 buffer, next image is rendered into the other. several display sizes and types are used in various products that uses slcdc. slcdc module has the capability of directly interfacing to the selected di splay devices. both serial and parallel interfaces are supported. slcdc module only supports write to the di splay controller. slcdc read operations from the display controller are not supported. 44.1 slcdc module pin list table 44-1 is a list of the slcdc module pins. table 44-1. slcdc module pin list pin name direction description lcd interfaces slcdc_lcd_data[15:0] output data bus used to write information to external lcd controller. slcdc_lcd_cs output used as a chip select for external display controller in serial mode. in parallel mode, used as write strobe for the external display controller. this signal polarity is programmable. slcdc_lcd_rs output lcd register select signal that indicates to the lcd device whether data being written is display data or control data. this signal polarity is programmable. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-2 freescale semiconductor figure 44-1. slcdc system diagram 44.2 functional description the purpose of slcdc is to transparently and efficien tly transfer image data from system memory to an external lcd controller. system memory can be either internal or external memory. figure 44-1 shows the block diagram of slcdc module within the system. slcdc module contains a dma controller that is designed to operate as an alternate master. slcdc dma interface requests control of ahb to do 32-bit reads from system memory. the purpose of dma within slcdc is to transfer image and control data from system memory to slcdc fifo where it is formatted and sent out to the extern al lcd controller. dma only performs read accesses from system memory. the data is collected in 32-bit words and stored in two internal fifos. data is pulled from the fifos, as needed, and put in corr ect format for the external lcd controller. slcdc has both control and status registers which are accessible via ip bus. these registers are used to store information about the type of lcd controller a ttached to the system. slcdc can be configured to write image data to an external lcd controller via a 4-line serial, 3-line serial, an 8-bit or 16-bit parallel interface. during automatic transfers, slcdc is responsible for properly sequencing display data and control strings in a data stream that is sent to the lcd controller to fill its internal display ram. display data is typically written to the external controller in pages. each write to the controller fills one column of the current page. slcdc assumes that the controller automatically incr ements its display ram pointers after each write. control registers dma controller fifo dma request dma grant dma control dma address dma data lcd_data[15/8:0] lcd_cs lcd_rs bit manipulation & display interface data fifo command slcdc irq lcd display slcdc/ lcdc mux control, and data ahb address smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-3 note changing slcdc configuration in middle of transfer can cause corruption of data stream output to lcd. slcd c configuration must only be changed when go bit and busy bit of slcdc control/status register are cleared. 44.2.1 word size definition due to increased complexity of color displays, sl cdc supports 16- or 8-bit transfers of command or display data. this is controlled by wrd_def_com and wrd_def_dat bits in lcd transfer configuration register. all registers in slcdc are defined in words. wrd_def_dat controls definition of word for all data registers: ? data_buffer_size ? lcd_config wrd_def_com controls the definition of word for all command registers: ? command_buffer_size wrd_def_write controls the defini tion of lcddat for the register: ? lcd_write_data 44.2.2 image endianness in the examples of automatic transfers shown in this document, all memory images are either big endian or 32-bit little endian. however, it is possible that user may have an image that is stored in half word (16-bit) or byte (8-bit little endian). slcdc can co mpensate for this by using the imgend bits in the lcd_transfer_config register. these bits causes sl cdc to convert 16- or 8- bit little endian image to a big endian image. the resultant big endian decode is used for the rest of the data processing. 44.2.3 accessing the lcd controller slcdc provides two methods of acce ssing the external display device. ? the first, and preferred method, is through automatic writes handled by slcdc. ? the second, is through direct ip regist er access via lcd write data register. table 44-2. image endianness imgend conversion 32-bit word data stored in memory 32-bit data after conversion 00 big endian or 32-bit little endian to big endian 0x12345678 0x12345678 01 16-bit little endian to big endian 0x56781234 0x12345678 10 8-bit little endian to big endian 0x78563412 0x12345678 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-4 freescale semiconductor 44.2.3.1 automatic slcdc transfers slcdc is designed to take a bloc k of data from system memory and write it, without software intervention, to an external display controller. this is done by giving slcdc a starting address and a data block size (in words). this method can be used for both lcd display data as well as command data. transfers are initiated by setting the go bit in slcdc cont rol/status register. data transfer is done in the background. upon completion, a maskable interrupt is generated. automatic transfers are accomplished in one of three ways: ? a block of data is transferred to the lcd contro ller with control strings automatically inserted to navigate through the lcd controlle r?s internal ram. this mode makes use of a second buffer in system memory to store the software commands necessary for lcd c ontroller ram addressing. ? a block of data is transferred from system memory to the display controller while tying the lcd_rs pin low. ? a block of data is transferred from system memory to the display controller while tying the lcd_rs pin high. automatic transfer mode control bits (automode[1 :0]) of slcdc control/status register configures the slcdc for one of the three supported automatic transfer modes. 44.2.3.1.1 automatic display da ta transfers (automode[1:0] 1 =10) slcdc is designed to display a frame buffer from syst em memory to external lcd controller without any software intervention while transferring. to accomplis h this, slcdc must automa tically transmit control strings for lcd controller ram addr essing at appropriate times in the frame buffer data stream. lcd controller rams are typically organized into pages. after ram page is filled, controller?s page address must be set to the next page. slcdc contains count ers that monitor the number of display data words written to the lcd controller to determine when the current page of ram is filled. after this page is filled, slcdc inserts a control string into the data stream to set controller ram?s page address to next page. slcdc requires this control string be stored in a command buffer in system memory. the organization of command buffer is discussed later in this section. to correctly move a complete frame of image data from system memory to the lcd controller, slcdc must be programmed with the following lcd information: ? command word definition (8-bit or 16-bit words) ? data word definition (8-bit or 16-bit words) ? number of words in a page of lcd image data ? number of words in the lcd frame data buffer ? type of lcd interface (serial or parallel) ? data clock polarity of the lcd (for serial interfaces only) ? endianness of the image (big endian, little 32-bit, little 16-bit, or little 8-bit) ? chip-select polarity for the lcd ? transfer clock speed requirements of the lcd ? control string needed at the start of each page of lcd display data (sto red in a separate command buffer in system memory) 1. automode [1:0] = 11 is reserved. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-5 slcdc uses number of words per page of lcd image data information (stored in wordppage[12:0] bits of lcd config register) to determine when a se t of addressing commands must be sent to the lcd. when the current display ram page is full, slcdc must increment the page address and reset the column address of the lcd controller to 0. this is acco mplished by reading the next control string from the command buffer and transmitting it to the lcd contro ller. slcdc continues to send display data and command strings as needed until the controller?s disp lay ram is filled. transfer is finished when the number of data words transferred equals the number of words in the buffer as defined by databufsiz bits in data buffer size registers. figure 44-2. sample lcd controller memory mapping (monochrome) (8-bit command/8-bit data) figure 44-2 shows an example of how an external lcd controller ram is filled during automatic slcdc writes for a monochrome display. comma nd and data word sizes are both defined as bytes. in this example, lcd controller requires three ?command? words (bytes) to set the page and column address. setting go bit of control/status register starts the data transf er from system memory to the lcd controller. the first word written to lcd sets the page address to 0. the ne xt two words written are control strings that set the lcd column address to 0. word write #4 starts transfer of image data to the lcd. the first word of display data maps to the display column 0. the msb of th e word maps to row 7 and the lsb maps to row 0. commands stored in command buffer, written display data stored in data buffer, written to lcd controller ram at start of each page of lcd controller ram msb row 0 row 7 page 0 page 1 write #5 write #6 write #7 write # n+1 write # n+2 write # n+3 lsb row 8 row 15 write #n+8 write #n+9 write #n+10 write # 2n + 4 write # 2n + 5 write # 2n + 6 write # n+7 column n-3 column n-1 column n-2 column 0 column 1 column 2 column 3 write #4 row m-8 row m-1 page address 0 command page m 8 1 msb lsb lsb msb msb lsb lcd_data[0] lcd_data[1] lcd_data[2] lcd_data[3] lcd_data[7] lcd_data[6] lcd_data[5] lcd_data[4] page address 1 command page address command m 8 -1 write # write # m 8 (n+3)-n+1 m 8 (n+3)-n+2 write # (n+3)-1 m 8 write # (n+3)-2 m 8 write # (n+3) m 8 write # m 8 (n+3)-n+3 write # m 8 (n+3)-n+4 n = number of columns m = number of rows column address 0 command (lsb) write #1 write #2 column address 0 command (msb) column address 0 command (lsb) column address 0 command (msb) column address 0 command (lsb) column address 0 command (msb) write #3 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-6 freescale semiconductor words of display data continue to be written to lcd until slcdc?s internal word counter equa ls the value stored in wordppage[12:0] bits of lcd config register. at this point, slcdc issues a command string, taken from the command buffer, to increment the page address and rese t the column address of lcd. this sequence continues until lcd controller?s da ta ram is filled. after display buffer has been filled, irq bit of slcdc control/status register is se t. also, busy bit and go bit is cleared. an interrupt is generated if irqen bit is set and the system is configured for slcdc interrupts. figure 44-3. slcdc lcd controller memory mapping (2-bit color/gray scale) (8-bit command/8-bit data) figure 44-3 shows the mapping for a 2-bit color/gray scal e display. command and data word sizes are defined as bytes. for this configuration, each column of data within the page requires 2 word writes. the sequence remains the same as 1-bit per pixel case shown in figure 44-2 , however twice as many display data writes are required to fill the page. slcdc is designed to deal with a large variety of lcd controllers from multiple vendors. while the hardware interface to the external controller is some what standard, software interface can vary from chip to chip. to deal with the software differences be tween lcd controllers, slcdc makes use of a separate msb lsb row 0 row 7 page 0 page 1 write #5 write #6 write #7 write # 2n write # 2n+1 write # 2n+2 msb lsb row 8 row 15 write # 2n+8 write # 2n+9 write # 2n+10 write # 4n+3 write # 4n+4 write # 4n+5 write # 2n+7 column n-1 column n-2 column n-3 column 0 column 1 column 2 write #4 page address 0 command page row m-8 row m-1 write # m 8 m 8 (2n+3)-2n+2 write # (2n+3)-1 m 8 write # (2n+3)-2 m 8 write # (2n+3)-3 m 8 write # 2n-1 write # 4n+2 write # (2n+3)-4 m 8 write # 2n+3 write # 4n+6 write # (2n+3) m 8 write # m 8 (2n+3)-2n+3 write # m 8 (2n+3)-2n+4 column address 0 command (lsb) lsb msb lsb msb write #1 write #2 page address 1 command page address command m 8 n = number of columns m = number of rows 1 -1 lcd_data[0] lcd_data[1] lcd_data[2] lcd_data[3] lcd_data[7] lcd_data[6] lcd_data[5] lcd_data[4] write # m 8 (2n+3)-2n+1 column address 0 command (msb) write #3 column address 0 command (lsb) column address 0 command (msb) column address 0 command (lsb) column address 0 command (msb) commands stored in command buffer, written at start of each page of lcd controller ram display data stored in data buffer, written to lcd controller ram smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-7 command buffer stored in system memory to go along with the display data buffer. figure 44-4 shows the organization of the information in system memory. lcd page and column command buffer should be set up to contain the commands necessary to navigate through the lcd controller?s internal ram. each command in the buffer is preceded by a tag. slcdc uses the tags to determine the lcd_rs pin value during the command word transmission. figure 44-4. automatic display data transfer memory configuration (8-bit command/8-bit data) figure 44-5 shows how the commands and tags are organized in system memory. in this example, command string length is 3, that is, three words are required to be transmitted to the lcd controller at the start of each page of lcd ram. each of the comma nd words have a tag placed adjacent to it in the memory. the command is placed immediately after its tag in the memory. currently slcdc only uses the least-significant bit of the tag field. this bit, labeled ?rs? in figure 44-5 , sets the lcd_rs pin value while the command word is being transferred to the lcd controller. if rs tag bit is set to ?1?, lcd_rs is driven system memory command buffer lcd display data buffer lcd page & column page 0 display data page 1 display data page x display data page 0, column 0 commands page 1, column 0 commands page 2, column 0 commands page x-2, column 0 commands page x-1, column 0 commands page x, column 0 commands command base data base tag tag tag tag tag tag tag tag 31 0 16 15 tag string 0, byte 1 tag string 0, byte 2 tag string 0, byte 3 tag string 1, byte 1 string 2, byte 1 tag string 3, byte 1 tag string 1, byte 2 tag string 1, byte 3 tag string 2, byte 2 tag string 2, byte 3 string x-2 tag tag string 3, byte 2 string 3, byte 3 string x-2 string x-2 string x-1 string x-1 string x-1 tag tag string x string x string x page 2 display data page 3, column 0 commands address address smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-8 freescale semiconductor to 1 during the transfer of the corresponding command byte. similarly, if rs tag bit is set to ?0?, lcd_rs is driven to 0 during the transfer of the corresponding command byte. figure 44-5. command buffer tag organization (8-bit words) figure 44-6 shows a 16-bit command and 16-bit data transacti on for a 16-bit color display. in this example, command length is 3. each lcd data transfer is for one display pixel. the mapping of display pixels for 16-bit color is generally ?rrrrggggbbbbxxx? (r =red g=green b=blue x=ignored). check your display to see what the 16-bit color mapping is. in this case, a page consists of a row of pixels. three 16-bit words of command data are transferred to the display firs t, then 16-bit transfers of data will occur until the wordppage are transferred. three more command words are sent designating the next page, and the cycle repeats itself. page address command column address command (msbyte) column address command (lsbyte) page address command tag column address command (msbyte) tag column address command (lsbyte) tag rs rs rs command buffer lcd page and column command base 8 24 31 15 23 0 rs rs rs unused portion of tag unused portion of tag unused portion of tag 16 7 page 0, column 0 commands page 1, column 0 commands page 2, column 0 commands tag tag string 0, byte 1 tag string 0, byte 2 tag string 0, byte 3 tag string 1, byte 1 string 2, byte 1 tag string 3, byte 1 tag string 1, byte 2 tag string 1, byte 3 tag string 2, byte 2 tag string 2, byte 1 tag tag string 3, byte 2 string 3, byte 3 page 3, column 0 commands page x-2, column 0 command page x-1, column 0 command page x, column 0 commands tag tag tag tag tag tag tag string x-2 string x-2 string x-2 string x-1 string x-1 string x-1 tag tag string x string x string x address smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-9 figure 44-6. sample lcd controller memory map (16-bit color) (16-bit command/16-bit data) msb page 1 write #5 write #6 write #7 write # n+1 write # n+2 write # n+3 column n-3 column n-1 column n-2 column 0 column 1 column 2 column 3 write #4 page address 0 command msb lsb lsb lcd_data[0] lcd_data[1] lcd_data[2] lcd_data[3] lcd_data[7] lcd_data[6] lcd_data[5] lcd_data[4] n = number of columns m = number of rows column address 0 command (lsb) write #1 write #2 column address 0 command (msb) write #3 commands stored in command buffer, written display data stored in data buffer, written to lcd controller ram at start of each page of lcd controller ram lcd_data[8] lcd_data[9] lcd_data[10] lcd_data[11] lcd_data[15] lcd_data[14] lcd_data[13] lcd_data[12] msb page 2 write #n+8 write #n+9 write #n+10 write # 2n+4 write # 2n+5 write # 2n+6 write #n+7 page address 1 command msb lsb lsb column address 1 command (lsb) column address 1 command (msb) row 1 row 2 msb page m write # m(n+3)-2 write # m(n+3)-1 write # m(n-3) write #m(n+3)-n+1 page address m-1 command msb lsb lsb column address 1 command (lsb) column address 1 command (msb) row m write #m(n+3)-n+2 write #m(n+3)-n+3 write #m(n+3)-n+4 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-10 freescale semiconductor figure 44-7 shows how a 16-bit command word is stored in system memory. the 16-bit command is stored in the least significant half-word of memory (15?0). tag is stored in the most significant half-word of memory (31?16). currently only bit 16 of the tag is used for rs. figure 44-7. command buffer tag organization (16-bit words) figure 44-8 shows how 16-bit word commands and 16-bit word data is stored in system memory. because command data is 17-bits long (16-bits of command + 1- bit tag), each command takes up 1 word of system memory. each 16-bit word of data can be placed in a half-word of system memory. page address command column address command page address command tag column address command tag rs rs command buffer lcd page & column command base 16 31 23 0 rs rs unused portion of tag unused portion of tag 15 7 page 0, column 0 commands page 1, column 0 commands tag string 0, half 1 tag string 0, half 2 tag string 2, half 1 tag string 1, half 2 tag string 1, half 3 tag string 2, half 2 page 2, column 0 commands page x-2, column 0 command s page x-1, column 0 command s page x, column 0 commands tag tag string x-2 string x-1 string x-1 tag string x tag string x-2 tag string x column address command rs unused portion of tag tag string 0, half 3 tag string 2, half 3 tag string 1, half 1 tag string x-2 string x-1 tag tag tag string x address smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-11 figure 44-8. automatic display data transfer memory configuration (16-bit command/16-bit data) system memory command buffer lcd display data buffer lcd page & column page 0 display data page 1 display data page x display data page 0, column 0 commands page 1, column 0 commands page x-2, column 0 commands page x-1, column 0 commands page x, column 0 commands command base data base address 31 0 16 15 tag string 0, half2 tag page 2 display data page 2, column 0 commands string 0, half1 tag string 0, half3 tag string 1, half2 tag string 1, half1 tag string 1, half3 tag string 2, half2 tag string 2, half1 tag string 2, half3 tag string x-2 tag string x-2 tag string x-2 tag string x-1 tag string x-1 tag string x-1 tag string x tag string x tag string x address smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-12 freescale semiconductor figure 44-9. slcdc automatic mode write sequence (monochrome display) figure 44-9 and figure 44-10 show the sequence in which the data words are written to the lcd controller when automode[1:0] =10. these figures illustrate how the command strings, taken from the command buffer, are interleaved with displa y data taken from the data buffer. it is important to note that different combinations of word definitions are allowed. for example, there can be 8-bit command words and 16- bit data words. in this case, commands would be stored in system memory much like figure 44-5 , and data would be stored like figure 44-8 . refer section 44.3, ?lcd controller interface ? to determine how mixed transfers occur. page 0, column 0 page 0, column 1 page 0, column 2 page 0, column (n-2) page 0, column (n-1) page address 1 command string page 1, column 0 page 1, column 1 page address 0 command string page 1, column (n-2) page 1, column (n-1) , column (n-2) page x , column (n-1) page x page address 2 command string page 2, column 0 done filling display buffer: column address 0 command string (msb) column address 0 command string (lsb) column address 0 command string (msb) column address 0 command string (lsb) column address 0 command string (msb) column address 0 command string (lsb) set irq flag, (if enabled) assert interrupt smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-13 figure 44-10. slcdc automatic mode data flow (automode[1:0] = 10) 44.2.3.1.2 automatic command data transfers (automode[1:0]=00) slcdc provides a convenient method of moving data from system memory to an external device, like a lcd controller. when automode[1:0] bits = 00, slcdc ignores the command buffer and transfers the contents of specified data buffer to slcdc output pi ns, without inserting the pa ge and column addressing control strings. when automode[1:0] = 00, lcd_rs output is held to 0 during the entire transfer. this method is used for sending a block of commands to the lcd controller for initialization. the buffer transmitted is defined by databaseadr[16:0] bits of data base address register and databufsize[16:0] bits of data buffer size re gister. setting go bit of slcdc control/status register starts the transfer and sets the busy stat us bit. after the number of words transferred to the external device is equal to the buffer size defined by the data buffer size register, busy and go bit will be cleared, and irq flag will be set. a sy stem interrupt is generated if irqen bit is set. 44.2.3.1.3 automatic command data transfers (automode[1:0]=01) slcdc provides a convenient general purpose method of moving data from system memory to an external device, like a lcd controller. when automode[1:0] bits = 01, slcdc ignores the command buffer and transfers the contents of the specified data buffe r to the slcdc output pins without inserting page and column addressing control strings. when automode[1: 0] = 01, lcd_rs output is held to 1 during the entire transfer. the buffer transmitted is defi ned by databaseadr[31:0] bits of data base address register and databufsiz[16:0] bits of data buffer size register. setting go bit of lcd display data page address & column address commands flow of data from slcdc last write to the display controller first write to the (triggered by go) page 0 page x-2 page x-1 page x page 1 page 2 display controller smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-14 freescale semiconductor slcdc control/status register starts the transfer and sets the busy status bit. after the number of words transferred to the external device is equal to the buffer size defined by data buffer size register, busy and go bit is cleared, and irq flag is set. a system interrupt is genera ted if irqen bit is set. 44.2.3.2 direct register access single words are written to the external lcd contro ller via 9-bit lcd write data register. any write to the lcd write data register results in a write to the external display controller, provided that slcdc is not currently in middle of a transfer (indica ted by busy=1 in control/status register). the value written to lcddat[15:0] bits of lcd write data register are transmitted according to settings stored in lcd transfer configuration register, that is, transfer is done according to the settings of worddefwrite, xfrmode, cspol, and sckpol bits of lcd transfer configuration register. typical lcd controllers use a register select signal to distinguish betw een display data writes and control command writes. rs bit of lcd write data register determines whether a write is presented to the external controller as a command string or a display data string. lcd_rs pin is held to the value stored in the rs bit during byte transfer. since transfer to the ex ternal device is slow compared to the system clock rates, busy bit in the control/status register is used to indicate that a transfer is in progress. a transfer initiated by a write to the write data register causes an interrupt if irqen bit of slcdc control/status register is set. worddefwrite in lcd transfer confi guration register determines if an 8- or 16-bit transfer occurs. an 8-bit transfer causes lcddat[7:0] bits to be transferred, and lcddat[15:8] to be ignored. another direct write cannot be done until the pr evious transfer has completed (busy=0). 44.2.4 aborting slcdc transfers abort bit in slcdc control/status register is used to terminate a slcdc transfer that is in progress. termination occurs gracefully. any byte transfer that is in progress when abort is asserted is completed before the slcdc goes to an idle state. busy status bit clears upon entry to the idle state. irq flag will also assert, indicating that the abort is comple te. a slcdc interrupt is generated, if enabled. 44.2.5 low-power mode operation slcdc does not contain any control registers to pr ogram slcdc behavior during low-power modes. any power savings in the usage of slcdc are gained by reducing the system clock to a lower rate. 44.2.6 memory map table 44-3. sdlc memory map address register access reset value section/page 0x1002_2000 (databaseadr) data buffer base address register r/w 1 0x0000_0000 44.2.9/44-18 0x1002_2004 (databufsize) data buffer size register r/w 0x0000_0000 44.2.10/44-18 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-15 44.2.7 register summary the conventions in figure 44-11 and table 44-4 serve as a key for register summary and individual register diagrams. 0x1002_2008 (combaseadr) command base address register r/w 0x0000_0000 44.2.11/44-19 0x1002_200c (combufsiz) command buffer size register r/w 0x0000_0000 44.2.12/44-19 0x1002_2010 (comstringsiz) command string size register r/w 0x0000_0000 44.2.13/44-20 0x1002_2014 (fifoconfig) fifo configuration register r/w 0x0000_0000 44.2.14/44-21 0x1002_2018 (lcdconfig) lcd controller configuration register r/w 0x0000_0000 44.2.15/44-21 0x1002_201c (lcdtransconfig) lcd transfer configuration register r/w 0x0000_0000 44.2.16/44-22 0x1002_2020 (slcdccontrol/stat us) smart lcd control/status register r/w 0x0000_0000 44.2.17/44-23 0x1002_2024 (lcdclockconfig) lcd clock configuration register r/w 0x0000_0000 44.2.18/44-26 0x1002_2028 (lcd write data) lcd write register r/w 0x0000_0000 44.2.19/44-26 1 some r/w registers may contain some read-only or write-only bits. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 44-11. key to register fields table 44-4. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. w write only. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. table 44-3. sdlc memory map (continued) address register access reset value section/page smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-16 freescale semiconductor 44.2.8 sldc register descriptions this section provides deta iled descriptions of various slcdc registers. table 44-5 provides the detail summary for slcdc registers. w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the module, but it always reads as zero. (previously designated slfclr) reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 44-5. slcdc register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1002_2000 (databaseadr) r databaseadr[31:2] w r databaseadr[31:2] 00 w 0x1002_2004 (databufsize) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 w r databufsiz[16:0] w 0x1002_2008 (combaseadr) r combaseadr[31:2] w r combaseadr[31:2] 00 w 0x1002_200c (combufsiz) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0co mb ufs iz[1 6:0] w r combufsiz[16:0] w table 44-4. register conventions (continued) convention description smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-17 0x1002_2010 (comstringsiz) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 00 0 0 0 0 0 0 comstringsiz[7:0] w 0x1002_2014 (fifoconfig) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 burst w 0x1002_2018 (lcdconfig) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 00 0 wordppage[12:0] w 0x1002_201c (lcdtransconfig) r 00 0 0 0 0 0 0 0 0 0 0 0 0 imgend w r 00 0 0 0 0 0 0 0 0 word def write wor d def dat wor d def com xfr mod e cs pol sck pol w 0x1002_2020 (slcdccontrol/st at u s ) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 000 autom ode [1:0] 00 pr ot1 irq en irq undr flow irq 0 bus y 00 w w1c w1c w1c abo rt go 0x1002_2024 (lcdclockconfig) r 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 00 0 0 0 0 0 0 0 0 divide[5:0] w 0x1002_2028 (lcd write data) r 0 00 00 00 00 00 00 00 rs w r lcddat[15:0] w table 44-5. slcdc register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-18 freescale semiconductor 44.2.9 data buffer base address register (databaseadr) 44.2.10 data buffer size register (databufsize) address 0x1002_2000 (databaseadr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r databaseadr w reset0000000000000000 1514131211109876543210 r databaseadr 0 0 w reset0000000000000000 figure 44-12. data buffer base address register table 44-6. data buffer base address register field description field description 31?2 databaseadr data buffer base address. this register contains the pointer in r-ahb address space to the start of lcd data buffer. this value is used to form the 32-bit data buffer base address. data buffer base address value is forced to be word-aligned because the two lsbs are forced to 0. for example, data buffer base address [1:0] = 00. 1?0 reserved. these bits are reserved and should read zero. address 0x1002_2004 (databufsize) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 00 w reset0000000000000000 1514131211109876543210 r databufsize(17:0) w reset0000000000000000 figure 44-13. data buffer size register table 44-7. data buffer size register description field description 31?17 reserved. these bits are reserved and should read zero. 16?0 databufsiz data buffer size. this register defines the length (in words) of lcd image or control buffer stored in the system memory. this value is used to determine when dma transfer of data buffer from system memory to lcd controller is complete. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-19 note slcdc dma address generator width is 17-bits. therefore, it is possible that a data buffer can be incorrectly addressed by slcdc, if it extends beyond a 128 kbyte boundary. therefore, it is recommended that data buffer base address be set at the begi nning of a 128 kbyte boundary. the sum of databaseadr[16:0] and databufsiz[16:0] must not exceed a multiple of 128k. 44.2.11 command buffer base address register (combaseadr) 44.2.12 command buffer size register (combufsiz) address 0x1002_2008 (combaseadr) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r combaseadr(31:2) w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r combaseadr(31:2) 0 0 w reset0000000000000000 figure 44-14. command buffer base address register table 44-8. command base address register field description field description 31?2 combaseadr command buffer base address. this register contains the pointer in r-ahb address space to the start of lcd command buffer that contains the lcd controller page and column address commands. this buffer is used when slcdc is configured for transfers with automatic page address and column address command insertion. the command buffer base address value is forced to be word-aligned because the two lsbs are forced to 0. for example, command buffer base address [1:0] = 00. 1?0 reserved. these bits are reserved and should read zero. address 0x1002_200c (combufsiz) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 00comb ufsiz (16:0) w reset000000000000000 0 151413121110987654321 0 r combufsiz (16:0) w reset000000000000000 0 figure 44-15. command buffer size register smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-20 freescale semiconductor note slcdc dma address generator width is 17-bits. therefore, it is possible that a command buffer can be incorrectly addressed by the slcdc if it extends beyond a 128 kilobyte boundary. therefore, it is recommended that the command buffer base address be se t at the beginning of a 128 kilobyte boundary. the sum of combaseadr[16:0] and combufsiz[16:0] must not exceed a multiple of 128k. 44.2.13 command string size register (comstringsiz) table 44-9. command buffer size register field description field description 31?17 reserved. these bits are reserved and read zero. 16?0 combufsiz command buffer size. this register defines the length (in words) of lcd control buffer stored in system memory. this value is used to determine when dma transfer of command buffer from system memory to the lcd controller is complete. address 0x1002_2010 (comstringsiz) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 00 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 00 00 00 0 comstringsiz w reset0000000000000000 figure 44-16. command string size register table 44-10. command string size register field description field description 31?8 reserved. these bits are reserved and read zero. 7?0 comstringsiz command string size. length (in words) of the lcd command string made up of lcd controller page and column address commands. this command string is used when slcdc begins to fill a new page of the lcd controller?s ram. note: these strings are only transmitted to the lcd controller when slcdc is configured for transfers with automatic page and column address command insertion. command strings are stored along with tags in the lcd command buffer located in system memory. these bits represent the number of words that must be sent to the lcd controller to set the page and column address, not the number of words needed to store the corresponding commands and tags in system memory. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-21 44.2.14 fifo configuration register (fifoconfig) 44.2.15 lcd controller configur ation register (lcdconfig) address 0x1002_2014 (fifoconfig) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 00 w reset0000000000000000 1514131211109876543210 r0 000 000 000 000 burst w reset0000000000000000 figure 44-17. fifo configuration register table 44-11. fifo configuration register description field description 31?3 reserved. these bits are reserved and should read zero. 2?0 burst dma burst length. length (in 32-bit words) of the dma burst. that is, these bits determine the number of 32-bit word reads that occur when slcdc has ownership of r-ahb bus. 000 burst length set to 1 32-bit word 001 burst length set to 2 32-bit word ... 111 burst length set to 8 32-bit words address 0x1002_2018 (lcdconfig) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 00 w reset0000000000000000 1514131211109876543210 r0 00 wordppage w reset0000000000000000 figure 44-18. lcd controller configuration register table 44-12. lcd controller configuration register field description field description 31?13 reserved. these bits are reserved and should read zero. 12?0 wordppage lcd bytes per page. number of words per page for external lcd controller connected to slcdc module. these bits are used by slcdc to determine when control characters must be sent to the controller. 0 = 0 words per lcd page, 1 = 1 word per lcd page ? 8191 = 8191 words per lcd page smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-22 freescale semiconductor 44.2.16 lcd transfer configuration register (lcdtransconfig) address 0x1002_201c (lcdtransconfig) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 imgend w reset0000000000 0 0 0000 1514131211109876 5 4 3 2 1 0 r0 00 00 00 00 0word def write wor ddef dat wor ddef com xfr mod e csp ol skcp ol w reset0000000000 0 0 0000 figure 44-19. lcd transfer configuration register table 44-13. lcd transfer configuration register field description field description 31?18 reserved. these bits are reserved and should read zero. 17?16 imgend image endianness. this field defines the image endianness. 00 big endian or 32-bit little endian 01 16-bit little endian 10 8-bit little endian 11 reserved 15?6 reserved. these bits are reserved and should read zero. 5 worddefwrite word define, write data. it defines word for the lcd write data register transfers. 0 8-bit data words 1 16-bit data words 4 worddefdat word define, data. it defines word for lcd data registers and data transfers. all registers associated with data transfers (data buffer size, lcd config) must take this into consideration. 0 8-bit data words 1 16-bit data words 3 worddefcom word define, command. it defines word for lcd command registers and command data transfers. all registers associated with data transfers (command buffer size) must take this into consideration. 0 8-bit command words 1 16-bit command words 2 xfrmode image data transfer width. this bit selects the width of lcd display interface data bus. data transfers to the lcd controller can be done in a serial or parallel manner. 0 word serial transfers 1 word parallel transfers smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-23 44.2.17 slcdc control/status regi ster (slcdccontrol/status) 1 cspol chip select polarity. selects lcd_cs signal polarity. it affects the lcd_cs pin behavior. 0 lcd_cs is asserted low. therefore, slcdc will drive lcd_cs to 0 during serial transfer of data to external lcd controller. in parallel mode, lcd_cs will normally be high. lcd data will change when lcd_cs goes low. lcd_cs rising edge is used by the lcd controller to latch the parallel data. 1 lcd_cs is asserted high. therefore, slcdc will drive lcd_cs to 1 during serial transfer of data to external lcd controller. in parallel mode, lcd_cs will normally be low. lcd data will change when lcd_cs goes high. lcd_cs falling edge is used by lcd controller to latch the parallel data. 0 sckpol serial data clock polarity. it selects whether serial data transitions on rising/falling edge of serial data clock during transfers of data in serial mode. it has no effect during parallel data transfers. 0 serial data will transition on the rising edge of serial clock. therefore, data should be latched by the display device on the falling edge of serial clock. 1 serial data will transition on the falling edge of serial clock. therefore, data should be latched by the display device on the rising edge of serial clock. 0x1002_2020 (slcdccontrol/status) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 000 w reset000 0 0 00 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 00 automode 0 0 prot 1 irqe n irq undr flow tea 0 busy abo rt go w reset000 0 0 00 0 0 0 0 0 0 0 0 0 figure 44-20. slcdc control/status register table 44-13. lcd transfer configuration register field description (continued) field description smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-24 freescale semiconductor table 44-14. slcdc control/status register field description field description 31?13 reserved. these bits are reserved and should read zero. 12?11 automode automatic transfer mode. these bits control how slcdc transfers the data buffer to the lcd controller upon being triggered by the go bit. data base address bits designate the location of transferred data buffer in the system memory. transfers triggered by go bit can be configured to automatically insert page address and column address commands in the data stream to navigate through the lcd controller?s ram. this is done without cpu intervention. slcdc can be also be configured to send the data buffer to the lcd controller without inserting any command strings. in this mode, the value of the lcd_rs signal can be configured to be either 1 or 0 during the transfer. 00 slcdc transfers the data buffer defined by data base address and data buffer size without inserting control strings. with this setting, lcd_rs signal is tied to 0 during the entire transfer. 01 slcdc transfers the data buffer defined by data base address and data buffer size without inserting control strings. with this setting, lcd_rs signal is tied to 1 during the entire transfer. 10 when transmitting data buffer defined by data base address and data buffer size, slcdc inserts command strings to set the lcd controller?s page and column addresses. these command strings are taken from the buffer defined by command base address and command string size. this insertion of command strings is done at beginning of each page of lcd controller ram. 11 reserved 10?9 reserved. these bits are reserved and should read zero. 8 prot1 r-ahb protection code. this bit controls the hprot[1] signal value sent to r-ahb each time a slcdc access is done. this value controls the access type done on the bus (user or privileged). slcdc_hprot[0] output of slcdc is tied to 1 to indicate a data access. prot1 bit resets to 0. 0 slcdc_hprot[1:0] driven to 01 indicating slcdc accesses will be user data accesses. 1 slcdc_hprot[1:0] driven to 11 indicating slcdc accesses will be privileged data accesses. 7 irqen interrupt enable. this bit controls whether a slcdc interrupt is generated upon completion of slcdc transfer or not. slcdc transfers can end in three ways: 1) when a transfer error occurs on the r-ahb. 2) when slcdc completes the data transfer to the lcd controller. 3) when a slcdc transfer is aborted by setting abort bit in slcdc control/status register. slcdc transfers are initiated by assertion of go bit or a write to lcd write data register. clearing irqen bit prevents an interrupt from being generated when slcdc completes a transfer. 0 slcdc interrupt is masked. no interrupt is generated from slcdc. 1 slcdc interrupt is generated upon completion of a slcdc transfer. 6 irq slcdc interrupt flag. this bit indicates that an interrupt condition occurred in slcdc. interrupt flag is set when a slcdc transfer is completed or aborted. slcdc transfers are initiated by assertion of go bit or a write to lcd write data register. this bit is cleared by writing a 1 to it. 0 slcdc interrupt is not pending 1 interrupt condition occurred in slcdc. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-25 5 undrflow slcdc fifo underflow. this bit indicates that slcdc fifo became empty during data transfer from system memory to lcdc. although fifo underflow does not cause an error in slcdc transfer, it indicates the output portion of slcdc had to wait for fifo to be filled during transfer. this bit is cleared by writing a 1 to it. note: underflow flag will not set until some data has been read into the slcdc fifos. it only sets when fifos does not refill fast enough for the slcdc bit manipulator. in this case, slcdc bit manipulator stalls while it waits for data to be read from system memory into the fifos. it is also not set in case when a slcdc transfer is initiated, but slcdc is never granted control of bus, and thus able to fill the fifos. fifos must go from a non-empty state to an empty state to set it. 0 no underflow occurred in slcdc fifo. 1 slcdc fifo became empty during data transfer to the lcd controller. this causes the output portion of slcdc to wait, delaying data transfer to the lcd controller. 4 tea slcdc dma transfer error. this bit indicates that slcdc dma received a transfer error acknowledge from r-ahb bus while trying to read data from system memory. this is indicated by hresp0=1 and hready=1 on the r-ahb bus. this is a fatal condition and causes slcdc to terminate its transfer. this bit is cleared by writing a 1 to it. 0 no transfer error acknowledge error occurred. 1 a transfer error acknowledge was received by the slcdc dma from the r-ahb. 3 reserved. this bit is reserved and should read zero. 2 busy slcdc busy. this bit indicates that slcdc is in the process of transferring image buffer from system memory to lcd controller. data transfer is initiated by setting the go bit or by writing data to the lcd write data register. this bit is a read-only bit and clears after data transfer to the lcd controller is completed. 0 slcdc idle. 1 slcdc in process of transferring image buffer. 1 abort abort slcdc transfer. this bit causes slcdc to abort the current data transfer. termination occurs gracefully, that is, ongoing byte transfer to the lcd controller is completed before slcdc goes to an idle state. this bit is cleared automatically when slcdc has transitioned to the idle state. 0 do not abort the current data transfer. 1 abort the current slcdc data transfer. 0 go start slcdc transfer. this bits starts automatic transfer of image data from system memory to the external lcd controller. this bit always reads 1 until data transfer is complete. after data transfer is complete or has been aborted, go bit will read 0. note: writing 1 to this bit has no effect if busy bit is set. 0 do not start slcdc transfer. 1 start slcdc image data transfer. table 44-14. slcdc control/status regi ster field description (continued) field description smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-26 freescale semiconductor 44.2.18 lcd clock configuratio n register (lcdclockconfig) 44.2.19 lcd write data register (lcdwritedata) address 0x1002_2024 (lcdclockconfig) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 00 w reset0000000000000000 1514131211109876543210 r0 00 00 00 00 0 divide w reset0000000000000000 figure 44-21. lcd clock configuration register table 44-15. lcd clock configuration register field description field description 31?6 reserved. these bits are reserved and should read zero. 5?0 divide lcd clock divide value. this bit sets the divide ratio used to generate the lcd clock from hclk_slcdc clock. setting divide to 0 disables the lcd_clk by gating hclk_slcdc clock from the fractional divider. these bits must be set to some non-zero value before lcd transfers can occur. frequency relations: 0 lcd_clk off 1 lcd_clk = hclk_slcdc clock*1/128 2 lcd_clk = hclk_slcdc clock*2/128 ? 63 lcd_clk=hclk_slcdc clock*63/128 0x1002_2028 (lcd write data) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 00 00 00 00 00 00 0 0 rs w reset0000000000000000 1514131211109876543210 r lcddat w reset0000000000000000 figure 44-22. lcd write data register smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-27 44.3 lcd controller interface slcdc transfers data from the display memory buffer in system memory to the external display device. transfers can be done via a 4-wire serial, 3-wire serial, 8-bit parallel, or a 16-bit parallel interface. 44.3.1 serial interface in serial mode (xfrmode bit in lcd transfer configuration register is 0), data is transmitted to the display device via lcd_cs, lcd_data[7:6] and lcd_rs. data is transmitted on lcd_data[7], serial clock toggles on lcd_data[6] and lcd_rs tells the display whether it is display data or command data. lcd_cs is used as a chip select signa l. lcd_cs signal is asserted during all transfers. lcd_cs signal polarity is programmable using the cspol bit of lcd transfer configuration register ( section 44.2.16, ?lcd transfer configur ation register (lcdtransconfig) ?). figure 44-23 shows timing associated with the transfer of one byte of data to the display. the polarity of the serial data clock on lcd_data[6] pin can be configured using sckpol bit of lcd transfer configuration register ( section 44.2.16, ?lcd transfer configuration register (lcdtransconfig) ?). this bit must be set in accordance with the external display device requirements. if external device latches the serial data on rising edge of serial clock, sc kpol must be set to 1. if external device latches the serial data on fa lling edge of serial clock, sckpol must be cleared. the command and data word definitions determines how l ong the data string is in serial mode. figure 44-23 shows 8-bit transfers. a serial transfer of 16- bits has same timing as 8-bit transfers, however 16-bits of data is transferred. it is possible to ha ve a command defined as 8-b its and serial defined as 16-bits (or vice versa). in this case, when a command is being transferred, 8-bits of data are sent, and when data is being transferred, 16-bits of data is sent. table 44-16. lcd write data register field description field description 31?17 reserved. these bits are reserved and should read zero. 16 rs lcd register select. determines the value placed on lcd_rs pin during byte transfer from write data register 0 lcd_rs signal is tied to 0 during transfer. 1 lcd_rs signal is set to 1 during transfer. 15?0 lcddat lcd controller data. data written is transferred to the external lcd controller. this register gives direct write access to the lcd controller. data is determined to be command or display data via rs bit. data written to this register is only transferred to the lcd controller if slcdc is not in middle of another transfer (indicated by the busy bit of control/status register ( section 44.2.17, ?slcdc control/status register (slcdccontrol/status) ?). a read of these bits gives the last value written to this register (or the reset value), and not a value from the lcd controller. the amount of data that is transferred is determined by worddefwrite bit in the lcd transfer configuration register ( section 44.2.16, ?lcd transfer configuration register (lcdtransconfig) ?). during 8-bit word transfers, lcddat[7:0] is transferred, and lcddat[15:8] is ignored. smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-28 freescale semiconductor figure 44-23. slcdc serial transfers to lcd device tcss tcyc tds tcsh tdh tcl tch trsh trss tcss tcyc tds tcsh tdh tcl tch trsh trss tcss tcyc tds tcsh tdh tcl tch trsh trss lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when sckpol = 1 and cspol = 0 this diagram illustrates the timing when sckpol = 0 and cspol = 0 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when sckpol = 1 and cspol = 1 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when sckpol = 0 and cspol = 1 tcss tcyc tds tcsh tdh tcl tch trsh trss smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-29 t prop is the propagation delay from slcdc outputs to the pin outputs. 44.3.2 parallel interface slcdc module can be configured to execute parallel transfers of display data from the system memory to an external display device. figure 44-24 shows the timing associated with an slcdc parallel transfer to an external lcd device. the timing is based on the frequency of lcd_clk, which is programmable via lcd clock configuration register ( section 44.2.18, ?lcd clock configuration register (lcdclockconfig) ?). in parallel mode, lcd_cs pin is used as a write st robe by the external lcd controller. lcd_cs latching edge occurs one lcd_clk cycle after data is made available to the display on the lcd_data[15:0] pins. lcd_cs signal polarity is programmable using the cspol bit in the lcd transfer configuration register. data transfers of 16- or 8-bit are determin ed by the word definition bits in the lcd transfer configuration register ( section 44.2.16, ?lcd transfer configur ation register (lcdtransconfig) ?). all 8-bit data transfer uses lcd_data[7:0]. lcd_data [15:8] shows 0?s. it is possible for there to be a 8-bit command data transfers and 16- bit display data transfers (and vice versa). in this case, when command data is transferred, only lcd_data[7:0] is used, and display data uses lcd_data[15:0]. t prop is the propagation delay from the slcdc outputs to the pin outputs. table 44-17. slcdc serial interface timing symbol parameter minimum (ns) typical (ns) maximum (ns) t css chip select setup time (t cyc / 2) ( ) t prop ?? t csh chip select hold time (t cyc / 2) ( ) t prop ?? t cyc serial clock cycle time 39 ( ) t prop ?2641 t cl serial clock low pulse 18 ( ) t prop ?? t ch serial clock high pulse 18 ( ) t prop ?? t ds data setup time (t cyc / 2) ( ) t prop ?? t dh data hold time (t cyc / 2) ( ) t prop ?? t rss register select setup time (15 * t cyc / 2) ( ) t prop ?? t rsh register select hold time (t cyc / 2) ( ) t prop ?? table 44-18. slcdc parallel interface timing symbol parameter minimum (ns) typical (ns) maximum (ns) t cyc parallel clock cycle time 78 ( ) t prop ? 4923 t ds data setup time (t cyc / 2) ( ) t prop ?? t dh data hold time (t cyc / 2) ( ) t prop ?? t rss register select setup time (t cyc / 2) ( ) t prop ?? t rsh register select hold time (t cyc / 2) ( ) t prop ?? smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-30 freescale semiconductor figure 44-24. slcdc parallel transfers to lcd device 44.4 lcd clock configuration slcdc uses a fractional divider to generate the lcd data clock from hclk_slcdc clock signal. the fractional divider is programmed by setting a divide value using divide[5:0] bits of the lcd clock configuration register ( section 44.2.18, ?lcd clock configuration register (lcdclockconfig) ). lcd_clk frequency is calculated using equation 44-1 : eqn. 44-1 divide value is taken directly from divide[5:0] bits of the lcd clock configuration register ( section 44.2.18, ?lcd clock configurat ion register (lcdclockconfig) ?). setting divide[5:0] to 0, disables the lcd_clk signal. these bits must be set to some non-zero value before lcd transfers can occur. lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc this diagram illustrates the timing when cspol=0 this diagram illustrates the timing when cspol=1 lcd_clk hclkx dividevalue () 128 ------------------------------------------------------------ - = smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 freescale semiconductor 44-31 44.5 r-ahb interface and slcdc fifos slcdc uses a dma interface to access system memory without cpu intervention. when slcdc needs data, dma requests ahb control and reads 32-bit word s from the system memory. the number of 32-bit words read during the burst is determined by the va lue stored in the burst[2:0] bits of the fifo configuration register ( section 44.2.14, ?fifo configura tion register (fifoconfig) ?). ahb control is relinquished by dma after the burst is complete. sl cdc generates idle cycles when data transfer is complete. the amount of r-ahb bandwidth requi red by slcdc can be controlled by the system software. the frequency of lcd frame updates and th e rate of lcd_clk affect how often the slcdc requests the use of r-ahb. data read by the dma interface is stored in two 32-bit 8 word fifos that are used to buffer data between the dma and the slcdc display interface. one fifo is used to buffer data from the command buffer and the other is used to buffer data from the display data buffer. when one fifo has enough room to store the data read during a dma burst, it will request serv icing. because dma burst length is programmable, the occupancy level of the fifos can vary when servicing is requested. table 44-19. lcd_clk frequency range hclk_slcdc clock frequency (mhz) minimum lcd_clk frequency (mhz) maximum lcd_clk frequency (mhz) resolution of step (khz) 52 0 25.59 406.25 26 0 12.8 203.13 16.8 0 8.27 131.25 smart liquid crystal display controller (slcdc) MCIMX27 multimedia applications processor reference manual, rev. 0.2 44-32 freescale semiconductor |
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